ADG3301BKSZ-REEL7 [ADI]
Low Voltage 1.15 V to 5.5 V, Single-Channel Bidirectional Logic Level Translator; 低电压1.15 V至5.5 V ，单通道双向逻辑电平转换器
| 型号： | ADG3301BKSZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Voltage 1.15 V to 5.5 V, Single-Channel Bidirectional Logic Level Translator |
| 文件： | 总20页 (文件大小：785K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage 1.15 V to 5.5 V, Single-Channel
Bidirectional Logic Level Translator
ADG3301
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Bidirectional level translation
Operates from 1.15 V to 5.5 V
Low quiescent current < 5 µA
No direction pin
V
V
CCY
CCA
A
Y
EN
APPLICATIONS
ADG3301
SPI®, MICROWIRE® level translation
Low voltage ASIC level translation
Smart card readers
GND
Figure 1.
Cell phones and cell phone cradles
Portable communication devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
Portable POS systems
Low cost serial interfaces
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3301 is a single-channel, bidirectional logic level
translator. It can be used in multivoltage digital system applica-
tions such as data transfer between a low voltage DSP/controller
and a higher voltage device. The internal architecture allows the
device to perform bidirectional logic level translation without an
additional signal to set the direction in which the translation
takes place.
1. Bidirectional level translation.
2. Fully guaranteed over the 1.15 V to 5.5 V supply range.
3. No direction pin.
4. Compact 6-lead SC70 package.
The voltage applied to VCCA sets the logic levels on the A side of
the device, while VCCY sets the levels on the Y side. For proper
operation, VCCA must always be less than VCCY. The VCCA
-
compatible logic signals applied to the A pin appear as VCCY
-
compatible levels on the Y pin. Similarly, VCCY-compatible logic
levels applied to the Y pin appear as VCCA-compatible logic levels
on the A pin. The enable pin (EN) provides three-state operation
on both the A pin and the Y pin. When the device enable pin is
pulled low, the terminals on both sides of the device are in the
high impedance state. The EN pin is referred to the VCCA supply
voltage and driven high for normal operation.
The ADG3301 is available in a compact 6-lead SC70 package
and is guaranteed to operate over the 1.15 V to 5.5 V supply
voltage range and extended −40°C to +85°C temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADG3301
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 12
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
Level Translator Architecture ................................................... 16
Input Driving Requirements..................................................... 16
Output Load Requirements ...................................................... 16
Enable Operation ....................................................................... 16
Power Supplies............................................................................ 16
Data Rate ..................................................................................... 17
Applications..................................................................................... 18
Layout Guidelines....................................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
12/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG3301
SPECIFICATIONS
VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
Symbol
Conditions
Min
Typ2 Max
Unit
LOGIC INPUTS/OUTPUTS
A Side
Input High Voltage3
VIHA
VIHA
VILA
VOHA
VOLA
CA
VCCA = 1.15 V
VCCA = 1.2 V to 5.5 V
VCCA − 0.3
0.65 × VCCA
V
Input Low Voltage3
Output High Voltage
Output Low Voltage
Capacitance3
0.35 × VCCA
V
V
V
pF
µA
VY = VCCY, IOH = 20 µA, see Figure 27
VY = 0 V, IOL = 20 µA, see Figure 27
f = 1 MHz, EN = 0, see Figure 32
VA = 0 V/VCCA, EN = 0, see Figure 29
VCCA − 0.4
0.4
9
Leakage Current
ILA, HiZ
1
Y Side
Input High Voltage3
Input Low Voltage3
Output High Voltage
Output Low Voltage
Capacitance3
VIHY
VILY
VOHY
VOLY
CY
0.65 × VCCY
VCCY − 0.4
V
V
V
V
pF
µA
0.35 × VCCY
VA = VCCA, IOH = 20 µA, see Figure 28
VA = 0 V, IOL = 20 µA, see Figure 28
f = 1 MHz, EN = 0, see Figure 33
VY = 0 V/VCCY, EN = 0, see Figure 30
0.4
1
6
Leakage Current
Enable (EN)
ILY, HiZ
Input High Voltage3
VIHEN
VIHEN
VILEN
ILEN
CEN
tEN
VCCA = 1.15 V
VCCA = 1.2 V to 5.5 V
VCCA − 0.3
0.65 × VCCA
V
V
V
µA
pF
µs
Input Low Voltage3
Leakage Current
Capacitance3
0.35 × VCCA
1
VEN = 0 V/VCCA, VA = 0 V, see Figure 31
3
1
Enable Time3
1.8
RS = RT = 50 Ω, VA = 0 V/VCCA (A→Y),
VY = 0 V/VCCY (Y→A), see Figure 34
SWITCHING CHARACTERISTICS3
3.3 V 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V 0.5 V
A→Y Level Translation
RS = RT = 50 Ω, CL = 50 pF,
see Figure 35
Propagation Delay
Rise Time
6
2
2
10
ns
tP, A
Y
→
3.5
3.5
ns
tR, A
Y
→
Fall Time
ns
tF, A
→
Y
Maximum Data Rate
Part-to-Part Skew
Y→A Level Translation
50
50
Mbps
ns
DMAX, A
Y
→
3
tPPSKEW, A
Y
→
RS = RT = 50 Ω, CL = 15 pF,
see Figure 36
Propagation Delay
Rise Time
4
1
3
7
3
7
ns
tP, Y
A
→
ns
tR, Y
A
→
Fall Time
ns
tF, Y
A
→
Maximum Data Rate
Part-to-Part Skew
Mbps
ns
DMAX, Y
A
→
2
tPPSKEW, Y
A
→
1.8 V 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Translation
RS = RT = 50 Ω, CL = 50 pF,
see Figure 35
Propagation Delay
Rise Time
8
2
2
11
5
ns
tP, A
Y
→
ns
tR, A
Y
→
Fall Time
5
ns
tF, A
→
Y
Maximum Data Rate
Part-to-Part Skew
50
Mbps
ns
DMAX, A
Y
→
4
tPPSKEW, A
Y
→
Rev. 0 | Page 3 of 20
ADG3301
Parameter1
Symbol
Conditions
Min
Typ2 Max
Unit
RS = RT = 50 Ω, CL = 15 pF,
see Figure 36
Y→A Translation
Propagation Delay
Rise Time
5
2
2
8
ns
tP, Y
A
→
3.5
3.5
ns
tR, Y
A
→
Fall Time
ns
tF, Y
→
A
Maximum Data Rate
Part-to-Part Skew
50
Mbps
ns
DMAX, Y
A
→
3
tPPSKEW, Y
A
→
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Translation
RS = RT = 50 Ω, CL = 50 pF,
see Figure 35
Propagation Delay
Rise Time
9
3
2
18
5
ns
tP, A
Y
→
ns
tR, A
Y
→
Fall Time
5
ns
tF, A
→
Y
Maximum Data Rate
Part-to-Part Skew
Y→A Translation
40
40
Mbps
ns
DMAX, A
Y
→
10
tPPSKEW, A
Y
→
RS = RT = 50 Ω, CL = 15 pF,
see Figure 36
Propagation Delay
Rise Time
5
2
2
9
4
4
ns
tP, Y
A
→
ns
tR, Y
A
→
Fall Time
ns
tF, Y
A
→
Maximum Data Rate
Part-to-Part Skew
Mbps
ns
DMAX, Y
A
→
4
tPPSKEW, Y
A
→
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V 0.3 V
A→Y Translation
RS = RT = 50 Ω, CL = 50 pF,
see Figure 35
Propagation Delay
Rise Time
12
7
25
12
5
ns
tP, A
Y
→
ns
tR, A
Y
→
Fall Time
3
ns
tF, A
→
Y
Maximum Data Rate
Part-to-Part Skew
Y→A Translation
25
25
Mbps
ns
DMAX, A
Y
→
15
tPPSKEW, A
Y
→
RS = RT = 50 Ω, CL = 15 pF,
see Figure 36
Propagation Delay
Rise Time
14
5
35
16
6.5
ns
tP, Y
A
→
ns
tR, Y
A
→
Fall Time
2.5
ns
tF, Y
A
→
Maximum Data Rate
Part-to-Part Skew
Mbps
ns
DMAX, Y
A
→
23.5
tPPSKEW, Y
A
→
2.5 V 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Translation
RS = RT = 50 Ω, CL = 50 pF,
see Figure 35
Propagation Delay
Rise Time
7
10
4
ns
tP, A
Y
→
2.5
2
ns
tR, A
Y
→
Fall Time
5
ns
tF, A
→
Y
Maximum Data Rate
Part-to-Part Skew
Y→A Translation
60
60
Mbps
ns
DMAX, A
Y
→
4
tPPSKEW, A
Y
→
RS = RT = 50 Ω, CL = 15 pF,
see Figure 36
Propagation Delay
Rise Time
5
1
3
8
4
5
ns
tP, Y
A
→
ns
tR, Y
A
→
Fall Time
ns
tF, Y
A
→
Maximum Data Rate
Part-to-Part Skew
Mbps
ns
DMAX, Y
A
→
3
tPPSKEW, Y
A
→
Rev. 0 | Page 4 of 20
ADG3301
Parameter1
Symbol
Conditions
Min
Typ2 Max
Unit
POWER REQUIREMENTS
Power Supply Voltages
VCCA
VCCY
ICCA
VCCA ≤ VCCY
1.15
1.65
5.5
5.5
5
V
V
µA
Quiescent Power Supply Current
VA = 0 V/VCCA, VY = 0 V/VCCY
VCCA = VCCY = 5.5 V, EN = 1
VA = 0 V/VCCA, VY = 0 V/VCCY
,
0.17
0.27
ICCY
,
5
µA
VCCA = VCCY = 5.5 V, EN = 1
Three-State Mode Power Supply Current
IHiZA
IHiZY
VCCA = VCCY = 5.5 V, EN = 0
VCCA = VCCY = 5.5 V, EN = 0
0.1
0.1
5
5
µA
µA
1 Temperature range for the B version is −40°C to +85°C.
2 All typical values are at TA = 25°C, unless otherwise noted.
3 Guaranteed by design, not subject to production test.
Rev. 0 | Page 5 of 20
ADG3301
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VCCA to GND
−0.3 V to +7 V
VCCY to GND
VCCA to +7 V
Digital Inputs (A)
Digital Inputs (Y)
EN to GND
−0.3 V to VCCA + 0.3 V
−0.3 V to VCCY + 0.3 V
−0.3 V to +7 V
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance (4-Layer Board)
6-Lead SC70
Only one absolute maximum rating may be applied at any one
time.
−40°C to +85°C
−65°C to +150°C
150°C
494.1°C/W
300°C
260(+0/−5)°C
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (< 20 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 20
ADG3301
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
6
5
4
V
Y
CCA
CCY
ADG3301
A
TOP VIEW
(Not to Scale)
GND
EN
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
Power Supply Voltage Input for the A I/O Pin (1.15 V ≤ VCCA ≤ VCCY).
1
2
3
4
5
6
VCCA
A
GND
EN
Y
Input/Output A. Referenced to VCCA
.
Ground (0 V).
Active High Enable Input.
Input/Output Y. Referenced to VCCY
.
VCCY
Power Supply Voltage Input for the Y I/O Pin (1.65 V ≤ VCCY ≤ 5.5V).
Rev. 0 | Page 7 of 20
ADG3301
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
T
= 25°C
A
T = 25°C
A
1 CHANNEL
= 50pF
1 CHANNEL
C = 15pF
L
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
C
L
V
= 3.3V, V
= 5V
CCY
CCA
V
= 3.3V, V
= 5V
CCY
CCA
V
= 1.8V, V
= 3.3V
CCY
CCA
V
= 1.8V, V
= 3.3V
CCA
CCY
40
V
= 1.2V, V
= 1.8V
40
V
= 1.2V, V
= 1.8V
CCA
CCY
35
CCA
25
DATA RATE (Mbps)
CCY
0
5
10
15
20
30
35
45
50
0
5
10
15
20
25
30
45
50
DATA RATE (Mbps)
Figure 6. ICCY vs. Data Rate (Y→A Level Translation)
Figure 3. ICCA vs. Data Rate (A→Y Level Translation)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
C
1 CHANNEL
V
V
9
8
7
6
5
4
3
2
1
0
= 50pF
= 1.2V
= 1.8V
L
CCA
CCY
20Mbps
V
= 3.3V, V
= 5V
CCY
CCA
10Mbps
5Mbps
V
= 1.8V, V = 3.3V
CCY
CCA
V
= 1.2V, V
= 1.8V
CCY
CCA
1Mbps
53
13
23
33
43
63
73
0
5
10
15
20
25
30
35
40
45
50
DATA RATE (Mbps)
CAPACITIVE LOAD (pF)
Figure 4. ICCY vs. Data Rate (A→Y Level Translation)
Figure 7. ICCY vs. Capacitive Load at Pin Y for A→Y
(1.2 V→1.8 V) Level Translation
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
C
1 CHANNEL
V
V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
= 15pF
= 1.2V
=1.8V
L
CCA
CCY
V
= 3.3V, V
= 5V
CCY
CCA
20Mbps
V
= 1.8V, V
= 3.3V
CCA
CCY
40
10Mbps
5Mbps
V
= 1.2V, V
= 1.8V
CCA
CCY
1Mbps
0
5
10
15
20
25
30
35
45
50
13
23
33
CAPACITIVE LOAD (pF)
43
53
DATA RATE (Mbps)
Figure 5. ICCA vs. Data Rate (Y→A Level Translation)
Figure 8. ICCA vs. Capacitive Load at Pin A for Y→A
(1.8 V→1.2 V) Level Translation
Rev. 0 | Page 8 of 20
ADG3301
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
V
V
1 CHANNEL
V
V
= 1.8V
= 3.3V
= 3.3V
= 5V
CCA
CCY
CCA
CCY
50Mbps
50Mbps
30Mbps
20Mbps
30Mbps
20Mbps
10Mbps
5Mbps
10Mbps
5Mbps
63
13
23
33
43
53
73
13
23
33
43
53
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 12. ICCA vs. Capacitive Load at Pin A for Y→A
(5 V→3.3 V) Level Translation
Figure 9. ICCY vs. Capacitive Load at Pin Y for A→Y
(1.8 V→3.3 V) Level Translation
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
DATA RATE = 50kbps
1 CHANNEL
V
V
9
8
7
6
5
4
3
2
1
0
= 1.8V
= 3.3V
V
= 1.2V, V
= 1.8V
CCY
CCA
CCY
CCA
50Mbps
30Mbps
V
= 1.8V, V
= 3.3V, V
= 3.3V
= 5V
CCA
CCY
20Mbps
10Mbps
V
CCA
CCY
5Mbps
13
23
33
43
53
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 13. Rise Time vs. Capacitive Load at Pin Y
Figure 10. ICCA vs. Capacitive Load at Pin A for Y→A
(3.3 V→1.8 V) Level Translation
(A→Y Level Translation)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12
T
= 25
°
C
T
= 25°C
A
A
1 CHANNEL
V
V
1 CHANNEL
DATA RATE = 50kbps
50Mbps
= 3.3V
= 5V
CCA
CCY
V
= 1.2V, V
= 1.8V
CCY
CCA
10
8
30Mbps
20Mbps
V
= 1.8V, V
= 3.3V
CCY
CCA
6
4
V
= 3.3V, V
= 5V
CCY
CCA
10Mbps
5Mbps
2
0
13
13
23
33
43
53
63
73
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 14. Fall Time vs. Capacitive Load at Pin Y
Figure 11. ICCY vs. Capacitive Load at Pin Y for A→Y
(3.3 V→5 V) Level Translation
(A→Y Level Translation)
Rev. 0 | Page 9 of 20
ADG3301
10
12
10
8
DATA RATE = 50kbps
= 25°C
T
= 25°C
A
V
= 1.2V, V = 1.8V
CCY
T
CCA
A
1 CHANNEL
DATA RATE = 50kbps
9
8
7
6
5
4
3
2
1
0
1 CHANNEL
V
= 1.2V, V
= 1.8V
CCY
CCA
6
V
= 1.8V, V
= 3.3V
CCY
CCA
4
V
= 1.8V, V
= 3.3V
CCY
CCA
2
V
= 3.3V, V
63
= 5V
73
CCA
CCY
V
= 3.3V, V
CCY
= 5V
53
CCA
0
13
23
33
43
53
13
18
23
28
33
38
43
48
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 15. Rise Time vs. Capacitive Load at Pin A
Figure 18. Propagation Delay (tPHL) vs. Capacitive Load at Pin Y
(Y→A Level Translation)
(A→Y Level Translation)
9
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
DATA RATE = 50kbps
1 CHANNEL
DATA RATE = 50kbps
8
7
6
5
4
3
2
1
0
V
= 1.2V, V = 1.8V
CCY
CCA
V
= 1.2V, V
= 1.8V
CCY
CCA
V
= 1.8V, V
= 3.3V
CCY
CCA
V
V
= 1.8V, V
= 3.3V
CCY
= 3.3V, V
= 5V
CCY
CCA
CCA
V
= 3.3V, V
43
= 5V
CCA
CCY
13
18
23
28
33
38
48
53
13
18
23
28
33
38
43
48
53
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 19. Propagation Delay (tPLH) vs. Capacitive Load at Pin A
Figure 16. Fall Time vs. Capacitive Load at Pin A
(Y→A Level Translation)
(Y→A Level Translation)
9
14
12
10
8
T
= 25°C
A
T
= 25°C
A
1 CHANNEL
DATA RATE = 50kbps
1 CHANNEL
DATA RATE = 50kbps
8
7
6
5
4
3
2
1
0
V
= 1.2V, V
= 1.8V
CCY
CCA
V
= 1.2V, V
= 1.8V
CCY
CCA
6
V
= 1.8V, V
= 3.3V
CCY
CCA
V
= 1.8V, V
= 3.3V
CCA
CCY
4
V
= 3.3V, V
= 5V
CCY
CCA
V
= 3.3V, V
= 5V
CCY
CCA
2
0
13
18
23
28
33
38
43
48
53
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 20. Propagation Delay (tPHL) vs. Capacitive Load at Pin A
Figure 17. Propagation Delay (tPLH) vs. Capacitive Load at Pin Y
(Y→A Level Translation)
(A→Y Level Translation)
Rev. 0 | Page 10 of 20
ADG3301
T
= 25°C
A
T
= 25°C
A
DATA RATE = 25Mbps
= 50pF
DATA RATE = 50Mbps
C
1 CHANNEL
C
L
= 15pF
L
1 CHANNEL
400mV/DIV
5ns/DIV
400mV/DIV
3ns/DIV
Figure 21. Eye Diagram at Y Output
Figure 24. Eye Diagram at A Output
(1.2 V to 1.8 V Level Translation, 25 Mbps)
(3.3 V to 1.8 V Level Translation, 50 Mbps)
T
= 25°C
C
= 15pF
T = 25°C
A
DATA RATE = 50Mbps
CL = 50pF
A
L
DATA RATE = 25Mbps
1 CHANNEL
1 CHANNEL
1V/DIV
200mV/DIV
3ns/DIV
5ns/DIV
Figure 22. Eye Diagram at A Output
(1.8 V to 1.2 V Level Translation, 25 Mbps)
Figure 25. Eye Diagram at Y Output
(3.3 V to 5 V Level Translation, 50 Mbps)
T = 25°C
A
T
= 25°C
C
= 50pF
A
L
DATA RATE = 50Mbps
= 15pF
DATA RATE = 50Mbps 1 CHANNEL
C
L
1 CHANNEL
3ns/DIV
500mV/DIV
3ns/DIV
800mV/DIV
Figure 23. Eye Diagram at Y Output
Figure 26. Eye Diagram at A Output
(1.8 V to 3.3 V Level Translation, 50 Mbps)
(5 V to 3.3 V Level Translation, 50 Mbps)
Rev. 0 | Page 11 of 20
ADG3301
TEST CIRCUITS
EN
V
ADG3301
CCY
V
CCA
0.1µF
0.1µF
EN
V
Y
ADG3301
CCY
V
CCA
A
Y
0.1µF
0.1µF
K2
K1
K
A
GND
A
I
I
OL
OH
GND
Figure 30. Three-State Leakage Current at Pin Y
Figure 27. VOH/VOL Voltages at Pin A
EN
ADG3301
V
CCA
V
CCY
0.1µF
0.1µF
V
ADG3301
CCY
V
CCA
0.1µF
K2
A
Y
0.1µF
K1
Y
A
GND
EN
A
I
I
OH
OL
GND
K
Figure 28. VOH/VOL Voltages at Pin Y
Figure 31. EN Pin Leakage Current
EN
EN
V
ADG3301
CCY
V
ADG3301
CCY
V
CCA
V
CCA
0.1µF
0.1µF
A
Y
Y
A
A
K
CAPACITANCE
METER
GND
GND
Figure 29. Three-State Leakage Current at Pin A
Figure 32. Capacitance at Pin A
EN
V
Y
ADG3301
CCY
V
CCA
A
CAPACITANCE
METER
GND
Figure 33. Capacitance at Pin Y
Rev. 0 | Page 12 of 20
ADG3301
→
A
Y DIRECTION
V
V
CCA
CCY
ADG3301
+
+
0.1µF
10µF
0.1µF
10µF
1MΩ
A
Y
V
V
A
Y
K1
K2
50pF
1MΩ
SIGNAL SOURCE
EN
GND
R
50Ω
S
Z
= 50Ω
0
V
EN
R
T
50Ω
→
Y
A DIRECTION
V
V
CCA
CCY
ADG3301
+
+
0.1µF
10µF
0.1µF
10µF
1MΩ
A
Y
V
V
A
Y
K1
K2
15pF
1MΩ
SIGNAL SOURCE
EN
GND
R
50Ω
S
Z
= 50Ω
0
V
EN
R
T
50Ω
V
CCA
tEN1
V
EN
0V
V
/V
CCA CCY
V
/V
A
Y
A
0V
V
/V
CCY CCA
90%
V /V
Y
0V
V
CCA
tEN2
V
EN
0V
V
/V
Y
A
V
/V
CCA CCY
0V
V
/V
CCY CCA
V /V
Y
A
10%
0V
NOTE:
→
→
tEN IS THE LARGEST OF tEN1 AND tEN2 IN BOTH A Y AND Y A DIRECTIONS.
Figure 34. Enable Time
Rev. 0 | Page 13 of 20
ADG3301
V
CCY
EN
V
CCY
ADG3301
EN
+
ADG3301
V
+
CCA
+
0.1µF
10µF
V
CCA
0.1µF
10µF
SIGNAL
SOURCE
+
0.1µF
= 50Ω
10µF
SIGNAL
SOURCE
0.1µF
10µF
R
S
R
S
Z
0
V
V
Y
A
50Ω
A
Y
Z
= 50Ω
50Ω
0
Y
A
V
V
Y
A
R
50Ω
T
R
50Ω
50pF
T
15pF
GND
GND
V
V
A
V
V
Y
50%
90%
50%
90%
tP, A→Y
tP, A→Y
tP, Y→A
tP, Y→A
Y
A
50%
10%
50%
10%
tF, A→Y
tR, A→Y
tF, Y→A
tR, Y→A
Figure 35. Switching Characteristics (A→Y Level Translation)
Figure 36. Switching Characteristics (Y→A Level Translation)
Rev. 0 | Page 14 of 20
ADG3301
TERMINOLOGY
VIHA
tR, A→Y
Logic input high voltage at Pin A.
Rise time when translating logic levels in the A→Y direction.
VILA
tF, A→Y
Logic input low voltage at Pin A.
Fall time when translating logic levels in the A→Y direction.
VOHA
DMAX, A→Y
Logic output high voltage at Pin A.
Guaranteed data rate when translating logic levels in the A→Y
direction under the driving and loading conditions specified in
Table 1.
VOLA
Logic output low voltage at Pin A.
tPPSKEW, A→Y
CA
Difference in propagation delay between any one channel and
the same channel on a different part (under same
driving/loading conditions) when translating in the A→Y
direction.
Capacitance measured at Pin A (EN = 0).
ILA
,
HiZ
Leakage current at Pin A when EN = 0 (Pin A three-stated).
tP, Y → A
VIHY
Propagation delay when translating logic levels in the Y→A
direction.
Logic input high voltage at Pin Y.
VILY
tR, Y→A
Logic input low voltage at Pin Y.
Rise time when translating logic levels in the Y→A direction.
VOHY
tF, Y→A
Logic output high voltage at Pin Y.
Fall time when translating logic levels in the Y→ A direction.
VOLY
DMAX, Y→A
Logic output low voltage at Pin Y.
Guaranteed data rate when translating logic levels in the Y→A
direction under the driving and loading conditions specified in
Table 1.
CY
Capacitance measured at Pin Y (EN = 0).
ILY, HiZ
tPPSKEW, Y→A
Leakage current at pin and when EN = 0 (Pin A three-stated).
Difference in propagation delay between any one channel and
the same channel on a different part (under the same driving/
loading conditions) when translating in the Y→A direction.
VIHEN
Logic input high voltage at the EN pin.
ICCA
VILEN
VCCA supply current.
Logic input low voltage at the EN pin.
ICCY
CEN
VCCY supply current.
Capacitance measured at EN pin.
IHiZA
ILEN
VCCA supply current during three-state mode (EN = 0).
Enable (EN) pin leakage current.
IHiZY
tEN
VCCY supply current during three-state mode (EN = 0).
Three-state enable time for Pin A and Pin Y.
tP, A → Y
Propagation delay when translating logic levels in the A→Y
direction.
Rev. 0 | Page 15 of 20
ADG3301
THEORY OF OPERATION
The ADG3301 level translator allows the level shifting
INPUT DRIVING REQUIREMENTS
necessary for data transfer in a system where multiple supply
voltages are used. The device requires two supplies, VCCA and
VCCY (VCCA ≤ VCCY). These supplies set the logic levels on each
side of the device. When driving the A pin, the device translates
the VCCA-compatible logic levels to VCCY-compatible logic levels
available at the Y pin. Similarly, because the device is capable of
bidirectional translation, when driving the Y pin the VCCY-com-
patible logic levels are translated to VCCA-compatible logic levels
available at the A pin. When EN = 0, the A pin and the Y pin
are three-stated. When EN is driven high, the ADG3301 goes
into normal operation mode and performs level translation.
To ensure correct operation of the ADG3301, the circuit that
drives the input of an ADG3301 channel must have an output
impedance of less than or equal to 150 Ω and a minimum peak
current driving capability of 36 mA.
OUTPUT LOAD REQUIREMENTS
The ADG3301 level translator is designed to drive CMOS-
compatible loads. If current driving capability is required, it is
recommended to use buffers between the ADG3301 outputs
and the load.
ENABLE OPERATION
LEVEL TRANSLATOR ARCHITECTURE
The ADG3301 provides three-state operation at the A I/O pin
and Y I/O pin by using the enable (EN) pin as shown in Table 4.
The ADG3301 consists of a single bidirectional channel that can
translate logic levels in either the A→Y or the Y→A direction.
It uses a one-shot accelerator architecture that ensures excellent
switching characteristics. Figure 37 shows a simplified block
diagram of the ADG3301 level translator.
Table 4. Truth Table
EN
Y I/O Pin
A I/O Pin
0
1
Hi-Z1
Hi-Z1
Normal operation2
Normal operation2
V
V
CCY
CCA
1 High impedance state.
2 In normal operation, the ADG3301 performs level translation.
T1
T2
While EN = 0, the ADG3301 enters into tri-state mode. In this
mode, the current consumption from both the VCCA and VCCY
supplies is reduced, allowing the user to save power, which is
critical especially on battery-operated systems. The EN input pin
can be driven with either VCCA- or VCCY-compatible logic levels.
6kΩ
U1
U2
P
Y
A
ONE-SHOT GENERATOR
N
POWER SUPPLIES
For proper operation of the ADG3301, the voltage applied to
the VCCA must be always less than or equal to the voltage applied
to VCCY. To meet this condition, the recommended power-up
sequence is VCCY first and then VCCA. The ADG3301 operates
properly only after both supply voltages reach their nominal
values. It is not recommended to use the part in a system where,
during power-up, VCCA may be greater than VCCY due to a
significant increase in the current taken from the VCCA supply
For optimum performance, the VCCA and VCCY pins should be
decoupled to GND, and placed as close as possible to the device.
U4
U3
6kΩ
T4
T3
Figure 37. Simplified Block Diagram of an ADG3301 Channel
The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), while the
translation in the Y→A direction is performed using the
inverters U3 and U4. The one-shot generator detects a rising
or falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS transis-
tors (T1 and T2) for a rising edge, or the NMOS transistors
(T3 and T4) for a falling edge. This charges/discharges the
capacitive load faster, which results in fast rise and fall times.
Rev. 0 | Page 16 of 20
ADG3301
power dissipation (the junction temperature does not exceed
the value specified under the Absolute Maximum Ratings
section).
DATA RATE
The maximum data rate at which the device is guaranteed to
operate is a function of the VCCA and VCCY supply voltage combi-
nation and the load capacitance. It represents the maximum
frequency of a square wave that can be applied to the I/O pins,
which ensures that the device operates within the datasheet
specifications in terms of output voltage (VOL and VOH) and
Table 5 shows the guaranteed data rates at which the ADG3301
can operate in both directions (A→Y or Y→A level translation)
for various VCCA and VCCY supply combinations.
Table 5. Guaranteed Data Rate (Mbps)1
VCCY
1.8 V
(1.65 V to 1.95 V)
2.5 V
(2.3 V to 2.7 V)
3.3 V
(3.0 V to 3.6 V)
5 V
VCCA
(4.5 V to 5.5 V)
1.2 V (1.15 V to 1.3 V)
1.8 V (1.65 V to 1.95 V)
2.5 V (2.3 V to 2.7 V)
3.3 V (3.0 V to 3.6 V)
5 V (4.5 V to 5.5 V)
25
–
–
–
–
30
45
–
–
–
40
50
60
–
40
50
50
50
–
–
1 The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction.
Rev. 0 | Page 17 of 20
ADG3301
APPLICATIONS
The ADG3301 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the
A pin, and the higher voltage logic signals are connected to the
Y pin. The ADG3301 can provide level translation in both
directions from A→Y or Y→A, eliminating the need for a level
translator IC for each direction. The internal architecture allows
the ADG3301 to perform bidirectional level translation without
an additional signal to set the direction in which the translation
is made. This simplifies the design by eliminating the timing
requirements for the direction signal and reduces the number of
ICs used for level translation.
LAYOUT GUIDELINES
As with any high speed digital IC, the printed circuit board
layout is important for the overall performance of the circuit.
Care should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each VCC pin (VCCA and
VCCY) should be bypassed using low effective series resistance
(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the VCCA and VCCY pins. The parasitic induc-
tance of the high-speed signal track might cause significant
overshoot. This effect can be reduced by keeping the length of
the tracks as short as possible. A solid copper plane for the
return path (GND) is also recommended.
Figure 38 shows an application where a 1.8 V microprocessor
transfers data to or from a 3.3 V peripheral device using the
ADG3301 level translator.
100nF
100nF
1
2
3
V
V
6
5
4
CCA
CCY
1.8V
3.3V
ADG3301
A
Y
I/O
I/O
H
L
MICROPROCESSOR/
MICROCONTROLLER/
DSP
PERIPHERAL
DEVICE
GND
EN
GND
GND
Figure 38 1.8 V to 3.3 V Level Translation Circuit
Rev. 0 | Page 18 of 20
ADG3301
OUTLINE DIMENSIONS
2.20
2.00
1.80
2.40
2.10
1.80
6
1
5
2
4
3
1.35
1.25
1.15
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
0.40
0.10
1.10
0.80
0.30
0.10
0.30
0.15
0.22
0.08
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 39. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG3301BKSZ-REEL2
ADG3301BKSZ-REEL72
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Branding1 Package Option
6-Lead Thin Shrink Small Outline Transistor Package
6-Lead Thin Shrink Small Outline Transistor Package
S0H
S0H
KS-6
KS-6
1 Branding on this package is limited to three characters due to space constraints.
2 Z = Pb-free part.
Rev. 0 | Page 19 of 20
ADG3301
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05517-0-12/05(0)
Rev. 0 | Page 20 of 20
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