ADG3300BRUZ-REEL7 [ADI]
Low Voltage 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator; 低电压1.15 V至5.5 V ， 8通道双向逻辑电平转换器
| 型号： | ADG3300BRUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Voltage 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator |
| 文件： | 总20页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage 1.15 V to 5.5 V, 8-Channel
Bidirectional Logic Level Translator
ADG3300
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Bidirectional level translation
Operates from 1.15 V to 5.5 V
Low quiescent current <1 µA
No direction pin
V
V
CCY
CCA
A1
A2
A3
A4
A5
A6
A7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
APPLICATIONS
Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communications devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
A8
EN
Portable POS systems
GND
Low cost serial interfaces
Figure 1.
GENERAL DESCRIPTION
internally pulled down by 6 kΩ resistors, while the Y terminals
are in the high impedance state. The EN pin is referred to VCCA
supply voltage and driven high for normal operation.
The ADG3300 is a bidirectional logic level translator that con-
tains eight bidirectional channels. It can be used in multivoltage
digital system applications such as data transfer between a low
voltage DSP/controller and a higher voltage device. The internal
architecture allows the device to perform bidirectional logic
level translation without an additional signal to set the direction
of the translation.
The ADG3300 is available in a compact 20-lead TSSOP package,
and it is guaranteed to operate over the 1.15 V to 5.5 V supply
voltage range and extended −40°C to +85°C temperature range.
The voltage applied to VCCA sets the logic levels on the A side of
the device, while VCCY sets the levels on the Y side. For proper
operation, VCCA must always be less than VCCY. The VCCA-com-
patible logic signals applied to the A side of the device appear as
VCCY-compatible levels on the Y side. Similarly, VCCY-compatible
PRODUCT HIGHLIGHTS
1. Bidirectional level translation.
2. Fully guaranteed over the 1.15 V to 5.5 V supply range.
3. No direction pin.
logic levels applied to the Y side of the device appear as VCCA
compatible logic levels on the A side.
-
4. 20-lead TSSOP package.
The enable pin provides three-state operation of the Y side pins.
When the enable pin (EN) is pulled low, the A1 to A8 pins are
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADG3300
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 12
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Level Translator Architecture.................................................... 15
Input Driving Requirements..................................................... 15
Output Load Requirements ...................................................... 15
Enable Operation ....................................................................... 15
Power Supplies............................................................................ 15
Data Rate ..................................................................................... 16
Applications..................................................................................... 17
Layout Guidelines....................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
4/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG3300
SPECIFICATIONS1
VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ2
Max Unit
LOGIC INPUTS/OUTPUTS
A Side
Input High Voltage3
VIHA
VIHA
VILA
VOHA
VOLA
RA,HiZ
VCCA = 1.15 V
VCCA = 1.2 V to 5.5 V
VCCA − 0.3
VCCA − 0.4
V
V
V
V
V
Input Low Voltage3
Output High Voltage
Output Low Voltage
Three-State Pull-Down Resistance
Y Side
Input Low Voltage3
Input High Voltage3
Output High Voltage
Output Low Voltage
Capacitance3
0.4
VY = VCCY, IOH = 20 µA, Figure 27
VY = 0 V, IOL = 20 µA, Figure 27
EN = 0
VCCA − 0.4
4.2
0.4
8.4
6
6
kΩ
VIHY
VILY
VOHY
VOLY
CY
VCCY − 0.4
VCCY − 0.4
V
V
V
V
pF
µA
0.4
0.4
1
VA = VCCA, IOH = 20 µA, Figure 28
VA = 0 V, IOL = 20 µA, Figure 28
f = 1 MHz, EN = 0, Figure 31
VY = 0 V/VCCY, EN = 0, Figure 29
Leakage Current
ILY, HiZ
Enable (EN)
Input High Voltage3
VIHEN
VIHEN
VILEN
ILEN
VCCA = 1.15 V
VCCA = 1.2 V to 5.5 V
VCCA − 0.3
VCCA − 0.4
V
V
V
Input Low Voltage3
Leakage Current
Capacitance3
0.4
1
VEN = 0 V/VCCA, VA = 0 V, Figure 30
µA
pF
µs
CEN
tEN
3
1
Enable Time3
1.8
RS = RT = 50 Ω, VA = 0 V/VCCA (A Y),
Figure 32
SWITCHING CHARACTERISTICS3
3.3 V 0.3 V ꢀ VCCA ꢀ VCCY, VCCY = 5 V 0.5 V
A Y Level Translation
Propagation Delay
Rise Time
RS = RT = 50 Ω, CL = 50 pF, Figure 33
tP, A-Y
tR, A-Y
tF, A-Y
6
2
2
10
3.5
3.5
ns
ns
ns
Fall Time
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
DMAX, A-Y
tSKEW, A-Y
tPPSKEW, A-Y
50
50
Mbps
ns
ns
2
4
3
RS = RT = 50 Ω, CL = 15 pF, Figure 34
Y A Level Translation
Propagation Delay
Rise Time
tP, Y-A
tR, Y-A
4
1
7
3
ns
ns
Fall Time
tF, Y-A
3
7
ns
Mbps
ns
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
DMAX, Y-A
tSKEW, Y-A
tPPSKEW, Y-A
2
3.5
2
ns
1.8 V 0.15 V ꢀ VCCA ꢀ VCCY, VCCY = 3.3 V 0.3 V
A Y Translation
RS = RT = 50 Ω, CL = 50 pF, Figure 33
Propagation Delay
Rise Time
Fall Time
tP, A-Y
tR, A-Y
tF, A-Y
8
2
2
11
5
5
ns
ns
ns
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
DMAX, A-Y
tSKEW, A-Y
tPPSKEW, A-Y
50
Mbps
ns
ns
2
4
4
Rev. 0 | Page 3 of 20
ADG3300
Parameter
Symbol
Conditions
Min
Typ2
Max Unit
RS = RT = 50 Ω, CL = 15 pF, Figure 34
Y A Translation
Propagation Delay
Rise Time
Fall Time
tP, Y-A
tR, Y-A
tF, Y-A
5
2
2
8
3.5
3.5
ns
ns
ns
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
1.15 V to 1.3 V ꢀ VCCA ꢀ VCCY, VCCY = 3.3 V 0.3 V
A Y Translation
DMAX, Y-A
tSKEW, Y-A
tPPSKEW, Y-A
50
Mbps
ns
ns
2
3
3
RS = RT = 50 Ω, CL = 50 pF, Figure 33
Propagation Delay
Rise Time
Fall Time
tP, A-Y
tR, A-Y
tF, A-Y
9
3
2
18
5
5
ns
ns
ns
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
Y A Translation
DMAX, A-Y
tSKEW, A-Y
tPPSKEW, A-Y
40
40
Mbps
ns
ns
2
5
10
RS = RT = 50 Ω, CL = 15 pF, Figure 34
Propagation Delay
Rise Time
Fall Time
tP, Y-A
tR, Y-A
tF, Y-A
DMAX, Y-A
tSKEW, Y-A
tPPSKEW, Y-A
5
2
2
9
4
4
ns
ns
ns
Mbps
ns
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
1.15 V to 1.3 Vꢀ VCCA ꢀ VCCY, VCCY = 1.8 V 0.3 V
A Y Translation
2
4
4
ns
RS = RT = 50 Ω, CL = 50 pF, Figure 33
Propagation Delay
Rise Time
Fall Time
tP, A-Y
tR, A-Y
tF, A-Y
12
7
3
25
12
5
ns
ns
ns
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
Y A Translation
DMAX, A-Y
tSKEW, A-Y
tPPSKEW, A-Y
25
25
Mbps
ns
ns
2
5
15
RS = RT = 50 Ω, CL = 15 pF, Figure 34
Propagation Delay
Rise Time
Fall Time
tP, Y-A
tR, Y-A
tF, Y-A
DMAX, Y-A
tSKEW, Y-A
tPPSKEW, Y-A
14
5
2.5
35
16
6.5
ns
ns
ns
Mbps
ns
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
2.5 V 0.2 V ꢀ VCCA ꢀ VCCY, VCCY = 3.3 V 0.3 V
A Y Translation
3
6.5
23.5 ns
RS = RT = 50 Ω, CL = 50 pF, Figure 33
Propagation Delay
Rise Time
Fall Time
tP, A-Y
tR, A-Y
tF, A-Y
7
2.5
2
10
4
5
ns
ns
ns
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
Y A Translation
DMAX, A-Y
tSKEW, A-Y
tPPSKEW, A-Y
60
60
Mbps
ns
ns
1.5
2
4
RS = RT = 50 Ω, CL = 15 pF, Figure 34
Propagation Delay
Rise Time
Fall Time
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
tP, Y-A
tR, Y-A
tF, Y-A
DMAX, Y-A
tSKEW, Y-A
tPPSKEW, Y-A
5
1
3
8
4
5
ns
ns
ns
Mbps
ns
2
3
3
ns
Rev. 0 | Page 4 of 20
ADG3300
Parameter
Symbol
Conditions
Min
Typ2
Max Unit
POWER REQUIREMENTS
Power Supply Voltages
VCCA
VCCY
ICCA
VCCA ꢀ VCCY
1.15
1.65
5.5
5.5
5
V
V
µA
Quiescent Power Supply Current
VA = 0 V/VCCA, VY = 0 V/VCCY
VCCA = VCCY = 5.5 V, EN = 1
VA = 0 V/VCCA, VY = 0 V/VCCY
,
,
0.17
0.27
ICCY
5
µA
V
CCA = VCCY = 5.5 V, EN = 1
Three-State Mode Power Supply Current
IHiZA
IHiZY
VCCA = VCCY = 5.5 V, EN = 0
VCCA = VCCY = 5.5 V, EN = 0
0.1
0.1
5
5
µA
µA
1 Temperature range is a follows: B version: −40°C to +85°C.
2 All typical values are at TA = 25°C, unless otherwise noted.
3 Guaranteed by design; not subject to production test.
Rev. 0 | Page 5 of 20
ADG3300
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
Rating
VCCA to GND
VCCY to GND
Digtal Inputs (A)
Digtal Inputs (Y)
−0.3 V to +7 V
VCCA to +7 V
−0.3 V to (VCCA + 0.3 V)
−0.3 V to (VCCY + 0.3 V)
−0.3 V to +7 V
EN to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance (4-Layer Board)
20-Lead TSSOP
−40°C to +85°C
−65°C to +150°C
150°C
78°C/W
300°C
260°C
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 20
ADG3300
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
20
19
18
17
16
15
14
13
12
11
A1
Y1
V
V
CCY
CCA
3
A2
Y2
ADG3300
TOP VIEW
(Not to Scale)
4
A3
A4
A5
A6
A7
A8
EN
Y3
5
Y4
6
Y5
7
Y6
8
Y7
9
Y8
10
GND
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin. No.
Mnemonic Description
1
2
3
4
5
6
7
8
A1
VCCA
A2
A3
A4
A5
A6
A7
A8
EN
GND
Y8
Y7
Y6
Y5
Y4
Y3
Y2
VCCY
Y1
Input/Output A1. Referenced to VCCA
Power Supply Voltage Input for the A1 to A8 I/O pins (1.15 V ꢀ VCCA < VCCY).
.
Input/Output A2. Referenced to VCCA
Input/Output A3. Referenced to VCCA
Input/Output A4. Referenced to VCCA
Input/Output A5. Referenced to VCCA
Input/Output A6. Referenced to VCCA
Input/Output A7. Referenced to VCCA
Input/Output A8. Referenced to VCCA
Active High Enable Input.
.
.
.
.
.
.
.
9
10
11
12
13
14
15
16
17
18
19
20
Ground.
Input/Output Y8. Referenced to VCCY
Input/Output Y7. Referenced to VCCY
Input/Output Y6. Referenced to VCCY
Input/Output Y5. Referenced to VCCY
Input/Output Y4. Referenced to VCCY
Input/Output Y3. Referenced to VCCY
Input/Output Y2. Referenced to VCCY
.
.
.
.
.
.
.
Power Supply Voltage Input for the Y1 to Y8 I/O pins (1.65 V ꢀ VCCY ꢀ 5.5 V).
Input/Output Y1. Referenced to VCCY
.
Rev. 0 | Page 7 of 20
ADG3300
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
T = 25°C
A
1 CHANNEL
T
= 25°C
A
1 CHANNEL
C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
C
L
= 15pF
= 50pF
L
V
= 3.3V, V
= 5V
CCY
CCA
V
= 3.3V, V
= 5V
CCY
CCA
V
= 1.8V, V
= 3.3V
CCY
CCA
V
= 1.8V, V
= 3.3V
CCA
CCY
40
V
= 1.2V, V
= 1.8V
CCA
25
DATA RATE (Mbps)
CCY
V
= 1.2V, V
= 1.8V
40
CCA
CCY
35
0
5
10
15
20
30
35
45
50
0
5
10
15
20
25
30
45
50
DATA RATE (Mbps)
Figure 6. ICCY vs. Data Rate (Y A Level Translation)
Figure 3. ICCA vs. Data Rate (A Y Level Translation)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
V
V
1 CHANNEL
C
9
8
7
6
5
4
3
2
1
0
= 1.2V
= 1.8V
= 50pF
CCA
CCY
L
20Mbps
V
= 3.3V, V
= 5V
CCY
CCA
10Mbps
5Mbps
V
= 1.8V, V
= 3.3V
CCY
CCA
V
= 1.2V, V
CCY
= 1.8V
CCA
1Mbps
53
13
23
33
43
63
73
0
5
10
15
20
25
30
35
40
45
50
CAPACITIVE LOAD (pF)
DATA RATE (Mbps)
Figure 7. ICCY vs. Capacitive Load at Pin Y for A Y (1.2 V 1.8 V)
Level Translation
Figure 4. ICCY vs. Data Rate (A Y Level Translation)
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
T
= 25°C
A
T
= 25°C
A
1 CHANNEL
= 15pF
1 CHANNEL
V
V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
C
L
= 1.2V
=1.8V
CCA
CCY
V
= 3.3V, V
= 5V
CCY
CCA
20Mbps
V
= 1.8V, V
= 3.3V
CCA
CCY
40
10Mbps
5Mbps
V
= 1.2V, V
= 1.8V
CCA
CCY
1Mbps
0
5
10
15
20
25
30
35
45
50
13
23
33
CAPACITIVE LOAD (pF)
43
53
DATA RATE (Mbps)
Figure 8. ICCA vs. Capacitive Load at Pin A for Y A (1.8 V 1.2 V)
Level Translation
Figure 5. ICCA vs. Data Rate (Y A Level Translation)
Rev. 0 | Page 8 of 20
ADG3300
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
V
V
1 CHANNEL
V
V
= 1.8V
= 3.3V
= 3.3V
= 5V
CCA
CCY
CCA
CCY
50Mbps
50Mbps
30Mbps
20Mbps
30Mbps
20Mbps
10Mbps
5Mbps
10Mbps
5Mbps
63
13
23
33
43
53
73
13
23
33
43
53
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 9. ICCY vs. Capacitive Load at Pin Y for A Y (1.8 V 3.3 V)
Level Translation
Figure 12. ICCA vs. Capacitive Load at Pin A for Y A (5 V 3.3 V)
Level Translation
5.0
10
9
8
7
6
5
4
3
2
1
0
T
= 25°C
T = 25°C
A
1 CHANNEL
DATA RATE = 50kbps
A
1 CHANNEL
V
V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= 1.8V
= 3.3V
V
= 1.2V, V
= 1.8V
CCY
CCA
CCY
CCA
50Mbps
30Mbps
V
= 1.8V, V
= 3.3V, V
= 3.3V
= 5V
CCA
CCY
20Mbps
10Mbps
V
CCA
CCY
5Mbps
13
23
33
43
53
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 10. ICCA vs. Capacitive Load at Pin A for Y A (3.3 V 1.8 V)
Level Translation
Figure 13. Rise Time vs. Capacitive Load at Pin Y (A Y Level Translation)
12
4.0
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
V
V
1 CHANNEL
DATA RATE = 50kbps
50Mbps
= 3.3V
= 5V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
CCA
CCY
10
8
V
= 1.2V, V
= 1.8V
CCY
CCA
30Mbps
20Mbps
V
= 1.8V, V
= 3.3V
CCY
CCA
6
4
V
= 3.3V, V
= 5V
CCY
CCA
10Mbps
5Mbps
2
0
13
23
33
43
53
63
73
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 14. Fall Time vs. Capacitive Load at Pin Y (A Y Level Translation)
Figure 11. ICCY vs. Capacitive Load at Pin Y for A Y (3.3 V 5 V)
Level Translation
Rev. 0 | Page 9 of 20
ADG3300
10
12
10
8
DATA RATE = 50kbps
T
= 25°C
A
V
= 1.2V, V
= 1.8V
CCY
A
T
= 25°C
CCA
1 CHANNEL
DATA RATE = 50kbps
9
8
7
6
5
4
3
2
1
0
1 CHANNEL
V
= 1.2V, V
= 1.8V
CCA
CCY
6
V
= 1.8V, V
= 3.3V
CCA
CCY
4
V
= 1.8V, V
= 3.3V
CCA
CCY
2
V
= 3.3V, V
63
= 5V
73
CCA
CCY
V
= 3.3V, V
= 5V
CCY
CCA
0
13
23
33
43
53
13
18
23
28
33
38
43
48
53
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 18. Propagation Delay (tPHL) vs.
Figure 15. Rise Time vs. Capacitive Load at Pin A (Y A Level Translation)
Capacitive Load at Pin Y (A Y Level Translation)
9
8
7
6
5
4
3
2
1
0
4.0
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
DATA RATE = 50kbps
1 CHANNEL
DATA RATE = 50kbps
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 1.2V, V = 1.8V
CCY
CCA
V
= 1.2V, V
= 1.8V
CCA
CCY
V
= 1.8V, V
= 3.3V
= 5V
CCA
V
CCY
V
= 1.8V, V = 3.3V
CCY
= 3.3V, V
CCA
CCA
CCY
V
= 3.3V, V
43
= 5V
CCA
CCY
13
18
23
28
33
38
48
53
13
18
23
28
33
38
43
48
53
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 19. Propagation Delay (tPLH) vs.
Capacitive Load at Pin A (Y A Level Translation)
Figure 16. Fall Time vs. Capacitive Load at Pin A (Y A Level Translation)
9
8
7
6
5
4
3
2
1
0
14
T
= 25°C
A
T
= 25°C
A
1 CHANNEL
DATA RATE = 50kbps
1 CHANNEL
DATA RATE = 50kbps
12
10
8
V
= 1.2V, V
= 1.8V
CCY
CCA
V
= 1.2V, V = 1.8V
CCY
CCA
6
V
= 1.8V, V = 3.3V
CCY
CCA
V
= 1.8V, V
= 3.3V
CCA
CCY
4
V
= 3.3V, V
= 5V
CCA
CCY
V
= 3.3V, V = 5V
CCY
CCA
2
0
13
18
23
28
33
38
43
48
53
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 20. Propagation Delay(tPHL) vs.
Capacitive Load at Pin A (Y A Level Translation)
Figure 17. Propagation Delay (tPLH) vs.
Capacitive Load at Pin Y (A Y Level Translation)
Rev. 0 | Page 10 of 20
ADG3300
T
= 25°C
C
= 50pF
T
= 25°C
A
L
A
DATA RATE = 25Mbps
1 CHANNEL
DATA RATE = 50Mbps
C
= 15pF
L
1 CHANNEL
400mV/DIV
3ns/DIV
200mV/DIV
5ns/DIV
Figure 21. Eye Diagram at Y Output (1.2 V to 1.8 V Level Translation, 25 Mbps)
Figure 24. Eye Diagram at A Output (3.3 V to 1.8 V Level Translation, 50 Mbps)
T
= 25°C
T
= 25°C
A
A
DATA RATE = 25Mbps
C
1 CHANNEL
DATA RATE = 50Mbps
CL = 50pF
1 CHANNEL
= 50pF
L
400mV/DIV
5ns/DIV
1V/DIV
3ns/DIV
Figure 22. Eye Diagram at A Output (1.8 V to 1.2 V Level Translation, 25 Mbps)
Figure 25. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 50 Mbps)
T
= 25°C
T
= 25°C
C = 50pF
L
A
A
DATA RATE = 50Mbps
= 15pF
DATA RATE = 50Mbps 1 CHANNEL
C
L
1 CHANNEL
500mV/DIV
3ns/DIV
3ns/DIV
800mV/DIV
Figure 23. Eye Diagram at Y Output (1.8 V to 3.3 V Level Translation, 50 Mbps)
Figure 26. Eye Diagram at A Output (5 V to 3.3 V Level Translation, 50 Mbps)
Rev. 0 | Page 11 of 20
ADG3300
TEST CIRCUITS
EN
V
ADG3300
CCY
V
CCA
0.1µF
0.1µF
V
Y
ADG3300
CCY
V
CCA
A
Y
0.1µF
0.1µF
K2
K1
A
GND
EN
A
I
I
OL
OH
GND
K
Figure 27. VOH/VOL Voltages at Pin A
Figure 30. EN Pin Leakage Current
EN
ADG3300
EN
V
ADG3300
CCY
V
CCA
V
CCY
V
CCA
0.1µF
0.1µF
K2
A
Y
A
Y
K1
CAPACITANCE
METER
GND
GND
I
I
OH
OL
Figure 31.Capacitance at Pin Y
Figure 28. VOH/VOL Voltages at Pin Y
EN
V
ADG3300
CCY
V
CCA
0.1µF
0.1µF
K
A
Y
A
GND
Figure 29. Three-State Leakage Current at Pin Y
Rev. 0 | Page 12 of 20
ADG3300
V
V
CCA
CCY
ADG3300
+
+
0.1µF
10µF
0.1µF
10µF
1MΩ
A
Y
V
V
A
Y
K1
K2
50pF
1MΩ
SIGNAL SOURCE
EN
GND
Z
= 50Ω
R
0
V
S
EN
50Ω
R
T
50Ω
V
CCA
tEN1
V
EN
0V
V
CCA
V
A
0V
V
CCY
90%
V
Y
0V
V
CCA
tEN2
V
EN
0V
V
A
V
CCA
0V
V
CCY
V
Y
10%
0V
NOTES
1. tEN IS WHICHEVER IS LARGER BETWEEN tEN1 AND tEN2
.
Figure 32. Enable Time
V
CCY
EN
V
CCY
ADG3300
EN
+
ADG3300
V
+
CCA
+
0.1µF
10µF
V
CCA
0.1µF
10µF
SIGNAL
SOURCE
+
0.1µF
= 50Ω
10µF
SIGNAL
SOURCE
0.1µF
10µF
Z
R
S
0
V
V
Y
A
A
Y
Z = 50Ω
0
R
Y
S
A
V
R
V
Y
A
R
50Ω
T
50Ω
50pF
T
50Ω
15pF
50Ω
GND
GND
V
A
V
Y
50%
50%
90%
tP,A-Y
tP,A-Y
tP,Y-A
tP,Y-A
V
A
V
Y
90%
50%
10%
50%
10%
tF,Y-A
tR,Y-A
tF,A-Y
tR,A-Y
Figure 34. Switching Characteristics (Y A Level Translation)
Figure 33. Switching Characteristics (A Y Level Translation)
Rev. 0 | Page 13 of 20
ADG3300
TERMINOLOGY
Table 4.
Symbol
VIHA
Description
Logic input high voltage at Pins A1 to A8.
Logic input low voltage at Pins A1 to A8.
VILA
VOHA
VOLA
RA,HiZ
VIHY
Logic output high voltage at Pins A1 to A8.
Logic output low voltage at Pins A1 to A8.
Pull-down resistance measured at Pins A1 to A8 when EN = 0.
Logic input high voltage at Pins Y1 to Y8.
VILY
Logic input low voltage at Pins Y1 to Y8.
VOHY
VOLY
CY
ILY, HiZ
VIHEN
VILEN
CEN
Logic output high voltage at Pins Y1 to Y8.
Logic output low voltage at Pins Y1 to Y8.
Capacitance measured at Pins Y1 to Y8 (EN = 0).
Leakage current at Pins Y1 to Y8 when EN = 0 (high impedance state at Pins Y1 to Y8).
Logic input high voltage at the EN pin.
Logic input low voltage at the EN pin.
Capacitance measured at EN pin.
ILEN
Enable (EN) pin leakage curent.
tEN
Three-state enable time for Pins Y1 to Y8.
Propagation delay when translating logic levels in the A Y direction.
Rise time when translating logic levels in the A Y direction.
Fall time when translating logic levels in the A Y direction.
tP, A-Y
tR, A-Y
tF, A-Y
DMAX, A-Y
Guaranteed data rate when translating logic levels in the A Y direction under the driving and loading conditions
specified in Table 1.
tSKEW, A-Y
Difference between propagation delays on any two channels when translating logic levels in the A Y direction.
tPPSKEW, A-Y
Difference in propagation delay between any one channel and the same channel on a different part (under the
same driving/loading conditions) when translating logic levels in the A Y direction.
tP, Y-A
Propagation delay when translating logic levels in the Y A direction.
Rise time when translating logic levels in the Y A direction.
Fall time when translating logic levels in the Y A direction.
tR, Y-A
tF, Y-A
DMAX, Y-A
Guaranteed data rate when translating logic levels in the Y A direction under the driving and loading conditions
specified in Table 1.
tSKEW, Y-A
Difference between propagation delays on any two channels when translating logic levels in the Y A direction.
tPPSKEW, Y-A
Difference in propagation delay between any one channel and the same channel on a different part (under the
same driving/loading conditions) when translating in the Y A direction.
VCCA
VCCY
ICCA
VCCA supply voltage.
VCCY supply voltage.
VCCA supply current.
ICCY
VCCY supply current.
IHiZA
IHiZY
VCCA supply current during three-state mode (EN = 0).
VCCY supply current during three-state mode (EN = 0).
Rev. 0 | Page 14 of 20
ADG3300
THEORY OF OPERATION
The ADG3300 level translator allows the level shifting necessary
for data transfer in a system where multiple supply voltages are
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3300, the circuit that
drives the input of an ADG3300 channels should have an output
impedance of less than or equal to 150 Ω and a minimum
current driving capability of 36 mA.
used. The device requires two supplies, VCCA and VCCY (VCCA
VCCY). These supplies set the logic levels on each side of the
device. When driving the A pins, the device translates the VCCA
≤
-
compatible logic levels to VCCY-compatible logic levels available
at the Y pins. Similarly, since the device is capable of bidirectional
translation, when driving the Y pins, the VCCY-compatible logic
levels are translated to VCCA-compatible logic levels available at
the A pins. When EN = 0, the A1 to A8 are internally pulled
down with 6 kΩ resistors while Y1 to Y8 pins are three-stated.
When EN is driven high, the ADG3300 goes into normal
operation mode and performs level translation.
OUTPUT LOAD REQUIREMENTS
The ADG3300 level translator is designed to drive CMOS-
compatible loads. If current driving capability is required, it is
recommended to use buffers between the ADG3300 outputs
and the load.
ENABLE OPERATION
The ADG3300 provides three-state operation at the Y I/O pins
by using the enable (EN) pin as shown in Table 5.
LEVEL TRANSLATOR ARCHITECTURE
The ADG3300 consists of eight bidirectional channels. Each
channel can translate logic levels in either the A Y or the Y A
direction. It uses a one-shot accelerator architecture, which
ensures excellent switching characteristics. Figure 35 shows a
simplified block diagram of a bidirectional channel.
Table 5. Truth Table
EN
Y I/O Pins
A I/O Pins
0
1
Hi-Z1
6 kΩ pull-down to GND
Normal operation2
Normal operation2
1 High impedance state.
V
V
CCY
2 In normal operation, the ADG3300 performs level translation.
CCA
T1
T2
When EN = 0, the ADG3300 enters into three-state mode. In
this mode the current consumption from both the VCCA and
VCCY supplies is reduced, allowing the user to save power, which
is critical, especially for battery-operated systems. The EN input
pin can be driven with either VCCA- or VCCY-compatible logic
levels.
6kΩ
U1
U2
P
Y
A
ONE-SHOT GENERATOR
N
POWER SUPPLIES
For proper operation of the ADG3300, the voltage applied to
the VCCA must always be less than or equal to the voltage applied
to VCCY. To meet this condition, the recommended power-up
sequence is VCCY first and then VCCA. The ADG3300 operates
properly only after both supply voltages reach their nominal
values. It is not recommended to use the part in a system where
VCCA might be greater than VCCY during power-up due to a sig-
nificant increase in the current taken from the VCCA supply. For
optimum performance, the VCCA and VCCY pins should be
decoupled to GND as close as possible to the device.
U4
U3
6kΩ
T4
T3
Figure 35. Simplified Block Diagram of an ADG3300 Channel
The logic level translation in the A Y direction is performed
using a level translator (U1) and an inverter (U2), and the
translation in the Y A direction is performed using the inverters
U3 and U4. The one-shot generator detects a rising or falling
edge present on either the A side or the Y side of the channel. It
sends a short pulse that turns on the PMOS transistors (T1–T2)
for a rising edge, or the NMOS transistors (T3–T4) for a falling
edge. This charges/discharges the capacitive load faster, which
results in fast rise and fall times.
The inputs of the unused channels (A or Y) should be tied to
their corresponding VCC rail (VCCA or VCCY) or to GND.
Rev. 0 | Page 15 of 20
ADG3300
DATA RATE
The maximum data rate at which the device is guaranteed
to operate is a function of the VCCA and VCCY supply voltage
combination and the load capacitance. It is given by the
maximum frequency of a square wave that can be applied to
the device, which meets the VOH and VOL levels at the output and
does not exceed the maximum junction temperature (see
Table 2). Table 6 shows the guaranteed data rates at which the
ADG3300 can operate in both directions (A Y and Y A level
translation) for various VCCA and VCCY supply combinations.
Table 6. Guaranteed Data Rate (Mbps)1
VCCY
1.8 V
(1.65 V to 1.95 V)
2.5 V
(2.3 V to 2.7 V)
3.3 V
(3.0 V to 3.6 V)
5 V
VCCA
(4.5 V to 5.5 V)
1.2 V (1.15 V to 1.3 V)
1.8 V (1.65 V to 1.95 V)
2.5 V (2.3 V to 2.7 V)
3.3 V (3.0 V to 3.6 V)
5 V (4.5 V to 5.5 V)
25
-
-
-
-
30
45
-
-
-
40
50
60
-
40
50
50
50
-
-
1 The load capacitance used is 50 pF when translating in the A Y direction and 15 pF when translating in the Y A direction.
Rev. 0 | Page 16 of 20
ADG3300
APPLICATIONS
other devices without causing contention issues. Figure 37 shows
an application where a 3.3 V microprocessor is connected to
1.8 V peripheral devices using the three-state feature.
The ADG3300 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the
A pins, and the higher voltage logic signals are connected to the
Y pins. The ADG3300 can provide level translation in both
directions from A Y and Y A on all eight channels, eliminating
the need for a level translator IC for each direction. The internal
architecture allows the ADG3300 to perform bidirectional level
translation without an additional signal to set the direction of
the translation. It also allows simultaneous data flow in both
directions on the same part, for example, four channels translate
in the A Y direction while the other four translate in the Y A
direction. This simplifies the design by eliminating the timing
requirements for the direction signal and reduces the number of
ICs used for level translation.
100nF
100nF
I/O
1
I/O
1
Y1
A1
L
H
3.3V
1.8V
V
V
CCY
Y2
CCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
8
A2
I/O
I/O
2
3
L
L
L
L
L
L
L
H
H
Y3ADG3300 A3
Y4
Y5
Y6
Y7
Y8
A4
A5
A6
A7
A8
I/O
I/O
I/O
I/O
I/O
4
5
6
7
8
PERIPHERAL
DEVICE 1
MICROPROCESSOR/
MICROCONTROLLER/
DSP
H
H
H
H
H
GND
CS
GND
EN
GND
100nF
100nF
I/O
1
Y1
A1
1.8V
L
Figure 36 shows an application where a 1.8 V microprocessor
can read or write data to or from a 3.3 V peripheral device using
an 8-bit bus.
V
V
CCY
CCA
A2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
8
Y2
Y3
L
L
L
L
L
L
L
A3
ADG3300
Y4
Y5
Y6
Y7
Y8
A4
A5
A6
A7
A8
EN
PERIPHERAL
DEVICE 2
100nF
100nF
I/O
1
A1
Y1
I/O
1
3.3V
L
H
1.8V
GND
GND
V
V
CCY
CCA
I/O
I/O
2
3
A2
A3
Y2
Y3
Y4
I/O
I/O
2
3
H
L
Figure 37. 1.8 V to 3.3 V Level Translation Circuit
Using the Three-State Feature
H
L
A4
A5
I/O
I/O
4
5
I/O
I/O
4
5
H
L
MICROPROCESSOR/
MICROCONTROLLER/
DSP
PERIPHERAL
DEVICE
ADG3300
LAYOUT GUIDELINES
Y5
H
L
As with any high speed digital IC, the printed circuit board
layout is important in the overall circuit performance. Care
should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each VCC pin (VCCA and
VCCY) should be bypassed using low effective series resistance
(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the VCCA and VCCY pins. The parasitic induc-
tance of the high speed signal track might cause significant
overshoot. This effect can be reduced by keeping the length
of the tracks as short as possible. A solid copper plane for the
return path (GND) is also recommended.
I/O
I/O
I/O
6
7
8
A6
Y6
Y7
Y8
I/O
I/O
I/O
6
7
8
H
H
H
L
L
L
A7
A8
EN
GND
GND
GND
Figure 36. 1.8 V to 3.3 V 8-Bit Level Translation Circuit
When the application requires level translation between a
microprocessor and multiple peripheral devices, the ADG3300
Y I/O pins (Y1 to Y8) can be three-stated by setting EN = 0.
This feature allows the ADG3300 to share the data buses with
Rev. 0 | Page 17 of 20
ADG3300
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AC
Figure 38 . 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG3300BRUZ1
ADG3300BRUZ-REEL1
ADG3300BRUZ-REEL71
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
RU-20
RU-20
TSSOP
TSSOP
TSSOP
RU-20
1 Z = Pb-free part.
Rev. 0 | Page 18 of 20
ADG3300
NOTES
Rev. 0 | Page 19 of 20
ADG3300
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05061–0–4/05(0)
Rev. 0 | Page 20 of 20
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