ADG5412BF [ADI]
Bidirectional Fault Protection and Detection, 10 ohm RON, Quad SPST Switches;
| 型号： | ADG5412BF |
| 厂家： | 
ADI |
| 描述： | Bidirectional Fault Protection and Detection, 10 ohm RON, Quad SPST Switches |
| 文件： | 总28页 (文件大小：583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Bidirectional Fault Protection and
Detection, 10 Ω RON, Quad SPST Switches
ADG5412BF/ADG5413BF
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source and drain pins
Low on resistance: 10 Ω
ADG5412BF
D1
D2
D3
D4
S1
S2
S3
S4
On-resistance flatness of 0.5 Ω
3 kV human body model (HBM) ESD rating
Latch-up immune under any circumstance
Known state without digital inputs present
FAULT
DETECTION
+ SWITCH
DRIVER
FF
VSS to VDD analog signal range
5 V to 22 V dual-supply operation
8 V to 44 V single-supply operation
Fully specified at 15 V, 20 V, +12 V, and +36 V
IN1 IN2 IN3 IN4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1. ADG5412BF
APPLICATIONS
ADG5413BF
Analog input/output modules
Process control/distributed control systems
Data acquisition
D1
S1
D2
D3
D4
S2
S3
S4
Instrumentation
Avionics
FAULT
DETECTION
+ SWITCH
DRIVER
Automatic test equipment
Communication systems
Relay replacement
FF
IN1 IN2 IN3 IN4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 2. ADG5413BF
GENERAL DESCRIPTION
The ADG5412BF and ADG5413BF contain four independently
controlled single-pole/single-throw (SPST) switches. The
ADG5412BF has four switches that turn on with Logic 1 inputs.
The ADG5413BF has two switches that turn on and two switches
that turn off with Logic 1 inputs. Each switch conducts equally
well in both directions when on, and each switch has an input
signal range that extends to the supplies. The digital inputs are
compatible with 3 V logic inputs over the full operating supply
range.
The low on resistance of these switches, combined with on-
resistance flatness over a significant portion of the signal range
make them an ideal solution for data acquisition and gain switching
applications where excellent linearity and low distortion are critical.
PRODUCT HIGHLIGHTS
1. Switch pins are protected against voltages greater than the
supply rails, up to −55 V and +55 V.
2. Switch pins are protected against voltages between −55 V
and +55 V, in an unpowered state.
3. Overvoltage detection with digital output indicates
operating state of switches.
4. Trench isolation guards against latch-up.
5. Optimized for low on resistance and on-resistance flatness.
6. The ADG5412BF/ADG5413BF can be operated from a
dual-supply of 5 V up to 22 V or a single power supply
of 8 V up to 44 V.
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. Under
normal operating conditions, if the analog input signal levels on
any switch pin exceed VDD or VSS by a threshold voltage, VT, the
switch turns off. Input signal levels up to +55 V and −55 V relative
to ground are blocked, in both the powered and unpowered
condition.
Rev. B
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Technical Support
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ADG5412BF/ADG5413BF
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits..................................................................................... 19
Terminology.................................................................................... 23
Theory of Operation ...................................................................... 2ꢀ
Switch Architecture.................................................................... 2ꢀ
Fault Protection .......................................................................... 26
Applications Information.............................................................. 27
Power Supply Rails..................................................................... 27
Power Supply Sequencing Protection...................................... 27
Signal Range................................................................................ 27
Low Impedance Channel Protection....................................... 27
High ꢁoltage Surge Suppression .............................................. 27
Intelligent Fault Detection ........................................................ 27
Large ꢁoltage, High Frequency Signals................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
1ꢀ ꢁ Dual-Supply....................................................................... 3
2ꢂ ꢁ Dual-Supply....................................................................... ꢀ
12 ꢁ Single-Supply ....................................................................... 7
36 ꢁ Single-Supply ....................................................................... 9
Continuous Current per Channel, Sx or Dx........................... 11
Absolute Maximum Ratings.......................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 14
REVISION HISTORY
1/16—Rev. A to Rev. B
Changes to Table 6.......................................................................... 12
Added Figure 4, Renumbered Sequentially ................................ 13
Changes to Table 7.......................................................................... 13
Changes to Figure 3ꢀ...................................................................... 19
Changes to Figure ꢀꢂ...................................................................... 2ꢀ
Changes to Applications Information Section ........................... 27
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide.......................................................... 28
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ ꢀ
Changes to Table 3............................................................................ 7
Changes to Table 4............................................................................ 9
Changes to Switch Architecture Section ..................................... 2ꢀ
3/15—Rev. 0 to Rev. A
Added LFCSP Package.......................................................Universal
Changes to Output Leakage Current, IS or ID/With Overvoltage
Parameter, Table 3............................................................................. 7
Changes to Output Leakage Current, IS or ID/With Overvoltage
Parameter, Table 4............................................................................. 9
7/14—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
ADG5412BF/ADG5413BF
SPECIFICATIONS
±±15 5ꢀDUA-SDPPAY5
VDD = 15 V 10%, VSS = −15 V 10%, ꢀGD = 0 V, CDECOUPLIGꢀ = 0.1 μF, unless otherwise noted.
Table 1.
−40°C5to5
+81°C5
−40°C5to5
+±21°C5Dnit5 CTeosntd5 itions/Comments5
Parameter5+21°C5
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
5
VDD = 13.5 V, VSS = −13.5 V, see Figure 32
VS = 10 V, IS = −10 mA
VS = 9 V, IS = −10 mA
VDD to VSS
16.5
16
V
10
11.2
9.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
14
10.7
13.5
0.6
0.5
1.1
0.5
On-Resistance Match Between Channels, ∆RON 0.05
VS = 10 V, IS = −10 mA
VS = 9 V, IS = −10 mA
0.5
0.05
0.35
0.6
0.9
0.1
0.4
0.7
0.7
0.5
On-Resistance Flatness, RFLAT(ON)
VS = 10 V, IS = −10 mA
VS = 9 V, IS = −10 mA
1.1
0.5
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
See Figure 28
VDD = 16.5 V, VSS = −16.5 V
VS = 10 V, VD = ∓10 V, see Figure 33
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
1.5
0.1
1.5
0.3
2.0
5.5
5.5
2.5
24
20
5.5
Drain Off Leakage, ID (Off)
VS = 10 V, VD = ∓10 V, see Figure 33
Channel On Leakage, ID (On), IS (On)
VS = VD = 10 V, see Figure 34
FAULT
Input Leakage Current, IS or ID
With Overvoltage
78
40
μA typ
μA typ
VDD = 16.5 V, VSS = 16.5 V, GND = 0 V, VS
or VD = 55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, INx = 0 V or
floating, VS or VD = 55 V, see Figure 38
Power Supplies Grounded or Floating
Output Leakage Current, IS or ID
With Overvoltage
20
nA typ
VDD = 16.5 V, VSS = 16.5 V, GND = 0 V, VS
or VD = 55 V, see Figure 37
200
10
250
250
nA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V, VS or VD =
55 V, INx = 0 V, see Figure 38
30
10
50
10
100
10
nA max
μA typ
VDD = floating, VSS = floating, GND = 0 V,
VS or VD = 55 V, INx = 0 V, see Figure 38
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.7
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
5.0
Rev. B | Page 3 of 28
ADG5412BF/ADG5413BF
Data Sheet
−40°C to
+85°C
−40°C to
+125°C
Parameter
+25°C
Unit
Test Conditions/Comments
Output Voltage
High, VOH
Low, VOL
V min
V min
V max
2.0
0.8
DYNAMIC CHARACTERISTICS1
tON
400
495
410
510
285
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
525
545
550
555
tOFF
Break-Before-Make Time Delay, tD
(ADG5413BF Only)
185
630
ns min
ns typ
ns max
ns typ
ns max
ns typ
μs typ
ns typ
VS1 = VS2 = 10 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
460
585
720
930
85
615
RL = 1 kΩ, CL = 2 pF, see Figure 42
1050
1100
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see
Figure 45
60
600
Charge Injection, QINJ
Off Isolation
−680
−70
pC typ
dB typ
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 35
Channel-to-Channel Crosstalk
−90
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 10 kΩ, VS = 15 V p-p, f = 20 Hz to
20 kHz, see Figure 40
Total Harmonic Distortion Plus Noise, THD + N
0.0015
−3 dB Bandwidth
Insertion Loss
270
−0.72
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 39
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
13
12
24
pF typ
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 16.5 V, VSS = −16.5 V, digital inputs =
0 V, 5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
μA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = 55 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
1.8
1.1
IGND
ISS
1.8
5
22
VDD/VSS
GND = 0 V
GND = 0 V
V max
1 Guaranteed by design; not subject to production test.
Rev. B | Page 4 of 28
Data Sheet
ADG5412BF/ADG5413BF
±±20 0ꢀDUA-SDPPAY0
VDD = 20 V ꢀ0%, VSS = −20 V ꢀ0%, ꢁGD = 0 V, CDECOUPLIGꢁ = 0.ꢀ μF, unless otherwise noted.
Table 2.
−42°C0to0
+85°C0
−42°C0to0
+1±5°C0Dnit0 CoTensdti0tions/Comments0
VDD = 18 V, VSS = −18 V, see
Parameter0+±5°C0
0
ANALOG SWITCH
Figure 32
Analog Signal Range
On Resistance, RON
VDD to VSS
16.5
16.5
0.5
V
10
11.5
9.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
VS = 15 V, IS = −10 mA
VS = 13.5 V, IS = −10 mA
VS = 15 V, IS = −10 mA
VS = 13.5 V, IS = −10 mA
VS = 15 V, IS = −10 mA
VS = 13.5 V, IS = −10 mA
14.5
14
11
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
0.05
0.35
0.05
0.35
1.0
1.4
0.1
0.4
0.7
0.5
0.5
1.5
0.5
0.5
1.5
0.5
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
See Figure 28
VDD = 22 V, VSS = −22 V
VS = 15 V, VD = ∓15 V, see Figure 33
0.1
1.5
0.1
1.5
0.3
2.0
nA typ
nA max
nA typ
nA max
nA typ
nA max
5.5
5.5
2.5
24
20
5.5
Drain Off Leakage, ID (Off)
VS = 15 V, VD = ∓15 V, see Figure 33
Channel On Leakage, ID (On), IS (On)
VS = VD = 15 V, see Figure 34
FAULT
Input Leakage Current, IS or ID
With Overvoltage
78
40
μA typ
μA typ
VDD = 22 V, VSS = −22 V, GND = 0 V,
VS or VD = 55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, INx = 0 V or
floating, VS or VD = 55 V, see
Figure 38
Power Supplies Grounded or Floating
Output Leakage Current, IS or ID
With Overvoltage
0.4
μA typ
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS or VD = 55 V, see Figure 37
1.0
10
1.0
1.0
μA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V, VS or
VD = 55 V, INx = 0 V, see Figure 38
30
10
50
10
100
10
nA max
μA typ
VDD = floating, VSS = floating, GND
= 0 V, VS or VD = 55 V, INx = 0 V,
see Figure 38
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.7
5.0
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Rev. B | Page 5 of 28
ADG5412BF/ADG5413BF
Data Sheet
−40°C to
+85°C
−40°C to
+125°C
Parameter
+25°C
Unit
Test Conditions/Comments
Output Voltage
High, VOH
Low, VOL
2.0
0.8
V min
V max
DYNAMIC CHARACTERISTICS1
tON
400
500
415
515
295
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
530
550
555
565
tOFF
Break-Before-Make Time Delay, tD
(ADG5413BF Only)
200
515
ns min
ns typ
ns max
ns typ
ns max
ns typ
μs typ
ns typ
VS1 = VS2 = 10 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
370
480
840
1200
85
500
RL = 1 kΩ, CL = 2 pF, see Figure 42
1400
1700
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see
Figure 45
60
600
Charge Injection, QINJ
−640
−70
pC typ
dB typ
dB typ
% typ
VS = 0 V, RS = 0 Ω, CL = 1 nF, see
Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz
to 20 kHz, see Figure 40
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−90
0.001
−3 dB Bandwidth
Insertion Loss
270
−0.73
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 39
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
12
11
23
pF typ
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 22 V, VSS = −22 V, digital
inputs = 0 V, 5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = 55 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
1.8
1.1
IGND
ISS
1.8
5
22
VDD/VSS
GND = 0 V
GND = 0 V
V max
1 Guaranteed by design; not subject to production test.
Rev. B | Page 6 of 28
Data Sheet
ADG5412BF/ADG5413BF
12 V SINGLE-SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 μF, unless otherwise noted.
Table 3.
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD = 10.8 V, VSS = 0 V, see Figure 32
0 V to VDD
37
V
22
24.5
10
11.2
0.05
0.5
0.05
0.5
12.5
14.5
0.6
0.9
0.7
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
31
14
16.5
0.7
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
0.6
0.6
19
0.7
23
1.1
1.3
Threshold Voltage, VT
LEAKAGE CURRENTS
See Figure 28
VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.1
1.5
0.1
1.5
0.3
2.0
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 33
5.5
24
20
5.5
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 33
VS = VD = 1 V/10 V, see Figure 34
5.5
2.5
Channel On Leakage, ID (On), IS (On)
FAULT
Input Leakage Current, IS or ID
With Overvoltage
78
40
μA typ
μA typ
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS or
VD = 55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, INx = 0 V or floating, VS or
VD = 55 V, see Figure 38
Power Supplies Grounded or Floating
Output Leakage Current, IS or ID
With Overvoltage
20
nA typ
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS or
VD = 55 V, see Figure 37
200
10
250
250
nA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V, VS or VD =
55 V, INx = 0 V, see Figure 38
30
10
50
10
100
10
nA max
μA typ
VDD = floating, VSS = floating, GND = 0 V,
VS or VD = 55 V, INx = 0 V, see Figure 38
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.7
5.0
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Output Voltage
High, VOH
2.0
0.8
V min
V max
Low, VOL
Rev. B | Page 7 of 28
ADG5412BF/ADG5413BF
Data Sheet
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
DYNAMIC CHARACTERISTICS1
Unit
Test Conditions/Comments
tON
400
485
375
460
260
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 47
RL = 300 Ω, CL = 35 pF
515
495
540
520
tOFF
Break-Before-Make Time Delay, tD
(ADG5413BF Only)
170
720
ns min
ns typ
ns max
ns typ
ns max
ns typ
μs typ
ns typ
pC typ
dB typ
VS1 = VS2 = 8 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
560
660
640
800
85
700
865
RL = 1 kΩ, CL = 2 pF, see Figure 42
960
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see Figure 45
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 35
60
600
−340
−65
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
−90
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 10 kΩ, VS = 6 V p-p, f = 20 Hz to
20 kHz, see Figure 40
Total Harmonic Distortion Plus Noise, THD + N
0.007
−3 dB Bandwidth
Insertion Loss
270
−0.74
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 39
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 39
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
16
15
25
pF typ
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V, VSS = 0 V, digital inputs = 0 V,
5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = 55 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
1.8
1.1
IGND
ISS
1.8
8
44
VDD
VSS = GND = 0 V
VSS = GND = 0 V
V max
1 Guaranteed by design; not subject to production test.
Rev. B | Page 8 of 28
Data Sheet
ADG5412BF/ADG5413BF
36 V SINGLE-SUPPLY
VDD = 36 V ꢀ0%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.ꢀ μF, unless otherwise noted.
Table 4.
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD = 32.4 V, VSS = 0 V, see Figure 32
0 V to VDD
37
V
22
24.5
10
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
31
11
14
16.5
0.7
On-Resistance Match Between Channels, ∆RON 0.05
0.5
0.05
0.35
12.5
14.5
0.1
0.6
0.5
19
0.5
On-Resistance Flatness, RFLAT(ON)
23
0.4
0.7
0.5
0.5
Threshold Voltage, VT
LEAKAGE CURRENTS
See Figure 28
VDD = 39.6 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.1
nA typ
VS = 1 V/30 V, VD = 30 V/1 V, see
Figure 33
1.5
0.1
5.5
24
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/30 V, VD = 30 V/1 V, see
Figure 33
1.5
0.3
2.0
5.5
2.5
20
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/30 V, see Figure 34
5.5
FAULT
Input Leakage Current, IS or ID
With Overvoltage
78
40
μA typ
μA typ
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS or
VD = +55 V, −40 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, INx = 0 V or
floating, VS or VD = 55 V, see Figure 38
Power Supplies Grounded or Floating
Output Leakage Current, IS or ID
With Overvoltage
20
nA typ
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS or
VD = +55 V, −40 V, see Figure 37
200
10
250
250
nA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V, VS or
VD = 55 V, INx = 0 V, see Figure 38
30
10
50
10
100
10
nA max
μA typ
VDD = floating, VSS = floating, GND =
0 V, VS or VD = 55 V, INx = 0 V, see
Figure 38
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.7
5.0
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Rev. B | Page 9 of 28
ADG5412BF/ADG5413BF
Data Sheet
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
Output Voltage
High, VOH
Low, VOL
2.0
0.8
V min
V max
DYNAMIC CHARACTERISTICS1
tON
400
490
375
460
285
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 47
RL = 300 Ω, CL = 35 pF
520
485
545
510
tOFF
Break-Before-Make Time Delay, tD
(ADG5413BF Only)
195
375
ns min
ns typ
ns max
ns typ
ns max
ns typ
μs typ
ns typ
pC typ
VS1 = VS2 = 18 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
250
350
1500
2000
85
60
600
−610
360
RL = 1 kΩ, CL = 2 pF, see Figure 42
2300
2700
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see Figure 45
VS = 18 V, RS = 0 Ω, CL = 1 nF, see
Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 10 kΩ, VS = 18 V p-p, f = 20 Hz to
20 kHz, see Figure 40
Charge Injection, QINJ
Off Isolation
−70
−90
dB typ
dB typ
% typ
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N 0.001
−3 dB Bandwidth
Insertion Loss
270
−0.75
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 39
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
12
11
23
pF typ
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V, VSS = 0 V, digital inputs =
0 V, 5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Isolation Mode
IDD
VS = +55 V, −40 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
1.8
1.1
IGND
ISS
1.8
8
44
VDD
VSS = GND = 0 V
VSS = GND = 0 V
V max
1 Guaranteed by design; not subject to production test.
Rev. B | Page 10 of 28
Data Sheet
ADG5412BF/ADG5413BF
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter
25°C
85°C
125°C
Unit
Test Conditions/Comments
16-LEAD TSSOP
θJA = 112.6°C/W
83
64
59
48
39
29
mA max
mA max
VS = VSS + 4.5 V to VDD − 4.5 V
VS = VSS to VDD
16-LEAD LFCSP
θJA = 30.4°C/W
152
118
99
80
61
52
mA max
mA max
VS = VSS + 4.5 V to VDD − 4.5 V
VS = VSS to VDD
Rev. B | Page 11 of 28
ADG5412BF/ADG5413BF
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Sx and Dx
Sx to VDD or VSS
VS to VD
Rating
48 V
−0.3 V to +48 V
−48 V to +0.3 V
−55 V to +55 V
80 V
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
80 V
Digital Inputs
GND − 0.7 V to +48 V or 30 mA,
whichever occurs first
Peak Current, Sx or Dx Pins
288 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data1 + 15%
Continuous Current, Sx or Dx
Pins
Digital Output
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
Operating Temperature
Range
−40°C to +125°C
Storage Temperature Range
Junction Temperature
−65°C to +150°C
150°C
Thermal Impedance, θJA
(4-Layer Board)
16-Lead TTSOP
16-Lead LFSCP
112.6°C/W
30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
As per JEDEC J-STD-020
ESD (HBM: ANSI/ESD
STM5.1-2007)
I/O Port to Supplies
I/O Port to I/O Port
All Other Pins
5.5 kV
5.5 kV
3 kV
1 See Table 5.
Rev. B | Page 12 of 28
Data Sheet
ADG5412BF/ADG5413BF
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
D1
S1
IN2
D2
S2
V
S1
1
2
3
4
12
11
S2
V
ADG5412BF/
ADG5413BF
TOP VIEW
(Not to Scale)
V
V
SS
DD
SS
DD
ADG5412BF/
ADG5413BF
GND
FF
S3
D3
IN3
GND
10 FF
TOP VIEW
9
S4
S3
S4
D4
IN4
NOTES
1. THE EXPOSED PAD IS INTERNALLY CONNECTED.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE CONNECTED TO THE LOWEST SUPPLY VOLTAGE, V
.
SS
Figure 4. LFCSP Pin Configuration
Figure 3. TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1
2
3
4
5
6
7
8
15
16
1
2
3
4
5
6
7
IN1
D1
S1
VSS
GND
S4
D4
IN4
IN3
D3
S3
Logic Control Input.
Overvoltage Protected Drain Terminal. This pin can be an input or an output.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
Overvoltage Protected Drain Terminal. This pin can be an input or an output.
Logic Control Input.
Logic Control Input.
Overvoltage Protected Drain Terminal. This pin can be an input or an output.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
9
10
11
12
8
9
10
FF
Fault Flag Digital Output. This pin has a high output when the device is in normal operation or a low when
a fault condition occurs on any of the Sx inputs.
13
14
15
16
11
12
13
14
EP
VDD
S2
D2
IN2
Exposed
Pad
Most Positive Power Supply Potential.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
Overvoltage Protected Drain Terminal. This pin can be an input or an output.
Logic Control Input.
The exposed pad is internally connected. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be connected to the lowest supply voltage, VSS.
Table 8. ADG5412BF Truth Table
INx
Switch Condition (S1 to S4)
1
0
On
Off
Table 9. ADG5413BF Truth Table
Switch Condition
INx
0
1
S1, S4
S2, S3
On
Off
Off
On
Rev. B | Page 13 of 28
ADG5412BF/ADG5413BF
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
25
40
35
30
25
20
15
10
5
V
V
= +22V
= –22V
V
V
= +15V
= –15V
DD
SS
T
= 25°C
DD
A
SS
V
V
= +20V
= –20V
DD
SS
20
15
10
5
V
V
= +16.5V
= –16.5V
DD
SS
V
V
= +18V
= –18V
DD
SS
V
V
= +13.5V
= –13.5V
DD
SS
+125°C
+85°C
+25°C
–40°C
V
V
= +15V
= –15V
DD
SS
0
0
–25 –20 –15 –10
–5
0
5
10
15
20
25
14
40
–15 –12
–9
–6
–3
0
3
6
9
12
15
V , V (V)
V , V (V)
S D
S
D
Figure 5. RON as a Function of VS,VD (Dual-Supply)
Figure 8. RON as a Function of VS,VD for Different Temperatures,
15 V Dual-Supply
25
20
15
10
5
40
V
V
= +20V
= –20V
T
= 25°C
DD
A
SS
35
30
25
20
15
10
5
V
V
= 12V
= 0V
DD
SS
V
V
= 10.8V
= 0V
DD
SS
+125°C
+85°C
V
V
= 13.2V
= 0V
DD
SS
+25°C
–40°C
0
0
–20
0
2
4
6
8
10
12
–15
–10
–5
0
5
10
15
20
V , V (V)
V , V (V)
S D
S
D
Figure 6. RON as a Function of VS,VD (12 V Single-Supply)
Figure 9. RON as a Function of VS,VD for Different Temperatures,
2ꢀ V Dual-Supply
25
20
15
10
5
40
V
= 12V
T
= 25°C
DD
A
V
= 0V
SS
35
30
25
20
15
10
5
V
V
= 36V
= 0V
DD
SS
V
V
= 32.4V
= 0V
DD
SS
+125°C
+85°C
+25°C
–40°C
V
V
= 39.6V
= 0V
DD
SS
0
0
0
5
10
15
20
V , V (V)
25
30
35
0
2
4
6
8
10
12
V , V (V)
S
D
S
D
Figure 7. RON as a Function of VS,VD (36 V Single-Supply)
Figure 1ꢀ. RON as a Function of VS,VD for Different Temperatures,
12 V Single-Supply
Rev. B | Page 14 of 28
Data Sheet
ADG5412BF/ADG5413BF
40
35
30
25
20
15
10
5
2
1
V
V
= 36V
DD
= 0V
SS
0
V
V
V
= 12V
= 0V
DD
SS
–1
–2
–3
–4
–5
–6
–7
–8
= 1V/10V
BIAS
+125°C
+85°C
+25°C
–40°C
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
S
S
D
D
I , I (ON) + +
I , I (ON) – –
S
D
S
D
0
0
4
8
12
16
20
24
28
32
36
0
20
40
60
80
100
120
V , V (V)
TEMPERATURE (°C)
S
D
Figure 14. Leakage Current vs. Temperature, 12 V Single-Supply
Figure 11. RON as a Function of VS,VD for Different Temperatures,
36 V Single-Supply
2
1
0
4
V
V
V
= 36V
= 0V
DD
SS
2
0
= 1V/30V
BIAS
V
V
V
= +15V
= –15V
DD
SS
–1
–2
–3
–4
–5
–6
–7
–8
= +10V/–10V
BIAS
–2
–4
–6
–8
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
S
S
D
D
S
S
D
D
–10
–12
I , I (ON) + +
I , I (ON) – –
I , I (ON) + +
I , I (ON) – –
S
D
S
D
S
D
S
D
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Leakage Current vs. Temperature, 15 V Dual-Supply
Figure 15. Leakage Current vs. Temperature, 36 V Single-Supply
4
5
0
V
V
V
= +20V
= –20V
DD
SS
2
0
= +15V/–15V
BIAS
V
V
= +15V
= –15V
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
DD
SS
–2
–4
–6
–8
–10
–12
–14
V
V
V
V
= –30V
= +30V
= –55V
= +55V
S
S
S
S
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
S
S
D
D
I , I (ON) + +
I , I (ON) – –
S
D
S
D
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Leakage Current vs. Temperature, 20 V Dual-Supply
Figure 16. Overvoltage Drain Leakage Current vs. Temperature,
15 V Dual-Supply
Rev. B | Page 15 of 28
ADG5412BF/ADG5413BF
Data Sheet
10
0
–20
V
V
T
= +15V
= –15V
= 25°C
V
V
= +20V
= –20V
DD
DD
SS
SS
0
–10
–20
–30
–40
–50
–60
A
–40
–60
–80
V
V
V
V
= –30V
= +30V
= –55V
= +55V
S
S
S
S
–100
–120
0
20
40
60
80
100
120
1k
10k
100k
1M
10M
100M
1G
1G
40
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 17. Overvoltage Drain Leakage Current vs. Temperature,
±±2 ꢀ Dual-Supply
Figure ±2. Off Isolation vs. Frequency, ±15 ꢀ Dual-Supply
5
0
0
–20
V
V
= +15V
= –15V
= 25°C
DD
SS
T
A
V
V
= 12V
= 0V
DD
SS
–5
–10
–15
–20
–25
–30
–35
–40
–45
–40
–60
–80
V
V
V
V
= –30V
= +30V
= –55V
= +55V
S
S
S
S
–100
–120
0
20
40
60
80
100
120
10k
100k
1M
10M
100M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 18. Overvoltage Drain Leakage Current vs. Temperature,
1± ꢀ Single-Supply
Figure ±1. Crosstalk vs. Frequency, ±15 ꢀ Dual-Supply
5
100
0
T
= 25°C
V
V
= 36V
= 0V
A
DD
SS
0
–5
–100
–200
–300
–400
–500
–600
–700
–800
V
V
= 12V
= 0V
DD
SS
–10
–15
–20
–25
–30
V
V
= 36V
= 0V
DD
SS
V
V
V
V
= –38V
= +38V
= –40V
= +55V
S
S
S
S
0
5
10
15
20
(V)
25
30
35
0
20
40
60
80
100
120
V
TEMPERATURE (°C)
S
Figure 19. Overvoltage Drain Leakage Current vs. Temperature,
36 ꢀ Single-Supply
Figure ±±. Charge Injection vs. Source ꢀoltage (ꢀS), Single-Supply
Rev. B | Page 16 of 28
Data Sheet
ADG5412BF/ADG5413BF
100
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
T
= 25°C
V
V
= +15V
= –15V
= 25°C
A
DD
SS
0
–100
–200
–300
–400
–500
–600
–700
–800
T
A
V
V
= +15V
= –15V
DD
SS
V
V
= +20V
= –20V
DD
SS
–20
–15
–10
–5
0
5
10
15
20
10k
100k
1M
10M
100M
1G
V
(V)
FREQUENCY (Hz)
S
Figure 23. Charge Injection vs. Source Voltage (VS), Dual-Supply
Figure 26. Bandwidth vs. Frequency
0
480
460
440
420
400
380
360
340
320
V
V
T
= +15V
= –15V
= 25°C
DD
tON (+12V)
tON (±20V)
tOFF (±15V)
tON (+36V)
tOFF (+12V)
tOFF (±20V)
tON (±15V)
tOFF (+36V)
SS
–20
–40
A
WITH DECOUPLING CAPACITORS
–60
–80
–100
–120
–140
10k
100k
1M
10M
100M
1G
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 24. ACPSRR vs. Frequency, ±±1 V Dual-Supply
Figure 27. tON, tOFF Times vs. Temperature
0.020
0.015
0.010
0.005
0
0.9
0.8
0.7
0.6
0.5
LOAD = 10kΩ
T
= 25°C
A
V
= 12V, V = 0V, V = 6V p-p
SS S
DD
V
= 15V, V = –15V, V = 15V p-p
SS S
DD
V
= 20V, V = –20V, V = 20V p-p
SS S
DD
V
= 36V, V = 0V, V = 18V p-p
SS S
DD
0
5000
10000
FREQUENCY (Hz)
15000
20000
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 21. THD + N vs. Frequency, ±±1 V Dual-Supply
Figure 28. Threshold Voltage (VT) vs. Temperature
Rev. B | Page 17 of 28
ADG5412BF/ADG5413BF
Data Sheet
24
20
16
12
8
T
V
V
= 25°C
T
A
= +10V
= –10V
DD
SS
SOURCE
V
DD
DISTORTIONLESS
OPERATING
REGION
2
DRAIN
4
0
1
10
FREQUENCY (MHz)
100
CH1 5.00V CH2 5.00V
CH3 5.00V
M200ns
–10.00ns
A
CH2
16.1V
T
Figure 29. Drain Output Response to Positive Overvoltage
Figure 31. Large Voltage Signal Tracking vs. Frequency
T
3
DRAIN
V
SS
SOURCE
CH2 –16.1V
CH1 5.00V CH2 5.00V
CH3 5.00V
M200ns
–10.00ns
A
T
Figure 30. Drain Output Response to Negative Overvoltage
Rev. B | Page 18 of 28
Data Sheet
ADG5412BF/ADG5413BF
TEST CIRCUITS
I
I
D
S
V
Sx
Dx
A
A
R
10kΩ
L
|V | > |V | OR |V |
SS
Sx
Dx
S
DD
I
DS
V
S
R
= V/I
DS
ON
Figure 37. Switch Overvoltage Leakage
Figure 32. On Resistance
V
= V = GND = 0V
SS
DD
I
I
D
S
Sx
Dx
I
(OFF)
A
I
(OFF)
A
S
D
A
A
Sx
Dx
R
10kΩ
L
V
S
V
V
D
S
Figure 38. Switch Unpowered Leakage
Figure 33. Off Leakage
I
(ON)
A
D
Sx
Dx
NC
V
D
NC = NO CONNECT
Figure 34. On Leakage
V
V
DD
SS
V
V
SS
DD
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
DD
SS
V
V
DD
SS
Sx
50Ω
Sx
50Ω
INx
IN
V
S
INx
V
S
Dx
Dx
V
OUT
V
V
R
50Ω
OUT
L
V
IN
R
50Ω
L
GND
GND
V
OUT
V
WITH SWITCH
OUT
OFF ISOLATION = 20 log
V
S
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 39. Bandwidth
Figure 35. Off Isolation
V
V
SS
DD
V
V
DD
SS
0.1µF
0.1µF
0.1µF
0.1µF
AUDIO
PRECISION
NETWORK
ANALYZER
V
V
DD
SS
V
V
DD
SS
R
V
S
OUT
S1
R
50Ω
L
Sx
V
INx
IN
S
Dx
V p-p
R
L
50Ω
S2
Dx
V
OUT
V
R
10kΩ
L
V
S
GND
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 36. Channel-to-Channel Crosstalk
Figure 40. THD + N
Rev. B | Page 19 of 28
ADG5412BF/ADG5413BF
Data Sheet
V
V
V
V
DD
SS
SS
0.1µF
0.1µF
V
+ 0.5V
DD
DD
SOURCE
VOLTAGE
V
S1
D1
D
(V )
S
C *
L
2pF
R
L
V
S
1kΩ
0V
ADG5412BF/
ADG5413BF
tRESPONSE
V
– 1V
DD
S2 TO S4
GND
OUTPUT
(V
)
D
0V
*INCLUDES TRACK CAPACITANCE
Figure 41. Overvoltage Response Time, tRESPONSE
V
V
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
V
V
DD
SS
SOURCE
VOLTAGE
V
D
S1
D1
(V )
S
C *
L
2pF
R
L
1kΩ
V
S
0V
ADG5412BF/
ADG5413BF
tRECOVERY
S2 TO S4
GND
OUTPUT
(V
)
D
1V
0V
*INCLUDES TRACK CAPACITANCE
Figure 42. Overvoltage Recovery Time, tRECOVERY
V
V
DD
SS
SS
0.1µF
0.1µF
V
+ 0.5V
DD
V
V
DD
SOURCE
VOLTAGE
S1
D1
S2 TO S4
(V )
S
V
S
0V
ADG5412BF/
ADG5413BF
tDIGRESP
FF
C *
L
12pF
OUTPUT
(V
)
GND
FF
0.1V
OUT
0V
*INCLUDES TRACK CAPACITANCE
Figure 43. Interrupt Flag Response Time, tDIGRESP
Rev. B | Page 20 of 28
Data Sheet
ADG5412BF/ADG5413BF
V
V
V
V
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
DD
SS
SOURCE
S1
D1
S2 TO S4
VOLTAGE
(V )
V
S
S
0V
ADG5412BF/
ADG5413BF
FF
tDIGREC
C *
L
12pF
0.9V
OUT
OUTPUT
GND
(V
)
FF
0V
*INCLUDES TRACK CAPACITANCE
Figure 44. Interrupt Flag Recovery Time, tDIGREC
V
V
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
V
V
DD
SS
SOURCE
S1
D1
S2 TO S4
VOLTAGE
(V )
S
V
S
5V
0V
R
1kΩ
ADG5412BF/
ADG5413BF
PULLUP
tDIGREC
OUTPUT
FF
5V
C *
L
12pF
3V
OUTPUT
GND
(V
)
FF
0V
*INCLUDES TRACK CAPACITANCE
Figure 45. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor
V
V
DD
SS
V
0.1µF
0.1µF
IN
50%
50%
0V
0V
V
S1
V
SS
D1
90%
DD
90%
V
V
OUT1
OUT2
V
V
S1
OUT1
C
35pF
R
300Ω
L
L
S2
D2
V
V
S2
OUT2
C
R
300Ω
L
L
90%
90%
35pF
IN1,
IN2
0V
ADG5413BF
GND
tD
tD
Figure 46. Break-Before-Make Time Delay, tD
Rev. B | Page 21 of 28
ADG5412BF/ADG5413BF
Data Sheet
V
V
DD
SS
0.1µF
0.1µF
ADG5412BF/
ADG5413BF
V
50%
50%
IN
V
V
SS
DD
V
L
OUT
Sx
Dx
R
300Ω
C
L
V
S
35pF
INx
90%
V
OUT
10%
GND
tOFF
tON
Figure 47. Switching Times, tON and tOFF
V
V
DD
SS
0.1µF
0.1µF
ADG5412BF/
ADG5413BF
V
V
SS
DD
V
IN
V
R
OUT
S
Sx
Dx
OFF
ON
C
1nF
L
V
S
INx
V
OUT
∆V
OUT
Q
= C × ∆V
L
OUT
GND
INJ
Figure 48. Charge Injection, QINJ
Rev. B | Page 22 of 28
Data Sheet
ADG5412BF/ADG5413BF
TERMINOLOGY
IDD
tOFF
OFF represents the delay between applying the digital control
I
DD represents the positive supply current.
t
input and the output switching off (see Figure 47).
ISS
ISS represents the negative supply current.
tD
tD represents the off time measured between the 90% point of both
switches when switching from one address state to another.
VD, VS
VD and VS represent the analog voltage on the Dx pins and the
Sx pins, respectively.
tDIGRESP
t
DIGRESP is the time required for the FF pin to go low (0.3 V),
RON
measured with respect to voltage on the source pin exceeding
the supply voltage by 0.5 V.
RON represents the ohmic resistance between the Dx pins and
the Sx pins.
tDIGREC
ΔRON
tDIGREC is the time required for the FF pin to return high (3 V),
ΔRON represents the difference between the RON of any two
channels.
measured with respect to voltage on the Sx pin falling below the
supply voltage plus 0.5 V.
RFLAT(ON)
tRESPONSE
RFLAT(ON) is the flatness that is defined as the difference between
tRESPONSE represents the delay between the source voltage
the maximum and minimum value of on resistance measured
over the specified analog signal range.
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 90% of the supply voltage.
IS (Off)
tRECOVERY
IS (Off) is the source leakage current with the switch off.
tRECOVERY represents the delay between an overvoltage on the Sx
ID (Off)
pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 10% of the supply voltage.
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
VINL
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
V
INL is the maximum input voltage for Logic 0.
VINH
INH is the minimum input voltage for Logic 1.
INL, IINH
V
Channel-to-Channel Crosstalk
Crosstalk is a measure of unwanted signal that is coupled through
from one channel to another as a result of parasitic capacitance.
I
IINL and IINH represent the low and high input currents of the
digital inputs.
−3 dB Bandwidth
CD (Off)
Bandwidth is the frequency at which the output is attenuated
CD (Off) represents the off switch drain capacitance, which is
by 3 dB.
measured with reference to ground.
On Response
CS (Off)
On response is the frequency response of the on switch.
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
CIN
CIN is the digital input capacitance.
tON
tON represents the delay between applying the digital control
input and the output switching on (see Figure 47).
Rev. B | Page 23 of 28
ADG5412BF/ADG5413BF
Data Sheet
AC Power Supply Rejection Ratio (ACPSRR)
VT
ACPSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. ACPSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
0.62 V p-p.
VT is the voltage threshold at which the overvoltage protection
circuitry engages. See Figure 28.
Rev. B | Page 24 of 28
Data Sheet
ADG5412BF/ADG5413BF
THEORY OF OPERATION
During overvoltage conditions, the leakage current into and out
of the switch pins is limited to tens of microamperes. This limit
protects the switch and connected circuitry from over stresses as
well as restricting the current drawn from the signal source. When
an overvoltage event occurs, the channels undisturbed by the
overvoltage input continue to operate normally without
additional crosstalk.
SWITCH ARCHITECTURE
Each channel of the ADG5412BF/ADG5413BF consists of a
parallel pair of N-channel diffused metal-oxide semiconductor
(NDMOS) and P-channel DMOS (PDMOS) transistors. This
construction provides excellent performance across the signal
range. The ADG5412BF/ADG5413BF channels operate as stand-
ard switches when input signals with a voltage between VSS and
ESD Performance
VDD are applied. For example, the on resistance is 10 Ω typically
and the appropriate control pin, INx, controls the opening or
closing of the switch.
The ADG5412BF/ADG5413BF has an ESD rating of 3 kV for
the human body model (HBM). ESD protection cells allow the
voltage at the pins to exceed the supply voltage. See Figure 49
for a switch channel overview.
Additional internal circuitry enables the switch to detect over-
voltage inputs by comparing the voltage on the source or drain
pin with VDD and VSS. A signal is considered overvoltage if it
exceeds the supply voltages by the voltage threshold, VT. The
threshold voltage is typically 0.7 V, but can range from 0.8 V
(when operating at −40°C) down to 0.6 V at +125°C. See Figure 28
to see the change in VT with operating temperature.
Trench Isolation
In the ADG5412BF and ADG5413BF, an insulating oxide layer
(trench) is placed between the NDMOS and the PDMOS
transistors of each switch. Parasitic junctions, which occur between
the transistors in junction-isolated switches, are eliminated, and
the result is a switch that is latch-up immune under all
The maximum voltage that can be applied to any switch input is
+55 V or −55 V. When the device is powered using the single-
supply of 25 V or greater, the maximum signal level reduces
from −55 V to −40 V at VDD = 40 V to remain within the 80 V
maximum rating. Construction of the process allows the channel
to withstand 80 V across the switch when it is opened. These
overvoltage limits apply whether the power supplies are present
or not.
circumstances. These devices pass a JESD78D latch-up test of
500 mA for 1 sec, which is the harshest test in the specification.
NDMOS
PDMOS
ESD
PROTECTION
ESD
PROTECTION
P-WELL
N-WELL
Sx
Dx
FAULT
DETECTOR
SWITCH
FAULT
DRIVER DETECTOR
TRENCH
AND
BURIED OXIDE LAYER
HANDLE WAFER
INx
Figure 49. Switch Channel and Control Function
When an overvoltage condition is detected on either the source pin
or drain pin, the switch is automatically opened regardless of the
digital logic state, INx. The source and drain pins both become
high impedance and ensure that no current flows through the
switch. In Figure 29, the voltage on the drain pin can be seen to
follow the voltage on the source pin until the switch has turned off
completely and the drain voltage discharges through the load. The
maximum voltage and the rate at which the output voltage dis-
charges is dependent on the load at the pin. The ADG5412F/
ADG5413F are pin-compatible devices that are overvoltage
protected on the source pin only, with ESD diodes on the drain
pin that limit the maximum voltage while the switch is opening.
Figure 50. Trench Isolation
Rev. B | Page 25 of 28
ADG5412BF/ADG5413BF
Data Sheet
+22V 0V
–22V
FAULT PROTECTION
When the voltages at the switch inputs exceed VDD or VSS by VT,
the switch turns off or, if the device is unpowered, the switch
remains off. The switch input remains high impedance regardless
of the digital input state or the load resistance, and the output
acts as a virtual open circuit. Signal levels up to +55 V and
−55 V are blocked in both the powered and unpowered condition
as long as the 80 V limitation between the switch and supply
pins is met.
V
GND
V
SS
DD
ADG5413BF
S1
S2
S3
S4
D1
D2
D3
D4
+22V
‒55V
+55V
FAULT
DETECTION
+ SWITCH
DRIVER
Power-On Protection
FF
0V
The following three conditions must be satisfied for the switch
to be in the on condition:
5V
IN1 IN2 IN3 IN4
VDD to VSS ≥ 8 V
Input signal is between VSS − VT and VDD + VT
Digital logic control input, INx, is turned on
Figure 51. ADG5413BF in Multiplexer Configuration under Overvoltage
Conditions
Power-Off Protection
When the switch is turned on, signal levels up to the supply rails
are passed.
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. This
state ensures that no current flows and prevents damage to the
switch or downstream circuitry. The switch output is a virtual
open circuit.
The switch responds to an analog input that exceeds VDD or VSS
by a threshold voltage, VT, by turning off. The absolute input
voltage limits are −55 V and +55 V, while maintaining an 80 V
limit between the source pin and the supply rails. The switch
remains off until the voltage at the switch pin returns to between
The switch remains off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to ±55 V
are blocked in the unpowered condition.
VDD and VSS.
The fault response time (tRESPONSE) when powered by ±±5 V
dual-supply is typically 460 ns, and the fault recovery time
(tRECOVERY) is 720 ns. These vary with supply voltages and output
load conditions.
Digital Input Protection
The ADG54±2BF and the ADG54±3BF can tolerate digital
input signals being present on the device without power. When
the device is unpowered, the switch is guaranteed to be in the
off state, regardless of the state of the digital logic signals.
Exceeding ±55 V on any switch input may damage the ESD
protection circuitry on the device.
The maximum stress across the switch channel is 80 V; therefore,
the user must pay close attention to this limit if using the device
in a multiplexed configuration and one channel is on while another
channel is in a fault condition.
The digital inputs are protected against positive faults up to 44 V.
The digital inputs do not offer protection against negative
overvoltages. ESD protection diodes connected to GND are
present on the digital inputs.
For example, consider the case where the device is set up in a
multiplexer configuration as shown in Figure 5±.
Overvoltage Interrupt Flag
The voltages on the switch inputs of the ADG54±2BF and the
ADG54±3BF are continuously monitored and the state of the
switch is indicated by an active low digital output pin, FF.
VDD/VSS = ±22 V, S± = 22 V, all switches are on
D± is externally multiplexed with D2; therefore, D± and D2
= 22 V
The voltage on the FF pin indicates if any of the switch input
pins are experiencing a fault condition. The output of the FF pin
is a nominal 3 V when all switch pins are within normal operating
range. If any switch pin voltage exceeds the supply voltage by
VT, the FF output reduces to below 0.8 V.
S2 has a −55 V fault and S3 has a +55 V fault
The voltage between S2 and D± or between S2 and D2 =
+22 V − (−55 V) = +77 V
The voltage between S3 and D3 = 55 V− 0 V = 55 V
These calculations are all within device specifications: 55 V
maximum fault on switch inputs and a maximum of 80 V across
the off switch channel.
Rev. B | Page 26 of 28
Data Sheet
ADG5412BF/ADG5413BF
APPLICATIONS INFORMATION
The overvoltage protected family of switches and multiplexers
provide a robust solution for instrumentation, industrial,
aerospace, and other harsh environments where overvoltage
signals can be present and the system must remain operational
both during and after the overvoltage has occurred.
The ADG5412BF/ADG5413BF enable the designer to remove
these resistors and retain the precision performance without
compromising the protection of the circuit.
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5412BF/ADG5413BF is not intended for use in very
high voltage applications. The maximum operating voltage of
the transistor is 80 ꢀ. In applications where the inputs are likely
to be subject to overvoltages exceeding the breakdown voltage,
use transient voltage suppressors (TꢀSs), or similar.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 μF decoupling
capacitors are required.
The ADG5412BF and the ADG5413BF can operate with bipolar
supplies between 5 ꢀ and 22 ꢀ. The supplies on ꢀDD and
ꢀSS need not be symmetrical but the ꢀDD to ꢀSS range must
not exceed 44 ꢀ. The ADG5412BF and the ADG5413BF can
also operate with single supplies between 8 ꢀ and 44 ꢀ with
ꢀSS connected to GND.
INTELLIGENT FAULT DETECTION
The ADG5412BF/ADG5413BF digital output pin, FF, can
interface with a microprocessor or control system and be used
as an interrupt flag. This feature provides real-time diagnostic
information on the state of the device and the system to which it
connects.
These devices are fully specified at 15 ꢀ, 20 ꢀ, +12 ꢀ, and
+36 ꢀ supply ranges.
The control system can use the digital interrupt to start a variety
of actions, such as
POWER SUPPLY SEQUENCING PROTECTION
The switch channel remains open when the device is unpowered
and signals from −55 ꢀ to +55 ꢀ can be applied without damaging
the device. Only when the supplies are connected and a suitable
digital control signal is placed on the INx pin does the switch
channel close and then allow a signal to pass. Placing the
ADG5412BF/ADG5413BF between external connectors and
sensitive components offers protection in systems where a
signal is presented to the switch pins before the supply voltages
are available.
Initiating investigation into the source of the overvoltage fault
Shutting down critical systems in response to the overvoltage
Data recorders marking data during these events as
unreliable or out of specification
For systems that are sensitive during a start-up sequence, the
active low operation of the flag allows the system to ensure that
the ADG5412BF/ADG5413BF are powered on and that all
input voltages are within normal operating range before
initiating operation.
SIGNAL RANGE
The FF pin is a weak pull-up, which allows the signals to be
combined into a single interrupt for larger modules that contain
multiple devices.
The ADG5412BF/ADG5413BF switches have fault detection
circuitry on their inputs that compares the voltage levels at the
switch terminals with ꢀDD and ꢀSS, relative to ground. To protect
downstream circuitry from overvoltages, supply the ADG5412BF/
ADG5413BF by voltages that match the intended signal range.
The low on-resistance switch allows signals up to the supply
rails to be passed with very little distortion. A signal that
exceeds the supply rail by the threshold voltage is then blocked.
This offers protection to both the device and any downstream
circuitry.
The recovery time, tDIGREC, can be decreased from a typical 60 μs
to 600 ns by using a 1 kΩ pull-up resistor.
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 31 illustrates the voltage range and frequencies that the
ADG5412BF/ADG5413BF can reliably convey. For signals that
extend across the full signal range from ꢀSS to ꢀDD, keep the
frequency below 3 MHz. If the required frequency is greater
than 3 MHz, decrease the signal voltage appropriately to ensure
signal integrity.
LOW IMPEDANCE CHANNEL PROTECTION
The ADG5412BF/ADG5413BF can be used as protective
elements in signal chains that are sensitive to both channel
impedance and overvoltage signals. Traditionally, series
resistors are used to limit the current during an overvoltage
condition to protect susceptible components. These series
resistors affect the performance of the signal chain and reduce
the precision that can be reached. A compromise must be
reached on the value of the series resistance that is high enough
to sufficiently protect sensitive components but low enough that
the precision performance of the signal chain is not sacrificed.
Rev. B | Page 27 of 28
ADG5412BF/ADG5413BF
OUTLINE DIMENSIONS
Data Sheet
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 52. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
5
8
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG5412BFBRUZ
ADG5412BFBRUZ-RL7
ADG5412BFBCPZ-RL7
EVAL-ADG5412BFEBZ
ADG5413BFBRUZ
ADG5413BFBRUZ-RL7
ADG5413BFBCPZ-RL7
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RU-16
RU-16
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
CP-16-17
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
RU-16
RU-16
CP-16-17
1 Z = RoHS Compliant Part.
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D12473-0-1/16(B)
Rev. B | Page 28 of 28
相关型号：
ADG5412BFBCPZ-RL7
Bidirectional Fault Protection and Detection, 10 Ω RON, Quad SPST Switches
ADI
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