ADGS1612 [ADI]
SPI Interface, 1 Ω RON, ±5 V, 12 V, 5 V, 3.3 V, Mux Configurable, Quad SPST Switch;
| 型号： | ADGS1612 |
| 厂家： | 
ADI |
| 描述： | SPI Interface, 1 Ω RON, ±5 V, 12 V, 5 V, 3.3 V, Mux Configurable, Quad SPST Switch |
| 文件： | 总29页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPI Interface, 1 Ω RON, ± ± ꢀ, 1ꢁ ꢀ, ± ꢀ,
3.3 ꢀ, Mux Configurable, Quad SPST Switch
ADGS161ꢁ
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
SPI interface with error detection
Includes CRC, invalid read/write address, and SCLK count
error detection
Supports burst mode and daisy-chain mode
Industry-standard SPI Mode 0 and SPI Mode 3 interface
compatible
ADGS1612
S1
S2
D1
D2
S3
S4
D3
D4
Guaranteed break-before-make switching allowing external
wiring of switches to deliver multiplexer configurations
1 Ω typical on resistance at 25°C
0.23 Ω typical on resistance flatness at 25°C
V
SS to VDD analog signal range
SPI
SDO
INTERFACE
Fully specified at 5 V, 12 V, 5 V, and 3.3 V
3.3 V to 8 V dual-supply operation
3.3 V to 16 V single-supply operation
SCLK
SDI
CS
RESET/V
L
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
4 mm × 4 mm, 24-lead LFCSP package
Figure 1.
APPLICATIONS
Communication systems
Medical systems
Audio and video signal routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Relay replacements
signals. The ADGS1612 exhibits break-before-make switching
action for use in multiplexer applications. Note that throughout
GENERAL DESCRIPTION
The ADGS1612 contains four independent single-pole/single-
throw (SPST) switches. A serial peripheral interface (SPI) controls
the switches. The SPI interface has robust error detection features,
including cyclic redundancy check (CRC) error detection,
invalid read/write address detection, and serial clock (SCLK)
count error detection.
RESET
this data sheet, the multifunction pin,
/VL, is referred to
either by the entire pin name or by a single function of the pin,
for example, VL, when only that function is relevant.
PRODUCT HIGHLIGHTS
1. The SPI interface removes the need for parallel conversion
and logic traces and reduces general-purpose input/output
(GPIO) channel count.
2. Daisy-chain mode removes additional logic traces when
multiple devices are used.
It is possible to daisy-chain multiple ADGS1612 devices together.
Daisy-chaining enables the configuration of multiple devices with a
minimal amount of digital lines. The ADGS1612 can also operate
in burst mode to decrease the time between SPI commands.
3. CRC, invalid read/write address, and SCLK count error
detection ensure a robust digital interface.
4. CRC error detection capabilities allow the use of the
ADGS1612 in safety critical systems.
5. Guaranteed break-before-make switching allows the use of
the ADGS1612 in multiplexer configurations with external
wiring.
Each switch conducts equally well in both directions when on, and
each switch has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
The ultralow on resistance (RON) of these switches make them
ideal solutions for data acquisition and gain switching
applications where low RON and low distortion are critical. The
RON profile is very flat over the full analog input range, ensuring
excellent linearity and low distortion when switching audio
6. Minimum distortion.
Rev. 0
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ADGS161ꢁ
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Address Mode............................................................................. 22
Error Detection Features........................................................... 22
Clearing the Error Flags Register............................................. 23
Burst Mode.................................................................................. 23
Software Reset............................................................................. 23
Daisy-Chain Mode..................................................................... 23
Power-On Reset.......................................................................... 24
Applications Information.............................................................. 25
Break-Before-Make Switching.................................................. 25
Digital Input Buffers .................................................................. 25
Power Supply Rails..................................................................... 25
Register Summary .......................................................................... 26
Register Details ............................................................................... 27
Switch Data Register .................................................................. 27
Error Configuration Register.................................................... 27
Error Flags Register.................................................................... 28
Burst Enable Register................................................................. 28
Software Reset Register ............................................................. 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Dual Supply ......................................................................... 3
12 V Single Supply........................................................................ 5
5 V Single Supply.......................................................................... 7
3.3 V Single Supply....................................................................... 9
Continuous Current per Channel, Sx or Dx........................... 11
Timing Characteristics .............................................................. 11
Absolute Maximum Ratings.......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions........................... 14
Typical Performance Characteristics ........................................... 15
Test Circuits..................................................................................... 19
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 22
REVISION HISTORY
1/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 29
Data Sheet
ADGS161ꢁ
SPECIFICATIONS
5 V DUAL SUPPLY
Positive supply (VDD) = 5 V 1ꢀ0, negative supply (VSS) = −5 V 1ꢀ0, digital supply (VL) = 2.7 V to 5.5 V, GND = ꢀ V, unless otherwise noted.
Table 1.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
V
1
Ω typ
VS = ±±.ꢀ V, IS = −10 mA;
see Figure 29
1.2
0.0±
1.±
1.6
Ω max
Ω typ
VDD = +±.ꢀ V, VSS = −±.ꢀ V
VS = ±±.ꢀ V, IS = −10 mA
On Resistance Match Between
Channels, ∆RON
0.08
0.23
0.28
0.09
0.32
0.1
Ω max
Ω typ
Ω max
On Resistance Flatness, RFLAT (ON)
VS = ±±.ꢀ V, IS = −10 mA
0.37
LEAKAGE CURRENTS
VDD = +ꢀ.ꢀ V, VSS = −ꢀ.ꢀ V
Source Off Leakage, IS (Off)
±0.1
±0.3
±0.1
±0.3
±0.2
±0.±
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = ±±.ꢀ V, VD = ∓±.ꢀ V; see Figure 32
±1.0
±1.0
±1.ꢀ
±6.0
±6.0
±10.0
Drain Off Leakage, ID (Off)
VS = ±±.ꢀ V, VD = ∓±.ꢀ V; see Figure 32
Channel On Leakage, ID (On), IS (On)
VS = VD = ±±.ꢀ V; see Figure 28
DIGITAL OUTPUT
Output Voltage
Low, VOL
0.±
0.2
V max
V max
μA typ
μA max
pF typ
ISINK = ꢀ mA
ISINK = 1 mA
VOUT = VGND or VL
Output Current, Low (IOL) or High (IOH)
0.001
±
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ ꢀ.ꢀ V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ ꢀ.ꢀ V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.3ꢀ
0.8
0.8
Low, VINL
V max
V max
μA typ
μA max
pF typ
Input Current, Low (IINL) or High (IINH
)
0.001
±
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
On Time, tON
38ꢀ
±80
2ꢀ0
30ꢀ
17ꢀ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 3ꢀ pF
VS = 2.ꢀ V; see Figure 36
RL = 300 Ω, CL = 3ꢀ pF
VS = 2.ꢀ V; see Figure 36
RL = 300 Ω, CL = 3ꢀ pF
VS1 = VS2 = 2.ꢀ V, see Figure 3ꢀ
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 37
RL = ꢀ0 Ω, CL = ꢀ pF, f = 100 kHz; see
Figure 31
±8ꢀ
33ꢀ
±8ꢀ
360
11ꢀ
Off Time, tOFF
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
120
−6ꢀ
−93
dB typ
dB typ
Channel to Channel Crosstalk
RL = ꢀ0 Ω, CL = ꢀ pF, f = 1 MHz; see
Figure 30
Rev. 0 | Page 3 of 29
ADGS161ꢁ
Data Sheet
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
Total Harmonic Distortion Plus Noise,
THD + N
0.007
% typ
RL = 110 Ω, ꢀ V p-p, f = 20 Hz to
20 kHz; see Figure 33
−3 dB Bandwidth
Insertion Loss
3±
−0.08
MHz typ RL = ꢀ0 Ω, CL = ꢀ pF; see Figure 3±
dB typ
RL = ꢀ0 Ω, CL = ꢀ pF, f = 1 MHz; see
Figure 3±
Off Switch Source Capacitance,
CS (Off)
63
pF typ
VS = 0 V, f = 1 MHz
Off Switch Drain Capacitance, CD (Off) 63
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +ꢀ.ꢀ V, VSS = −ꢀ.ꢀ V
All switches open
On Switch Capacitance, CD (On), CS (On)
POWER REQUIREMENTS
1ꢀ±
Positive Supply Current, IDD
0.01
0.01
130
μA typ
μA max
μA typ
μA max
μA typ
μA max
1
All switches closed, VL = ꢀ.ꢀ V
All switches closed, VL = 2.7 V
1
220
Digital Supply Current, IL
Inactive
6.3
μA typ
μA max
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
mA typ
Digital inputs = 0 V or VL
8.0
Inactive, SCLK = 1 MHz
SCLK = ꢀ0 MHz
1±
CS = VL and SDI = 0 V or VL, VL = ꢀ V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS = VL and SDI = 0 V or VL, VL = ꢀ V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = ꢀ V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = ꢀ V
CS and SCLK = 0 V or VL, VL = 3 V
7
390
210
1ꢀ
Inactive, SDI = 1 MHz
SDI = 2ꢀ MHz
7.ꢀ
230
120
1.8
Active at ꢀ0 MHz
Digital inputs toggle between 0 V
and VL, VL = ꢀ.ꢀ V
2.1
1.0
mA max
mA typ
0.7
Digital inputs toggle between 0 V
and VL, VL = 2.7 V
mA max
μA typ
μA max
V min
Negative Supply Current, ISS
VDD/VSS
0.01
Digital inputs = 0 V or VL
1
±3.3
±8
GND = 0 V
GND = 0 V
V max
Rev. 0 | Page ± of 29
Data Sheet
ADGS161ꢁ
12 V SINGLE SUPPLY
VDD = 12 V 1ꢀ0, VSS = ꢀ V, VL = 2.7 V to 5.5 V, GND = ꢀ V, unless otherwise noted.
Table 2.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
1.±ꢀ
V
0.9ꢀ
Ω typ
VS = 0 V to 10 V, IS = −10 mA;
see Figure 29
VDD = 10.8 V, VSS = 0 V
1.1
0.03
1.2ꢀ
Ω max
Ω typ
On Resistance Match Between Channels,
∆RON
VS = 0 V to 10 V, IS = −10 mA
0.06
0.2
0.23
0.07
0.27
0.08
0.32
Ω max
Ω typ
Ω max
On Resistance Flatness, RFLAT (ON)
VS = 0 V to 10 V, IS = −10 mA
VDD = 10.8 V, VSS = 0 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.1
nA typ
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 32
±0.3
±0.1
±1.0
±6.0
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 32
±0.3
±0.2
±0.±
±1.0
±1.ꢀ
±6.0
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/10 V; see Figure 28
±10.0
DIGITAL OUTPUT
Output Voltage
Low, VOL
0.±
0.2
V max
V max
μA typ
μA max
pF typ
ISINK = ꢀ mA
ISINK = 1 mA
VOUT = VGND or VL
Output Current, Low (IOL) or High (IOH)
0.001
±
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ ꢀ.ꢀ V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ ꢀ.ꢀ V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.3ꢀ
0.8
0.8
Low, VINL
V max
V max
μA typ
μA max
pF typ
Input Current, Low (IINL) or High (IINH
)
0.001
±
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
On Time, tON
36ꢀ
±60
190
23ꢀ
200
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 3ꢀ pF
VS = 8 V; see Figure 36
RL = 300 Ω, CL = 3ꢀ pF
VS = 8 V; see Figure 36
RL = 300 Ω, CL = 3ꢀ pF
VS1 = VS2 = 8 V, see Figure 3ꢀ
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 37
RL = ꢀ0 Ω, CL = ꢀ pF, f = 100 kHz;
see Figure 31
±70
260
±70
280
1±0
Off Time, tOFF
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
1±0
−6ꢀ
−93
dB typ
dB typ
Channel to Channel Crosstalk
RL = ꢀ0 Ω, CL = ꢀ pF, f = 1 MHz; see
Figure 30
Rev. 0 | Page ꢀ of 29
ADGS161ꢁ
Data Sheet
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
Total Harmonic Distortion Plus Noise,
THD + N
0.012
% typ
RL = 110 Ω, ꢀ V p-p, f = 20 Hz to
20 kHz; see Figure 33
−3 dB Bandwidth
Insertion Loss
3±
−0.07
MHz typ
MHz typ
RL = ꢀ0 Ω, CL = ꢀ pF; see Figure 3±
RL = ꢀ0 Ω, CL = ꢀ pF, f = 1 MHz; see
Figure 3±
Off Switch Source Capacitance, CS (Off) 60
dB typ
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 12 V
Off Switch Drain Capacitance, CD (Off)
On Switch Capacitance, CD (On), CS (On)
POWER REQUIREMENTS
60
1ꢀ±
Positive Supply Current, IDD
0.01
320
320
μA typ
μA max
μA typ
μA max
μA typ
μA max
All switches open
1
All switches closed, VL = ꢀ.ꢀ V
All switches closed, VL = 2.7 V
±80
±80
Digital Supply Current, IL
Inactive
6.3
1±
7
μA typ
μA max
μA typ
Digital inputs = 0 V or VL
8.0
Inactive, SCLK = 1 MHz
CS = VL and SDI = 0 V or VL,
VL = ꢀ V
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS = VL and SDI = 0 V or VL,
VL = ꢀ V
μA typ
μA typ
SCLK = ꢀ0 MHz
390
210
1ꢀ
μA typ
μA typ
μA typ
μA typ
μA typ
mA typ
CS = VL and SDI = 0 V or VL, VL = 3 V
Inactive, SDI = 1 MHz
SDI = 2ꢀ MHz
CS and SCLK = 0 V or VL, VL = ꢀ V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = ꢀ V
CS and SCLK = 0 V or VL, VL = 3 V
7.ꢀ
230
120
1.8
Active at ꢀ0 MHz
Digital inputs toggle between 0 V
and VL, VL = ꢀ.ꢀ V
2.1
mA max
mA typ
0.7
Digital inputs toggle between 0 V
and VL, VL = 2.7 V
1.0
3.3
16
mA max
V min
V max
VDD
GND = 0 V, VSS = 0 V
GND = 0 V, VSS = 0 V
Rev. 0 | Page 6 of 29
Data Sheet
ADGS161ꢁ
5 V SINGLE SUPPLY
VDD = 5 V 1ꢀ0, VSS = ꢀ V, VL = 2.7 V to 5.5 V, GND = ꢀ V, unless otherwise noted.
Table 3.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
2.7
V
1.7
Ω typ
VS = 0 V to ±.ꢀ V, IS = −10 mA; see
Figure 29
VDD = ±.ꢀ V, VSS = 0 V
2.1ꢀ
0.0ꢀ
2.±
Ω max
Ω typ
On Resistance Match Between Channels,
∆RON
VS = 0 V to ±.ꢀ V, IS = −10 mA
0.09
0.±
0.ꢀ3
0.12
0.ꢀꢀ
0.1ꢀ
0.6
Ω max
Ω typ
Ω max
On Resistance Flatness, RFLAT (ON)
VS = 0 V to ±.ꢀ V, IS = −10 mA
VDD = ꢀ.ꢀ V, VSS = 0 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.1
nA typ
VS = 1 V or ±.ꢀ V, VD = ±.ꢀ V/1 V;
see Figure 32
±0.3
±0.1
±1.0
±6.0
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/±.ꢀ V, VD = ±.ꢀ V/1 V; see
Figure 32
±0.3
±0.2
±0.±
±1.0
±1.ꢀ
±6.0
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/±.ꢀ V; see Figure 28
±10.0
DIGITAL OUTPUT
Output Voltage
Low, VOL
0.±
0.2
V max
V max
μA typ
μA max
pF typ
ISINK = ꢀ mA
ISINK = 1 mA
VOUT = VGND or VL
Output Current, Low (IOL) or High (IOH)
0.001
±
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ ꢀ.ꢀ V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ ꢀ.ꢀ V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.3ꢀ
0.8
0.8
Low, VINL
V max
V max
μA typ
μA max
pF typ
Input Current, Low (IINL) or High (IINH
)
0.001
±
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
On Time, tON
±0ꢀ
ꢀ10
290
36ꢀ
16ꢀ
ns typ
ns max
ns typ
Ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 3ꢀ pF
VS = 2.ꢀ V; see Figure 36
RL = 300 Ω, CL = 3ꢀ pF
VS = 2.ꢀ V; see Figure 36
RL = 300 Ω, CL = 3ꢀ pF
VS1 = VS2 = 2.ꢀ V, see Figure 3ꢀ
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 37
RL = ꢀ0 Ω, CL = ꢀ pF, f = 100 kHz; see
Figure 31
ꢀ1ꢀ
±10
ꢀ2ꢀ
±ꢀꢀ
9ꢀ
Off Time, tOFF
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
72
−6ꢀ
−93
dB typ
dB typ
Channel to Channel Crosstalk
RL = ꢀ0 Ω, CL = ꢀ pF, f = 1 MHz; see
Figure 30
Rev. 0 | Page 7 of 29
ADGS161ꢁ
Data Sheet
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
Total Harmonic Distortion Plus Noise,
THD + N
0.093
% typ
RL = 110 Ω, f = 20 Hz to 20 kHz,
VS = 3.ꢀ V p-p ; see Figure 33
−3 dB Bandwidth
Insertion Loss
38
−0.1ꢀ
MHz typ
dB typ
RL = ꢀ0 Ω, CL = ꢀ pF; see Figure 3±
RL = ꢀ0 Ω, CL = ꢀ pF, f = 1 MHz; see
Figure 3±
Off Switch Source Capacitance, CS (Off) 72
Off Switch Drain Capacitance, CD (Off) 72
On Switch Capacitance, CD (On), CS (On) 160
POWER REQUIREMENTS
pF typ
pF typ
pF typ
VS = 2.ꢀ V, f = 1 MHz
VS = 2.ꢀ V, f = 1 MHz
VS = 2.ꢀ V, f = 1 MHz
VDD = ꢀ.ꢀ V
Positive Supply Current, IDD
0.01
0.01
130
μA typ
μA max
μA typ
μA max
μA typ
μA max
All switches open
1
All switches closed, VL = ꢀ.ꢀ V
All switches closed, VL = 2.7 V
1
220
Digital Supply Current, IL
Inactive
6.3
1±
μA typ
μA max
μA typ
Digital inputs = 0 V or VL
8.0
Inactive, SCLK = 1 MHz
CS = VL and SDI = 0 V or VL,
VL = ꢀ V
7
μA typ
μA typ
μA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS = VL and SDI = 0 V or VL,
VL = ꢀ V
CS = VL and SDI = 0 V or VL,
VL = 3 V
SCLK = ꢀ0 MHz
390
210
Inactive, SDI = 1 MHz
SDI = 2ꢀ MHz
1ꢀ
μA typ
μA typ
μA typ
μA typ
mA typ
CS and SCLK = 0 V or VL, VL = ꢀ V
7.ꢀ
230
120
1.8
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = ꢀ V
CS and SCLK = 0 V or VL, VL = 3 V
Active at ꢀ0 MHz
Digital inputs toggle between 0 V
and VL, VL = ꢀ.ꢀ V
2.1
mA max
mA typ
0.7
Digital inputs toggle between 0 V
and VL, VL = 2.7 V
1.0
3.3
16
mA max
V min
V max
VDD
GND = 0 V, VSS = 0 V
GND = 0 V, VSS = 0 V
Rev. 0 | Page 8 of 29
Data Sheet
ADGS161ꢁ
3.3 V SINGLE SUPPLY
VDD = 3.3 V, VSS = ꢀ V, VL = 2.7 V to 3.3 V, GND = ꢀ V, unless otherwise noted.
Table 4.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
3.6
V
3.2
3.±
Ω typ
VS = 0 V to VDD, IS = −10 mA, VDD =
3.3 V, VSS = 0 V; see Figure 29
On Resistance Match Between Channels,
∆RON
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
0.06
1.2
0.07
1.3
0.08
1.±
Ω typ
Ω typ
VS = 0 V to VDD, IS = −10 mA
VS = 0 V to VDD, IS = −10 mA
VDD = 3.3 V, VSS = 0 V
Source Off Leakage, IS (Off)
±0.1
nA typ
VS = 0.6 V/3 V, VD = 3 V/0.6 V; see
Figure 32
±0.3
±0.1
±1.0
±6.0
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 0.6 V/3 V, VD = 3 V/0.6 V; see
Figure 32
±0.3
±0.2
±0.±
±1.0
±1.ꢀ
±6.0
nA max
V max
Channel On Leakage, ID (On), IS (On)
VS = VD = 0.6 V/3 V; see Figure 28
±10.0
DIGITAL OUTPUT
Output Voltage
Low, VOL
0.±
0.2
V max
V max
μA typ
μA max
pF typ
ISINK = ꢀ mA
ISINK = 1 mA
VOUT = VGND or VL
Output Current, Low (IOL) or High (IOH)
0.001
±
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, Low (IINL) or High (IINH
1.3ꢀ
0.8
V min
V max
μA typ
μA max
pF typ
)
0.001
±
VIN = VGND or VL
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
On Time, tON
ꢀ±ꢀ
720
±70
630
1ꢀꢀ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 3ꢀ pF
VS = 1.ꢀ V; see Figure 36
RL = 300 Ω, CL = 3ꢀ pF
VS = 1.ꢀ V; see Figure 36
RL = 300 Ω, CL = 3ꢀ pF
VS1 = VS2 = 1.ꢀ V, see Figure 3ꢀ
730
69ꢀ
73ꢀ
760
ꢀ0
Off Time, tOFF
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
ꢀ0
VS = 1.ꢀ V, RS = 0 Ω, CL = 1 nF; see
Figure 37
Off Isolation
Channel to Channel Crosstalk
−6ꢀ
−93
dB typ
dB typ
CL = ꢀ pF, f = 100 kHz; see Figure 31
RL = ꢀ0 Ω, CL = ꢀ pF, f = 1 MHz; see
Figure 30
Total Harmonic Distortion Plus Noise,
THD + N
0.18
% typ
RL = 110 Ω, f = 20 Hz to 20 kHz,
VS = 2 V p-p; see Figure 33
−3 dB Bandwidth
Insertion Loss
ꢀ0
−0.27
MHz typ
dB typ
RL = ꢀ0 Ω, CL = ꢀ pF; see Figure 3±
RL = ꢀ0 Ω, CL = ꢀ pF, f = 1 MHz; see
Figure 3±
Off Switch Source Capacitance, CS (Off) 76
Off Switch Drain Capacitance, CD (Off) 76
On Switch Capacitance, CD (On), CS (On) 160
pF typ
pF typ
pF typ
VS = 1.ꢀ V, f = 1 MHz
VS = 1.ꢀ V, f = 1 MHz
VS = 1.ꢀ V, f = 1 MHz
Rev. 0 | Page 9 of 29
ADGS161ꢁ
Data Sheet
Parameter
25°C
0.01
0.01
−40°C to +85°C −40°C to +125°C Unit
μA typ
Test Conditions/Comments
POWER REQUIREMENTS
Positive Supply Current, IDD
VDD = 3.3 V
All switches open
1
μA max
μA typ
μA max
All switches closed, VL = 3.3 V
Digital inputs = 0 V or VL
1
Digital Supply Current, IL
Inactive
3.2
7
μA typ
μA max
μA typ
±.8
Inactive, SCLK = 1 MHz
SCLK = ꢀ0 MHz
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS = VL and SDI = 0 V or VL,
VL = 3 V
210
μA typ
Inactive, SDI = 1 MHz
SDI = 2ꢀ MHz
7.ꢀ
120
0.7
μA typ
μA typ
mA typ
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 3 V
Active at ꢀ0 MHz
Digital inputs toggle between 0 V
and VL, VL = 2.7 V
1.0
3.3
16
mA max
V min
V max
VDD
GND = 0 V, VSS = 0 V
GND = 0 V, VSS = 0 V
Rev. 0 | Page 10 of 29
Data Sheet
ADGS161ꢁ
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5. Four Channels On
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR Dx
VDD = +ꢀ V, VSS = −ꢀ V (θJA = 60°C/W)
VDD = 12 V, VSS = 0 V (θJA = 60°C/W)
VDD = ꢀ V, VSS = 0 V (θJA = 60°C/W)
VDD = 3.3 V, VSS = 0 V (θJA = 60°C/W)
31ꢀ
330
2±9
203
19±
200
161
137
106
108
96
mA max
mA max
mA max
mA max
87
Table 6. One Channel On
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR Dx
VDD = +ꢀ V, VSS = −ꢀ V (θJA = 60°C/W)
VDD = 12 V, VSS = 0 V (θJA = 60°C/W)
VDD = ꢀ V, VSS = 0 V (θJA = 60°C/W)
VDD = 3.3 V, VSS = 0 V (θJA = 60°C/W)
ꢀ66
ꢀ91
±ꢀ0
366
292
301
2ꢀ1
218
126
127
120
113
mA max
mA max
mA max
mA max
TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V; GND = ꢀ V; all specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter
Limit at TMIN, TMAX
Unit
Description
t1
t2
t3
t±
tꢀ
t6
t7
t8
20
8
8
10
6
8
10
20
20
20
20
8
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
SCLK period
SCLK high pulse width
SCLK low pulse width
CS falling edge to SCLK rising edge
Data setup time
Data hold time
SCLK active edge to CS rising edge
CS falling edge to SDO data available
SCLK falling edge to SDO data available
CS rising edge to SDO returns to high impedance
CS high time between SPI commands
CS falling edge to SCLK becomes stable
CS rising edge to SCLK becomes stable
1
t9
t10
t11
t12
t13
8
1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. The t9 parameter determines the maximum SCLK frequency when SDO is used.
Rev. 0 | Page 11 of 29
ADGS161ꢁ
Data Sheet
Timing Diagrams
t1
SCLK
CS
t2
t7
t4
t3
t6
t5
SDI
R/W
A6
A5
1
D2
D2
D1
D1
D0
D0
t10
t9
SDO
0
0
t8
Figure 2. Addressable Mode Timing Diagram
t1
SCLK
CS
t2
t3
t4
t7
t6
t5
SDI
D7
D6
D0
D7
D6
D1
D0
INPUT BYTE FOR DEVICE N
t9
INPUT BYTE FOR DEVICE N + 1
t10
SDO
0
0
0
D7
D6
D1
D0
ZERO BYTE
INPUT BYTE FOR DEVICE N
t8
Figure 3. Daisy-Chain Timing Diagram
t11
CS
SCLK
t13
t12
CS
Figure 4. SCLK/ Timing Diagram
Rev. 0 | Page 12 of 29
Data Sheet
ADGS161ꢁ
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 8.
Parameter
Rating
VDD to VSS
18 V
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
VDD to GND
VSS to GND
RESET/VL to GND
VDD ≤ ꢀ.ꢀ V
VDD > ꢀ.ꢀ V
Analog Inputs1
−0.3 V to +18 V
+0.3 V to −18 V
−0.3V to VDD + 0.3 V
−0.3 V to +6 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
−0.3 V to +6 V
Table 9. Thermal Resistance
Package Type
CP-2±-171
θJA
θJC
Unit
60
13
°C/W
Digital Inputs1
Peak Current, Sx or Dx Pins2
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESDꢀ1.
ꢀ±6 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current, Sx or Dx2, 3 Data + 1ꢀ%
Temperature Ranges
ESD CAUTION
Operating
−±0°C to +12ꢀ°C
Storage
Junction Temperature
−6ꢀ°C to +1ꢀ0°C
1ꢀ0°C
Reflow Soldering Peak
Temperature, Pb-Free
260°C
1 Overvoltages at the digital, Sx, and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2 Sx refers to the S1 to S± pins, and Dx refers to the D1 to D± pins.
3 See Table ꢀ and Table 6.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
Rev. 0 | Page 13 of 29
ADGS161ꢁ
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
18
17
16
15
14
13
D1
S1
D2
S2
ADGS1612
NIC
V
SS
TOP VIEW
V
GND 4
DD
(Not to Scale)
5
6
S4
D4
S3
D3
NOTES
1. THE EXPOSED PAD IS CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY
OF THE SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE EXPOSED PAD BE SOLDEREDTO
THE SUBSTRATE, V
.
SS
2. NIC = NOT INTERNALLY CONNECTED.
Figure 5. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
±, 11
ꢀ
6
D1
S1
VSS
GND
S±
D±
NIC
Drain Terminal 1. This pin can be an input or an output.
Source Terminal 1. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
Ground (0 V) Reference.
Source Terminal ±. This pin can be an input or an output.
Drain Terminal ±. This pin can be an input or an output.
Not Internally Connected. These pins are not internally connected.
7, 8, 10, 12,
16, 19, 2±
9
RESET/VL
Reset/Logic Power Supply Input. Under normal operation, drive the RESET/VL pin with a 2.7 V to ꢀ.ꢀ V supply.
Pull the pin low to complete a hardware reset. All switches are opened, and the appropriate registers are set
to their default settings.
13
1±
1ꢀ
17
18
20
D3
S3
VDD
S2
D2
SDO
Drain Terminal 3. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Most Positive Power Supply Potential.
Source Terminal 2. This pin can be an input or an output.
Drain Terminal 2. This pin can be an input or an output.
Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
21
CS
Active Low Control Input. CS is the frame synchronization signal for the input data. When CS goes low, it
powers on the SCLK buffers and enables the input shift register. Data is transferred in on the falling edges of
the following clocks. Taking CS high updates the switch condition.
22
23
SCLK
SDI
Serial Clock Input. Data is captured on the positive edge of SCLK. Data is transferred at rates of up to ꢀ0 MHz.
Serial Data Input. Data is captured on the positive edge of the serial clock input.
EPAD
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.
Rev. 0 | Page 1± of 29
Data Sheet
ADGS161ꢁ
TYPICAL PERFORMANCE CHARACTERISTICS
1.4
1.2
1.0
0.8
0.6
0.4
1.4
V
V
= 12V
= 0V
T
T
= +125°C
= +85°C
T
T
= +25°C
= –40°C
DD
SS
A
A
A
A
1.2
1.0
0.8
0.6
T
= 25°C
DD
V
V
= +3.3V,V = –3.3V
SS
= +8V, V = –8V
SS
A
DD
DD
V
= +5V, V = –5V
SS
0.4
–8
0
2
4
6
8
10
12
–6
–4
–2
0
2
4
6
8
V
OR V VOLTAGE (V)
D
V
OR V VOLTAGE (V)
S
S
D
Figure 9. On Resistance (RON) as a Function of VS (VD) for Various
Temperatures, 12 V Single Supply
Figure 6. On Resistance (RON) as a Function of VS, VD (Dual Supply)
3.5
2.5
V
V
= 5V
= 0V
T
T
= +125°C
= +85°C
T
T
= +25°C
= –40°C
T
= 25°C
DD
SS
A
A
A
A
A
V
V
V
V
= 16V, V = 0V
DD
SS
3.0
2.5
2.0
1.5
1.0
0.5
= 12V, V = 0V
= 5V, V = 0V
= 3.3V, V = 0V
DD
DD
DD
SS
SS
SS
2.0
1.5
1.0
0
2
4
6
8
10
12
14
16
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
OR V VOLTAGE (V)
V OR V VOLTAGE (V)
S D
S
D
Figure 7. On Resistance (RON) as a Function of VS, VD (Single Supply)
Figure 10. On Resistance (RON) as a Function of VS (VD) for Various
Temperatures, 5 V Single Supply
1.4
2.5
V
V
= 5V
= 0V
T
T
= +125°C
= +85°C
T
T
= +25°C
= –40°C
DD
SS
A
A
A
A
1.2
1.0
0.8
0.6
2.0
1.5
1.0
T
T
T
T
= +125°C
= +85°C
= +25°C
= –40°C
A
A
A
A
V
V
= +5V
= –5V
DD
SS
0.4
–6
–4
–2
0
2
4
6
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
S
OR V VOLTAGE (V)
D
V
OR V VOLTAGE (V)
D
S
Figure 8. On Resistance (RON) as a Function of VS (VD) for Various
Temperatures, 5 V Dual Supply
Figure 11. On Resistance (RON) as a Function of VS (VD) for Various
Temperatures, 3.3 V Single Supply
Rev. 0 | Page 1ꢀ of 29
ADGS161ꢁ
Data Sheet
20
15
10
5
18
16
14
12
10
8
+I (ON), +I (ON)
D
S
+I (OFF), +I (OFF)
D
S
–I (OFF), +I (OFF)
D
S
D
S
S
S
–I (OFF), –I (OFF)
D
D
S
D
S
S
+I (OFF), –I (OFF)
–I (OFF), +I (OFF)
–I (ON), –I (ON)
D
+I (OFF), –I (OFF)
S
–I (OFF), +I (OFF)
S
–I (OFF), +I (OFF)
S
+I (OFF), –I (OFF)
D
D
+I (OFF), –I (OFF)
D
D
6
0
4
–5
–10
2
0
–2
–4
–15
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Leakage Current vs. Temperature, 3.3 V Single Supply
Figure 12. Leakage Current vs. Temperature, 5 V Dual Supply
0
25
T
V
V
= 25°C
= +5V
SS
+I (ON), +I (ON)
A
DD
D
S
–I (OFF), +I (OFF)
20
15
D
S
D
S
S
S
= –5V
–20
–40
+I (OFF), –I (OFF)
–I (ON), –I (ON)
D
–I (OFF), +I (OFF)
S
+I (OFF), –I (OFF)
D
D
10
–60
5
0
–80
–5
–100
–120
–140
–10
–15
–20
0
20
40
60
80
100
120
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 13. Leakage Current vs. Temperature, 12 V Single Supply
Figure 16. Off Isolation vs. Frequency, 5 V Dual Supply
20
0
–20
T
= 25°C
DD
SS
A
+I (OFF), +I (OFF)
D
S
V
V
= +5V
= –5V
–I (OFF), –I (OFF)
D
D
S
D
S
S
–I (OFF), +I (OFF)
15
10
5
+I (OFF), –I (OFF)
S
–40
–I (OFF), +I (OFF)
S
+I (OFF), –I (OFF)
D
D
–60
–80
–100
–120
–140
–160
0
–5
0
20
40
60
80
100
120
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 17. Crosstalk vs. Frequency, 5 V Dual Supply
Figure 14. Leakage Current vs. Temperature, 5 V Single Supply
Rev. 0 | Page 16 of 29
Data Sheet
ADGS161ꢁ
300
0
–1
–2
–3
–4
–5
–6
T
= 25°C
A
V
V
V
V
= 12.0V, V = 0V
DD
DD
DD
DD
SS
= 5V, V = –5V
SS
250
200
150
100
50
= 5V, V = 0V
SS
SS
= 3.3V, V = 0V
T
= 25°C
DD
A
V
= +5V
0
–6
–4
–2
0
2
4
6
8
10
12
14
1k
10k
100k
1M
10M
100M
1G
V
(V)
FREQUENCY (Hz)
S
Figure 18. Charge Injection vs. Source Voltage, VS
Figure 21. Bandwidth
600
500
400
300
200
100
0
5.5V DUAL SUPPLY, tON
13.2V SINGLE SUPPLY, tON
5.5V SINGLE SUPPLY, tON
0
–10
WITH 10µF AND 100nF DECOUPLING CAP
WITH 100nF DECOUPLING CAP
WITHOUT DECOUPLING CAP
–20
–30
–40
–50
–60
–70
–80
5.5V DUAL SUPPLY, tOFF
13.2V SINGLE SUPPLY, tOFF
5.5V SINGLE SUPPLY, tOFF
–90
–100
–110
–120
T
V
V
= 25°C
DD
SS
A
= +5V
= –5V
–40
25
60
85
125
TEMPERATURE (°C)
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 19. AC Power Supply Power Rejection Ratio (AC PSRR) vs. Frequency,
5 V Dual Supply
Figure 22. tON, tOFF Times vs. Temperature, VL = 5.5 V
0.20
0.18
600
500
400
300
200
100
0
3.3V SINGLE SUPPLY, tON
3.3V SINGLE SUPPLY, tOFF
R
V
V
V
V
= 110Ω, T = 25°C
L
A
= +12.0V, V = 5V p-p
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
DD
DD
DD
DD
S
= +5V , V = –5V, V = 5V p-p
SS S
= +5V, V = 3.5V
S
= +3.3V, V = 2V
S
0
5k
10k
FREQUENCY (Hz)
15k
20k
–40
25
60
85
125
TEMPERATURE (°C)
Figure 20. THD + N vs. Frequency, 5 V Dual Supply
Figure 23. tON, tOFF Times vs. Temperature, VL = 3.3 V
Rev. 0 | Page 17 of 29
ADGS161ꢁ
Data Sheet
100
90
80
70
60
50
40
30
20
10
0
2.0
1.5
SCLK = 2.5MHz
SCLK IDLE
1.0
0.5
0
T
= 25°C
DD
SS
A
V
V
= +5V
= –5V
–0.5
–1.0
–1.5
–2.0
–2.5
12.0V SINGLE SUPPLY
5.0V DUAL SUPPLY
5.0V SINGLE SUPPLY
3.3V SINGLE SUPPLY
T
= 25°C
DD
SS
A
V
V
= +5V
= –5V
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
TIME (µs)
V
(V)
L
Figure 26. Digital Feedthrough
Figure 24. IDD vs. VL
180
160
140
120
100
80
450
T
= 25°C
A
400
350
300
250
200
150
100
50
60
T
= 25°C
DD
SS
A
V
V
= +5V
= –5V
40
C
C
C
OFF
OFF
S
S
D
D
20
V
V
= 5V
= 3V
L
L
/C ON
0
–5
0
–4
–3
–2
–1
0
1
2
3
4
5
0
10
20
30
40
50
SOURCE VOLTAGE
SCLK FREQUENCY (MHz)
Figure 27. Source/Drain Capacitance vs. Source Voltage (VS)
CS
Figure 25. IL vs. SCLK Frequency When Is High
Rev. 0 | Page 18 of 29
Data Sheet
ADGS161ꢁ
TEST CIRCUITS
I
(ON)
A
I
(OFF)
A
I
D
(OFF)
A
D
S
Sx
Dx
Sx
Dx
NC
V
V
D
V
D
S
NC = NO CONNECT
Figure 28. On Leakage
Figure 32. Off Leakage
V
V
DD
SS
0.1µF
0.1µF
AUDIO PRECISION
V
V
DD
SS
R
S
I
DS
Sx
50Ω
V p-p
V
S
V1
Dx
V
OUT
R
1kΩ
L
Sx
Dx
GND
V
S
R
= V1/I
DS
ON
Figure 33. THD + N
Figure 29. On Resistance
V
V
V
V
V
V
DD
SS
DD
SS
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
DD
DD
SS
V
NC
OUT
S1
D1
R
L
50Ω
Sx
Dx
50Ω
V
S
D2
S2
R
50Ω
L
V
S
V
OUT
R
GND
L
50Ω
GND
V
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
WITH SWITCH
OUT
S
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 30. Channel to Channel Crosstalk
Figure 34. Bandwidth
V
V
SS
DD
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
Sx
50Ω
V
S
Dx
V
OUT
R
L
50Ω
GND
V
OUT
OFF ISOLATION = 20 log
V
S
Figure 31. Off Isolation
Rev. 0 | Page 19 of 29
ADGS161ꢁ
Data Sheet
V
V
V
V
DD
DD
SS
SS
0.1µF
0.1µF
SCLK
50%
50%
0V
0V
80%
80%
V
OUT1
S1
S2
D1
D2
V
V
S1
S2
V
OUT1
R
300ꢀ
C
L1
35pF
L1
V
OUT2
R
300ꢀ
C
L2
35pF
L
80%
80%
INPUT LOGIC
GND
V
OUT2
0V
t
t
D
D
Figure 35. Break-Before-Make Time Delay, tD
V
V
V
V
DD
DD
SS
SS
0.1µF
0.1µF
SCLK
V
OUT
50%
50%
Sx
Dx
R
300ꢀ
C
L
35pF
L
90%
V
S
V
INPUT LOGIC
GND
OUT
10%
tON
tOFF
Figure 36. Switching Times
V
V
V
DD
DD
SS
SS
3V
V
SYNC
R
V
S
S
D
V
OUT
C
1nF
L
S
Q
= C × ∆V
L OUT
INJ
INPUT LOGIC
GND
V
OUT
∆V
OUT
SWITCH OFF
SWITCH ON
Figure 37. Charge Injection
V
SS
NETWORK
ANALYZER
V
V
DD
SS
INTERNAL
BIAS
R
L
50ꢀ
V
S
V
NIC
OUT
R
S1
D1
L
50ꢀ
GND
V
OUT
AC PSRR = 20 log
V
S
NOTES
1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED
FROM THE AC PSRR MEASUREMENT.
Figure 38. AC PSRR
Rev. 0 | Page 20 of 29
Data Sheet
ADGS161ꢁ
TERMINOLOGY
IDD
CD (On), CS (On)
IDD is the positive supply current.
CD (On) and CS (On) are the on switch capacitances, measured
with reference to ground.
ISS
I
SS is the negative supply current.
CIN
CIN is the digital input capacitance.
VD, VS
VD and VS are the analog voltages on Terminal D and Terminal
tON
S, respectively.
tON is the delay between applying the digital control input and
the output switching on.
RON
RON is the ohmic resistance between Terminal D and Terminal
S.
tOFF
tOFF is the delay between applying the digital control input and
the output switching off.
ΔRON
ΔRON is the difference between the RON of any two channels.
tD
tD is the off time measured between the 8ꢀ0 point of both
switches when switching from one address state to another.
RFLAT (ON)
RFLAT (ON) is the difference between the maximum and minimum
values of on resistance, measured over the specified analog
Off Isolation
signal range.
Off isolation is a measure of unwanted signal coupling through
an off switch.
IS (Off)
IS (Off) is the source leakage current with the switch off.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
Crosstalk
ID (On), IS (On)
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
ID (On) and IS (On) are the channel leakage currents with the
switch on.
IDS
Bandwidth
IDS is the drain to source current.
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
V1
V1 is the voltage drop across the switch, Sx, to Dx.
On Response
VINL
On response is the frequency response of the on switch.
VINL is the maximum input voltage for Logic ꢀ.
Insertion Loss
VINH
Insertion loss is the loss due to the on resistance of the switch.
VINH is the minimum input voltage for Logic 1.
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
IINL, IINH
I
INL and IINH is the low and high input currents of the digital
inputs.
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. AC PSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
ꢀ.62 V p-p.
CD (Off)
CD (Off) is the off switch drain capacitance, which is measured
with reference to ground.
CS (Off)
CS (Off) is the off switch source capacitance, which is measured
with reference to ground.
Rev. 0 | Page 21 of 29
ADGS161ꢁ
Data Sheet
THEORY OF OPERATION
The ADGS1612 is a set of serially controlled, quad SPST switches
with error detection features. SPI Mode ꢀ and SPI Mode 3 can
be used with the device, and it operates with SCLK frequencies
of up to 5ꢀ MHz. The default mode for the ADGS1612 is address
mode, in which the registers of the device are accessed by a 16-bit
reads. A register write occurs on the 16th SCLK rising edge
during SPI writes.
During any SPI command, SDO sends out eight alignment bits
on the first eight SCLK falling edges. The alignment bits observed
at SDO are ꢀx25.
CS
SPI command bounded by . The SPI command becomes 24-bit
ERROR DETECTION FEATURES
if the user enables CRC error detection. Other error detection
features include SCLK count error and invalid read/write error. If
any of these SPI interface errors occur, they are detectable by
reading the error flags register. The ADGS1612 can also operate
in two other modes, namely burst mode and daisy-chain mode.
Protocol and communication errors on the SPI interface are
detectable. There are three detectable errors: incorrect SCLK error
detection, invalid read and write address error detection, and
CRC error detection. Each of these errors has a corresponding
enable bit in the error configuration register. In addition, there
is an error flag bit for each of these errors in the error flags
register.
CS
The interface pins of the ADGS1612 are , SCLK, SDI, and
CS
SDO. Hold low when using the SPI interface. Data is captured
on the SDI pin on the rising edge of SCLK, and data is propagated
out on the SDO pin on the falling edge of SCLK. SDO has an
open-drain output; thus, connect a pull-up resistor to this
output. When not pulled low by the ADGS1612, SDO is in a
high impedance state.
Cyclic Redundancy Check (CRC) Error Detection
The CRC error detection feature extends a valid SPI frame by
eight SCLK cycles. These eight extra cycles are needed to send the
CRC byte for that SPI frame. The CRC byte is calculated by the SPI
W
block using the 16-bit payload: the R/ bit, Address Bits[6:ꢀ], and
ADDRESS MODE
Data Bits[7:ꢀ]. The CRC polynomial used in the SPI block is
x8 + x2 + x1 + 1 with a seed value of ꢀ. For a timing diagram with
CRC enabled, see Figure 4ꢀ. Register writes occur at the 24th SCLK
rising edge with CRC error checking enabled.
Address mode is the default mode for the ADGS1612 on
power-up. A single SPI frame in address mode is bounded by a
CS
CS
falling edge and the succeeding rising edge. The SPI frame
is composed of 16 SCLK cycles. The timing diagram for address
mode is shown in Figure 39. The first SDI bit indicates whether
the SPI command is a read or write command. When the first
bit is set to ꢀ, a write command is issued, and if the first bit is set
to 1, a read command is issued. The next seven bits determine the
target register address. The remaining eight bits provide the data
to the addressed register. The last eight bits are ignored during a
read command, because during these clock cycles, SDO
During an SPI write, the microcontroller/CPU provides the
CRC byte through SDI. The SPI block checks the CRC byte just
before the 24th SCLK rising edge. On this same edge, the register
write is prevented if an incorrect CRC byte is received by the
SPI interface. The CRC error flag is asserted in the error flags
register in the case of the incorrect CRC byte being detected.
During an SPI read, the CRC byte is provided to the microcon-
troller through SDO.
propagates out the data contained in the addressed register.
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates out
on SDO from the ninth to the 16th SCLK falling edge during SPI
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
SDI
R/W A6
0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
0
1
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Figure 39. Address Mode Timing Diagram
1
2
8
9
10
16
17
18
19
20
21
22
23
24
CS
SCLK
SDI
R/W A6
0
A0
D7
D6
D0
C7
C6
C5
C4
C3
C2
C1
C0
SDO
0
1
D7
D6
D0
C7
C6
C5
C4
C3
C2
C1
C0
Figure 40. Timing Diagram with CRC Enabled
Rev. 0 | Page 22 of 29
Data Sheet
ADGS161ꢁ
SCLK Count Error Detection
BURST MODE
SCLK count error detection allows the user to detect if an incorrect
number of SCLK cycles are sent by the microcontroller or CPU.
When in address mode, with CRC disabled, 16 SCLK cycles are
expected. If 16 SCLK cycles are not detected, the SCLK count
error flag asserts in the error flags register. When less than
16 SCLK cycles are received by the device, a write to the register
map never occurs. When the ADGS1612 receives more than
16 SCLK cycles, a write to the memory map still occurs at the
16th SCLK rising edge, and the flag asserts in the error flags
register. With CRC enabled, the expected number of SCLK
cycles is 24. SCLK count error detection is enabled by default
and can be configured by the user through the error
The SPI interface can accept consecutive SPI commands
CS
mode. Burst mode is enabled through the burst enable register.
This mode uses the same 16-bit command to communicate
with the device. In addition, the response of the device at SDO
is still aligned with the corresponding SPI command. Figure 41
shows an example of SDI and SDO during burst mode.
without the need to deassert the
line, which is called burst
The invalid read/write address and CRC error checking functions
operate similarly during burst mode as they do during address
mode. However, SCLK count error detection operates in a
slightly different manner. The total number of SCLK cycles
CS
within a given
frame are counted, and if the total is not a
configuration register.
multiple of 16 or a multiple of 24 when CRC is enabled, the
SCLK count error flag asserts.
Invalid Read/Write Address Error
An invalid read/write address error detects when a nonexistent
register address is a target for a read or write. In addition, this
error asserts when a write to a read only register is attempted.
The invalid read/write address error flag asserts in the error
flags register when an invalid read/write address error occurs.
The invalid read/write address error is detected on the ninth
SCLK rising edge, which means a write to the register never
occurs when an invalid address is targeted. Invalid read/write
address error detection is enabled by default and can be
disabled by the user through the error configuration register.
CS
SDI
COMMAND 0[15:0] COMMAND 1[15:0] COMMAND 2[15:0] COMMAND 3[15:0]
SDO
RESPONSE 0[15:0] RESPONSE 1[15:0] RESPONSE 2[15:0] RESPONSE 3[15:0]
Figure 41. Burst Mode Frame
SOFTWARE RESET
When in address mode, the user can initiate a software reset. To
do so, write two consecutive SPI commands, namely ꢀxA3 fol-
lowed by ꢀxꢀ5, targeting Register ꢀxꢀB. After a software reset,
all register values are set to default.
CLEARING THE ERROR FLAGS REGISTER
DAISY-CHAIN MODE
To clear the error flags register, write the special 16-bit SPI
frame, ꢀx6CA9, to the device. This SPI command does not
trigger the invalid R/W address error. When CRC is enabled,
the user must also send the correct CRC byte to complete an
error clear command. At the 16th or 24th SCLK rising edge, the
error flags register resets to zero.
The connection of several ADGS1612 devices in a daisy-chain
configuration is possible, and Figure 42 shows this setup. All
devices share the same and SCLK line, whereas the SDO pin of
a device forms a connection to the SDI pin of the next device,
creating a shift register. In daisy-chain mode, SDO is an eight-cycle
delayed version of SDI. When in daisy-chain mode, all commands
target the switch data register. Therefore, it is not possible to
CS
make configuration changes while in daisy-chain mode.
DEVICE 1
DEVICE 2
ADGS1612
ADGS1612
S1
S2
S3
S4
D1
S1
S2
S3
S4
D1
D2
D3
D4
D2
D3
RESET/V
D4
L
SDO
SPI
INTERFACE
SPI
INTERFACE
SDO
SDI
SCLK
CS
RESET/V
L
Figure 42. Two SPI Controlled Switches Connected in a Daisy-Chain Configuration
Rev. 0 | Page 23 of 29
ADGS161ꢁ
Data Sheet
The ADGS1612 can only enter daisy-chain mode when in
address mode by sending the 16-bit SPI command, ꢀx25ꢀꢀ
(see Figure 43). When the ADGS1612 receives this command,
the SDO of the device sends out the same command because
the alignment bits at SDO are ꢀx25, which allows multiple
daisy-connected devices to enter daisy-chain mode in a single
SPI frame. A hardware reset is required to exit daisy-chain mode.
An SCLK rising edge reads in data on SDI while data is
propagated out of SDO on an SCLK falling edge. The expected
CS
goes high; if this is not the case, the SPI interface sends the last
eight bits received to the switch data register.
number of SCLK cycles must be a multiple of eight before
POWER-ON RESET
The digital section of the ADGS1612 enters an initialization phase
during VL power-up. This initialization also occurs after a
hardware or software reset. After VL power-up or a reset, ensure
that a minimum of 12ꢀ μs from the time of power-up or reset
before any SPI command is issued. Ensure that VL does not
drop out during the 12ꢀ μs initialization phase because this may
result in incorrect operation of the ADGS1612.
For the timing diagram of a typical daisy-chain SPI frame, see
CS
Figure 44. When
goes high, Device 1 writes Command ꢀ,
Bits[7:ꢀ] to its switch data register, Device 2 writes Command 1,
Bits[7:ꢀ] to its switches, and so on. The SPI block uses the last
eight bits it received through SDI to update the switches. After
entering daisy-chain mode, the first eight bits sent out by SDO
CS
on each device in the chain are ꢀxꢀꢀ. When
goes high, the
internal shift register value does not reset back to zero.
1
2
3
4
5
6
7
0
8
1
9
10
11
12
13
14
15
16
CS
SCLK
SDI
0
0
1
0
0
1
0
0
0
0
0
0
0
0
SDO
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
Figure 43. SPI Command to Enter Daisy-Chain Mode
CS
SDI
COMMAND 3[7:0] COMMAND 2[7:0] COMMAND 1[7:0] COMMAND 0[7:0]
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
SDO
8’h00
8’h00
8’h00
COMMAND 3[7:0] COMMAND 2[7:0] COMMAND 1[7:0]
SDO2
SDO3
8’h00
8’h00
COMMAND 3[7:0] COMMAND 2[7:0]
8’h00 COMMAND 3[7:0]
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 44. Example of an SPI Frame When Four ADGS1612 Devices Are Connected in Daisy-Chain Mode
Rev. 0 | Page 2± of 29
Data Sheet
ADGS161ꢁ
APPLICATIONS INFORMATION
BREAK-BEFORE-MAKE SWITCHING
DIGITAL INPUT BUFFERS
The ADGS1612 exhibits break-before-make switching action,
which allows the use of the device in multiplexer applications. A
multiplexer can be achieved by externally hardwiring the device
in the mux configuration that is required, as shown in Figure 45.
4:1 MUX
There are input buffers present on the digital inputs pins,
SCLK, and SDI. These buffers are active at all times. Therefore,
there is current draw from the VL supply if SCLK or SDI is
,
CS
toggling, regardless of whether
is active. For typical values of
CS
this current draw, refer to the Specifications section and Figure 26.
POWER SUPPLY RAILS
4 × SPST
To guarantee correct operation of the ADGS1612, ꢀ.1 μF
decoupling capacitors are required.
S1
The ADGS1612 can operate with bipolar supplies between
3.3 V and 8 V. The supplies on VDD and VSS do not have to be
symmetrical; however, the VDD to VSS range must not exceed
16 V. The ADGS1612 can also operate with single supplies
between 3.3 V and 16 V with VSS connected to GND.
S2
1
D
S3
S4
The voltage range that can be supplied to VL is from 2.7 V to 5.5 V.
SPI
The device is fully specified at 5 V, 12 V, 5 V, and 3.3 V analog
supply voltage ranges.
INTERFACE
SCLK SDI CS RESET/V
L
1
ALL Dx PINS ARE CONNECTED AS ONE DRAIN.
Figure 45. SPI Controlled Switch Configured as a 4:1 Mux
Rev. 0 | Page 2ꢀ of 29
ADGS161ꢁ
Data Sheet
REGISTER SUMMARY
Table 11. Register Summary
Reg. Name
Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Default
0x00
RW
R/W
R/W
R
0x01 SW_DATA
0x02 ERR_CONFIG
0x03 ERR_FLAGS
0x0ꢀ BURST_EN
0x0B SOFT_RESETB
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
RESERVED
RESERVED
SW±_EN SW3_EN
SW2_EN
SW1_EN
RW_ERR_EN
RW_ERR_FLAG
RESERVED
SOFT_RESETB
SCLK_ERR_EN
SCLK_ERR_FLAG
CRC_ERR_EN
CRC_ERR_FLAG
BURST_MODE_EN
0x06
0x00
0x00
R/W
R/W
0x00
Rev. 0 | Page 26 of 29
Data Sheet
ADGS161ꢁ
REGISTER DETAILS
SWITCH DATA REGISTER
Address: 0x01, Reset: 0x00, Name: SW_DATA
The switch data register controls the status of the four switches of the ADGS1612.
Table 12. Bit Descriptions for SW_DATA
Bits
[7:±]
3
Bit Name
RESERVED
SW±_EN
Settings
Description
Default
0x0
Access
R
These bits are reserved; set these bits to 0.
Enable bit for SW±.
SW± open.
0x0
R/W
0
1
SW± closed.
2
1
0
SW3_EN
SW2_EN
SW1_EN
Enable bit for SW3.
SW3 open.
SW3 closed.
0x0
0x0
0x0
R/W
R/W
R/W
0
1
Enable bit for SW2.
SW2 open.
SW2 closed.
0
1
Enable bit for SW1.
SW1 open.
SW1 closed.
0
1
ERROR CONFIGURATION REGISTER
Address: 0x02, Reset: 0x06, Name: ERR_CONFIG
The error configuration register allows the user to enable or disable the relevant error features as required.
Table 13. Bit Descriptions for ERR_CONFIG
Bits Bit Name
Settings Description
Default Access
[7:3] RESERVED
These bits are reserved; set these bits to 0.
0x0
0x1
R
2
1
RW_ERR_EN
Enable bit for detecting an invalid read/write address.
Disabled.
Enabled.
R/W
0
1
SCLK_ERR_EN
Enable bit for detecting the correct number of SCLK cycles in an SPI frame. When
CRC is disabled and burst mode is disabled, 16 SCLK cycles are expected. When
CRC is enabled and burst mode is disabled, 2± SCLK cycles are expected. A multiple
of 16 SCLK cycles is expected when CRC is disabled and burst mode is enabled. A
multiple of 2± SCLK cycles is expected when CRC is enabled and burst mode is
enabled.
0x1
0x0
R/W
R/W
0
1
Disabled.
Enabled.
0
CRC_ERR_EN
Enable bit for CRC error detection. SPI frames must be 2± bits wide when enabled.
0
1
Disabled.
Enabled.
Rev. 0 | Page 27 of 29
ADGS161ꢁ
Data Sheet
ERROR FLAGS REGISTER
Address: 0x03, Reset: 0x00, Name: ERR_FLAGS
The error flags register allows the user to determine if an error occurred. To clear the error flags register, the special 16-bit SPI command,
ꢀx6CA9, must be written to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, then
the user must include the correct CRC byte during the SPI write for the clear error flags register command to complete.
Table 14. Bit Descriptions for ERR_FLAGS
Bits Bit Name
Settings Description
Default Access
[7:3] RESERVED
These bits are reserved and are set to 0.
0x0
0x0
R
R
2
RW_ERR_FLAG
Error flag for invalid read/write address. The error flag asserts during an SPI read
if the target address does not exist. The error flag also asserts when the target
address of an SPI write does not exist or is read only.
0
1
No error.
Error.
1
0
SCLK_ERR_FLAG
CRC_ERR_FLAG
Error flag for the detection of the correct number of SCLK cycles in an SPI frame.
No error.
Error.
0x0
0x0
R
R
0
1
Error flag that determines if a CRC error occurs during a register write.
0
1
No error.
Error.
BURST ENABLE REGISTER
Address: 0x05, Reset: 0x00, Name: BURST_EN
The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI
commands without deasserting
.
CS
Table 15. Bit Descriptions for BURST_EN
Bits
[7:1]
0
Bit Name
Settings
Description
Default
0x0
Access
R
RESERVED
These bits are reserved; set these bits to 0.
BURST_MODE_EN
Burst mode enable bit.
Disabled.
Enabled.
0x0
R/W
0
1
SOFTWARE RESET REGISTER
Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB
This software reset register is used to perform a software reset. Consecutively write ꢀxA3 and ꢀxꢀ5 to this register, and the device registers
reset to their default states.
Table 16. Bit Descriptions for SOFT_RESETB
Bits Bit Name
Settings Description
To perform a software reset, consecutively write 0xA3 followed by 0x0ꢀ to this
register.
Default Access
0x0 R/W
[7:0] SOFT_RESETB
Rev. 0 | Page 28 of 29
Data Sheet
ADGS161ꢁ
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN
1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
12
6
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
1.00
0.95
0.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8.
Figure 46. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.95 mm Package Height
(CP-24-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADGS1612BCPZ
ADGS1612BCPZ-RL7
EVAL-ADGS1612SDZ
Temperature Range
−±0°C to +12ꢀ°C
−±0°C to +12ꢀ°C
Package Description
Package Option
CP-2±-17
CP-2±-17
2±-Lead Lead Frame Chip Scale Package [LFCSP]
2±-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16054-0-1/18(0)
Rev. 0 | Page 29 of 29
相关型号：
ADGS1612BCPZ
SPI Interface, 1 Ω RON, ±5 V, 12 V, 5 V, 3.3 V, Mux Configurable, Quad SPST Switch
ADI
ADGS1612BCPZ-RL7
SPI Interface, 1 Ω RON, ±5 V, 12 V, 5 V, 3.3 V, Mux Configurable, Quad SPST Switch
ADI
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