ADL5367ACPZ-R7 [ADI]
500 MHz to 1700 MHz Balanced Mixer, LO Buffer and RF Balun; 500 MHz至1700 MHz的平衡混频器， LO缓冲器和RF巴伦
| 型号： | ADL5367ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | 500 MHz to 1700 MHz Balanced Mixer, LO Buffer and RF Balun |
| 文件： | 总24页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
500 MHz to 1700 MHz Balanced Mixer,
LO Buffer and RF Balun
ADL5367
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VCMI
20
IFOP
19
IFON
18
PWDN
17
COMM
16
RF frequency range of 500 MHz to 1700 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion loss: 7.7 dB
SSB noise figure of 8.3 dB
SSB noise figure with 5 dBm blocker of 21 dB
Input IP3 of 34 dBm
ADL5367
1
2
3
4
5
15
14
13
12
11
VPMX
RFIN
LOI2
VPSW
VGS1
VGS0
LOI1
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle 5 mm × 5 mm, 20-lead LFCSP
1500 V HBM/500 V FICDM ESD performance
RFCT
COMM
COMM
BIAS
GENERATOR
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
6
7
LGM3
8
9
10
VLO3
VLO2
LOSW
NC
NC = NO CONNECT
Figure 1.
GENERAL DESCRIPTION
The ADL5367 provides two switched LO paths that can be
used in TDD applications where it is desirable to rapidly switch
between two local oscillators. LO current can be externally set
using a resistor to minimize dc current commensurate with the
desired level of performance. For low voltage applications, the
ADL5367 is capable of operation at voltages down to 3.3 V with
substantially reduced current. Under low voltage operation, an
additional logic pin is provided to power down (<200 μA) the
circuit when desired.
The ADL5367 uses a highly linear, doubly balanced passive
mixer core along with integrated RF and LO balancing circuitry
to allow for single-ended operation. The ADL5367 incorporates
an RF balun, allowing optimal performance over a 500 MHz to
1700 MHz RF input frequency range. Performance is optimized for
RF frequencies from 500 MHz to 1200 MHz using a high-side LO
and for RF frequencies from 900 MHz to 1700 MHz using a
low-side LO. The balanced passive mixer arrangement provides
good LO-to-RF leakage, typically better than −35 dBm, and
excellent intermodulation performance. The balanced mixer
core also provides extremely high input linearity, allowing the
device to be used in demanding cellular applications where in-
band blocking signals may otherwise result in the degradation
of dynamic performance. A high linearity IF buffer amplifier
follows the passive mixer core to yield a typical power conversion
loss of 7.7 dB and can be used with a wide range of output
impedances.
The ADL5367 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency
(MHz)
Single
Mixer
Single Mixer +
IF Amp
Dual Mixer +
IF Amp
500 to 1700
ADL5367 ADL5357
ADL5365 ADL5355
ADL5358
ADL5356
1200 to 2500
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
ADL5367
TABLE OF CONTENTS
Features .............................................................................................. 1
Upconversion.............................................................................. 15
Spur Tables .................................................................................. 16
Circuit Description......................................................................... 17
RF Subsystem.............................................................................. 17
LO Subsystem ............................................................................. 17
Applications Information.............................................................. 19
Basic Connections...................................................................... 19
IF Port .......................................................................................... 19
Bias Resistor Selection ............................................................... 19
Mixer VGS Control DAC.......................................................... 19
Evaluation Board ............................................................................ 20
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Performance........................................................................... 4
3.3 V Performance........................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance........................................................................... 7
3.3 V Performance...................................................................... 14
REVISION HISTORY
10/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5367
SPECIFICATIONS
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20 dB over a limited bandwidth
14
50
dB
Ω
MHz
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage1
LO INTERFACE
500
1700
Differential impedance, f = 200 MHz
Externally generated
34||1.9
5.0
Ω||pF
MHz
V
30
3.3
450
5.5
LO Power
−6
0
+10
1670
0.4
dBm
dB
Ω
Return Loss
12.6
50
Input Impedance
LO Frequency Range
POWER-DOWN (PWDN) INTERFACE
PWDN Threshold
Logic 0 Level
730
MHz
2
1.0
V
V
Logic 1 Level
1.4
V
PWDN Response Time
Device enabled, IF output to 90% of its final level
Device disabled, supply current < 5 mA
Device enabled
160
220
0.0
70
ns
ns
μA
μA
PWDN Input Bias Current
Device disabled
1 Apply the supply voltage from the external circuit through the choke inductors.
2 PWDN function is intended for use with VS ≤ 3.6 V only.
Rev. 0 | Page 3 of 24
ADL5367
5 V PERFORMANCE
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
Table 3.
Parameter
Conditions
Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Loss
Voltage Conversion Loss
SSB Noise Figure
Including 1:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 50 Ω differential
6.5
28
7.7
1.4
8.3
21
8.5
dB
dB
dB
dB
SSB Noise Figure Under Blocking
5 dBm blocker present 10 MHz from wanted RF input,
LO source filtered
fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 1103 MHz,
each RF tone at 0 dBm
fRF1 = 950 MHz, fRF2 = 900 MHz, fLO = 1103 MHz,
each RF tone at 0 dBm
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
34
80
dBm
dBm
Input 1 dB Compression Point (IP1dB)1 Exceeding 20 dBm RF power results in damage to the device
25
dBm
dBm
dBm
dBc
dBc
dBc
LO-to-IF Leakage
LO-to-RF Leakage
RF-to-IF Isolation
IF/2 Spurious
Unfiltered IF output
−15
−40
−47
−75
−72
0 dBm input power
0 dBm input power
IF/3 Spurious
POWER SUPPLY
Positive Supply Voltage
Total Quiescent Current
4.5
5
97
5.5
V
mA
VS = 5 V
1 Exceeding 20 dBm RF power results in damage to the device.
3.3 V PERFORMANCE
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
Table 4.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Power Conversion Loss
Voltage Conversion Loss
SSB Noise Figure
Including 4:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential
7.3
1
8.1
28.5
dB
dB
dB
dBm
Input Third-Order Intercept (IIP3)
fRF1 = 1949.5 MHz, fRF2 = 1950.5 MHz, fLO = 1750 MHz,
each RF tone at −10 dBm
Input Second-Order Intercept (IIP2)
fRF1 = 1950 MHz, fRF2 = 1900 MHz, fLO = 1750 MHz,
each RF tone at −10 dBm
75
dBm
POWER INTERFACE
Supply Voltage
Quiescent Current
Power-Down Current
3.0
3.3
56
150
3.6
V
mA
μA
Resistor programmable
Device disabled
Rev. 0 | Page 4 of 24
ADL5367
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage, VS
RF Input Level
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
5.5 V
20 dBm
13 dBm
6.0 V
LO Input Level
IFOP, IFON Bias Voltage
VGS0, VGS1, LOSW, PWDN
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering, 60 sec)
5.5 V
1.2 W
25°C/W
150°C
−40°C to +85°C
−65°C to +150°C
260°C
ESD CAUTION
Rev. 0 | Page 5 of 24
ADL5367
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
VPMX
RFIN
RFCT
COMM
COMM
1
2
3
4
5
15 LOI2
14 VPSW
13 VGS1
12 VGS0
11 LOI1
ADL5367
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD. MUST BE SOLDERED
TO GROUND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
VPMX
RFIN
RFCT
COMM
Positive Supply Voltage for IF Amplifier.
RF Input. This pin must be ac-coupled.
RF Balun Center Tap (AC Ground).
Device Common (DC Ground).
4, 5, 16
6, 8
7
9
10
VLO3, VLO2 Positive Supply Voltages for LO Amplifier.
LGM3
LOSW
NC
LO Amplifier Bias Control.
LO Switch. LOI1 selected for 0 V, or LOI2 selected for 3 V.
No Connect.
11, 15
12, 13
14
LOI1, LOI2
LO Inputs. This pin must be ac-coupled.
VGS0, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting.
VPSW
Positive Supply Voltage for LO Switch.
17
18, 19
20
PWDN
IFON, IFOP
VCMI
Power Down. Connect this pin to ground for normal operation or connect this pin to 3.0 V for disable mode.
Differential IF Outputs.
No Connect. This pin can be grounded.
EPAD (EP)
Exposed pad must be soldered to ground.
Rev. 0 | Page 6 of 24
ADL5367
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
110
105
100
95
100
90
80
70
60
50
40
T
= –40°C
A
T
= –40°C
A
T
= +25°C
A
T
= +85°C
A
T
= +85°C
90
A
T
= +25°C
85
A
80
700 750 800 850 900 950 1000 1050 1100 1150 1200
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 3. Supply Current vs. RF Frequency
Figure 6. Input IP2 vs. RF Frequency
12
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
11
10
9
T
= +85°C
A
T
= +25°C
A
T
= +85ºC
= +25ºC
A
T
A
8
T
= –40ºC
A
T
= –40°C
A
7
6
5
700 750 800 850 900 950 1000 1050 1100 1150 1200
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 4. Power Conversion Loss vs. RF Frequency
Figure 7. SSB Noise Figure vs. RF Frequency
40
38
36
34
32
30
28
26
T
= +25°C
A
T
= –40°C
A
T
= +85°C
A
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 5. Input IP3 vs. RF Frequency
Rev. 0 | Page 7 of 24
ADL5367
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
110
105
100
95
86
84
82
80
78
76
74
72
70
V
= 5.25V
POS
V
= 5.25V
POS
V
= 5V
POS
V
= 5V
POS
V
= 4.75V
POS
V
= 4.75V
90
POS
85
80
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. Supply Current vs. Temperature
Figure 11. Input IP2 vs. Temperature
12
11
10
9
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
V
V
V
= 4.75V
POS
POS
POS
= 5V
= 5.25V
V
= 5.25V
POS
V
= 5V
8
POS
V
= 4.75V
POS
7
6
5
–40
–40
–20
0
20
40
60
80
–20
0
20
40
60
80
TEMPERATURE (ºC)
TEMPERATURE (°C)
Figure 9. Power Conversion Loss vs. Temperature
Figure 12. SSB Noise Figure vs. Temperature
40
38
36
34
32
30
28
26
V
V
= 5.25V
= 4.75V
POS
V
= 5V
POS
POS
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 10. Input IP3 vs. Temperature
Rev. 0 | Page 8 of 24
ADL5367
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
110
85
80
75
70
65
60
55
50
T
= +25°C
A
105
100
T
= –40°C
A
T
= +25°C
A
95
90
85
80
T
= +85°C
A
T
= +85°C
A
T
= –40°C
A
30
80
130
180
230
280
330
380
430
430
430
30
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 13. Supply Current vs. IF Frequency
Figure 16. Input IP2 vs. IF Frequency
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
12
11
10
9
T
= +85°C
A
T
= +25°C
A
8
T
= –40°C
A
7
6
5
30
30
80
130
180
230
280
330
380
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 17. SSB Noise Figure vs. IF Frequency
Figure 14. Power Conversion Loss vs. IF Frequency
40
38
36
34
32
30
28
26
T
= –40°C
A
T
= +25°C
A
T
= +85°C
A
30
80
130
180
230
280
330
380
IF FREQUENCY (MHz)
Figure 15. Input IP3 vs. IF Frequency
Rev. 0 | Page 9 of 24
ADL5367
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
–40
–50
–60
–70
–80
–90
–100
T
= +85°C
A
T
= +25°C
A
T
= –40°C
A
T
= –40°C
A
T
= +85°C
A
T
= +25°C
A
–6
–4
–2
0
2
4
6
8
10
10
10
700 750 800 850 900 950 1000 1050 1100 1150 1200
LO POWER (dBm)
RF FREQUENCY (MHz)
Figure 18. Power Conversion Loss vs. LO Power
Figure 21. IF/2 Spurious vs. RF Frequency
40
38
36
34
32
30
28
26
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
T
= –40°C
A
T
= +25°C
A
T
= +85°C
A
T
= +85°C
A
T
= –40°C
A
T
= +25°C
A
–6
–4
–2
0
2
4
6
8
700 750 800 850 900 950 1000 1050 1100 1150 1200
LO POWER (dBm)
RF FREQUENCY (MHz)
Figure 19. Input IP3 vs. LO Power
Figure 22. IF/3 Spurious vs. RF Frequency
90
85
80
75
70
65
60
55
50
T
= +25°C
A
T
= –40°C
A
T
= +85°C
A
–6
–4
–2
0
2
4
6
8
LO POWER (dBm)
Figure 20. Input IP2 vs. LO Power
Rev. 0 | Page 10 of 24
ADL5367
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
100
36.5
36.0
35.5
35.0
34.5
34.0
33.5
33.0
32.5
32.0
31.5
31.0
30.5
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
80
60
40
20
MEAN: 7.7
STANDARD DEVIATION: 0.18
0
7.2
7.4
7.6
7.8
8.0
8.2
30
80
130
180
230
280
330
380
430
CONVERSION LOSS (dB)
IF FREQUENCY (MHz)
Figure 23. Conversion Loss Distribution
Figure 26. IF Port Return Loss
100
80
60
40
20
0
0
5
10
15
20
MEAN: 34.67
STANDARD DEVIATION: 0.19
25
31
33
35 37
INPUT IP3 (dBm)
39
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 24. Input IP3 Distribution
Figure 27. RF Port Return Loss, Fixed IF
100
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
12
14
16
18
20
SELECTED
UNSELECTED
MEAN: 8.3
STANDARD DEVIATION: 0.05
7.8
8.0
8.2
8.4 8.8
8.6
9.0
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
NOISE FIGURE (dB)
LO FREQUENCY (MHz)
Figure 28. LO Return Loss, Selected and Unselected
Figure 25. SSB Noise Figure Distribution
Rev. 0 | Page 11 of 24
ADL5367
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
70
65
60
55
50
45
40
–20
–25
–30
–35
–40
–45
–50
T
= +25°C
A
T
= –40°C
A
T
= +85°C
A
T
= +85°C
T
= –40°C
A
A
T
= +25°C
A
700 750 800 850 900 950 1000 1050 1100 1150 1200
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
RF FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 29. LO Switch Isolation vs. RF Frequency
Figure 32. LO-to-RF Leakage vs. LO Frequency
–40
–42
–44
–46
–48
–50
–52
–54
–56
–58
–60
0
T
= +85°C
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
A
T
= +25°C
A
2LO TO RF
T
= –40°C
A
2LO TO IF
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
RF FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 33. 2LO Leakage vs. LO Frequency
Figure 30. RF-to-IF Isolation vs. RF Frequency
0
0
–10
–20
–30
–40
–50
–60
–70
–5
–10
–15
–20
–25
–30
T
= –40°C
A
3LO TO IF
T
= +25°C
A
T
= +85°C
A
3LO TO RF
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
LO FREQUENCY (MHz)
LO FREUQENCY (MHz)
Figure 31. LO-to-IF Leakage vs. LO Frequency
Figure 34. 3LO Leakage vs. LO Frequency
Rev. 0 | Page 12 of 24
ADL5367
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
10
15
14
13
12
11
10
9
30
25
9
CONVERSION LOSS
8
7
20
15
10
5
6
5
NOISE FIGURE
4
3
8
2
7
VGS = 0, 0
VGS = 0, 1
VGS = 1, 0
VGS = 1, 1
1
0
6
5
0
–30
700 750 800 850 900 950 1000 1050 1100 1150 1200
–25
–20
–15
–10
–5
0
5
10
RF FREQUENCY (MHz)
BLOCKER POWER (dBm)
Figure 38. SSB Noise Figure vs.10 MHz Offset Blocker Level
Figure 35. Power Conversion Loss and SSB Noise Figure vs. RF Frequency
140
40
VGS = 0, 0
VGS = 0, 1
38
36
VGS = 1, 0
VGS = 1, 1
120
100
80
60
40
20
0
34
32
30
28
26
24
22
20
600
800
1000
1200
1400
1600
1800
700 750 800 850 900 950 1000 1050 1100 1150 1200
BIAS RESISTOR VALUE (Ω)
RF FREQUENCY (MHz)
Figure 36. Input IP3 vs. RF Frequency
Figure 39. LO Supply Current vs. LO Bias Resistor Value
12
11
40
35
INPUT IP3
10
9
30
25
20
15
10
5
NOISE FIGURE
8
CONVERSION LOSS
7
6
5
4
600
0
800
1000
1200
1400
1600
1800
BIAS RESISTOR VALUE (Ω)
Figure 37. Power Conversion Loss, SSB Noise Figure, and
Input IP3 vs. LO Bias Resistor Value
Rev. 0 | Page 13 of 24
ADL5367
3.3 V PERFORMANCE
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
85
64
80
T
= –40°C
A
62
60
58
56
54
52
50
75
70
65
60
55
50
45
40
T
= –40°C
A
T = +25°C
A
T
= +25°C
A
T
= +85°C
A
T
= +85°C
A
700 750 800 850 900 950 1000 1050 1100 1150 1200
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 40. Supply Current vs. RF Frequency at 3.3 V
Figure 43. Input IP2 vs. RF Frequency at 3.3 V
10.0
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
T
T
= +85°C
= +25°C
A
T
= +85°C
A
A
T
= +25°C
A
T
= –40°C
A
T
= –40°C
A
700 750 800 850 900 950 1000 1050 1100 1150 1200
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 41. Power Conversion Loss vs. RF Frequency at 3.3 V
Figure 44. SSB Noise Figure vs. RF Frequency at 3.3 V
34
32
30
28
26
24
22
20
T
= –40°C
A
T
= +85°C
A
T
= +25°C
A
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 42. Input IP3 vs. RF Frequency at 3.3 V
Rev. 0 | Page 14 of 24
ADL5367
UPCONVERSION
TA = 25°C, fIF = 153 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted.
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
T
= +85°C
= –40°C
A
T
= +85°C
A
T
= +25°C
A
T
A
T
= +25°C
A
T
= –40°C
A
700 750 800 850 900 950 1000 1050 1100 1150 1200
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 45. Power Conversion Loss vs. RF Frequency, VS = 5 V, Upconversion
Figure 47. Power Conversion Loss vs. RF Frequency at 3.3 V, Upconversion
34
32
34
T
A
= –40°C
A
T = +25°C
A
32
30
28
26
24
22
20
T
= +85°C
30
28
26
24
22
20
T
= –40°C
A
T
= +85°C
A
T
= +25°C
A
700 750 800 850 900 950 1000 1050 1100 1150 1200
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 46. Input IP3 vs. RF Frequency, VS = 5 V, Upconversion
Figure 48. Input IP3 vs. RF Frequency at 3.3 V, Upconversion
Rev. 0 | Page 15 of 24
ADL5367
SPUR TABLES
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.
5 V Performance
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and
ZO = 50 Ω, unless otherwise noted.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−7.8
0.0
−24.6
−45.0
−77.4
−95.5
−35.7
−27.5
−72.8
−75.9
−53.0
−53.0
−80.2
−97.9
−47.4
−54.4
−80.9
−91.7
1
−39.7
−84.6
−71.8
−87.8
2
−68.8
−96.8
3
<−100 −78.6
<−100 <−100
4
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
5
6
7
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
N
8
9
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
3.3 V Performance
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 =
0 V, and ZO = 50 Ω, unless otherwise noted.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−12.6
0.0
−28.8
−42.7
−64.8
−90.1
−40.6
−27.1
−68.0
−63.0
−95.5
−43.0
−53.2
−65.9
−90.5
−97.0
−59.6
−50.7
−73.0
−77.8
1
−40.5
−78.6
−93.9
−71.8
−75.4
−96.4
2
−59.5
−66.3
−89.4
−95.6
3
4
<−100 <−100 −95.6
<−100 <−100 <−100 <−100
5
<−100 <−100 <−100 <−100 <−100 −98.9
<−100 <−100 <−100 <−100
6
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
N
8
9
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
Rev. 0 | Page 16 of 24
ADL5367
CIRCUIT DESCRIPTION
The ADL5367 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated
into a single die, using mature packaging and interconnection
technologies to provide a high performance, low cost design
with excellent electrical, mechanical, and thermal properties.
In addition, the need for external components is minimized,
optimizing cost and size.
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.
Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the IF
output. This termination is accomplished by the addition of a
sum network between the IF output and the mixer.
The RF subsystem consists of an integrated, low loss RF balun,
passive MOSFET mixer, sum termination network, and IF
amplifier.
The LO subsystem consists of an SPDT-terminated FET switch
and a three-stage limiting LO amplifier. The purpose of the LO
subsystem is to provide a large, fixed amplitude, balanced signal
to drive the mixer independent of the level of the LO input.
The IP3 performance can be optimized by adjusting the supply
current with an external resistor. Figure 37 and Figure 39
illustrate how various bias resistors affect the performance with a
5 V supply. Additionally, dc current can be saved by increasing
the resistor. It is permissible to reduce the dc supply voltage to
as low as 3.3 V, further reducing the dissipated power of the
part. (Note that no performance enhancement is obtained by
reducing the value of these resistors and excessive dc power
dissipation may result.)
A block diagram of the device is shown in Figure 49.
VCMI
IFOP
19
IFON
18
PWDN
17
COMM
16
20
ADL5367
1
2
3
4
5
15
14
13
12
11
VPMX
RFIN
LOI2
LO SUBSYSTEM
VPSW
VGS1
VGS0
LOI1
The LO amplifier is designed to provide a large signal level to
the mixer to obtain optimum intermodulation performance.
The resulting amplifier provides extremely high performance
centered on an operating frequency of 1100 MHz. The best
operation is achieved with either high-side LO injection for RF
signals in the 500 MHz to 1200 MHz range or low-side injection
for RF signals in the 900 MHz to 1700 MHz range. Operation
outside these ranges is permissible, and conversion loss is
extremely wideband, easily spanning 500 MHz to 1700 MHz,
but intermodulation is optimal over the aforementioned ranges.
RFCT
COMM
COMM
BIAS
GENERATOR
6
7
LGM3
8
9
10
The ADL5367 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.
VLO3
VLO2
LOSW
NC
NC = NO CONNECT
Figure 49. Simplified Schematic
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the part.
The RF balun can easily support an RF input frequency range
of 500 MHz to 1700 MHz.
The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.
Rev. 0 | Page 17 of 24
ADL5367
The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the
LO amplifier by raising the value of the external bias control
resistor. For dc current critical applications, the LO chain
can operate with a supply voltage as low as 3.3 V, resulting in
substantial dc power savings.
In addition, when operating with supply voltages below 3.6 V,
the ADL5367 has a power-down mode that permits the dc
current to drop to <200 μA.
All of the logic inputs are designed to work with any logic family
that provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.
Rev. 0 | Page 18 of 24
ADL5367
APPLICATIONS INFORMATION
BASIC CONNECTIONS
BIAS RESISTOR SELECTION
An external resistor, RBIAS LO, is used to adjust the bias current of the
integrated amplifiers at the LO terminals. It is necessary to have
a sufficient amount of current to bias the internal LO amplifier
to optimize dc current vs. optimum IIP3 performance. Figure 37
and Figure 39 provide the reference for the bias resistor selection
when lower power consumption is considered at the expense of
conversion gain and IP3 performance.
The ADL5367 mixer is designed to upconvert or downconvert
between radio frequencies (RF) from 500 MHz to 1700 MHz and
intermediate frequencies (IF) from dc to 450 MHz. Figure 50
depicts the basic connections of the mixer. It is recommended
to ac-couple the RF and LO input ports to prevent non-zero dc
voltages from damaging the RF balun or LO input circuit. The
RFIN capacitor value of 8 pF is recommended to provide the
optimized RF input return loss for the desired frequency band.
MIXER VGS CONTROL DAC
For upconversion, the IF input, Pin 18 (IFON) and Pin 19 (IFOP),
must be driven differentially or using a 1:1 ratio transformer for
single ended operation. An 8 pF capacitor is recommended for
the RF output, Pin 2 (RFIN).
The ADL5367 features two logic control pins, Pin 12 (VGS0)
and Pin 13 (VGS1), that allow programmability for internal
gate-to-source voltages for optimizing mixer performance over
desired frequency bands. The evaluation board defaults both
VGS0 and VGS1 to ground. Power conversion loss, NF, and
IIP3 can be optimized, as shown in Figure 35 and Figure 36.
IF PORT
The real part of the output impedance is approximately 50 Ω,
as seen in Figure 26, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion loss that is approximately the same as the power
conversion loss, as shown in Table 3.
IF1_OUT
T1
R1
0Ω
C25
560pF
C24
560pF
10kΩ
+5V
20
19
18
17
16
10pF
4.7µF
22pF
ADL5367
+5V
1
2
3
4
5
15
14
13
12
11
LO2_IN
+5V
8pF
RF-IN
10pF
0.01µF
10pF
BIAS
GENERATOR
22pF
LO1_IN
6
7
8
9
10
R
BIAS LO
10kΩ
+5V
10pF
10pF
Figure 50. Typical Application Circuit
Rev. 0 | Page 19 of 24
ADL5367
EVALUATION BOARD
An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 51. The evaluation board is fabricated using Rogers®
RO3003 material. Table 7 describes the various configuration
options of the evaluation board. Evaluation board layout is shown
in Figure 52 to Figure 55.
IF1_OUT
R1
0Ω
T1
C25
560pF
C24
560pF
PWR_UP
R21
10kΩ
R14
0Ω
L3
0Ω
C12
22pF
LO2_IN
VPOS
VPOS
VPMX
RFIN
LOI2
VPSW
VGS1
VGS0
LOI1
C2
C21
C20
R22
10kΩ
10µF
10pF
10pF
RF-IN
C22
1nF
C1
8pF
R23
15kΩ
ADL5367
RFCT
COMM
COMM
C5
0.01µF
C4
10pF
VGS1
VGS0
LO1_IN
C10
22pF
LOSEL
VPOS
R9
1.1kΩ
C6
10pF
R4
10kΩ
VPOS
C8
10pF
Figure 51. Evaluation Board Schematic
Rev. 0 | Page 20 of 24
ADL5367
Table 7. Evaluation Board Configuration
Components
Description
Default Conditions
C2, C6, C8,
C20, C21
Power Supply Decoupling. Nominal supply decoupling consists of
a 10 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.
C2 = 10 μF (Size 0603),
C6, C8, C20, C21 = 10 pF (Size 0402)
C1, C4, C5
RF Input Interface. The input channels are ac-coupled through C1.
C4 and C5 provide bypassing for the center taps of the RF input baluns.
C1 = 3 pF (Size 0402), C4 = 10 pF (Size 0402),
C5 = 0.01 μF (Size 0402)
T1, R1, C24, C25 IF Output Interface. T1 is a 1:1 impedance transformer used to provide
a single-ended IF output interface. Remove R1 for balanced output
T1 = TC1-1-13M+ (Mini-Circuits),
R1 = 0 Ω (Size 0402),
operation. C24 and C25 are used to block the dc bias at the IF ports.
C24, C25 = 560 pF (Size 0402)
C10, C12, R4
LO Interface. C10 and C12 provide ac coupling for the LO1_IN and
LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input
for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is
enabled when the LOSEL test point is logic low. LO2_IN is enabled
when LOSEL is pulled to logic high.
C10, C12 = 22 pF (Size 0402),
R4 = 10 kΩ (Size 0402)
R21
PWDN Interface. R21 pulls the PWDN logic low and enables the device.
The PWR_UP test point allows the PWDN interface to be exercised
using the an external logic generator. Grounding the PWDN pin for
nominal operation is allowed. Using the PWDN pin when supply
voltages exceed 3.3 V is not allowed.
R21 = 10 kΩ (Size 0402)
C22, L3, R9, R14,
R22, R23, VGS0,
VGS1
Bias Control. R22 and R23 form a voltage divider to provide 3 V for
logic control, bypassed to ground through C22. VGS0 and VGS1
jumpers provide programmability at the VGS0 and VGS1 pins. It is
recommended to pull these two pins to ground for nominal operation.
R9 sets the bias point for the internal LO buffers. R14 sets the bias point
for the internal IF amplifier.
C22 = 1 nF (Size 0402), L3 = 0 Ω (Size 0603),
R9 = 1.1 kΩ (Size 0402), R14 = 0 Ω (Size 0402),
R22 = 10 kΩ (Size 0402), R23 = 15 kΩ (Size 0402),
VGS0 = VGS1 = 3-pin shunt
Rev. 0 | Page 21 of 24
ADL5367
Figure 52. Evaluation Board Top Layer
Figure 54. Evaluation Board Power Plane, Internal Layer 2
Figure 53. Evaluation Board Ground Plane, Internal Layer 1
Figure 55. Evaluation Board Bottom Layer
Rev. 0 | Page 22 of 24
ADL5367
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.65
BSC
PIN 1
INDICATOR
4.75
BSC SQ
3.20
3.10 SQ
3.00
EXPOSED
PAD
(BOTTOM VIEW)
10
11
6
0.75
0.60
0.50
TOP VIEW
2.60 BSC
0.70
0.65
0.60
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.01 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.05
0.35
0.28
0.23
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHC
Figure 56. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad (CP-20-5)
Dimensions shown in millimeters
ORDERING GUIDE
Package Ordering
Model
Temperature Range
Package Description
Option
Quantity
1,500
1
ADL5367ACPZ-R71 −40°C to +85°C
ADL5367-EVALZ1
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7”Tape and Reel
Evaluation Board
CP-20-5
1 Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
ADL5367
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08083-0-10/09(0)
Rev. 0 | Page 24 of 24
相关型号：
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250 MHz - 1300 MHz RF/MICROWAVE QUADRAPHASE MODULATOR, LEAD FREE, MO-220VGGD-2, LFCSP-24
ROCHESTER
ADL5370ACPZ-WP
250 MHz - 1300 MHz RF/MICROWAVE QUADRAPHASE MODULATOR, LEAD FREE, MO-220VGGD-2, LFCSP-24
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