ADL5801-EVALZ [ADI]
High IP3, 10 MHz to 6 GHz, Active Mixer; 高IP3 ， 10 MHz至6 GHz的有源混频器
| 型号： | ADL5801-EVALZ |
| 厂家： | 
ADI |
| 描述： | High IP3, 10 MHz to 6 GHz, Active Mixer |
| 文件： | 总20页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High IP3,
10 MHz to 6 GHz, Active Mixer
ADL5801
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VPLO GND NC IFON IFOP GND
Broadband upconverter/downconverter
Power conversion gain of 1.8 dB
Broadband RF, LO, and IF ports
SSB noise figure (NF) of 9.75 dB
Input IP3: 28.5 dBm
Input P1dB: 13.3 dBm
Typical LO drive: 0 dBm
Single-supply operation: 5 V at 130 mA
Adjustable bias for low power operation
Exposed paddle, 4 mm × 4 mm, 24-lead LFCSP package
24
23
22
21
20
19
1
2
3
4
18
17
16
15
GND
GND
LOIP
LOIN
VPRF
GND
RFIP
RFIN
ADL5801
V2I
GND
GND
5
6
14 GND
13 VPDT
DET
APPLICATIONS
7
8
9
10
11
12
Cellular base station receivers
Radio link downconverters
Broadband block conversion
Instrumentation
VPLO GND ENBL VSET DETO GND
Figure 1.
GENERAL DESCRIPTION
The ADL5801 uses a high linearity, doubly balanced, active
mixer core with integrated LO buffer amplifier to provide high
dynamic range frequency conversion from 10 MHz to 6 GHz.
The mixer benefits from a proprietary linearization architecture
that provides enhanced input IP3 performance when subject to
high input levels. A bias adjust feature allows the input linearity,
SSB noise figure, and dc current to be optimized using a single
control pin. An optional input power detector is provided for
adaptive bias control. The high input linearity allows the device
to be used in demanding cellular applications where in-band
blocking signals may otherwise result in degradation in
dynamic performance. The adaptive bias feature allows the part
to provide high input IP3 performance when presented with
large blocking signals. When blockers are removed, the
ADL5801 can automatically bias down to provide low noise
figure and low power consumption.
The balanced active mixer arrangement provides superb LO-to-
RF and LO-to-IF leakage, typically better than −40 dBm. The IF
outputs are designed to provide a typical voltage conversion
gain of 7.8 dB when loaded into a 200 Ω load. The broad
frequency range of the open-collector IF outputs allows the
ADL5801 to be applied as an upconverter for various transmit
applications.
The ADL5801 is fabricated using a SiGe high performance IC
process. The device is available in a compact 4 mm × 4 mm,
24-lead LFCSP package and operates over a −40°C to +85°C
temperature range. An evaluation board is also available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADL5801
TABLE OF CONTENTS
Features .............................................................................................. 1
RF Voltage-to-Current (V-to-I) Converter............................. 11
Mixer Core .................................................................................. 11
Mixer Output Load .................................................................... 11
RF Detector ................................................................................. 11
Bias Circuit.................................................................................. 12
Applications Information .............................................................. 13
Basic Connections...................................................................... 13
RF and LO Ports ......................................................................... 13
IF Port .......................................................................................... 14
Evaluation Board ............................................................................ 15
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Spur Performance....................................................................... 10
Circuit Description......................................................................... 11
LO Amplifier and Splitter.......................................................... 11
REVISION HISTORY
2/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADL5801
SPECIFICATIONS
VS = 5 V, TA = 25°C, fRF = 900 MHz, fLO = 747 MHz, LO power = 0 dBm, Z01 = 50 Ω, VSET = 3.8 V, unless otherwise noted.
Table 1.
Parameter
Test Conditions
Min Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20 dB over a limited bandwidth
12
dB
Ω
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage2
50
10
6000 MHz
Differential impedance, f = 200 MHz
Can be matched externally to 3000 MHz
Externally generated
230
LF
4.75 VS
Ω
MHz
V
600
5.25
LO INTERFACE
LO Power
Return Loss
−10
0
15
50
+10
dBm
dB
Ω
Input Impedance
LO Frequency Range
POWER INTERFACE
Supply Voltage
Quiescent Current
Disable Current
10
6000 MHz
4.75
5
5.25
200
V
Resistor programmable
ENBL pin high
Time from ENBL pin low to enable
Time from ENBL pin high to disable
130
50
182
28
mA
mA
ns
Enable Time
Disable Time
ns
DYNAMIC PERFORMANCE at fRF = 900 MHz/1900 MHz
Power Conversion Gain3
fRF = 900 MHz
1.8
dB
fRF = 1900 MHz
fRF = 900 MHz
fRF = 1900 MHz
fCENT = 900 MHz, VSET = 2.0 V
fCENT = 1900 MHz, VSET = 2.0 V
fCENT = 900 MHz, VSET = 2.0 V
fCENT = 1900 MHz, VSET = 2.0 V
fCENT = 900 MHz
fCENT = 1900 MHz
fCENT = 900 MHz
fCENT = 1900 MHz
fRF = 900 MHz
fRF = 1900 MHz
Unfiltered IF output
1.8
7.8
7.8
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
Voltage Conversion Gain4
SSB Noise Figure
9.75
11.5
19.5
20
28.5
26.4
63
49.7
13.3
12.7
−27
−30
−35
−67.5
−53
−65.5
−72.6
SSB Noise Figure Under Blocking5
Input Third-Order Intercept6
Input Second-Order Intercept7
Input 1 dB Compression Point
LO-to-IF Output Leakage
LO-to-RF Input Leakage
RF-to-IF Output Isolation
IF/2 Spurious8
0 dBm input power, fRF = 900 MHz
0 dBm input power, fRF = 1900 MHz
0 dBm input power, fRF = 900 MHz
0 dBm input power, fRF = 1900 MHz
1 Z0 is the characteristic impedance assumed for all measurements and the PCB.
2 Supply voltage must be applied from an external circuit through choke inductors.
3 Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-13M+), and PCB loss.
4 ZSOURCE = 50 Ω, differential; ZLOAD = 200 Ω differential; ZSOURCE is the impedance of the source instrument; ZLOAD is the load impedance at the output.
5 fRF = fCENT, fBLOCKER = (fCENT − 5) MHz, fLO = (fCENT − 153) MHz, blocker level = 0 dBm.
6 fRF1 = (fCENT − 1) MHz, fRF2 = (fCENT) MHz, fLO = (fCENT – 153) MHz, each RF tone at −10 dBm.
7 fRF1 = (fCENT ) MHz, fRF2 = (fCENT + 100) MHz, fLO = (fCENT – 153) MHz, each RF tone at −10 dBm.
8 For details, see the Spur Performance section.
Rev. 0 | Page 3 of 20
ADL5801
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage, VPOS
VSET, ENBL
5.5 V
5.5 V
IFOP, IFON
5.5 V
RFIN Power
20 dBm
1.2 W
26.5°C/W
8.7°C/W
150°C
ESD CAUTION
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)1
θJC (at Exposed Paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
−40°C to +85°C
−65°C to +150°C
1 As measured on the evaluation board. For details, see the Evaluation Board
section.
Rev. 0 | Page 4 of 20
ADL5801
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
GND
GND
LOIP
LOIN
GND
GND
1
2
3
4
5
6
18 VPRF
17 GND
16 RFIP
15 RFIN
14 GND
13 VPDT
ADL5801
TOP VIEW
(Not to Scale)
NOTES
1. THERE IS AN EXPOSED PADDLE THAT
MUST BE SOLDERED TO GROUND.
2. NC = NO CONNECT.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 5, 6, 8, 12,
14, 17, 19, 23
GND
Device Common (DC Ground).
3, 4
7, 24
9
LOIP, LOIN
VPLO
ENBL
Differential LO Input Terminal. Internally matched to 50 Ω. Must be ac-coupled.
Positive Supply Voltage for LO System.
Device Enable. Pull high to disable the device; pull low to enable.
10
VSET
Input IP3 Bias Adjustment. The voltage presented to the VSET pin sets the internal bias of the mixer core
and allows for adaptive control of the input IP3 and NF characteristics of the mixer core.
11
DETO
Detector Output. The DETO pin should be loaded with a capacitor to ground. The developed voltage is
proportional to the rms input level. When the DETO output voltage is connected to the VSET input pin,
the part auto biases and increases input IP3 performance when presented with large signal input levels.
13
VPDT
Positive Supply Voltage for Detector.
15, 16
RFIN, RFIP
Differential RF Input Terminal. Internally matched to 50 Ω differential input impedance. Must be
ac-coupled.
18
VPRF
Positive Supply Voltage for RF Input System.
20, 21
IFOP, IFON
Differential IF Output Terminal. Bias must be applied through pull-up choke inductors or the center tap
of the IF transformer.
22
NC
Not Connected.
EPAD
The exposed paddle must be soldered to ground.
Rev. 0 | Page 5 of 20
ADL5801
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, VSET = 3.8 V as measured using a typical circuit schematic, unless otherwise noted. Insertion loss of input and
output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement.
6
6
5
4
3
2
1
0
35
30
25
20
15
10
5
5
4
T
= –40°C
A
3
T
= +25°C
A
2
GAIN = 900MHz
GAIN = 1900MHz
1
INPUT IP3 = 900MHz
INPUT IP3 = 1900MHz
T
= +85°C
A
0
–1
–2
–3
–4
500
1000
1500
2000
2500
3000
–15
–10
–5
0
5
10
15
RF FREQUENCY (MHz)
LO LEVEL (dBm)
Figure 6. Power Conversion Gain and Input IP3 vs. LO Power
Figure 3. Power Conversion Gain vs. RF Frequency
100
90
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
MEAN = 1.87
80
SD = 0.03
70
60
50
40
30
20
10
0
900MHz
1900MHz
0
50
100
150
200
250
IF FREQUENCY (MHz)
POWER CONVERSION GAIN (dB)
Figure 4. Power Conversion Gain vs. IF Frequency
Figure 7. Power Conversion Gain Distribution
3.0
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
3.0
2.5
2.0
1.5
1.0
0.5
0
GAIN = 900MHz
GAIN = 1900MHz
T
T
= –40°C
= +25°C
A
I
I
= 900MHz
POS
POS
2.5
2.0
1.5
1.0
0.5
0
= 1900MHz
A
T
= +85°C
A
–0.5
–1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
4.7
4.8
4.9
5.0
SUPPLY (V)
5.1
5.2
5.3
VSET (V)
Figure 8. Power Conversion Gain vs. Supply Voltage
Figure 5. Power Conversion Gain and Supply Current vs. VSET
Rev. 0 | Page 6 of 20
ADL5801
70
60
50
40
30
20
10
0
35
30
25
20
15
10
5
T
= –40°C
A
T
= +25°C
A
T
= –40°C
= +25°C
= +85°C
A
T
T
A
A
T
= +85°C
A
0
500
1000
1500
2000
2500
3000
500
1000
1500
2000
2500
3000
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 9. Input IP3 vs. RF Frequency
Figure 12. Input IP2 vs. RF Frequency
40
35
30
25
20
15
10
80
70
60
50
40
30
20
10
0
900MHz
900MHz
1900MHz
1900MHz
0
50
100
150
200
250
0
50
100
150
200
250
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 10. Input IP3 vs. IF Frequency
Figure 13. Input IP2 vs. IF Frequency
30
25
20
15
10
5
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
900MHz
1900MHz
INPUT IP3 = 900MHz
INPUT IP3 = 1900MHz
NF = 900MHz
NF = 1900MHz
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VSET (V)
VSET (V)
Figure 11. Input IP3 and Noise Figure vs. VSET
Figure 14. Input IP2 vs. VSET
Rev. 0 | Page 7 of 20
ADL5801
20
18
16
14
12
10
8
25
20
15
10
5
T
= +25°C
A
T
= +85°C
A
1900MHz
900MHz
T
= –40°C
A
6
4
2
0
0
0
100
200
300
400
500
600
700
500
1000
1500
2000
2500
3000
IF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 18. SSB Noise Figure vs. IF Frequency (VSET = 2.0 V)
Figure 15. Input P1dB vs. RF Frequency
30
25
20
15
10
5
20
18
16
14
12
10
8
900MHz
RF = 1846MHz, IF = 153 MHz
BLOCKER = 1841MHz
1900MHz
6
RF = 951MHz, IF = 153 MHz
BLOCKER = 946MHz
4
2
0
0
0
–30
–25
–20
–15
–10
–5
0
5
50
100
150
200
250
BLOCKER LEVEL (dBm)
IF FREQUENCY (MHz)
Figure 19. SSB Noise Figure vs. Blocker Level (VSET = 2.0 V)
Figure 16. Input P1dB vs. IF Frequency
20
18
16
14
12
10
8
T
= +85°C
18
16
14
12
10
8
A
T
= +25°C
A
1900MHz
900MHz
T
= –40°C
A
6
6
4
4
2
2
0
0
–15
–10
–5
0
5
10
15
500
1000
1500
2000
2500
3000
LO LEVEL (dBm)
RF FREQUENCY (MHz)
Figure 20. SSB Noise Figure vs. LO Power (VSET = 2.0 V)
Figure 17. SSB Noise Figure vs. RF Frequency (VSET = 2.0 V)
Rev. 0 | Page 8 of 20
ADL5801
0
5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
10
15
20
25
30
35
0
500
1000
1500
2000
2500
3000
1000
1500
2000
2500
3000
500
RF FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 21. RF Return Loss vs. RF Frequency
Figure 24. LO-to-IF Leakage vs. LO Frequency
0
5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
10
15
20
25
30
35
0
500
1000
1500
2000
2500
3000
500
1000
1500
2000
2500
3000
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 22. LO Return Loss vs. LO Frequency
Figure 25. LO-to-RF Leakage vs. LO Frequency
500
400
300
200
100
4
0
–10
–20
–30
–40
–50
–60
2
0
T
= +85°C
A
–2
–4
–6
T
= +25°C
A
T
= –40°C
1500
A
0
10
100
1000
3000
500
1000
2000
2500
3000
IF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 23. IF Differential Output Impedance (R Parallel C Equivalent)
Figure 26. RF-to-IF Leakage vs. RF Frequency
Rev. 0 | Page 9 of 20
ADL5801
SPUR PERFORMANCE
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board (see the Evaluation Board section). Mixer
spurious products are measured in decibels relative to the carrier (dBc) from the IF output power level. Data was measured for frequencies
less than 6 GHz only. The typical noise floor of the measurement system is −100 dBm.
900 MHz Performance
VS = 5 V, VSET = 3.8 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 900 MHz, fLO = 703 MHz, Z0 = 50 Ω.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−33.1
0.0
−23.3
−51.5
−67.5
−94.3
−78.0
−89.8
−83.1
−45.8
−19.0
−66.1
−65.9
−78.4
−70.7
−98.5
−23.6
−65.1
−73.5
−86.3
−95.1
−84.8
−83.3
−45.9
−29.6
−80.5
−70.2
−73.5
−90.7
−96.7
−30.7
−78.0
−65.0
−76.3
−89.4
−86.7
−55.4
−50.3
−89.8
−70.6
−87.3
−86.4
−41.5
−74.4
−71.3
−74.5
1
−48.8
−35.9
−68.8
−47.5
−95.6
−85.7
−57.7
−88.5
−81.4
2
−74.9
−64.8
−80.7
−74.7
−96.4
−86.8
−98.8
3
≤−100 −99.6
≤−100
4
≤−100 −92.7
−99.5
−78.7
−96.1
−99.4
−80.7
−95.4
−87.9
≤−100 ≤−100
5
−83.1
−99.6
−73.7
−96.1
−91.1
−95.5
−88.8
≤−100 ≤−100
≤−100 ≤−100
6
≤−100 −89.4
N
7
≤−100 ≤−100 −95.9
≤−100 −97.2
−99.8
−83.1
−86.0
−84.1
≤−100 ≤−100 −99.7
−85.7
≤−100
8
≤−100 ≤−100 −99.0
≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100
9
≤−100 ≤−100 ≤−100 −90.9
−88.4
−83.5
−87.6
−95.5
−87.4
≤−100 ≤−100 ≤−100 ≤−100 ≤−100
10
11
12
13
14
15
≤−100 ≤−100 ≤−100 −97.9
≤−100 ≤−100 −92.6
−99.0
−88.2
≤−100 ≤−100 ≤−100 ≤−100
−92.3 −99.3 ≤−100 ≤−100
≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100
≤−100 ≤−100 −95.1 −96.5 −90.4 ≤−100
≤−100 ≤−100 ≤−100 ≤−100 ≤−100
≤−100 ≤−100 ≤−100 ≤−100
1900 MHz Performance
VS = 5 V, VSET = 3.8 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 1900 MHz, fLO = 1703 MHz, Z0 = 50 Ω.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−31.4
0.0
−17.1
−53.6
−52.9
−73.2
−51.4
−38.5
−68.1
−72.6
−86.4
−83.7
1
−40.4
−38.4
−71.0
−64.2
−79.9
−94.6
−66.2
2
−66.0
−86.8
−65.2
−87.4
−79.3
3
≤−100 −66.2
−92.8
−81.5
−89.0
4
≤−100 −89.4
≤−100
−75.2
5
≤−100 ≤−100
6
≤−100 −86.4
≤−100 −99.0
−92.7
−87.7
≤−100 ≤−100
N
7
≤−100 −92.4
≤−100 −98.4
≤−100 ≤−100
≤−100 ≤−100
≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100
≤−100 −97.2 −95.6 ≤−100 ≤−100 ≤−100 ≤−100
8
≤−100 ≤−100 −97.5
≤−100 −95.4
9
10
11
12
13
14
15
≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100
≤−100 ≤−100 ≤−100 ≤−100 ≤−100
≤−100 ≤−100 ≤−100 ≤−100
≤−100 ≤−100
≤−100
Rev. 0 | Page 10 of 20
ADL5801
CIRCUIT DESCRIPTION
The ADL5801 includes a double-balanced active mixer with a
50 Ω input impedance and 250 Ω output impedance. In addition,
the ADL5801 integrates a local oscillator (LO) amplifier and
an RF power detector that can be used to optimize the mixer
dynamic range. The RF and LO are differential, providing max-
imum usable bandwidth at the input and output ports. The LO
also operates with a 50 Ω input impedance and can, optionally,
be operated differentially or single ended. The input, output, and
LO ports can be operated over an exceptionally wide frequency
range. The ADL5801 can be configured as a downconvert mixer
or as an upconvert mixer.
RF VOLTAGE-TO-CURRENT (V-TO-I) CONVERTER
The differential RF input signal is applied to a V-to-I converter
that converts the differential input voltage to output currents.
The V-to-I converter provides a 50 Ω input impedance. The V-to-
I section bias current can be adjusted up or down using the
VSET pin. Adjusting the current up improves IP3 and P1dB
input but degrades the SSB noise figure. Adjusting the current
down improves the SSB noise figure but degrades IP3 and P1dB
input. Conversion gain remains nearly constant over a wide
range of VSET pin settings, allowing the part to be adjusted
dynamically without affecting conversion gain. The current
adjustment can be made by connecting a resistor from the
VSET pin to the positive supply to increase the bias current or
from the VSET pin to ground to decrease the bias current.
Optionally, the VSET pin can be connected to the DETO pin to
provide automatic setting of the mixer core current.
The ADL5801 can be divided into the following sections: the
LO amplifier and splitter, the RF voltage-to-current (V-to-I)
converter, the mixer core, the output loads, the RF detector, and
the bias circuit. A simplified block diagram of the device is
shown in Figure 27. The LO block generates a pair of
differential LO signals to drive two mixer cores. The RF input
power is converted into RF currents by the V-to-I converter that
then feed into the two-mixer core. The internal differential load
of the mixer provides a wideband 250 Ω output impedance from
the mixer. Reference currents to each section are generated by
the bias circuit, which can be enabled or disabled using the ENBL
pin. A detailed description of each section of the ADL5801
follows.
MIXER CORE
The ADL5801 has a double-balanced mixer that uses high per-
formance SiGe NPN transistors. This mixer is based on the
Gilbert cell design of four cross-connected transistors.
MIXER OUTPUT LOAD
The mixer load uses a pair of 125 Ω resistors connected to the
positive supply. This provides a 250 Ω differential output resis-
tance. The mixer output should be pulled to the positive supply
externally using a pair of RF chokes or using an output trans-
former with the center tap connected to the positive supply. It
is possible to exclude these components when the mixer core
current is low, but both P1dB input and IP3 input are then
reduced.
VPLO GND NC IFON IFOP GND
24
23
22
21
20
19
1
2
3
4
18
17
16
15
GND
GND
LOIP
LOIN
VPRF
GND
RFIP
RFIN
ADL5801
V2I
The mixer load output can operate from direct current (dc) up
to approximately 600 MHz into a 200 Ω load. For upconversion
applications, the mixer load can be matched using off-chip
matching components. Transmit operation up to 2 GHz is
possible. See the Applications Information section for matching
circuit details.
GND
GND
5
6
14 GND
13 VPDT
DET
7
8
9
10
11
12
VPLO GND ENBL VSET DETO GND
RF DETECTOR
Figure 27. Block Diagram
An RF power detector is buffered from the V-to-I converter
section. This detector has a power response range from
approximately −25 dBm up to 0 dBm and provides a current
output. The output current is designed to be connected to the
VSET pin to boost the mixer core current when large RF signals
are present at the mixer input. An external capacitor can be
used to adjust the response time of this function. If not used,
the DETO pin can be left open or connected to ground.
LO AMPLIFIER AND SPLITTER
The LO input is conditioned by a series of amplifiers to provide
a well controlled and limited LO swing to the mixer core, result-
ing in excellent input IP3. The LO input is amplified using a
broadband low noise amplifier (LNA) and is then followed by
LO limiting amplifiers. The LNA input impedance is nominally
50 Ω. The LO circuit exhibits low additive noise, resulting in an
excellent mixer noise figure and output noise under RF
blocking. For optimal performance, the LO inputs should be
driven differentially but at lower frequencies; single-ended drive
is acceptable.
Rev. 0 | Page 11 of 20
ADL5801
alter the current in the LO section and, therefore, does not
provide a true power-down feature. In addition, if the VSET pin
is connected to the positive supply through a resistor to increase
the mixer core current, this continues to provide bias current to
the mixer core unless the resistor supply is also removed.
BIAS CIRCUIT
A band gap reference circuit generates the reference currents
used by mixers. The bias circuit can be enabled and disabled
using the ENBL pin. If the ENBL pin is grounded or left open,
the part is enabled. Pulling the ENBL pin high shuts off the bias
circuit and disables the part. However, the ENBL pin does not
Rev. 0 | Page 12 of 20
ADL5801
APPLICATIONS INFORMATION
BASIC CONNECTIONS
RF AND LO PORTS
The ADL5801 is designed to translate between radio frequencies
(RF) and intermediate frequencies (IF). For both upconversion
and downconversion applications, RFIP (Pin 16) and RFIN
(Pin 15) must be configured as the input interfaces. IFOP
(Pin 20) and IFON (Pin 21) must be configured as the output
interfaces. Individual bypass capacitors are needed in close
proximity to each supply pin (Pin 7, Pin 13, Pin 18, and Pin 24),
the VSET control pin (Pin 10), and the DETO detector output pin
(Pin 11). When the on-chip detector is chosen to form a closed
loop, automatically controlling the VSET pin, R7 can be
The RF and LO input ports are designed for a differential input
impedance of approximately 50 Ω. Figure 29 and Figure 30
illustrate the RF and LO interfaces, respectively. It is recommended
that each of the RF and LO differential ports be driven through a
balun for optimum performance. It is also necessary to ac couple
both RF and LO ports. Using proper value capacitors may help
improve the input return loss over desired frequencies. Table 4
lists the recommended components for various RF and LO
frequency bands. The characterization data is available in the
Typical Performance Characteristics section.
populated with a 0 Ω resistor. Alternatively, simply use a jumper
between the VSET and DETO test points for evaluation. Figure
28 illustrates the basic connections for ADL5801 operation.
IFOP IFON
T1
T5
T8
R11
R13
C50
VPOS
R3
L1
R2
L2
R50
C20
VPOS
L3
C2
C3
C19
C13
24
23
22
21
20
19
C10
VPLO GND NC IFON IFOP GND
1
GND
18
17
16
15
VPRF
GND
RFIP
RFIN
VPOS
GND
LOIP
LOIN
GND
GND
2
3
4
5
6
R8
R14
R16
C8
C9
C4
C5
L4
L5
RFIP
RFIN
LOIN
LOIP
ADL5801
R4
T3
T6
T9
T2
T4
T7
R12
GND 14
VPDT 13
VPOS
GND
8
VPLO
7
ENBL VSET DETO GND
R10
9
10
11
12
ENBL
C18 C17
R9
VPOS
VSET
C6
C7
R7
C12
DETO
C1
Figure 28. Basic Connections Schematic
Rev. 0 | Page 13 of 20
ADL5801
The self-resonant frequency of the selected choke inductors
must be higher than the intended IF frequency. A variety of
suitable choke inductors is commercially available from
manufacturers such as Coilcraft® and Murata. An impedance
transforming network may be required to transform the final
load impedance to 200 Ω at the IF outputs.
17
16
15
GND
RFIP
RFIN
C8
C9
RFIP
ADL5801
T3
GND 14
IFOP
T1
T5
Figure 29. RF Interface
T8
VPOS
1
2
3
4
5
6
GND
GND
C50
R3
R2
L3
C13
C4
C5
LOIP
LOIN
GND
GND
23
22
21
20
19
ADL5801
GND NC IFON IFOP GND
LOIP
T2
ADL5801
Figure 31. Biasing the IF Port Open-Collector Outputs
Using a Center-Tapped Impedance Transformer
Z
L
IMPEDANCE
TRANSFORMING T5
NETWORK
T1
Figure 30. LO Interface
T8
Table 4. Suggested Components for the RF and LO Interfaces
RF and LO
Frequency
R3
R2
T1, T3, T5
C8, C9
5.6 pF
5.6 pF
2 pF
C4, C5
100 pF
100 pF
8 pF
VPOS
C20
VPOS
C19
900 MHz
1900 MHz
2500 MHz
Mini-Circuits® TC1-1-13M+
Mini-Circuits TC1-1-13M+
Mini-Circuits TC1-1-43+
L1
L2
L3
C13
IF PORT
23
22
21
20
19
GND NC IFON IFOP GND
The IF port features an open-collector, differential output
interface. It is necessary to bias the open collector outputs using
one of the schemes presented in Figure 31 and Figure 32.
ADL5801
Figure 32. Biasing the IF Port Open-Collector Outputs
Using Pull-Up Choke Inductors
Figure 31 shows the use of center-tapped impedance transformers.
The turns ratio of the transformer should be selected to provide
the desired impedance transformation. In the case of a 50 Ω
load impedance, a 4:1 impedance ratio transformer should be
used to transform the 50 Ω load into a 200 Ω differential load at
the IF output pins.
Figure 32 shows a differential IF interface where pull-up choke
inductors are used to bias the open-collector outputs. The
shunting impedance of the choke inductors used to couple dc
current into the mixer core should be large enough at the IF
frequency of operation not to load down the output current
before it reaches the intended load. Additionally, the dc current
handling capability of the selected choke inductors must be at
least 45 mA.
Rev. 0 | Page 14 of 20
ADL5801
EVALUATION BOARD
An evaluation board is available for the ADL5801. The standard evaluation board is fabricated using Rogers® RO3003 material. Each RF,
LO, and IF port is configured for single-ended signaling via a balun transformer. The schematic for the evaluation board is shown in
Figure 33. Table 5 describes the various configuration options for the evaluation board. Layout for the board is shown in Figure 34 and
Figure 35.
IFOP IFON
T1
T5
T8
R11
C50
R13
VPOS
R3
L1
R2
R50
C20
VPOS
L2
L3
C2
C3
C19
C13
24
23
22
21
20
19
C10
VPLO GND NC IFON IFOP GND
1
GND
18
17
16
15
VPRF
GND
RFIP
RFIN
VPOS
GND
LOIP
LOIN
GND
GND
2
3
4
5
6
R8
R14
R16
L4
C8
C9
C4
C5
RFIP
RFIN
LOIN
LOIP
ADL5801
T2
T4
T7
T3
T6
T9
L5
R12
GND 14
VPDT 13
VPOS
C11
GND
8
VPLO
7
ENBL VSET DETO GND
9
10
11
12
R10
C18 C17
VPOS
VSET
ENBL
DETO
C6
C7
R9
R7
C12
C1
Figure 33. Evaluation Board Schematic
Rev. 0 | Page 15 of 20
ADL5801
Table 5. Evaluation Board Configuration
Components
Function
Default Conditions
C2, C3, C6, C7, C10, C11 Power supply decoupling. Nominal supply decoupling consists of a
0.1 µF capacitor to ground in parallel with 100 pF capacitors to ground,
positioned as close to the device as possible. Series resistors are provided
for enhanced supply decoupling using optional ferrite chip inductors.
C2, C6, C10, C11 = 0.1 µF (size 0402)
C3, C7 = 100 pF (size 0402)
C8, C9, L4, L5, R4, R8,
R12, T3, T6, T9, RFIN,
RFIP
RF input interfaces. Input channels are ac-coupled through C8 and C9.
R8 and R12 provide options when additional matching is needed. T3 is
a 1:1 balun used to interface to the 50 Ω differential inputs. T6 and T9
provide options when high frequency baluns are used and require smaller
balun footprints.
C8, C9 = 5.6 pF (size 0402)
L4, L5, R12 = 0 Ω (size 0402)
R4, R8 = open (size 0402)
T3 = TC1-1-13M+ (Mini-Circuits)
C13, C19, C20, C50, L1,
IF output interfaces. The 200 Ω open collector IF output interfaces are
C13 = open (size 0402)
C19, C20 = 100 pF (size 0402)
C50 = 0.1 µF (size 0402)
L1, L2 = open (size 0805)
L3 = open (size 0402)
L2, L3, R2, R3, R11, R13, biased through the center tap of a 4:1 impedance transformer at T1. C50
R50, T1, T5, T8, IFON,
IFOP
provides local bypassing with R50 available for additional supply
bypassing. L1 and L2 provide options when pull-up choke inductors are
used to bias the open-collector outputs. C13, L3, R2, and R3 are provided
for IF filtering and matching options. T5 and T8 provide options when high
frequency baluns are used and require smaller balun footprints.
R2, R3, R13, R50 = 0 Ω (size 0402)
R11 = open (size 0402)
T1 = TC4-1W+ (Mini-Circuits)
C4, C5 = 100 pF (size 0402)
R14 = 0 Ω (size 0402)
R16 = open (size 0402)
T2 = TC1-1-13M+ (Mini-Circuits)
C1 = 0.1 µF (size 0603)
C4, C5, R14, R16, T2, T4, LO interface. C4 and C5 provide ac coupling for the local oscillator input.
T7, LOIN, LOIP
T2 is a 1:1 balun that allows single-ended interfacing to the differential
50 Ω local oscillator input. T4 and T7 provide options when high frequency
baluns are used and require smaller balun footprints.
C1, C12, R7, DETO
DETO interface. C1 and C12 provide decoupling for the DETO pin. R7
provides access to the VSET pin when automatic input IP3 control is
needed.
C12 = 100 pF (size 0402)
R7 = open (size 0402)
C17, C18, R9, R10, VSET VSET bias control. C17 and C18 provide decoupling for the VSET pin. R9
and R10 form an optional resistor divider network between VPOS and
GND, allowing for a fixed bias setting. Supply 3.8 V at the VSET pin when
the DETO pin is not connected for automatic input IP3 control.
C17 = 100 pF (size 0402)
C18 = 0.1 µF (size 0603)
R9, R10 = open (size 0402)
Figure 34. Evaluation Board Top Layer
Figure 35. Evaluation Board Bottom Layer
Rev. 0 | Page 16 of 20
ADL5801
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
0.50
BSC
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
TOP
VIEW
3.75
BSC SQ
EXPOSED
PA D
(BOTTOMVIEW)
0.50
0.40
0.30
6
13
7
12
0.23 MIN
0.80 MAX
0.65 TYP
2.50 REF
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8
Figure 36. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad (CP-24-3)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Ordering
Model1
Temperature Range
Package Description
Quantity
1,500 per Reel
1
ADL5801ACPZ-R7
ADL5801-EVALZ
−40°C to +85°C
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-24-3
1 Z = RoHS Complaint Part.
Rev. 0 | Page 17 of 20
ADL5801
NOTES
Rev. 0 | Page 18 of 20
ADL5801
NOTES
Rev. 0 | Page 19 of 20
ADL5801
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08079-0-2/10(0)
Rev. 0 | Page 20 of 20
相关型号：
ADL5811
High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
ADI
ADL5811-EVALZ
High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
ADI
ADL5811ACPZ-R7
High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
ADI
ADL5812
Dual High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
ADI
ADL5812-EVALZ
Dual High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
ADI
©2020 ICPDF网 联系我们和版权申明