ADM1060ARUZ_技术文档

Communications System

Supervisory/Sequencing Circuit

ADM1060

FEATURES

Faults detected on 7 independent supplies

1 high voltage supply (2 V to 14.4 V)

4 positive voltage only supplies (2 V to 6 V)

2 positive/negative voltage supplies

(+2 V to +6 V and –2 V to –6 V)

Watchdog detector input—timeout delay programmable

from 200 ms to 12.8 sec

4 general-purpose logic inputs

Programmable logic block—combinatorial and sequencing

logic control of all inputs and outputs

fault detection and sequencing/combinatorial logic for up to

seven independent supplies. The seven supply fault detectors

consist of one high voltage detector (up to +14.4 V), two bipolar

voltage detectors (up to +6 V or down to −6 V), and four posi-

tive low voltage detectors (up to +6 V). All of the detectors can

be programmed to detect undervoltage, overvoltage, or out-of-

window (undervoltage or overvoltage) conditions. The inputs to

these supply fault detectors are via the VH (high voltage) pin,

VBn (positive or negative) pins, and VPn (positive only) pins.

Either the VH supply or one of the VPn supplies is used to

power the ADM1060 (whichever is highest). This ensures that

in the event of a supply failure, the ADM1060 is kept alive for as

long as possible, thus enabling a reliable fault flag to be asserted

and the system to be powered down in an ordered fashion.

9 programmable output drivers:

Open collector (external resistor required)

Open collector with internal pull-up to V_DD

Fast internal pull-up to V_DD

Open collector with internal pull-up to VPn

Fast internal pull-up to VPn

Internally charge-pumped high drive (for use with

external N-channel FETs—PDOs 1 to 4 only)

EEPROM—256 bytes of user EEPROM

Industry-standard 2-wire bus interface (SMBus)

Guaranteed PDO low with VPn, VH = 1 V

Other inputs to the ADM1060 include a watchdog detector

(WDI) and four general-purpose inputs (GPIn). The watchdog

detector can be used to monitor a processor clock. If the clock

does not toggle (transition from low to high or from high to

low) within a programmable timeout period (up to 18 sec.), a

fail flag will assert. The four general-purpose inputs can be con-

figured as logic buffers or to detect positive/negative edges and

to generate a logic pulse or level from those edges. Thus, the

user can input control signals from other parts of the system

(e.g., RESET or POWER_GOOD) to gate the sequencing of the

supplies supervised by the ADM1060.

APPLICATIONS

Central office systems

Servers

Infrastructure network boards

High density, multivoltage system cards

GENERAL DESCRIPTION

The ADM1060 is a programmable supervisory/sequencing

device that offers a single chip solution for multiple power

supply fault detection and sequencing in communications

systems.

The ADM1060 features nine programmable driver outputs

(PDOs). All nine outputs can be configured to be logic outputs,

which can provide multiple functions for the end user such as

RESET generation, POWER_GOOD status, enabling of LDOs,

and watchdog timeout assertion. PDOs 1 to 4 have the added

feature of being able to provide an internally charge-pumped

high voltage for use as the gate drive of an external N-channel

FET that could be placed in the path of one of the supplies

being supervised.

In central offices, servers, and other infrastructure systems, a

common backplane dc supply is reduced to multiple board sup-

plies using dc-to-dc converters. These multiple supplies are used

to power different sections of the board, such as 3.3 V logic

circuits, 5 V logic circuits, DSP core, and DSP I/O circuits. There

is usually a requirement that certain sections power up before

others; for example, a DSP core may need to power up before

the DSP I/O, or vice versa, to avoid damage, miscommunication,

or latch-up. The ADM1060 facilitates this, providing supply

(continued on Page 3)

.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

ADM1060* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

REFERENCE MATERIALS

Informational

• Optical and High Speed Networking ICs

Product Selection Guide

EVALUATION KITS

• ADM1060 Evaluation Board

• Supervisory Devices Complementary Parts Guide for

Altera FPGAs

DOCUMENTATION

Application Notes

• Supervisory Devices Complementary Parts Guide for

Xilinx FPGAs

Solutions Bulletins & Brochures

• AN-0973: Erasing and Programming the Sequencing

Engine EEPROM

• Power Supply Sequencing Bulletin (2007)

Technical Articles

• AN-667: Up/Down Sequence of Supplies Using the

ADM1060

• Single Chip Supervises and Sequences Power Supplies

• Temperature monitor measures three thermal zones

• AN-722: Watchdog Detection Using the ADM106x

• AN-723: Interrupt Generation Using the ADM106x

• AN-755: EEPROM Checksum Information for the ADM1060

• AN-897: ADC Readback Code

DESIGN RESOURCES

• ADM1060 Material Declaration

• PCN-PDN Information

Data Sheet

• ADM1060: Communications System Supervisory/

Sequencing Circuit Data Sheet

• Quality And Reliability

• Symbols and Footprints

SOFTWARE AND SYSTEMS REQUIREMENTS

• ADM1060 Evaluation Software

DISCUSSIONS

View all ADM1060 EngineerZone Discussions.

SAMPLE AND BUY

Visit the product page to see pricing options.

TECHNICAL SUPPORT

Submit a technical question or find your regional support

number.

DOCUMENT FEEDBACK

Submit feedback for this data sheet.

This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not

trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

ADM1060

TABLE OF CONTENTS

General Description......................................................................... 3

PROGRAMMABLE DRIVER OUTPUTS ............................. 33

Status/Faults .................................................................................... 35

FAULT REGISTERS................................................................... 38

MASK REGISTERS.................................................................... 39

Programming.................................................................................. 40

WRITE OPERATIONS ............................................................. 44

READ OPERATIONS................................................................ 45

Pin Configuration and Functional Descriptions........................ 49

Outline Dimensions....................................................................... 50

Ordering Guide .......................................................................... 50

Specifications..................................................................................... 5

Absolute Maximum Ratings............................................................ 7

Typical Performance Characteristics ............................................. 8

Inputs................................................................................................ 11

SFD REGISTER NAMES........................................................... 14

SFD Register Bit Maps ............................................................... 15

Programming .................................................................................. 21

Logic................................................................................................. 22

PLBA REGISTER BIT MAPS ................................................... 28

Outputs ............................................................................................ 33

REVISION HISTORY

12/03—Data sheet changed from Rev. A to Rev. B

Changes to Specifications.............................................................................5

Changes to Outputs section............................................................33

Updated Outline Dimensions.........................................................50

5/03—Data sheet changed from Rev. 0 to Rev. A.

Changes to Features.......................................................................... 1

Changes to Specifications................................................................ 5

Changes to Figure 1.......................................................................... 4

Changes to Absolute Maximum Ratings ....................................... 7

Changes to Figures 2, 8, 15–16..................................................8–10

Changes to Figure 17...................................................................... 11

Changes to Programmable Supply Fault Detectors section...... 11

Changes to Figure 18...................................................................... 12

Changes to Figure 19...................................................................... 13

Change to Table 9 ........................................................................... 15

Change to Table 14 ......................................................................... 16

Change to Table 19 ......................................................................... 17

Changes to Programmable Driver Outputs section................... 33

Change to Table 40 ......................................................................... 34

Changes to Figure 25–26 ............................................................... 43

Changes to Figure 37...................................................................... 47

Changes to Table 58........................................................................ 49

Changes to Ordering Guide section............................................. 50

Revision 0: Initial Version

Rev. B | Page 2 of 52

ADM1060

GENERAL DESCRIPTION

simple sequencing operation would be to daisy-chain each PLB

output into the input of the next PLB such that PDO9 does not

assert until PDO8 asserts, which in turn does not assert until

PDO7 asserts, and so on.

(continued from Page 1)

All of the inputs and outputs described previously are

controlled by the programmable logic block array (PLBA). This

is the logic core of the ADM1060. It is comprised of nine

macrocells, one for each PDO. These macrocells are essentially

just wide AND gates. Any/all of the inputs can be used as an

input to these macrocells. The output of a macrocell can also be

used as an input to any macrocell other than itself (an input to

itself would result in a nonterminating loop). The PLBA outputs

control the PDOs of the ADM1060 via delay blocks, where a

delay of 0 ms to 500 ms can be programmed on the rising

and/or the falling edge of the data. This results in a very flexible

sequencing ability. Thus, for instance, PDO1 can be

All of the functional capability described here is programmable

through the industry-standard 2-wire bus (SMBus) provided.

Device settings can be written to EEPROM memory for auto-

matic programming of the device on power-up. The EEPROM

is organized in 512 bytes, half of which are used to program all

of the functions on the ADM1060. The other 256 bytes of

EEPROM are for general-purpose system use such as date codes

and system ID. Read/write access to this is also via the 2-wire

interface. In addition, each output state can be directly over-

driven from the serial interface, allowing a further level of

control, as in a system controlled soft power-down.

programmed so that it will not assert until the VP2, VP3, and

VP4 supplies are in tolerance; VB1 and VH have been in

tolerance for 200 ms; and PDO7 has already been asserted. A

Rev. B | Page 3 of 52

ADM1060

PROGRAMMABLE

DELAY BLOCKS

ADM1060

PDB1

PROGRAMMABLE

LOGIC BLOCK

ARRAY

PDO1

15

(PLBA)

t_RISEt_FALL

HIGH SUPPLY

(14.4V)

FAULT DETECTOR

VH

8

PDB2

PDO2

PDO3

16 PDO2

PLB

MACROCELL 1

POSITIVE

SUPPLY FAULT

DETECTOR 1

VP1

VP2

9

t_RISEt_FALL

PDB3

10

PLB

MACROCELL 2

PDO3

PDO4

17

18

t_RISEt_FALL

VP3 11

PLB

MACROCELL 3

PDB4

POSITIVE

SUPPLY FAULT

DETECTOR 4

VP4

12

PDO4

PLB

MACROCELL 4

t_RISEt_FALL

PDB5

BIPOLAR

SUPPLY FAULT

DETECTOR 1

VB1 13

PLB

MACROCELL 5

PDO5

PDO6

PDO7

PDO8

PDO9

19 PDO5

t_RISEt_FALL

PLB

MACROCELL 6

PDB6

BIPOLAR

SUPPLY FAULT

DETECTOR 2

VB2

14

20

PDO6

t_RISEt_FALL

PLB

MACROCELL 7

GPI1 28

GPI2 27

INPUT LOGIC

SIGNAL

CONDITION

PDB7

GPI3

26

21 PDO7

22 PDO8

23 PDO9

PLB

MACROCELL 8

GPI4 25

WATCHDOG

FAULT

DETECTOR

t_RISEt_FALL

24

WDI

PDB8

PLB

MACROCELL 9

t_RISEt_FALL

PDB9

VREF

GND

6

7

t_RISEt_FALL

INTERNAL

5.25V SUPPLY

VCCP

SMBus DATA

DATA, ADDRESS, AND

REGULATED

5.25V SUPPLY

CHARGE PUMP

100kHz CLOCK

WRITE ENABLE BUSES

TO STORE CONTROL

INFORMATION LOCAL

TO FUNCTIONS

V

DD

ARBITRATOR

DEVICE

CONTROLLER

SMBus INTERFACE

EEPROM

5

4

3

2

1

Figure 1. Functional Block Diagram

Rev. B | Page 4 of 52

ADM1060

SPECIFICATIONS

(VH = 4.75 V to 14.4 V, VPn = 3.0 V to 6.0 V,¹T_A= −40°C to +85°C, unless otherwise noted.)

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER SUPPLY ARBITRATION

VDDCAP

2.7

V

Any VPn ≥ 3.0 V

VH ≥ 4.75 V

Any VPn = 6.0 V

VH = 14.4 V

4.75 5.1

POWER SUPPLY

Supply Current, I_DD

3

5

1

mA

VDDCAP = 4.75 V, no PDO FET drivers on, no

loaded PDO pull-ups to VDDCAP

VDDCAP = 4.75 V, all PDO FET drivers on (loaded

with 1 µA), no PDO pull-ups to VDDCAP

Max additional load that can be drawn from PDO

pull-ups to VDDCAP

Additional Current Available

from VDDCAP²

SUPPLY FAULT DETECTORS

Input Impedance

VH Input

52

190

52

kΩ

%

From VH to GND

From VPn to GND

From VBn to 2.25 V (internal reference)

From VBn to GND (positive mode)

From VBn to GND (negative mode)

VPn Inputs

VBn Inputs

30

Absolute Accuracy (VH, VPn, VBn Inputs)

Calibrated Absolute Accuracy³

VH, VPn Inputs

VBn Inputs

Glitch Filters (Digital)

–2.5

+2.5

–1.0

–1.5

0

+1.0

+1.5

100

%

µs

Factory preprogrammed to specific thresholds

See Figure 19. Eight timeout options between 0 µs

and 100 µs

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge Pump) Mode

(PDOs 1 to 4)

Output Impedance, R_OUT

V_OH

440

12.5 14

kΩ

V

11

I_OH= 0 µA

10.5

12

20

V

µA

I_OH= 1 µA

2 V < V_OH< 7 V

I_OUTAVG

Standard (Digital Output) Mode

(PDOs 1 to 9)

V_OH

2.4

V

V_PU(pull-up to VDDCAP or VPn) > 2.7 V, I_OH= 1 mA

V_PUto VPn = 6.0 V, I_OH= 0 mA

V_PU≤ 2.7 V, I_OH= 1 mA

I_OL= 2 mA

4.5

VPU – 0.3

V_OL

0.4

1.2

V

I_OL= 10 mA

2.0

20

V

I_OL= 15 mA

Total sink current (PDO1–PDO9)

Internal pull-up

Current load on any VPn pull-up (i.e., total source

current available through any number of PDO

pull-up switches configured on to any one)

2

I_SINK

mA

kΩ

mA

R_PULLUP-Weak Pull-Up

I_{SOURCE (VPn)}

20

2

Three-State Output Leakage Current

10

µA

V_PDO= 14.4 V

Rev. B | Page 5 of 52

ADM1060

Parameter

Min

2.0

–1

Typ

Max

Unit

Test Conditions/Comments

DIGITAL INPUTS (GPI 1–4, WDI, A0, A1)⁴

Input High Voltage, V_IH

Input Low Voltage, V_IL

V

µA

pF

µA

0.8

1

Input High Current, I_IH

Input Low Current, I_IL

Input Capacitance

Programmable Pull-Down Current, I_PULLDOWN

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, V_IH

Input Low Voltage, V_IL

Output Low Voltage, V_OL

PROGRAMMABLE DELAY BLOCK

Timeout

V_IN= 5.5 V

V_IN= 0 V

10

If known logic state required

2.0

V

0.8

0.4

I_OUT= −3.0 mA

0

500

ms

s

16 programmable options on both rising and

falling edge

WATCHDOG TIMER INPUT

Timeout

12.8

Eight programmable timeout options

EEPROM RELIABILITY

Endurance^{5, 6}

Data Retention⁷

100

10

Kcycles

Years

SERIAL BUS TIMING⁸

Clock Frequency, f_SCLK

Glitch Immunity, t_SW

Bus Free Time, t_BUF

Start Setup Time, t_SU;STA

Start Hold Time, t_HD;STA

SCL Low Time, t_LOW

SCL High Time, t_HIGH

SCL, SDA Rise Time, t_r

SCL, SDA Fall Time, t_f

Data Setup Time, t_SU;DAT

400

50

kHz

ns

µs

ns

µs

ns

See Figure 27

4.7

4

4.7

4

1000

300

250

300

Data Hold Time, t_HD;DAT

NOTES

¹At least one VPn must be ≥3.0 V if used as supply. VH must be ≥4.5 V if used as supply.

²Specification is not production tested, but is supported by characterization data at initial product release.

³1% threshold accuracy is only achievable on parts preprogrammed by Analog Devices. Contact ADM1060.program@analog.com for further details.

⁴Logic inputs will accept input high voltages up to 5.5 V even when the device is operating at supply voltages below 5 V.

⁵Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C.

⁶For programming and erasing of EEPROM, a minimum V_DD= 3.0 V is required 0°C to +85°C and a minimum V_DD= 4.5 V is required −40°C to 0°C.

⁷Retention lifetime equivalent at junction temperature (T_J) = 55°C as per JEDEC Std. 22 method A117.

⁸Timing specifications are tested at logic levels of V_IL= 0.8 V for a falling edge and V_IH= 2.0 V for a rising edge.

Rev. B | Page 6 of 52

ADM1060

ABSOLUTE MAXIMUM RATINGS

Table 2. Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rat-

ing only; functional operation of the device at these or any

other conditions above those indicated in the operational sec-

tion of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

17 V

Voltage on VH Pin, PDO Pins

Voltage on VP Pins

7 V

Voltage on VB Pins

–7 V to +7 V

–0.3 V to +6.5 V

5 mA

Voltage on Any Other Input

Input Current at Any Pin

Package Input Current

20 mA

Maximum Junction Temperature

(T_Jmax)

THERMAL CHARACTERISTICS

150°C

Storage Temperature Range

–65°C to +150°C

28-Lead TSSOP Package:

θ_JA= 98°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec)

215°C

ESD Rating, All Pins

2000 V

Rev. B | Page 7 of 52

ADM1060

TYPICAL PERFORMANCE CHARACTERISTICS

6

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VP1

5

VH

4

3

2

1

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

V

(V)

V

(V)

VH

VH, VP1

Figure 2. V_VDDCAPvs. V_VHand V_VP1

Figure 5. I_DDvs. V_VH

3.0

2.5

2.0

1.5

1.0

0.5

0

250

200

150

100

50

0

1

2

3

4

5

0

1

2

3

4

5

6

V

(V)

V

(V)

VP1

VH

Figure 3. I_DDvs. V_VP1(Supply)

Figure 6. I_VHvs. V_VH(Not Supply)

300

250

200

150

100

50

300

200

100

–6

–4

–2

0

2

4

6

0

–100

–200

–300

0

–400

0

1

2

3

4

5

V

(V)

V

(V)

VB1

VP1

Figure 4. I_VP1vs. V_VP1(Not Supply)

Figure 7. I_VB1vs. V_VB1

Rev. B | Page 8 of 52

ADM1060

1.5%

1.0%

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= 5V

VP1

V

= 4.75V

VDDCAP

0.5%

0.0%

V

= 2.7V

V

= 3.3V

VP1

VDDCAP

–0.5%

–1.0%

–1.5%

–40

–25

–10

5

20

35

50

65

80

0

5

10

15

20

25

30

35

40

10

80

TEMPERATURE (°C)

I

(µA)

LOAD

Figure 8. Percent Deviation in V_THRESHvs. Temperature

Figure 11. V_PDO(Weak Pull-Up to VP1) vs. Load Current

14.0

1.00

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

0.75

0.50

0.25

0µA LOAD

1µA LOAD

0

–40

–25

–10

5

20

35

50

65

80

0

2

4

6

8

TEMPERATURE (°C)

I

(mA)

LOAD

Figure 9. V_PDO(FET Drive Mode) vs. Temperature

Figure 12. V_PDO(Strong Pull-Down) vs. Load Current

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

V

= 5V

VP1

V

= 3.3V

VP1

0

0.5

1.0

(mA)

1.5

2

0

10

20

30

40

(µA)

50

60

70

I

LOAD

Figure 10. V_PDO(Strong Pull-Up to VP1) vs. Load Current

Figure 13. V_PDO(Weak Pull-Down) vs. Load Current

Rev. B | Page 9 of 52

ADM1060

110

108

106

104

102

100

98

96

94

92

90

–40

–25

–10

5

20

35

50

65

80

TEMPERATURE (°C)

Figure 14. Oscillator Frequency vs. Temperature

6.00

5.75

5.50

5.25

5.00

4.75

4.50

V

= 4.75V

= 2.7V

VDDCAP

V

VDDCAP

0

100

200

I

300

(µA)

LOAD

400

500

Figure 15. VCCP vs. Load Current

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= 2.7V

VDDCAP

V

= 4.75V

VDDCAP

–40

–25

–10

5

20

35

50

65

80

TEMPERATURE (°C)

Figure 16. GPI Threshold vs. Temperature

Rev. B | Page 10 of 52

ADM1060

INPUTS

VH

POWERING THE ADM1060

The ADM1060 is powered from the highest voltage input on

either the Positive Only supply inputs (VPn) or the High Volt-

age supply input (VH). The same pins are used for supply fault

detection (discussed below). A V_DDarbitrator on the device

chooses which supply to use. The arbitrator can be considered

as diode OR’ing the positive supplies together (as shown in

Figure 17).The diodes are supplemented with switches in a syn-

chronous rectifier manner to minimize voltage loss. This loss

can be reduced to ~0.2 V, resulting in the ability to power the

ADM1060 from a supply as low as 3.0 V. Note that the supply on

the VBn pins cannot be used to power the device, even if the

input on these pins is positive. Also, the minimum supply of

3.0 V must appear on one of the VPn pins in order to correctly

power up the ADM1060. A supply of no less than 4.5 V can be

used on VH. This is because there is no synchronous rectifier

circuit on the VH pin, resulting in a voltage drop of ~1.5 V

across the diode of the V_DDarbitrator.

VDDCAP PIN

VP1

VP2

OFF-CHIP

DECOUPLING

CAPACITOR

VP3

VP4

ON-CHIP SUPPLY

Figure 17. V_DDArbitrator Operation

PROGRAMMABLE SUPPLY FAULT DETECTORS

(SFDs)

The ADM1060 has seven programmable supply fault detectors

(SFDs): one high voltage detector (+2 V to +14.4 V), two bipolar

detectors (+1 V to +6 V, −2 V to –6 V) and four positive only

voltage detectors (+0.6 V to +6 V). Inputs are applied to these

detectors via the VH (high voltage supply input), VBn (bipolar

supply input), and VPn (positive only input) pins, respectively.

The SFDs detect a fault condition on any of these input supplies.

A fault is defined as undervoltage (where the supply drops

below a preprogrammed level), overvoltage (where the supply

rises above a preprogrammed level), or out-of-window (where

the supply deviates outside either the programmed overvoltage

or undervoltage threshold). Only one fault type can be selected

at a time.

An external capacitor to GND is required to decouple the

on-chip supply from noise. This capacitor should be connected

to the VDDCAP pin, as shown in Figure 17. The capacitor has

another use during “brown outs” (momentary loss of power).

Under these conditions, where the input supply, VPn, dips

transiently below V_DD, the synchronous rectifier switch

immediately turns off so that it does not pull V_DDdown. The

V_DDcapacitor can then act as a reservoir to keep the chip active

until the next highest supply takes over the powering of the

device. A 1 µF capacitor is recommended for this function. A

minimum capacitor value of 0.1 µF is required.

An undervoltage (UV) fault is detected by comparing the input

supply to a programmed reference (the undervoltage threshold).

If the input voltage drops below the undervoltage threshold, the

output of the comparator goes high, asserting a fault. The

undervoltage threshold is programmed using an 8-bit DAC. On

a given range, the UV threshold can be set with a resolution of

Note that in the case where there are two or more supplies

within 100 mV of each other, the supply that takes control of

V_DDfirst will keep control. For example, if VP1 is connected to a

3.3 V supply, V_DDwill power up to approximately 3.1 V through

VP1. If VP2 is then connected to another 3.3 V supply, VP1 will

still power the device, unless VP2 goes 100 mV higher than

VP1.

Step Size = Threshold Range/255

A second capacitor is required on the VCCP pin of the

ADM1060. This capacitor is the reservoir capacitor for the

central charge pump. Again, a 1 µF capacitor is recommended

for this function. A minimum capacitor value of 0.1 µF is

required.

An overvoltage (OV) fault is detected in exactly the same way,

using a second comparator and DAC to program the reference.

All thresholds are programmed using 8-bit registers, one regis-

ter each for the seven UV thresholds and one each for the seven

OV thresholds. The UV or OV threshold programmed by the

user is given by

V_R×N

255

V_T

=

+V_B

Rev. B | Page 11 of 52

ADM1060

VPn

where

Voltage Range

0.6 V to 1.8 V

1 V to 3 V

V_B(V)

0.604

1.003

2.005

4.849

–1.994

V_R(V)

1.204

1.999

3.997

9.666

–3.995

OV

RANGE SELECT

DAC (1 OR 2 BITS)

COMPARATOR

GLITCH

FILTER

2 V to 6 V

FAULT

OUTPUT

VREF

4.8 V to 14.4 V

–2 V to –6 V

DUAL 8-BIT

DAC FOR

SETTING UV

AND OV

FAULT TYPE

SELECT

UV

V_Tis the desired threshold voltage (UV or OV)

V_Ris the threshold voltage range

COMPARATOR

THRESHOLDS

N is the decimal value of the 8 bit code

V_Bis the bottom of threshold range

Figure 18. Positive Programmable Supply Fault Detector

SFD COMPARATOR HYSTERESIS

The code for a given threshold is therefore given by

The OV and UV comparators shown in Figure 18 are always

looking at VPn via a potential divider. In order to avoid

chattering (multiple transitions when the input is very close to

the set threshold level), these comparators have digitally

programmable hysteresis. The UV and OV hysteresis can be

programmed in two registers that are similar but separate to the

UV or OV threshold registers. Only the five LSBs of these

registers can be set. The hysteresis is added after the supply

voltage goes out of tolerance. Thus, the user can determine how

much above the UV threshold the input must rise again before a

UV fault is deasserted. Similarly, the user can determine how

much below the OV threshold the input must fall again before

an OV fault is deasserted. The hysteresis figure is given by

N = 255 × (V_T– V_B)/V_R

For example, if the user wishes to set a 5 V OV threshold on

VP1, the code to be programmed in the PS1OVTH register

(discussed later) would be

N = 255 × (5 – 2.005)/3.997

Thus, N = 191 (1011 1111 binary, or 0xBF)

The available threshold ranges and their resolutions are shown

in Table 3. Note that the low end of the detection range is fixed

at 33.33% of the top of the range. Note also that for a given SFD,

the ranges overlap; for example, VH goes from 2 V to 6 V and

then from 4.8 V to 14.4 V. This is to provide better threshold

setting resolution as supplies decrease in value.

V_H= V_R× N_THRESH/255

where

Table 3. Input Threshold Ranges and Resolution

V_His the desired hysteresis voltage

Input Name

Voltage Ranges

4.8 V to 14.4 V

2 V to 6 V

Resolution

37.6 mV

N_THRESHis the decimal value of the 5-bit hysteresis code

VH

15.6 mV

Therefore, if the low range threshold detector was selected, the

max hysteresis is defined as

2 V to 6 V

15.6 mV (Pos. Mode)

7.8 mV (Pos. Mode)

15.6 mV (Neg. Mode)

15.6 mV

VBn

VPn

1 V to 3 V

−6 V to −2 V

2 V to 6 V

(3 V – 1 V) × 31/255 = 242 mV, where (2⁵– 1 = 31)

The hysteresis programming resolution is the same as the

threshold detect ranges—that is, 37.5 mV on the high range,

15.6 mV on the midrange, 7.8 mV on the low range, and 4.7 mV

on the ultralow range.

1 V to 3 V

7.8 mV

0.6 V to 1.8 V

4.7 mV

Figure 18 illustrates the function of the programmable SFD (for

the case of a positive supply).

BIPOLAR SFDs

The two bipolar SFDs also allow the detection of faults on nega-

tive supplies. A polarity bit in the setup register for this SFD

(Bit 7 in Register BSnSEL—see register map overleaf) deter-

mines if a positive or negative input should be applied to VBn.

Only one range (−6 V to −2 V) is available when the SFDs are in

negative mode. Note that the bipolar SFDs cannot be used to

power the ADM1060, even if the voltage on VBn is positive.

Rev. B | Page 12 of 52

ADM1060

GLITCH FILTER INPUT

PROGRAMMED TIMEOUT

SFD FAULT TYPES

PROGRAMMED TIMEOUT

Three types of faults can be asserted by the SFD: an OV fault, a

UV fault, and an out-of-window fault (where the UV and OV

faults are OR’ed together). The type of fault required is

programmed using the fault type select bits (Bits 0, 1 in Register

_SnSEL). If an application requires separate fault conditions to

be detected on one supply (e.g., assert PDO1 if a UV fault

occurs on a 3.3 V supply, assert PDO9 if an OV fault occurs on

the same 3.3 V supply), that supply will need to be applied to

more than one input pin.

t₀

t_GF

t₀

t_GF

GLITCH FILTER OUTPUT

GLITCH FILTERING ON THE SFDs

t₀

t_GF

t₀

t_GF

The final stage of the SFD is a glitch filter. This block provides

time domain filtering on the output of the SFD. This allows the

user to remove any spurious transitions (such as supply bounce

at turn-on). This deglitching function is in addition to the

programmable hysteresis of the SFDs. The glitch filter timeout

is programmable up to 100 µs. If a pulse shorter than the

programmed timeout appears on the input, this pulse is masked

and the signal change will appear on the output. If an input

pulse longer than the programmed timeout appears on the

input, this pulse will appear on the output. The output will be

delayed (with respect to the input) by the length of the

programmed timeout.

Figure 19. Glitch Filtering on the SFDs

PROGRAMMING THE SFDs ON THE SMBus

The details of using the SMBus are described later, but the regis-

ter names associated with the supply fault detector blocks, the

bit map of those registers, and the function of each of the bits is

described in the following tables. The tables show how to set up

UV threshold, UV hysteresis, OV threshold, OV hysteresis,

glitch filtering, and fault type for each of the SFDs on the

ADM1060.

Figure 19 shows the implementation of glitch filtering.

Rev. B | Page 13 of 52

ADM1060

SFD REGISTER NAMES

Table 4. List of Registers for the Supply Fault Detectors

Hex

Default

Power-On Value

Address Table

Name

Description

A0

A1

A2

A3

A4

A8

A9

AA

AB

AC

B0

B1

B2

B3

B4

B8

B9

BA

BB

BC

C0

C1

C2

C3

C4

C8

C9

CA

CB

CC

D0

D1

D2

D3

D4

Table 5

BS1OVTH

BS1OVHYST

BS1UVTH

BS1UVHYST

BS1SEL

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

Overvoltage Threshold for Bipolar Voltage SFD1 (BS1SFD)

Digital Hysteresis on OV Threshold for BS1SFD

Undervoltage Threshold for BS1SFD

Table 6

Table 7

Table 8

Digital Hysteresis on UV Threshold for BS1SFD

Glitch Filter, Range, and Fault Type Select for BS1SFD

Overvoltage Threshold for Bipolar Voltage SFD2 (BS2SFD)

Digital Hysteresis on OV Threshold for BS2SFD

Undervoltage Threshold for BS2SFD

Table 9

Table 5

BS2OVTH

BS2OVHYST

BS2UVTH

BS2UVHYST

BS2SEL

Table 6

Table 7

Table 8

Digital Hysteresis on UV Threshold for BS2SFD

Glitch Filter, Range, and Fault Type Select for BS2SFD

Overvoltage Threshold for High Voltage SFD (HVSFD)

Digital Hysteresis on OV Threshold for HVSFD

Undervoltage Threshold for HVSFD

Table 9

Table 10

Table 11

Table 12

Table 13

Table 14

Table 15

Table 16

Table 17

Table 18

Table 19

Table 15

Table 16

Table 17

Table 18

Table 19

Table 15

Table 16

Table 17

Table 18

Table 19

Table 15

Table 16

Table 17

Table 18

Table 19

HSOVTH

HSOVHYST

HSUVTH

HSUVHYST

HSSEL

Digital Hysteresis on UV Threshold for HVSFD

Glitch Filter, Range, and Fault Type Select for HVSFD

Overvoltage Threshold for Positive Voltage SFD1 (PS1SFD)

Digital Hysteresis on OV Threshold for PS1SFD

Undervoltage Threshold for PS1SFD

PS1OVTH

PS1OVHYST

PS1UVTH

PS1UVHYST

PS1SEL

Digital Hysteresis on UV Threshold for PS1SFD

Glitch Filter, Range, and Fault Type Select for PS1SFD

Overvoltage Threshold for Positive Voltage SFD2 (PS2SFD)

Digital Hysteresis on OV Threshold for PS2SFD

Undervoltage Threshold for PS2SFD

PS2OVTH

PS2OVHYST

PS2UVTH

PS2UVHYST

PS2SEL

Digital Hysteresis on UV Threshold for PS2SFD

Glitch Filter, Range, and Fault Type Select for PS2SFD

Overvoltage Threshold for Positive Voltage SFD3 (PS3SFD)

Digital Hysteresis on OV Threshold for PS3SFD

Undervoltage Threshold for PS3SFD

PS3OVTH

PS3OVHYST

PS3UVTH

PS3UVHYST

PS3SEL

Digital Hysteresis on UV Threshold for PS3SFD

Glitch Filter, Range, and Fault Type Select for PS3SFD

Overvoltage Threshold for Positive Voltage SFD4 (PS4SFD)

Digital Hysteresis on OV Threshold for PS4SFD

Undervoltage Threshold for PS4SFD

PS4OVTH

PS4OVHYST

PS4UVTH

PS4UVHYST

PS4SEL

Digital Hysteresis on UV Threshold for PS4SFD

Glitch Filter, Range, and Fault Type Select for PS4SFD

Rev. B | Page 14 of 52

ADM1060

SFD Register Bit Maps

BIPOLAR SUPPLY FAIL DETECT (BSn SFD) REGISTERS

Table 5. Register 0xA0, 0xA8 BSnOVTH

(Power-On Default 0xFF)

Table 7. Register 0xA2, 0xAA BSnUVTH

(Power-On Default 0x00)

Bit

Name

R/W Description

Bit

Name

R/W Description

7–0

OV7–OV0

R/W 8-Bit Digital Value for OV

Threshold on BSn SFD

7–0

UV7–UV0 R/W 8-Bit Digital Value for UV Thresh-

old on BSn SFD

Table 6. Register 0xA1, 0xA9 BSnOVHYST

(Power-On Default 0x00)

Table 8. Register 0xA3, 0xAB BSnUVHYST

(Power-On Default 0x00)

Bit

Name

R/W Description

Bit

Name

R/W Description

7–5

4–0

Reserved

HY4–HY0

N/A Cannot Be Used

7–5

4–0

Reserved N/A Cannot Be Used

R/W 5-Bit Digital Value for Hysteresis

on OV Threshold of BSn SFD

HY4–HY0 R/W 5-Bit Digital Value for Hysteresis

on UV Threshold of BSn SFD

Table 9. Register 0xA4, 0xAC BSnSEL (Power-On Default 0x00)

Bit

Name

R/W

Description

7

POL

R/W

Polarity of Bipolar

SFDn

POL

Sign of Detection Range

0

Positive

1

Negative

6−4

GF2−GF0 R/W

GF2

GF1

0

GF0

0

Glitch Filter Delay (µs)

0

1

5

0

1

0

10

20

30

50

75

100

0

1

0

1

0

1

0

1

3

2

Reserved N/A

Cannot Be Used

RSEL

R/W

Note: When POL is set to 1 (SFD is in negative mode), RSEL is unused since there is only one range in

this mode.

RSEL1

Bottom of Range

Top of Range

3 V

Step Size (mV)

0

1 V

2 V

FS0

0

7.8

1

6 V

15.6

1−0

FS1−FS0

R/W

FS1

0

Fault Select Type

Overvoltage

Undervoltage

Out-of-Window

Not Allowed

0

1

0

1

Rev. B | Page 15 of 52

ADM1060

HIGH VOLTAGE SUPPLY FAULT DETECT (HV SFD) REGISTERS

Table 10. Register 0xB0 HSOVTH

(Power-On Default 0xFF)

Table 12. Register 0xB2 HSUVTH

(Power-On Default 0x00)

Bit

Name

R/W Description

Bit

Name

R/W Description

7–0

OV7–OV0

R/W 8-Bit Digital Value for OV

Threshold on HV SFD

7–0

UV7–UV0 R/W 8-Bit Digital Value for UV

Threshold on HV SFD

Table 11. Register 0xB1 HSOVHYST

(Power-On Default 0x00)

Table 13. Register 0xB3 HSUVHYST

(Power-On Default 0x00)

Bit

Name

R/W Description

Bit

Name

R/W Description

7–5

4–0

Reserved

HY4–HY0

N/A Cannot Be Used

7–5

4–0

Reserved N/A Cannot Be Used

R/W 5-Bit Digital Value for Hysteresis

on OV Threshold of HV SFD

HY4–HY0 R/W 5-Bit Digital Value for Hysteresis

on UV Threshold of HV SFD

Table 14. Register 0xB4 HSSEL (Power-On Default 0x00)

Bit

7

Name

R/W

N/A

R/W

Description

Reserved

GF2−GF0

Cannot Be Used

6−4

GF2

GF1

0

GF0

0

Glitch Filter Delay (µs)

0

1

5

0

1

0

10

20

30

50

75

100

0

1

0

1

0

1

0

1

3

2

Reserved

RSEL

N/A

W

Cannot Be Used

RSEL

Bottom of Range

Top of Range

6 V

Step Size (mV)

0

2 V

4.8 V

FS0

0

15.6

37.6

1

14.4 V

1−0

FS1−FS0

W

FS1

0

Fault Select Type

Overvoltage

Undervoltage

Out-of-Window

Not Allowed

0

1

0

1

Rev. B | Page 16 of 52

ADM1060

POSITIVE VOLTAGE SUPPLY FAULT DETECT (PSn SFD) REGISTERS

Table 15. Register 0xB8, 0xC0, 0xC8, 0xD0 PSnOVTH

(Power-On Default 0xFF)

Table 17. Register 0xBA, 0xC2, 0xCA, 0xD2 PSnUVTH

(Power-On Default 0x00)

Bit Name Description

Bit

Name

R/W Description

W

7−0 OV7−OV0 R/W 8-Bit Digital Value for OV Thresh-

old on PSn SFD.

7−0 UV7−UV0 R/W 8-Bit Digital Value for UV Thresh-

old on PSn SFD

Table 16. Register 0xB9, 0xC1, 0xC9, 0xD1 PSnOVHYST

(Power-On Default 0x00)

Table 18. Register 0xBB, 0xC3, 0xCB, 0xD3 PSnUVHYST

(Power-On Default 0x00)

Bit

Name

R/W Description

Bit

Name

W

Description

7–5 Reserved N/A Cannot Be Used

7−5 Reserved N/A Cannot Be Used

4−0 HY4−HY0 R/W 5-Bit Digital Value for Hysteresis

on OV Threshold of PSn SFD

4−0 HY4−HY0 R/W 5-Bit Digital Value for Hysteresis

on UV Threshold of PSn SFD

Table 19. Register 0xBC, 0xC4, 0xCC, 0xD4 PSnSEL (Power-On Default 0x00)

Bit

7

Name

R/W

N/A

R/W

Description

Reserved

GF2−GF0

Cannot Be Used

6−4

GF2

GF1

GF0

Glitch Filter Delay (µs)

0

1

5

0

1

0

10

0

1

20

1

0

30

1

0

1

50

1

0

75

1

100

3−2

1–0

RSEL1−RESL0 R/W

RSEL1

RSEL0

Bottom of Range

2 V

Top of Range

Step Size (mV)

0

6 V

15.6

7.8

0

1

1 V

3 V

1

X

0.6 V

1.8 V

4.7

FS1−FS0

R/W

FS1

0

FS0

0

Fault Select Type

Overvoltage

Undervoltage

Out-of-Window

Not Allowed

0

1

0

1

Rev. B | Page 17 of 52

ADM1060

WATCHDOG FAULT DETECTOR

watchdog signals can be selected as inputs to each of the PLBs

(see the PLBA section). They can also be inverted, if required;

for example, if a high-low-high pulse were required by a proces-

sor to reset. Thus, a fault on the watchdog can be used to

generate a pulsed or latched output on any or all of the nine

PDOs.

The ADM1060 has a watchdog fault detector. This can be used

to monitor a processor clock to ensure normal operation. The

detector monitors the WDI pin, expecting a low-to-high or

high-to-low transition within a preprogrammed period. The

watchdog timeout period can be programmed from 200 ms to a

maximum of 12.8 sec.

The latched signal can be cleared low by reading LATF1, then

LATF2 across the SMBus interface (see the Fault Registers sec-

tion). The RAM register list and the bit map for the watchdog

fault detector are shown below.

If no transition is detected, two signals are asserted. One is a

latched high signal, indicating a fault has occurred. The other

signal is a low-high-low pulse that can be used as a RESET sig-

nal for a processor core. The width of this pulse can be

programmed from 10 µs to a maximum of 10 ms. These two

Table 20. Watchdog Fault Detector Registers

Hex Address Table

Name

Default Power-On Value Description

9C Table 21 WDCFG 0x00

Program Length Watchdog Timeout and Length of Pulsed Output

Table 21. WDCFG Register 0x9C (Power-On Default 0x00)

Bit

Name

R/W

Description

7−5

4−3

Reserved

R/W

Unused

PULS1−PULS0 R/W

Length of Pulse Output once

the Watchdog Detector has

Timed Out

PULS1 PULS0 Pulse Length Selected (µs)

0

10

0

1

100

1

0

1,000

1

10,000

2–0

PER2−PER0

R/W

Watchdog Timeout Period

PER2

PER1

PER0

Watchdog Timeout Selected (ms)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Disabled

200

400

800

1,600

3,200

6,400

12,800

Rev. B | Page 18 of 52

ADM1060

debounce a manual reset switch. The length of the glitch filter

can also be programmed.

GENERAL-PURPOSE INPUTS (GPIs)

The ADM1060 has four general-purpose logic inputs (GPIs).

These are TTL/CMOS logic level compatible. Standard logic

signals can be applied to the pins: RESET from reset generators,

PWRGOOD signals, fault flags, manual resets, and so on. These

signals can be gated with the other inputs supervised by the

ADM1060 and used to control the status of the PDOs. The

inputs can be simply buffered, or a logic transition can be

detected and a pulse output generated. The width of this pulse is

programmable from 10 µs to a maximum of 10 ms. The

configuration of the GPIs is shown in the register and bit maps

below.

LOGIC STATE OF THE GPIs AND OTHER LOGIC

INPUTS

Each of the GPIs can have a weak (10 µA) pull-down current

source. The current sources can be connected to the inputs by

progamming the relevant bit in the PDEN register. This enables

the user to control the condition of these inputs, pulling them to

GND even when they are unused or left floating.

Note that the same pull-down function is provided for the

SMBus address pins, A0 and A1, and for the WDI pin. A register

is used to program which of the inputs is connected to the cur-

rent sources.

The GPIs also feature a glitch filter similar to that provided on

the SFDs. This enables the user to ignore spurious transitions

on the GPIs. For example, the glitch filter can be used to

Table 22. General-Purpose Inputs (GPIn) Registers

Hex Address

Name

Default Power-On Value

Description

98

GPI4CFG

0x00

GPI4 configuration setup of the glitch filter delay, pulse width,

level/edge detection, etc.

99

9A

9B

GPI3CFG

GPI2CFG

GPI1CFG

0x00

GPI3 configuration setup of the glitch filter delay, pulse width,

level/edge detection, etc.

GPI2 configuration setup of the glitch filter delay, pulse width,

level/edge detection, etc.

GPI1 configuration setup of the glitch filter delay, pulse width,

level/edge detection, etc.

Table 23. GPInCFG Registers Bit Map (Power-On Default 0x00)

Bit

7

Name

R/W

Description

Reserved N/A

Cannot Be Used

If High, Invert Input

6

INVIN

INTYP

R/W

5

Determines whether a Level or an Edge is Detected on

the Pin. If an edge is detected, a positive pulse of

programmable length is output.

INTYP Detect

0

1

Detect Level

Detect Edge

4–3

2–0

PULS1−0 R/W

GF2−GF0 R/W

Length of Pulse Output Once an Edge Has Been

Detected on Input

PULS1 PULS0 Pulse Length Selected (µs)

0

1

0

1

0

1

10

100

1,000

10,000

Length of Time for which the Input Is Ignored

Glitch Filter

Delay (µs)

GF2

0

GF1

0

GF0

0

1

5

0

1

0

10

20

30

50

75

100

0

1

0

1

0

1

0

1

Rev. B | Page 19 of 52

ADM1060

Table 24. Registers for the Pull-Down Current Sources on Logic Inputs

Hex Address

Name

Default Power On Value Description

0x00

Setup of the Pull-Down Current Sources on All Logic Inputs. Pulls the

selected input to GND.

91

PDEN

Table 25. PDEN Register 0x91 Bit Map (Power-On Default 0x00)

Bit Name

R/W Description

7

6

5

4

3

2

1

0

Reserved

N/A Cannot Be Used

PDENA1

PDENA0

R/W If high, address pin A1 is pulled to GND using a 10 µA pull-down current source.

R/W If high, address pin A0 is pulled to GND using a 10 µA pull-down current source.

PDENWDI R/W If high, WDI is pulled to GND using a 10 µA pull-down current source.

PDENGPI4 R/W If high, GPI4 is pulled to GND using a 10 µA pull-down current source.

PDENGPI3 R/W If high, GPI3 is pulled to GND using a 10 µA pull-down current source.

PDENGPI2 R/W If high, GPI2 is pulled to GND using a 10 µA pull-down current source.

PDENGPI1 R/W If high, GPI1 is pulled to GND using a 10 µA pull-down current source.

Rev. B | Page 20 of 52

ADM1060

PROGRAMMING

Table 26. Truth Table for PLB Input Inversion

PROGRAMMABLE LOGIC BLOCK ARRAY

POL Input Signal XOR Output

The ADM1060 contains a programmable logic block array

(PLBA). This block is the logical core of the device. The PLBA

(and the PDBs—see the Programmable Delay Block section)

provides the sequencing function of the ADM1060. The asser-

tion of the nine programmable driver outputs (PDO) is

controlled by the PLBA. The PLBA is comprised of nine macro-

cells, one per PDO channel. The main components of the

macrocells are two wide AND-OR gates, as shown in Figure 20.

Each AND gate represents a function (A or B) that can be used

independently to control the assertion of the PDO pin. There

are 21 inputs to each of these AND gates:

0

1

0

1

0

1

0

1

0

The last two entries in the truth table show that with the

INVERT (POL) bit set, the XOR output is always the inverse of

the input.

Similarly, the ignore gate shown is an OR gate, resulting in the

following truth table:

Table 27. Truth Table for PLB Input Masking

IMK Input Signal OR Output

•

The logic outputs of all seven supply fault detectors

The four GPI logic inputs

The watchdog fault detector (latched and pulsed)

The delayed output of any of the other macrocells (the

output of a macrocell cannot be an input to itself, since this

would result in a nonterminating loop).

0

1

0

1

0

1

0

1

It can be seen here that once the IMK bit is set, the OR output is

always 1, regardless of the input, thus ignoring it. Figure 21 is a

detailed diagram of the 21 inputs and the registers required to

program them. Those shown are just for function A of PLB1,

but function B and all of the functions in the other eight PLBs

are programmed exactly the same way. An enable register allows

the user to use function A, function B, or both. The output of

functions A and/or B is input to a programmable delay block

(PDB) where a delay can be programmed on both the rising and

falling edges of an input (see the Programmable Delay Block

section). The output of this PDB block can be progammed to

invert before any of the PDO pins is asserted.

All 21 inputs are hardwired to both function A and function B

AND gates. The user can then select which of these inputs con-

trols the output. This is done using two control signals, IMK (a

masking bit, setting it ignores the relevant input) and POL (a

polarity bit, setting it inverts the input before it is applied to the

AND gate). The effect of setting these bits can be seen in

Figure 20. The inverting gate shown is an XOR gate, resulting in

the following truth table:

SIGNAL INPUTS

POL (INVERT)

IMK (IGNORE)

ENABLE

FUNCTION A

PROGRAMMABLE

DELAY

2 WIDE AND GATES

(21 INPUTS)

PLBOUT

BLOCK

INVERT

OUTPUT

ENABLE

FUNCTION B

Figure 20. Simplified Programmable Logic Block Macrocell Schematic

Rev. B | Page 21 of 52

ADM1060

LOGIC

NOT CONNECTED

PLB1

PLB2

INVERT

0x00 P1PLBPOLA.0

IGNORE 0x01 P1PLBIMKA.0

PLB3

PLB4

INVERT

0x00 P1PLBPOLA.1

IGNORE 0x01 P1PLBIMKA.1

INVERT

0x00 P1PLBPOLA.2

IGNORE 0x01 P1PLBIMKA.2

PLB5

PLB6

INVERT

0x00 P1PLBPOLA.3

IGNORE 0x01 P1PLBIMKA.3

INVERT

0x00 P1PLBPOLA.4

IGNORE 0x01 P1PLBIMKA.4

PLB7

PLB8

INVERT

0x00 P1PLBPOLA.5

IGNORE 0x01 P1PLBIMKA.5

INVERT

0x00 P1PLBPOLA.6

IGNORE 0x01 P1PLBIMKA.6

PLB9

INVERT

0x00 P1PLBPOLA.7

IGNORE 0x01 P1PLBIMKA.7

VB1

INVERT

0x02 P1SFDPOLA.0

ENABLE

FUNCTION A

IGNORE 0x03 P1SFDIMKA.0

VB2

VH

0x07 P1EN.1

INVERT

RISE TIME

0x02 P1SFDPOLA.1

IGNORE 0x03 P1SFDIMKA.1

0x0C P1PDBTIM.7–4

INVERT

0x02 P1SFDPOLA.2

PDB

IGNORE 0x03 P1SFDIMKA.2

PLBOUT

VP1

INVERT

0x02 P1SFDPOLA.3

0x0C P1PDBTIM.3–0

FALL TIME

TO

FUNCTION B

IGNORE 0x03 P1SFDIMKA.3

0x07 P1EN.2

VP2

VP3

VP4

INVERT

0x02 P1SFDPOLA.4

IGNORE 0x03 P1SFDIMKA.4

INVERT

0x02 P1SFDPOLA.5

IGNORE 0x03 P1SFDIMKA.5

INVERT

0x02 P1SFDPOLA.6

IGNORE 0x03 P1SFDIMKA.6

GPI1

INVERT

0x04 P1GPIPOL.4

IGNORE 0x05 P1GPIIMK.4

GPI2

GPI3

INVERT

0x04 P1GPIPOL.5

IGNORE 0x05 P1GPIIMK.5

INVERT

0x04 P1GPIPOL.6

IGNORE 0x05 P1GPIIMK.6

GPI4

INVERT

0x04 P1GPIPOL.7

IGNORE 0x05 P1GPIIMK.7

WDI

_

P

L

INVERT

0x06 P1WDICFG.7

IGNORE 0x06 P1WDICFG.6

WDI

_

INVERT

0x06 P1WDICFG.5

IGNORE 0x06 P1WDICFG.4

Figure 21. Detailed Diagram for Function A of PLB1

Rev. B | Page 22 of 52

ADM1060

1. The IGNORE bit of all the other inputs (GPIs, PDBs, WDI)

in the relevant P1xxxIMK registers is set to 1. Thus, regard-

less of its status, the input to the function AND gate for

these inputs will be 1.

The control bits for these macrocells are stored locally in latches

that are loaded at power-up. These latches can also be updated

via the serial interface. The registers containing the macrocell

control bits and the function of each bit are defined in the tables

that follow.

2. Since the SFDs assert a 1 under a fault condition and a 0

when the supplies are in tolerance, the SFD outputs need to

be inverted before being applied to the function. Thus the

relevant bit in the P1SFDPOL register is set (see Table 38).

Figure 21 highlights all 21 inputs to a given function and the

register/bits that need to be set in order to condition the 21

inputs correctly. The diagram only shows function A of Pro-

grammable Logic Block 1 (PLB1), but all functions are

programmed in the same way.

3. The function is enabled (Bit 1 of Register P1EN—see

Table 36).

For example, if the user wishes to assert PLBOUT 200 ms after

all of the supplies are in spec (PLBOUT may be used to drive

the enable pin of an LDO), the supply fault detectors VBn, VH,

and VPn are required to control the function. The function is

programmed as follows:

4. A rise time of 200 ms is programmed (register

P1PDBTIM—see register map for details).

Table 28. Programmable Logic Block Array (PLBA) Registers

Hex

Address

Default Power-

On Value

Table

Name

Description

00

01

02

03

04

05

06

Table 29

P1PLBPOLA 0x00

Polarity sense for all eight other PLB outputs when used as inputs to the

A function of PLB1

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

P1PLBIMKA 0x00

Ignore mask for all eight other PLB outputs when used as inputs to the A

function of PLB1

P1SFDPOLA 0x00

P1SFDIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB1

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB1

P1GPIPOL

P1GPIIMK

P1WDICFG

0x00

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the A function of PLB1

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the B function of PLB1

Polarity sense and ignore mask bits for the pulsed and latched outputs of

the watchdog detector when used as inputs to both A and B functions of

PLB1

07

08

Table 36

Table 29

PS1EN

0x00

Enable bits for A and B functions of PLB1, polarity bit for PLB1 output

P1PLBPOLB

Polarity sense for all eight other PLB outputs when used as inputs to the

B function of PLB1

09

0A

0B

10

11

12

13

14

Table 30

Table 31

Table 32

Table 29

Table 30

Table 31

Table 32

Table 33

P1PLBIMKB

0x00

Ignore mask for all eight other PLB outputs when used as inputs to the B

function of PLB1

P1SFDPOLB 0x00

P1SFDIMKB 0x00

P2PLBPOLA 0x00

P2PLBIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB1

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB1

Polarity sense for all eight other PLB outputs when used as inputs to the

A function of PLB2

Ignore mask for all eight other PLB outputs when used as inputs to the A

function of PLB2

P2SFDPOLA 0x00

P2SFDIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB2

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB2

P2GPIPOL

0x00

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the A function of PLB2

Rev. B | Page 23 of 52

ADM1060

Hex

Address

Default Power-

On Value

Table

Name

Description

15

Table 34

P2GPIIMK

0x00

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the B function of PLB2

16

Table 35

P2WDICFG

0x00

Polarity sense and ignore mask bits for the pulsed and latched outputs of the

watchdog detector when used as inputs to both A and B functions of PLB2

17

18

Table 36

Table 29

PS2EN

0x00

Enable bits for A and B functions of PLB2, polarity bit for PLB2 output

P2PLBPOLB

Polarity sense for all eight other PLB outputs when used as inputs to the

B function of PLB2

19

1A

1B

20

21

22

23

24

25

26

Table 30

Table 31

Table 32

Table 29

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

P2PLBIMKB

0x00

Ignore mask for all eight other PLB outputs when used as inputs to the B

function of PLB2

P2SFDPOLB 0x00

P2SFDIMKB 0x00

P3PLBPOLA 0x00

P3PLBIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB2

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB2

Polarity sense for all eight other PLB outputs when used as inputs to the

A function of PLB3

Ignore mask for all eight other PLB outputs when used as inputs to the A

function of PLB3

P3SFDPOLA 0x00

P3SFDIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB3

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB3

P3GPIPOL

P3GPIIMK

P3WDICFG

0x00

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the A function of PLB3

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the B function of PLB3

Polarity sense and ignore mask bits for the pulsed and latched outputs of

the watchdog detector when used as inputs to both A and B functions of

PLB3

27

28

Table 36

Table 29

PS3EN

0x00

Enable bits for A and B functions of PLB3, polarity bit for PLB3 output

P3PLBPOLB

Polarity sense for all eight other PLB outputs when used as inputs to the

B function of PLB3

29

2A

2B

30

31

32

33

34

35

36

Table 30

Table 31

Table 32

Table 29

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

P3PLBIMKB

0x00

Ignore mask for all eight other PLB outputs when used as inputs to the B

function of PLB3

P3SFDPOLB 0x00

P3SFDIMKB 0x00

P4PLBPOLA 0x00

P4PLBIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB3

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB3

Polarity sense for all eight other PLB outputs when used as inputs to the

A function of PLB1

Ignore mask for all eight other PLB outputs when used as inputs to the A

function of PLB1

P4SFDPOLA 0x00

P4SFDIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB1

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB1

P4GPIPOL

P4GPIIMK

P4WDICFG

0x00

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the A function of PLB1

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the B function of PLB1

Polarity sense and ignore mask bits for the pulsed and latched outputs of

the watchdog detector when used as inputs to both A and B functions of

PLB4

37

38

Table 36

Table 29

PS4EN

0x00

Enable bits for A and B functions of PLB4, polarity bit for PLB4 output

P4PLBPOLB

Polarity sense for all eight other PLB outputs when used as inputs to the

B function of PLB4

Rev. B | Page 24 of 52

ADM1060

Hex

Address

Default Power-

On Value

Table

Name

Description

39

3A

3B

40

41

42

43

44

45

46

Table 30

P4PLBIMKB

0x00

Ignore mask for all eight other PLB outputs when used as inputs to the B

function of PLB4

Table 31

Table 32

Table 29

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

P4SFDPOLB 0x00

P4SFDIMKB 0x00

P5PLBPOLA 0x00

P5PLBIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB4

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB4

Polarity sense for all eight other PLB outputs when used as inputs to the

A function of PLB5

Ignore mask for all eight other PLB outputs when used as inputs to the A

function of PLB5

P5SFDPOLA 0x00

P5SFDIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB5

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB5

P5GPIPOL

P5GPIIMK

P5WDICFG

0x00

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the A function of PLB5

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the B function of PLB5

Polarity sense and ignore mask bits for the pulsed and latched outputs of the

watchdog detector when used as inputs to both A and B functions of PLB5

47

48

Table 36

Table 29

PS5EN

0x00

Enable bits for A and B functions of PLB5, polarity bit for PLB5 output

P5PLBPOLB

Polarity sense for all eight other PLB outputs when used as inputs to the

B function of PLB5

49

4A

4B

50

51

52

53

54

55

56

Table 30

Table 31

Table 32

Table 29

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

P5PLBIMKB

0x00

Ignore mask for all eight other PLB outputs when used as inputs to the B

function of PLB5

P5SFDPOLB 0x00

P5SFDIMKB 0x00

P6PLBPOLA 0x00

P6PLBIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB5

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB5

Polarity sense for all eight other PLB outputs when used as inputs to the

A function of PLB6

Ignore mask for all eight other PLB outputs when used as inputs to the A

function of PLB6

P6SFDPOLA 0x00

P6SFDIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB6

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB6

P6GPIPOL

P6GPIIMK

P6WDICFG

0x00

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the A function of PLB6

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the B function of PLB6

Polarity sense and ignore mask bits for the pulsed and latched outputs of

the watchdog detector when used as inputs to both A and B functions of

PLB6

57

58

Table 36

Table 29

PS6EN

0x00

Enable bits for A and B functions of PLB6, polarity bit for PLB6 output

P6PLBPOLB

Polarity sense for all eight other PLB outputs when used as inputs to the

B function of PLB6

59

5A

5B

60

Table 30

Table 31

Table 32

Table 29

P6PLBIMKB

0x00

Ignore mask for all eight other PLB outputs when used as inputs to the B

function of PLB6

P6SFDPOLB 0x00

P6SFDIMKB 0x00

P7PLBPOLA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB6

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB6

Polarity sense for all eight other PLB outputs when used as inputs to the

A function of PLB7

Rev. B | Page 25 of 52

ADM1060

Hex

Address

Default Power-

On Value

Table

Name

Description

61

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

P7PLBIMKA

0x00

Ignore mask for all eight other PLB outputs when used as inputs to the A

function of PLB7

62

63

64

65

66

P7SFDPOLA 0x00

P7SFDIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB7

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB7

P7GPIPOL

P7GPIIMK

P7WDICFG

0x00

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the A function of PLB7

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the B function of PLB7

Polarity sense and ignore mask bits for the pulsed and latched outputs of

the watchdog detector when used as inputs to both A and B functions of

PLB7

67

68

Table 36

Table 29

PS7EN

0x00

Enable bits for A and B functions of PLB7, polarity bit for PLB7 output

P7PLBPOLB

Polarity sense for all eight other PLB outputs when used as inputs to the

B function of PLB7

69

6A

6B

70

71

72

73

74

75

76

Table 30

Table 31

Table 32

Table 29

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

P7PLBIMKB

0x00

Ignore mask for all eight other PLB outputs when used as inputs to the B

function of PLB7

P7SFDPOLB 0x00

P7SFDIMKB 0x00

P8PLBPOLA 0x00

P8PLBIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB7

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB7

Polarity sense for all eight other PLB outputs when used as inputs to the

A function of PLB8

Ignore mask for all eight other PLB outputs when used as inputs to the A

function of PLB8

P8SFDPOLA 0x00

P8SFDIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB8

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB8

P8GPIPOL

P8GPIIMK

P8WDICFG

0x00

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the A function of PLB8

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the B function of PLB8

Polarity sense and ignore mask bits for the pulsed and latched outputs of

the watchdog detector when used as inputs to both A and B functions of

PLB8

77

78

Table 36

Table 29

PS8EN

0x00

Enable bits for A and B functions of PLB8, polarity bit for PLB8 output

P8PLBPOLB

Polarity sense for all eight other PLB outputs when used as inputs to the

B function of PLB8

79

7A

7B

80

81

82

83

Table 30

Table 31

Table 32

Table 29

Table 30

Table 31

Table 32

P8PLBIMKB

0x00

Ignore mask for all eight other PLB outputs when used as inputs to the B

function of PLB8

P8SFDPOLB 0x00

P8SFDIMKB 0x00

P9PLBPOLA 0x00

P9PLBIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB8

Ignore mask for all 7 SFD inputs (VH, two VBs, four VPs) to the B function

of PLB8

Polarity sense for all eight other PLB outputs when used as inputs to the

A function of PLB9

Ignore mask for all eight other PLB outputs when used as inputs to the A

function of PLB9

P9SFDPOLA 0x00

P9SFDIMKA 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB9

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A

function of PLB9

Rev. B | Page 26 of 52

ADM1060

Hex

Address

Default Power-

On Value

Table

Name

Description

84

85

86

Table 33

P9GPIPOL

0x00

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the A function of PLB9

Table 34

Table 35

P9GPIIMK

Polarity sense and ignore mask bits for all four GPIs when used as inputs

to the B function of PLB9

P9WDICFG

Polarity sense and ignore mask bits for the pulsed and latched outputs of

the watchdog detector when used as inputs to both A and B functions of

PLB9

87

88

Table 36

Table 29

PS9EN

0x00

Enable bits for A and B functions of PLB9, polarity bit for PLB9 output

P9PLBPOLB

Polarity sense for all eight other PLB outputs when used as inputs to the

B function of PLB9

89

8A

8B

Table 30

Table 31

Table 32

P9PLBIMKB

0x00

Ignore mask for all eight other PLB outputs when used as inputs to the B

function of PLB9

P9SFDPOLB 0x00

P9SFDIMKB 0x00

Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB9

Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B

function of PLB9

Rev. B | Page 27 of 52

ADM1060

PLBA REGISTER BIT MAPS

Table 29. PnPLBPOLA/PnPLBPOLB Registers Bit Map (Power-On Default 0x00)

Bit

Name

R/W Description

7–0

POL9−POL1 R/W

If high, invert the PLBn input before it is used in function A or B.

PLB1

0x00

0x08

PLB9

PLB8

PLB7

PLB6

PLB5

PLB4

PLB3

PLB2

0x10

0x18

PLB9

PLB8

PLB7

PLB6

PLB5

PLB4

PLB3

PLB1

PLB3

0x20

0x28

PLB9

PLB8

PLB7

PLB6

PLB5

PLB4

PLB2

PLB1

PLB4

0x30

0x38

PLB9

PLB8

PLB7

PLB6

PLB5

PLB3

PLB2

PLB1

PLB5

0x40

0x48

PLB9

PLB8

PLB7

PLB6

PLB4

PLB3

PLB2

PLB1

PLB6

0x50

0x58

PLB9

PLB8

PLB7

PLB5

PLB4

PLB3

PLB2

PLB1

PLB7

0x60

0x68

PLB9

PLB8

PLB6

PLB5

PLB4

PLB3

PLB2

PLB1

PLB8

0x70

0x78

PLB9

PLB7

PLB6

PLB5

PLB4

PLB3

PLB2

PLB1

PLB9

0x80

0x88

PLB8

PLB7

PLB6

PLB5

PLB4

PLB3

PLB2

PLB1

Function A

Function B

7

6

5

4

3

2

1

0

Table 30. PnPLBIMKA/PnPLBIMKB Registers Bit Map (Power-On Default 0x00)

Bit

Name

R/W Description

R/W

7–0

IGN9–IGN1

If high, mask the PLBn input before it is used in function A or B.

PLB1

0x01

0x09

PLB9

PLB8

PLB7

PLB6

PLB5

PLB4

PLB3

PLB2

0x11

0x19

PLB9

PLB8

PLB7

PLB6

PLB5

PLB4

PLB3

PLB1

PLB3

0x21

0x29

PLB9

PLB8

PLB7

PLB6

PLB5

PLB4

PLB2

PLB1

PLB4

0x31

0x39

PLB9

PLB8

PLB7

PLB6

PLB5

PLB3

PLB2

PLB1

PLB5

0x41

0x49

PLB9

PLB8

PLB7

PLB6

PLB4

PLB3

PLB2

PLB1

PLB6

0x51

0x59

PLB9

PLB8

PLB7

PLB5

PLB4

PLB3

PLB2

PLB1

PLB7

0x61

0x69

PLB9

PLB8

PLB6

PLB5

PLB4

PLB3

PLB2

PLB1

PLB8

0x71

0x79

PLB9

PLB7

PLB6

PLB5

PLB4

PLB3

PLB2

PLB1

PLB9

0x81

0x89

PLB8

PLB7

PLB6

PLB5

PLB4

PLB3

PLB2

PLB1

Function A

Function B

7

6

5

4

3

2

1

0

Table 31. PnSFDPOLA/PnSFDPOLB Registers Bit Map (Power-On Default 0x00)

Bit

7

Name

R/W Description

Reserved

N/A

Cannot Be Used

6–0

POL7−POL1 R/W

If high, invert the SFDn input before it is used in function A or B.

PLB1

0x02

0x0A

VP4

VP3

VP2

VP1

VH

PLB2

0x12

0x1A

VP4

VP3

VP2

VP1

VH

PLB3

0x22

0x2A

VP4

VP3

VP2

VP1

VH

PLB4

0x32

0x3A

VP4

VP3

VP2

VP1

VH

PLB5

0x42

0x4A

VP4

VP3

VP2

VP1

VH

PLB6

0x52

0x5A

VP4

VP3

VP2

VP1

VH

PLB7

0x62

0x6A

VP4

VP3

VP2

VP1

VH

PLB8

0x72

0x7A

VP4

VP3

VP2

VP1

VH

PLB9

0x82

0x8A

VP4

VP3

VP2

VP1

VH

Function A

Function B

6

5

4

3

2

1

0

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

Rev. B | Page 28 of 52

ADM1060

Table 32. PnSFDIMKA/PnSFDIMKB Registers Bit Map (Power-On Default 0x00)

Bit

7

Name

R/W Description

Reserved

IGN7−IGN1

N/A

R/W

Cannot Be Used

6−0

If high, mask the SFDn input before it is used in function A or B.

PLB1

0x03

0x0B

VP4

VP3

VP2

VP1

VH

PLB2

0x13

0x1B

VP4

VP3

VP2

VP1

VH

PLB3

0x23

0x2B

VP4

VP3

VP2

VP1

VH

PLB4

0x33

0x3B

VP4

VP3

VP2

VP1

VH

PLB5

0x43

0x4B

VP4

VP3

VP2

VP1

VH

PLB6

0x53

0x5B

VP4

VP3

VP2

VP1

VH

PLB7

0x63

0x6B

VP4

VP3

VP2

VP1

VH

PLB8

0x73

0x7B

VP4

VP3

VP2

VP1

VH

PLB9

Function A

Function B

0x83

0x8B

VP4

VP3

VP2

VP1

VH

6

5

4

3

2

1

0

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

VB2

VB1

Table 33. PnGPIPOL Registers Bit Map (Power-On Default 0x00)

Bit

Name

R/W Description

7−4

3−0

APOL4−APOL1

BPOL4−BPOL1

R/W

If high, invert the GPIn input before it is used in function A.

If high, invert the GPIn input before it is used in function B.

PLB1

0x04

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB2

0x14

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB3

0x24

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB4

0x34

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB5

0x44

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB6

0x54

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB7

PLB8

PLB9

0x64

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

0x74

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

0x84

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

7

6

5

4

3

2

1

0

Function A

Function B

Rev. B | Page 29 of 52

ADM1060

Table 34. PnGPIIMK Registers Bit Map (Power-On Default 0x00)

Bit

Name

R/W Description

7−4 AIMK4−AIMK1 R/W

3−0 BIMK4−BIMK1 R/W

If high, mask the GPIn input before it is used in function A.

If high, mask the GPIn input before it is used in function B.

PLB1

0x05

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB2

0x15

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB3

0x25

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB4

0x35

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB5

0x45

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB6

0x55

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB7

0x65

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB8

0x75

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

PLB9

0x85

GPI1

GPI2

GPI3

GPI4

GPI1

GPI2

GPI3

GPI4

7

6

5

4

3

2

1

0

Function A

Function B

Table 35. PnWDICFG Registers 0x06, 0x16, 0x26, 0x36, 0x46, 0x56, 0x66, 0x76, 0x86 (Power-On Default 0x00)

Bit Name R/W Description

7

6

5

4

3

2

1

0

APOLP R/W If high, invert the pulsed WDI input before it is used in function A.

AIMKP R/W If high, mask the pulsed WDI input before it is used in function A.

APOLL R/W If high, invert the latched WDI input before it is used in function A.

AIMKL R/W If high, mask the latched WDI input before it is used in function A.

BPOLP R/W If high, invert the pulsed WDI input before it is used in function B.

BIMKP R/W If high, mask the pulsed WDI input before it is used in function B.

BPOLL R/W If high, invert the latched WDI input before it is used in function B.

BIMKL R/W If high, mask the latched WDI input before it is used in function B.

Table 36. PnEN Register 0x07, 0x17, 0x27, 0x37, 0x47, 0x57, 0x67, 0x77, 0x87 (Power-On Default 0x00)

Bit Name

R/W Description

7–3 Reserved N/A Cannot Be Used

2

1

0

INVOP

ENA

R/W If high, invert the PLB output.

R/W If high, enable function A.

R/W If high, enable function B.

ENB

Rev. B | Page 30 of 52

ADM1060

PROGRAMMABLE DELAY BLOCK

PDB INPUT

Each output of the PLBA is fed into a separate programmable

delay block (PDB). The PDB enables the user to add a delay to

the logic block output before it is applied to either a PDO or one

of the other PLBs (the output of a PLB can be the input to any

of the other PLBs, but not itself). The PDB operation is similar

to that of the glitch filter (discussed in the SFD section). There

is an important difference between the two functions, however.

The delay on the falling edge of an input to the PDB can be

programmed independently of the rising edge. This allows the

user to program the length of the pulse output from the PDB.

Thus, for instance, the width of the pulse from the watchdog

fault detector can be adjusted, or the user can ensure that a sup-

ply supervised by one of the SFDs is within its UV/OV range

for a programmed period of time before asserting a PDO. A

delay of 0 ms to 500 ms can be programmed in the PnPDBTIM

registers. Four bits each are used to program the rising edge and

falling edge.

PROGRAMMED

FALL TIME = 0

PROGRAMMED RISE TIME

t₀

t_RISE

t₀

t_RISEt_FALL

t₀

t_RISE

t_FALL

t₀

PDB OUTPUT

PROGRAMMING RISE TIME ONLY

PDB INPUT

PROGRAMMED

RISE TIME

PROGRAMMED

FALL TIME

PROGRAMMED PROGRAMMED

FALL TIME

RISE TIME

t₀t_RISE

Once programmed, the PDB operates as follows. If the user

programs a delay on the rising edge of, say, 200 ms, the PDB

looks for a rising edge on the input. Once it sees the edge it

starts a timer. If the input remains high and the timer reaches

200 ms, the PDB immediately outputs a rising edge. If the input

falls low before the timer has reached 200 ms, no edge is output

from the PDB and the timer is reset. Because there is separate

control over the falling edge, if no delay is programmed on the

falling edge, the delay defaults to 0 ms and a falling edge on the

input will immediately appear on the output. If a falling edge

delay is programmed, the PDB operates exactly the opposite as

it does for a rising edge. Again, if a delay of, say, 200 ms is pro-

grammed on the falling edge, the PDB looks for a falling edge

on the input. Once it sees the edge, it starts a timer. If the input

remains low and the timer reaches 200 ms, the output transi-

tions from high to low. A valid rising edge must appear at the

output before a falling edge delay can be activated. The function

of the PDB is illustrated in Figure 22.

t₁

t_FALL

t₀t_RISE

t₁

t_FALL

t₀t_RISE

t₁

t_FALL

PDB OUTPUT

PROGRAMMING RISE TIME AND FALL TIME

t₁

t_FALL

Figure 22. Programmable Delay Block (PDB) Functionality

Aside from the extra timing flexibility, the programmable delay

also provides a crude form of filtering. In much the same way as

the glitch filter operates, an input must be high (or low) for a

programmed period of time before being seen on the output.

Transients that are shorter than the programmed timeouts will

not appear on the output. The bit map for the register that con-

trols both the rising and falling edges is shown in Table 38.

Rev. B | Page 31 of 52

ADM1060

Table 37. Programmable Delay Block (PDB) Registers

Default

Hex

Addr.

Power-On

Value

Table

Name

Description

0C

1C

2C

3C

4C

5C

6C

7C

8C

Table 38

P1PDBTIM 0x00

P2PDBTIM 0x00

P3PDBTIM 0x00

P4PDBTIM 0x00

P5PDBTIM 0x00

P6PDBTIM 0x00

P7PDBTIM 0x00

P8PDBTIM 0x00

P9PDBTIM 0x00

Delay for PDB1. Delay for rising edge and falling edge programmed separately.

Delay for PDB2. Delay for rising edge and falling edge programmed separately.

Delay for PDB3. Delay for rising edge and falling edge programmed separately.

Delay for PDB4. Delay for rising edge and falling edge programmed separately.

Delay for PDB5. Delay for rising edge and falling edge programmed separately.

Delay for PDB6. Delay for rising edge and falling edge programmed separately.

Delay for PDB7. Delay for rising edge and falling edge programmed separately.

Delay for PDB8. Delay for rising edge and falling edge programmed separately.

Delay for PDB9. Delay for rising edge and falling edge programmed separately.

Table 38. PnPDBTIM Registers 0x0C, 0x1C, 0x2C, 0x3C, 0x4C, 0x5C, 0x6C, 0x7C, 0x8C

Bit

Name

R/W Description

Programmed Rise Time

TR3 TR2 TR1 TR0 Delay (ms)

Bit

Name

R/W Description

Programmed Fall Time

TF3 TF2 TF1 TF0 Delay (ms)

7–4 TR3−TR0

W

3–0 TF3−TF0

W

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

5

10

20

40

60

80

100

150

200

250

300

400

500

10

20

40

60

80

100

150

200

250

300

400

500

Rev. B | Page 32 of 52

ADM1060

OUTPUTS

PROGRAMMABLE DRIVER OUTPUTS

• The (delayed) output from the associated PLB (enabled by

setting bit CFG4 to 1)

The ADM1060 has nine programmable driver outputs (PDOs).

These are the logic outputs of the device. Each PDO is normally

controlled by a single PDB. Thus, the PDOs can be set up to

assert when the conditions on the PDB are met, such as when

the SFDs are in tolerance, the levels on the GPI are correct, the

watchdog timer has not timed out, and so on. The PDOs can be

used for a number of functions; for example, to provide a

POWER_GOOD signal when all the SFDs are in tolerance, pro-

vide a reset generator output if one of the SFDs goes out of spec

(which can be used as a status signal for a DSP or other micro-

processor), or provide enable signals for LDOs on the supplies

that the ADM1060 is supervising.

• Data that is driven directly over the SMBus interface (enabled

by setting Bit CFG5 to 1). When set in this mode, the data

from the PDB is disabled and the data on the PDO is the data

on CFG4. Thus, the PDO can be software controlled to initi-

ate a software power-up/power-down.

• An on-chip clock (enabled by setting Bit CFG6 to 1). A

100 kHz clock is available to clock an external device such as

an LED.

More details on these data modes are given in the register map

of Table 40.

There are a number of pull-up options on the PDOs to enable

the user to program the output level.

The default setup of each of the PDOs is to be pulled low by a

weak (20 kΩ) pull-down resistor. This is also the setup of the

PDOs on power-up until the registers are loaded and the pro-

grammed conditions are latched. The outputs are actively

pulled low once 1 V or greater is seen at any VPn or VH. Until

there is a 1 V supply on the chip, the outputs are high imped-

ance. This provides a known condition for the PDOs during

power-up. The internal pull-down can be overdriven with an

external pull-up of suitable value tied from the PDO pin to the

required pull-up voltage. The 20 kV resistor must be accounted

for in calculating a suitable value. For example, if it is required

to pull PDOn up to 3.3 V, and 5 V is available as an external

supply, the pull-up resistor value is given by:

The outputs can be programmed as

• Open-drain (allows the user to connect an external pull-up

resistor)

• Open-drain with weak pull-up to V_DD

• Push-pull to V_DD

• Open-drain with weak pull-up to VPn

• Push-pull to VPn

• Internally charge-pumped high drive (12 V)

The last option is only available on PDO1−4. This allows the

user to directly drive the gate of an N-channel FET in the path

of a power supply. The required pull-up is selected by pro-

gramming Bits 0 to 3 in PnPDOCFG appropriately (see

Table 40).

3.3 V = 5 V × 20 kV/(R_UP+ 20 kV)

Therefore,

R

_UP= (100 kV – 66 kV)/3.3 = 10 kV

The data driving each of the PDOs can come from one of three

inputs. These inputs are enabled by a bit each in the

PnPDOCFG registers. The inputs are

The register list and the bit map for the PDOs are shown in

Table 39 and Table 40.

VFET (PDO1–4 ONLY)

V

DD

VP4

VP1

10

Ω

20kΩ

SEL

10

Ω

20kΩ

10

Ω

20kΩ

PDB_OUT

CFG4

PDO

M_CLK

20kΩ

Figure 23. Programmable Driver Output

Rev. B | Page 33 of 52

ADM1060

Table 39. Programmable Driver Outputs Registers

Default

Hex

Power-On

Value

Address Table

Name

Description

0D

1D

2D

3D

4D

5D

6D

7D

8D

Table 40 P1PDOCFG

Table 40 P2PDOCFG

Table 40 P3PDOCFG

Table 40 P4PDOCFG

Table 40 P5PDOCFG

Table 40 P6PDOCFG

Table 40 P7PDOCFG

Table 40 P8PDOCFG

Table 40 P9PDOCFG

0x00

Selects the format of the PDO1 output (open drain, open drain with internal

pull-up, charge pumped, etc.).

Selects the format of the PDO2 output (open drain, open drain with internal

pull-up, charge pumped, etc.).

Selects the format of the PDO3 output (open drain, open drain with internal

pull-up, charge pumped, etc.).

Selects the format of the PDO4 output (open drain, open drain with internal

pull-up, charge pumped, etc.).

Selects the format of the PDO5 output (open drain, open drain with internal

pull-up, etc.). Note: charge pumped output is not available on this driver.

Selects the format of the PDO6 output (open drain, open drain with internal

pull-up, etc.). Note: charge pumped output is not available on this driver.

Selects the format of the PDO7 output (open drain, open drain with internal

pull-up, etc.). Note: charge pumped output is not available on this driver.

Selects the format of the PDO8 output (open drain, open drain with internal

pull-up etc.). Note: charge pumped output is not available on this driver.

Selects the format of the PDO9 output (open drain, open drain with internal

pull-up, etc.). Note: charge pumped output is not available on this driver.

Table 40. PnPDOCFG Register 0x0D, 0x1D, 0x2D, 0x3D, 0x4D, 0x5D, 0x6D, 0x7D, 0x8D (Power-On Default 0x00)

Bit

7

Name

R/W

N/A

R/W

Description

Reserved

CFG6–CFG4

Cannot Be Used

6–4

Controls the logical state of the PDO. These three bits determine what effect, if any, the logi-

cal input to the PDO has on its output.

CFG6

CFG5

CFG4

PDO

State

0

Disabled, with weak pull-down

0

1

PLB_OUT Enabled, follows PLB logic output

0

1

0

Enables SMBus data, drive low

Enables SMBus data, drive high

Enables MCLK out onto pin

0

1

X

MCLK

3–0

CFG3–CFG0

R/W

CFG3

CFG2

CFG1

CFG0

Pull-Up Supply

Pull-Up Strength

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

none

VCP

VP1

VP2

VP3

VP4

V_DD

N/A

300 kΩ

Low

High

Low

High

Low

High

Low

High

Low

V_DD

High

Rev. B | Page 34 of 52

ADM1060

STATUS/FAULTS

Table 41. Fault Plane of ADM1060

Register Bit Assigned Function

FAULT/STATUS REPORTING ON THE ADM1060

As discussed previously, any number of the PDOs can be

programmed to assert under a set of preprogrammed

conditions. These conditions could be a fault on an SFD, a

change in status on a GPI, a timeout on the watchdog detector,

and so on. Because of the flexibility and the choice of

combinations available on the ADM1060, the assertion of the

PDO will tell the user nothing about what caused it to assert

(unless it is programmed to assert with only one input).

LATF1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

ANYFLT

Logic Output of VP4 SFD

Logic Output of VP3 SFD

Logic Output of VP2 SFD

Logic Output of VP1 SFD

Logic Output of VH SFD

Logic Output of VB2 SFD

Logic Output of VB1 SFD

LATF2

To enable the user to debug the cause of the PDO assertion, a

number of registers on the ADM1060 provide status and fault

information on the various individual functions supervised by

the device.

Logic Output of WDI

Logic Input on GPI4

Logic Input on GPI3

Logic Input on GPI2

Logic Input on GPI1

STATUS REGISTERS

A number of status registers indicate the logic state of all of the

functions controlled by the ADM1060. These logic states

include the output of both the UV and OV comparators of each

of the seven SFDs, the logic output of the SFDs themselves, the

logic state of the GPIs, the error condition on the WDI, and the

logic state of each of the nine PDOs. The content of these

registers, which is read-only, can be read at any time via the

SMBus interface. The register and bit map for each of these

status registers are described in the tables that follow.

Each bit represents the logical status of its assigned function,

i.e., the logical output of the SFDs and WDI, and the logic level

on the GPI inputs.

The important exception is the MSB of the LATF1 register. This

is the ANYFLT bit. This bit goes high if one of the other bits in

the two registers faults. A fault is defined as a change in polarity

from the last time the fault registers were read. Once ANYFLT

goes high, the contents of the two registers are latched, thus

preventing more than one of the other bits from changing

polarity before the content of the registers is read. Therefore, the

first faulting input can be determined.

FAULT REGISTERS

The ADM1060 also provides fault reporting. For example, if a

fault occurs causing a PDO to change its status, the user can

determine what function actually faulted. This is achieved by

providing a “fault plane” consisting of two registers, LATF1 and

LATF2, that the system controller can read out of the ADM1060

via the SMBus. Each bit in the two registers (with one important

exception, see below) is assigned to one of the inputs of the

devices as shown in Table 41.

The sequence in which the registers are read is determined by

ANYFLT. As long as ANYFLT remains at 0, only the content of

LATF1 is read. There are two reasons for this. The first is that

ANYFLT = 0 implies that no fault has occurred and, therefore,

there is no need to read the contents of LATF2. The second and

more important reason is that reading register LATF2 actually

resets the ANYFLT bit to 0. Thus, if a fault occurred on an SFD

after LATF1 had been read but before LATF2 had been read,

ANYFLT would change to 1, indicating that a fault had

occurred, but would be reset to 0 once LATF2 was read, thus

erasing the log of the fault. In summary then, LATF2 should

only be read if ANYFLT = 1. Reading the registers in this

sequence ensures that the contents are never reset before a fault

has been logged over the SMBus, thus ensuring that the

supervising processor or CPLD knows what function

supervised by the ADM1060 caused the fault. The faulting

function is determined by comparing the contents of the fault

plane (i.e., the contents of the two registers) with the values read

previously, and determining which bit changed polarity.

Rev. B | Page 35 of 52

ADM1060

The functionality of the fault plane is best illustrated with an

example. For instance, take VP1 to have an input supply of 5.0 V.

A UV/OV window of 4.5 V to 5.5 V is set up on VP1. The

supply is ramped in and out of this window, each time reading

the contents of LATF1 and LATF2. The values recorded are as

follows:

5. VP1 at 4.2 V: LATF1 = 10000000, LATF2 = 00000000. At first

glance, this would appear to be incorrect since the SFD out-

put should be at 1 (4.2 V is an undervoltage fault). However,

in ramping down from 5.8 V to 4.2 V, the supply passed into

the UV/OV window, the SFD output changed status from 1 to

0, ANYFLT was set high, and the register contents were

latched. It is these values that were read, before being reset by

reading LATF2.

1. VP1 at 5 V: LATF1 = LATF2 = 00000000. This is expected.

The supply is in tolerance, SFD output is 0, therefore no fault.

There are also two mask registers provided that enable the user

to ignore a fault on a given function. The bits of the error mask

registers are mapped in the same way as those of the fault regis-

ters with the exception that the ANYFLT bit cannot be masked.

Setting a 1 in the error mask register results in the equivalent bit

in the fault register always remaining at 0, regardless of whether

there is a fault on that function or not. The register and bit maps

for both the fault and error mask registers are shown below.

2. VP1 at 4.2 V: LATF1 = 10001000, LATF2 = 00000000. SFD

output has changed status to 1, therefore ANYFLT goes high.

3. VP1 at 5.0 V: LATF1 = 10000000, LATF2 = 00000000. SFD

output has changed status to 0, therefore ANYFLT goes high

again.

4. VP1 at 5.8 V: LATF1 = 10001000, LATF2 = 00000000. SFD

output again changed status from 0 to 1, so ANYFLT goes

high.

Table 42. Status Registers

Hex Addr. Table

Name

Default Power-On Value Description

D8

D9

DA

Table 43 UVSTAT

Table 44 OVSTAT

0x00

Logic output of the UV comparator on each of the seven SFDs

Logic output of the OV comparator on each of the seven SFDs

Logic output (post Fault Type block) on each of the seven SFDs

SFDSTAT

Table 45

DB

DE

DF

Table 46 GWSTAT

0x00

Logic state of the four GPIs and the Watchdog Fault Detector

Logic output of PDOs 1 to 8

Table 49 PDOSTAT1 0x00

Table 48 PDOSTAT2 0x00

Logic output of PDO 9

Table 43. Bit Map for UVSTAT Register 0xD8 (Power-On Default 0x00)

Bit Name

R/W Description

7

6

5

4

3

2

1

0

Reserved N/A Cannot Be Used

VP4UV

VP3UV

VP2UV

VP1UV

VHUV

R

If high, voltage on VP4 input is lower than the UV threshold.

If high, voltage on VP3 input is lower than the UV threshold.

If high, voltage on VP2 input is lower than the UV threshold.

If high, voltage on VP1 input is lower than the UV threshold.

If high, voltage on VH input is lower than the UV threshold.

If high, voltage on VB2 input is lower than the UV threshold.

If high, voltage on VB1 input is lower than the UV threshold.

VB2UV

VB1UV

Rev. B | Page 36 of 52

ADM1060

Table 44. Bit Map for OVSTAT Register 0xD9 (Power-On Default 0x00)

Bit Name

R/W Description

7

6

5

4

3

2

1

0

Reserved N/A Cannot Be Used

VP4OV

VP3OV

VP2OV

VP1OV

VHOV

R

If high, voltage on VP4 input is higher than the OV threshold.

If high, voltage on VP3 input is higher than the OV threshold.

If high, voltage on VP2 input is higher than the OV threshold.

If high, voltage on VP1 input is higher than the OV threshold.

If high, voltage on VH input is higher than the OV threshold.

If high, voltage on VB2 input is higher than the OV threshold.

If high, voltage on VB1 input is higher than the OV threshold.

VB2OV

VB1OV

Table 45. Bit Map for SFDSTAT Register 0xDA (Power-On Default 0x00)

Bit Name

R/W Description

7

6

5

4

3

2

1

0

Reserved N/A Cannot Be Used

VP4FLT

VP3FLT

VP2FLT

VP1FLT

VHFLT

R

If high, fault (UV, OV or Out-of-Window) has occurred on VP4 input.

If high, fault (UV, OV or Out-of-Window) has occurred on VP3 input.

If high, fault (UV, OV or Out-of-Window) has occurred on VP2 input.

If high, fault (UV, OV or Out-of-Window) has occurred on VP1 input.

If high, fault (UV, OV or Out-of-Window) has occurred on VH input.

If high, fault (UV, OV or Out-of-Window) has occurred on VB2 input.

If high, fault (UV, OV or Out-of-Window) has occurred on VB1 input.

VB2FLT

VB1FLT

Table 46. Bit Map for GWSTAT Register 0xDB (Power-On Default 0x00)

Bit

Name

R/W Description

7−5 Reserved N/A Cannot Be Used

4

3

2

1

0

WDISTAT

GPI4STAT

GPI3STAT

GPI2STAT

GPI1STAT

R

If high, timeout has elapsed on the Watchdog Detector.

Logic level currently being driven on GPI4 input.

Logic level currently being driven on GPI3 input.

Logic level currently being driven on GPI2 input.

Logic level currently being driven on GPI1 input.

Table 47. Bit Map for PDOSTAT1 Register 0xDE (Power-On Default 0x00)

Bit Name

R/W Description

7

6

5

4

3

2

1

0

PDO8STAT

R

Logic level currently being driven on PDO8 output.

PDO7STAT

PDO6STAT

PDO5STAT

PDO4STAT

PDO3STAT

PDO2STAT

PDO1STAT

Logic level currently being driven on PDO7 output.

Logic level currently being driven on PDO6 output.

Logic level currently being driven on PDO5 output.

Logic level currently being driven on PDO4 output.

Logic level currently being driven on PDO3 output.

Logic level currently being driven on PDO2 output.

Logic level currently being driven on PDO1 output.

Table 48. Bit Map for PDOSTAT2 Register 0xDF (Power-On Default 0x00)

Bit Name

R/W Description

7–1 Reserved

N/A Cannot Be Used

0

PDO9STAT

R

Logic level currently being driven on PDO9 output.

Rev. B | Page 37 of 52

ADM1060

FAULT REGISTERS

Table 49. List of Fault Registers

Hex Addr. Table

Name Default Power On Value Description

DC

DD

Table 50 LATF1 0x00

Table 51 LATF2 0x00

Fault Status Register for the seven SFDs

Fault Status Register for the four GPIs and the Watchdog Detector

Table 50. Bit Map for LATF1 Register 0xDC (Power-On Default 0x00)

Bit Name

R/W Description

7

ANYFLT

R

If high, a change in logic status (fault) has been logged on one of the 12 functions monitored since the last

time the Fault Registers were read.

6

5

4

3

2

1

0

VP4FLT

VP3FLT

VP2FLT

VP1FLT

VHFLT

R

If high, a fault has occurred on supply at input VP4.

If high, a fault has occurred on supply at input VP3.

If high, a fault has occurred on supply at input VP2.

If high, a fault has occurred on supply at input VP1.

If high, a fault has occurred on supply at input VH.

If high, a fault has occurred on supply at input VB2.

If high, a fault has occurred on supply at input VB1.

VB2FLT

VB1FLT

Table 51. Bit Map for LATF2 Register 0xDD (Power-On Default 0x00)

Bit Name

R/W Description

7–5 Reserved N/A Cannot Be Used

4

3

2

1

0

WDFLT

R

If high, the logic level on the WDI output has changed since the last time that the fault registers were read.

If high, the logic level on GPI4 input has changed since the last time that the fault registers were read.

If high, the logic level on GPI3 input has changed since the last time that the fault registers were read.

If high, the logic level on GPI2 input has changed since the last time that the fault registers were read.

If high, the logic level on GPI1 input has changed since the last time that the fault registers were read.

GPI4FLT

GPI3FLT

GPI2FLT

GPI1FLT

Rev. B | Page 38 of 52

ADM1060

MASK REGISTERS

Table 52. List of Mask Registers

Hex Addr. Table

Name

Default Power On Value Description

9D

9E

Table 53 ERRMASK1 0x00

Table 54 ERRMASK2 0x00

Error Mask Register for the seven SFDs

Error Mask Register for the four GPIs and the Watchdog Detector

Table 53. Bit Map for ERRMASK1 Register 0x9D (Power-On Default 0x00)

Bit Name

R/W Description

Unused

7

6

5

4

3

2

1

0

Reserved

X

VP4MASK R/W If high, a fault occurring on the supply at input VP4 is ignored and not logged in LATF1.

VP3MASK R/W If high, a fault occurring on the supply at input VP3 is ignored and not logged in LATF1.

VP2MASK R/W If high, a fault occurring on the supply at input VP2 is ignored and not logged in LATF1.

VP1MASK R/W If high, a fault occurring on the supply at input VP1 is ignored and not logged in LATF1.

VHMASK

R/W If high, a fault occurring on the supply at input VH is ignored and not logged in LATF1.

VB2MASK R/W If high, a fault occurring on the supply at input VB2 is ignored and not logged in LATF1.

VB1MASK R/W If high, a fault occurring on the supply at input VB1 is ignored and not logged in LATF1.

Table 54. Bit Map for ERRMASK2 Register 0x9E (Power-On Default 0x00)

Bit Name

R/W Description

Unused

7–5 Reserved

X

4

3

2

1

0

WDIMASK R/W If high, a change in the logic level on the WDI output is ignored and not logged in LATF2.

GPI4MASK R/W If high, a change in the logic level on the GPI4 input is ignored and not logged in LATF2.

GPI3MASK R/W If high, a change in the logic level on the GPI3 input is ignored and not logged in LATF2.

GPI2MASK R/W If high, a change in the logic level on the GPI2 input is ignored and not logged in LATF2.

GPI1MASK R/W If high, a change in the logic level on the GPI1 input is ignored and not logged in LATF2.

Rev. B | Page 39 of 52

ADM1060

PROGRAMMING

The ADM1060 provides a number of options that allow the user

to update the configuration differently over the SMBus inter-

face. All of these options are controlled in the register UPDCFG.

The options are

CONFIGURATION DOWNLOAD AT POWER-UP

The configuration of the ADM1060—the UV/OV thresholds,

glitch filter timeouts, PLB combinations, PDO pull-ups, etc.—is

dictated by the contents of the RAM. The RAM is comprised of

local latches that set the configuration. These latches are double

buffered and are actually comprised of two identical latches

(Latch A and Latch B). An update of the double-buffered latch

updates Latch A first and then Latch B. The advantage of this

architecture is explained below. These latches are volatile

memory and lose their contents at power-down. Therefore, at

power-up the configuration in the RAM must be restored. This

is achieved by downloading the contents of the EEPROM

(nonvolatile memory) to the local latches. This download

occurs in a number of steps.

1. Update the configuration in real time. The user writes to

RAM across the SMBus and the configuration is updated

immediately.

2. Update the A Latches “offline” and then update all B Latches

at the same time. With this method, the configuration of the

ADM1060 will remain unchanged and continue to operate in

the original setup until the instruction is given to update the

B Latches.

3. Change EEPROM register contents offline and then

download the revised EEPROM contents to the RAM regis-

ters. Again, with this method, the configuration of the

ADM1060 will remain unchanged and continue to operate in

the original setup until the instruction is given to change.

1. With no power applied to the device, the PDOs are all high

impedance.

2. Once 1 V appears on any of the inputs connected to the V_DD

arbitrator (VH or VPn), the PDOs are all (weakly) pulled to

GND.

The instruction to download from the EEPROM in option 3

above is also a useful way to restore the original EEPROM con-

tents if revisions to the configuration are unsatisfactory and the

user wants the ADM1060 to return to a known operating mode.

3. Once the supply rises above the undervoltage lockout of the

device (UVLO is 2.5 V), the EEPROM starts to download to

the RAM.

This type of operation is possible because of the topology of the

ADM1060. The local (volatile) registers, or RAM, are all double-

buffered latches. Setting Bit 0 of the UPDCFG register to 1

leaves the double-buffered latches open at all times. If Bit 0 is set

to 0, then when RAM write occurs across the SMBus only the

first side of the double-buffered latch is written to. The user

must then write a 1 to Bit 1 of the UPDCFG register. This gen-

erates a pulse to update all of the second latches at once.

EPROM writes work similarly.

4. The EEPROM downloads its contents to all Latch As.

5. Once the contents of the EEPROM are completely

downloaded, the device controller outputs a control pulse

enabling all Latch As to download to all Latch Bs, thus com-

pleting the configuration download. Any attempt to

communicate with the device prior to this download comple-

tion will result in a NACK being issued from the ADM1060.

A final bit in this register is used to enable EEPROM page

erasure. If this bit is set high, the contents of an EEPROM page

can all be set to 0. If low, the contents of a page cannot be

erased, even if the command code for page erasure is

programmed across the SMBus.

UPDATING THE CONFIGURATION

Once the device is powered up with all of the configuration

settings loaded from EEPROM into the RAM registers, the user

may wish to alter the configuration of functions on the

ADM1060; for example, change the UV or OV limit of an SFD,

the fault output of an SFD, the timeout of the watchdog detec-

tor, the rise time delay of one of the PDOs, and so on.

The bit map for register UPDCFG is shown in Table 56. A flow

chart for download at power-up and subsequent configuration

updates is shown in Figure 24.

Rev. B | Page 40 of 52

ADM1060

Table 55. List of Configuration Update Registers

Default Power-

Hex Addr. Table

Name

On Value

Description

90 Table 56 UPDCFG 0x00

Configuration Update Control register for changing configuration of the

ADM1060 after power-up

Table 56. Bit Map for UPDCFG Register 0x90 (Power-On Default 0x00)

Bit

7–4

3

Name

R/W

N/A

R/W

W

Description

Reserved

EE_ERASE

EEPROMLD

Cannot be used

If set high, EEPROM page erasure can be programmed.

2

If set high, the ADM1060 will download the contents of its EEPROM to the RAM registers. This bit

self-clears (returns to 0) after the download.

1

0

RAMLD

UPD

W

If set high, the ADM1060 will download the buffered RAM register data into the local latches. This bit

self-clears (returns to 0) after the download.

R/W

If set high, the ADM1060 will update its configuration in real time as a word is written to a local RAM

register via the SMBus.

SMBus

DEVICE

CONTROLLER

POWER-UP

(V >2.5V)

CC

EEPROMLD

DATA

RAMLD

UPD

FUNCTION (E.G.,

OV THRESHOLD

ON VP1)

LATCH A

LATCH B

EEPROM

Figure 24. Configuration Update Flow Diagram

Configuration Registers. These registers provide control and

configuration for various operating parameters of the

ADM1060.

INTERNAL REGISTERS

The ADM1060 contains a large number of data registers. A brief

description of the principal registers is given below. More

detailed descriptions are given in the relevant sections of this

data sheet.

Polarity Registers. These registers define the polarity of inputs

to the PLBA.

Mask Registers. These registers allow masking of individual

inputs to the PLBA and masking of faults in the fault reporting

registers.

Address Pointer Register. This register contains the address

that selects one of the other internal registers. When writing to

the ADM1060, the first byte of data is always a register address,

which is written to the Address Pointer register.

Rev. B | Page 41 of 52

ADM1060

EEPROM

GENERAL SMBus TIMING

The ADM1060 has 512 bytes of nonvolatile, electrically erasable

programmable read-only memory (EEPROM) from register

addresses 0xF800 to 0xF9FF. This may be used for permanent

storage of data that will not be lost when the ADM1060 is pow-

ered down, unlike the data in the volatile registers. Although

referred to as read-only memory, the EEPROM can be written

to (as well as read from) via the serial bus in exactly the same

way as the other registers. The only major differences between

the EEPROM and other registers are

Figure 25 and Figure 26 show timing diagrams for general read

and write operations using the SMBus. The SMBus specification

defines specific conditions for different types of read and write

operation, which are discussed later. The general SMBus proto-

col operates as follows:

1. The master initiates data transfer by establishing a START condi-

tion, defined as a high-to-low transition on the serial data line

SDA while the serial clock line SCL remains high. This indicates

that a data stream will follow.All slave peripherals connected to

the serial bus respond to the START condition and shift in the

next eight bits, consisting of a 7-bit slave address (MSB first) plus

1. An EEPROM location must be blank before it can be written

to. If it contains data, it must first be erased.

W

a R/ bit, which determines the direction of the data transfer,

2. Writing to EEPROM is slower than writing to RAM.

3. Writing to the EEPROM should be restricted because it has a

limited write/cycle life of typically 10,000 write operations,

due to the usual EEPROM wear-out mechanisms.

i.e., whether data will be written to or read from the slave device

(0 = write, 1 = read).

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the low

period before the ninth clock pulse, known as the acknowl-

edge bit, and holding it low during the high period of this

clock pulse. All other devices on the bus now remain idle

while the selected device waits for data to be read from or

The EEPROM is split into 16 (0 to 15) pages of 32 bytes each.

Pages 0 to 6, starting at address 0xF800, hold the configuration

data for the applications on the ADM1060 (the PLB, SFDs, GPIs,

WDI, PDOs, etc.). These EEPROM addresses are the same as

the RAM register addresses, prefixed by 0xF8. Page 7 is

reserved. Pages 8 to 15 are for customer use. Data can be

downloaded from EEPROM to RAM in one of two ways:

W

written to it. If the R/ bit is a 0, the master will write to the

W

slave device. If the R/ bit is a 1, the master will read from

the slave device.

2. Data is sent over the serial bus in sequences of nine clock pulses,

eight bits of data followed by an acknowledge bit from the slave

device. Data transitions on the data line must occur during the

low period of the clock signal and remain stable during the high

period, as a low-to-high transition when the clock is high may be

interpreted as a STOP signal.

1. At power-up, pages 0 to 6 are downloaded.

2. Setting Bit 2 of the UPDCFG register (0x90) performs a user

download of pages 0 to 6.

SERIAL BUS INTERFACE

Control of the ADM1060 is carried out via the serial system

management bus (SMBus). The ADM1060 is connected to this

bus as a slave device under the control of a master device. It

takes approximately 2 ms after power-up for the ADM1060 to

download from its EEPROM. Therefore, access to the

If the operation is a write operation, the first data byte after

the slave address is a command byte. This tells the slave

device what to expect next. It may be an instruction such as

telling the slave device to expect a block write, or it may

simply be a register address that tells the slave where

subsequent data is to be written.

ADM1060 is restricted until the download is completed.

Since data can flow in only one direction as defined by the

IDENTIFYING THE ADM1060 ON THE SMBus

W

R/ bit, it is not possible to send a command to a slave

device during a read operation. Before doing a read

operation, it may first be necessary to do a write operation to

tell the slave what sort of read operation to expect and/or the

address from which data is to be read.

The ADM1060 has a 7-bit serial bus slave address. When the

device is powered up, it will do so with a default serial bus

address. The five MSBs of the address are set to 10101, and the

two LSBs are determined by the logical states of Pins A1 and A0.

This allows the connection of four ADM1060s to the one

SMBus. The device also has a number of identification registers

(read only) that can be read across the SMBus. These are

3. When all data bytes have been read or written, stop condi-

tions are established. In WRITE mode, the master will pull

the data line high during the 10^thclock pulse to assert a STOP

condition. In READ mode, the master device will release the

SDA line during the low period before the ninth clock pulse,

but the slave device will not pull it low. This is known as No

Acknowledge. The master will then take the data line low

during the low period before the 10^thclock pulse, then high

during the 10^thclock pulse to assert a STOP condition.

Name

Address Value Function

Manufacturer ID for Analog Devices

MANID 0x93

0x41

0x3E

DEVID

REVID

0x94

0x95

Device ID

0x– – Silicon Revision

0x– – S/W Brand

MARK1 0x96

MARK2 0x97

Rev. B | Page 42 of 52

ADM1060

9

1

SCL

SDA

1

0

1

A1

A0

R/W

D7

D6

D5

1

D4

D3

D2

D1

D0

0

1

ACK. BY

SLAVE

ACK. BY

SLAVE

START BY MASTER

FRAME 2

FRAME 1

SLAVE ADDRESS

COMMAND CODE

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

STOP

BY

MASTER

ACK. BY

SLAVE

ACK. BY

SLAVE

FRAME N

DATA BYTE

FRAME 3

DATA BYTE

Figure 25. General SMBus Write Timing Diagram

1

9

1

9

SCL

SDA

D6

D5

1

D4

D3

D2

D1

D0

1

0

1

A1

A0 R/W

D7

0

1

ACK. BY

SLAVE

ACK. BY

MASTER

START BY MASTER

FRAME 1

SLAVE ADDRESS

FRAME 2

DATA BYTE

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

STOP

BY

MASTER

ACK. BY

MASTER

NO ACK.

FRAME N

DATA BYTE

FRAME 3

DATA BYTE

Figure 26. General SMBus Read Timing Diagram

t_HD;STA

t_LOW

t_R

t_F

SCL

t_HIGH

t_SU;STA

t_SU;STO

t_HD;STA

t_SU;DAT

t_HD;DAT

SDA

t_BUF

S

P

S

Figure 27. Serial Bus Timing Diagram

the EEPROM is arranged as 16 pages of 32 bytes, and an entire

page must be erased.

SMBus PROTOCOLS FOR RAM AND EEPROM

The ADM1060 contains volatile registers (RAM) and nonvola-

tile EEPROM. User RAM occupies address locations from 0x00

to 0xDF, while EEPROM occupies addresses from 0xF800 to

0xF9FF.

Page erasure is enabled by setting Bit 3 in register UPDCFG

(address 0x90) to 1. If this is not set, page erasure cannot occur,

even if the command byte (0xFE) is programmed across the

SMBus.

Data can be written to and read from both RAM and EEPROM

as single data bytes.

Data can be written only to unprogrammed EEPROM locations.

To write new data to a programmed location, it is first necessary

to erase it. EEPROM erasure cannot be done at the byte level;

Rev. B | Page 43 of 52

ADM1060

page erasure to take place, the page address has to be given

in the previous write word transaction (see write byte below).

Also, Bit 3 in register UPDCFG (address 0x90) must be

set to 1.

WRITE OPERATIONS

The SMBus specification defines several protocols for different

types of read and write operations. The ones used in the

ADM1060 are discussed below. The following abbreviations are

used in the diagrams:

1

2

3

4

5

6

COMMAND

BYTE

(0xFE)

SLAVE

ADDRESS

S

W

A

P

S

START

P

STOP

Figure 29. EEPROM Page Erasure

R

READ

As soon as the ADM1060 receives the command byte, page

erasure begins. The master device can send a STOP

command as soon as it sends the command byte. Page

erasure takes approximately 20 ms. If the ADM1060 is

accessed before erasure is complete, it will respond with No

Acknowledge.

W

A

WRITE

ACKNOWLEDGE

NO ACKNOWLEDGE

The ADM1060 uses the following SMBus write protocols:

WRITE BYTE/WORD

SEND BYTE

In this operation the master device sends a command byte and

one or two data bytes to the slave device, as follows:

In this operation, the master device sends a single command

byte to a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write

bit (low).

2. The master sends the 7-bit slave address followed by the write

bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master sends a data byte.

6. The master asserts a STOP condition on SDA and the trans-

action ends.

7. The slave asserts ACK on SDA.

In the ADM1060, the send byte protocol is used for two

purposes:

8. The master sends a data byte (or may assert STOP at this

point).

1. To write a register address to RAM for a subsequent single

byte read from the same address or block read, or to write

starting at that address. This is illustrated in Figure 28.

9. The slave asserts ACK on SDA.

10. The master asserts a STOP condition on SDA to end the

transaction.

1

2

3

4

5

6

RAM

ADDRESS

(0x00 TO 0xDF)

In the ADM1060, the write byte/word protocol is used for three

purposes:

SLAVE

ADDRESS

S

W

A

P

Figure 28. Setting a RAM Address for Subsequent Read

1. To write a single byte of data to RAM. In this case the com-

mand byte is the RAM address from 0x00 to 0xDF and the

(only) data byte is the actual data. This is illustrated in

Figure 30.

2. To erase a page of EEPROM memory. EEPROM memory can

be written to only if it is unprogrammed. Before writing to

one or more EEPROM memory locations that are already

programmed, the page or pages containing those locations

must first be erased. EEPROM memory is erased by writing a

command byte.

1

2

3

4

5

6

7

8

RAM

ADDRESS

(0x00 TO 0xDF)

SLAVE

ADDRESS

S

W

A

DATA

A

P

The master sends a command code that tells the slave device

to erase the page. The ADM1060 command code for a page

erasure is 0xFE (1111 1110 binary). Note that in order for

Figure 30. Single Byte Write to RAM

Rev. B | Page 44 of 52

ADM1060

2. To set up a 2-byte EEPROM address for a subsequent read,

write, block read, block write, or page erase. In this case, the

command byte is the high byte of the EEPROM address from

0xF8 to 0xF9. The (only) data byte is the low byte of the

EEPROM address. This is illustrated in Figure 31.

9. The slave asserts ACK on SDA after each data byte.

10. The master asserts a STOP condition on SDA to end the

transaction.

1

2

3

4

5

6

7

8

9

10

SLAVE

ADDRESS

COMMAND 0xFC

(BLOCK WRITE)

BYTE

COUNT

S

W A

A

A DATA 1 A DATA 2 A DATA N A P

1

2

3

4

5

6

7

8

EEPROM

ADDRESS

HIGH BYTE

(0xF8 TO 0xF9)

EEPROM

ADDRESS

LOW BYTE

(0x00 TO 0xFF)

Figure 33. Block Write to EEPROM or RAM

SLAVE

ADDRESS

A

P

S

W

A

Unlike some EEPROM devices that limit block writes to within

a page boundary, there is no limitation on the start address

when performing a block write to EEPROM, except

Figure 31. Setting an EEPROM Address

Note for page erasure that as a page consists of 32 bytes, only

the three MSBs of the address low byte are important. The

lower five bits of the EEPROM address low byte only specify

addresses within a page and are ignored during an erase

operation.

1. There must be at least N locations from the start address to

the highest EEPROM address (0xF9FF) to avoiding writing

to invalid addresses.

2. If the addresses cross a page boundary, both pages must be

erased before programming.

3. To write a single byte of data to EEPROM. In this case the

command byte is the high byte of the EEPROM address from

0xF8 to 0xF9. The first data byte is the low byte of the

EEPROM address and the second data byte is the actual data.

This is illustrated in Figure 32.

Note that the ADM1060 features a clock extend function for

writes to EEPROM. Programming an EEPROM byte takes

approximately 250 µs, which would limit the SMBus clock for

repeated or block write operations. The ADM1060 pulls SCL

low and extends the clock pulse when it cannot accept any more

data.

1

2

3

4

5

6

7

8

9

10

EEPROM

ADDRESS

HIGH BYTE

(0xF8 TO 0xF9)

EEPROM

ADDRESS

LOW BYTE

(0x00 TO 0xFF)

SLAVE

ADDRESS

S

W

A

DATA

A

P

A

READ OPERATIONS

Figure 32. Single Byte Write to EEPROM

The ADM1060 uses the following SMBus read protocols:

BLOCK WRITE

RECEIVE BYTE

In this operation, the master device writes a block of data to a

slave device. The start address for a block write must previously

have been set. In the case of the ADM1060, this is done by a

Send Byte operation to set a RAM address or a Write Byte/Word

operation to set an EEPROM address.

In this operation, the master device receives a single byte from a

slave device, as follows:

1. The master device asserts a START condition on SDA.

2. The master sends the 7-bit slave address followed by the read

bit (high).

1. The master device asserts a start condition on SDA.

3. The addressed slave device asserts ACK on SDA.

4. The master receives a data byte.

2. The master sends the 7-bit slave address followed by the write

bit (low).

3. The addressed slave device asserts ACK on SDA.

5. The master asserts NO ACK on SDA.

4. The master sends a command code that tells the slave device

to expect a block write. The ADM1060 command code for a

block write is 0xFC (1111 1100 binary).

6. The master asserts a STOP condition on SDA and the trans-

action ends.

In the ADM1060, the receive byte protocol is used to read a

single byte of data from a RAM or EEPROM location whose

address has previously been set by a send byte or write

byte/word operation. This is illustrated in Figure 34.

5. The slave asserts ACK on SDA.

6. The master sends a data byte that tells the slave device how

many data bytes will be sent. The SMBus specification allows

a maximum of 32 data bytes to be sent in a block write.

1

2

3

4

5

6

SLAVE

ADDRESS

S

R

A

DATA

A

P

7. The slave asserts ACK on SDA.

8. The master sends N data bytes.

Figure 34. Single Byte Read from EEPROM or RAM

Rev. B | Page 45 of 52

ADM1060

BLOCK READ

ERROR CORRECTION

In this operation, the master device reads a block of data from a

slave device. The start address for a block read must previously

have been set. In the case of the ADM1060, this is done by a

Send Byte operation to set a RAM address, or a Write

Byte/Word operation to set an EEPROM address. The block

read operation itself consists of a Send Byte operation that

sends a block read command to the slave, immediately followed

by a repeated start and a read operation that reads out multiple

data bytes, as follows:

The ADM1060 provides the option of issuing a PEC (packet

error correction) byte after a write to RAM, a write to

EEPROM, a block write to RAM/EEPROM, or a block read

from RAM/EEPROM. This enables the user to verify that the

data received by or sent from the ADM1060 is correct. The PEC

byte is an optional byte sent after the last data byte has been

written to or read from the ADM1060. The protocol is as

follows:

1. The ADM1060 issues a PEC byte to the master. The master

should check the PEC byte and issue another block read if the

PEC byte is incorrect.

1. The master device asserts a START condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

2. A NACK is generated after the PEC byte to signal the end of

the read.

3. The addressed slave device asserts ACK on SDA.

Note: The PEC byte is calculated using CRC-8. The Frame

Check Sequence (FCS) conforms to CRC-8 by the polynomial

4. The master sends a command code that tells the slave device

to expect a block read. The ADM1060 command code for a

block read is 0xFD (1111 1101 binary).

C(x) = x⁸+ x²+ x¹+ 1

5. The slave asserts ACK on SDA.

Consult the SMBus 1.1 specification for more information. An

example of a block read with the optional PEC byte is shown in

Figure 36.

6. The master asserts a repeat start condition on SDA.

1

2

3

4

5

6

7

8

9

10

11

12

7. The master sends the 7-bit slave address followed by the

read bit (high).

SLAVE

ADDRESS

COMMAND 0xFD

(BLOCK READ)

SLAVE

ADDRESS

BYTE

COUNT

A

S

R

A

DATA 1

A

S

W

A

13

14 15

8. The slave asserts ACK on SDA.

DATA

32

A

PEC

A P

9. The ADM1060 sends a byte count data byte that tells the

master how many data bytes to expect. The ADM1060 will

always return 32 data bytes (0x20), which is the maximum

allowed by the SMBus 1.1 specification.

Figure 36. Block Read from EEPROM or RAM with PEC

10. The master asserts ACK on SDA.

11. The master receives 32 data bytes.

12. The master asserts ACK on SDA after each data byte.

13. The master asserts a STOP condition on SDA to end the

transaction.

1

2

3

4

5

6

7

8

9

10

11

12

SLAVE

ADDRESS

COMMAND 0xFD

(BLOCK READ)

SLAVE

ADDRESS

BYTE

COUNT

A

S

R

A

DATA 1

A

S

W

A

13 14

DATA

32

A

P

Figure 35. Block Read from EEPROM or RAM

Rev. B | Page 46 of 52

ADM1060

5V_OUT

5V_IN

5VSB_OUT

5VSB_IN

3.3V_OUT

3.3V_IN

3.3VSB_OUT

3.3VSB_IN

1

µ

F

5

7

VCCP

VDDCAP

VH

8

12V_IN

9

VP1

VP2

PDO1

15

10

PDO2 16

11 VP3

VP4

12

PDO3

PDO4

17

18

ADM1060

13 VB1

VB2

PWR_OK

PDO5 19

20

14

PDO6

PDO7 21

28 GPI1

27 GPI2

PDO8 22

PDO9 23

GPI3

26

PWRGD

25 GPI4

VOUT

VIN

24

WDI

LDO

ACK

A0 A1

SCL

4

SDA

3

1

2

CLKOUT

EN

0.9V_OUT

1.8V

3.3V

VIN_CORE

VIN

VOUT

DC/DC

CONVERTER

µP

EN

–5V_OUT

VIN

VOUT

INVERTER

Figure 37. ADM1060 Application Diagram

Rev. B | Page 47 of 52

ADM1060

Table 57. ADM1060 Register Map

BLOCK

PLB1

PLB2

PLB3

PLB4

PLB5

PLB6

PLB7

PLB8

PLB9

0

1

2

3

4

5

6

7

8

9

A

B

C

D

0

1

2

3

4

5

6

7

8

9

P1PLBPOLA P1PLBIMKA P1SFDPOLA P1SFDIMKA P1GPIPOL P1GPIIMK P1WDICFG P1EN

P2PLBPOLA P2PLBIMKA P2SFDPOLA P2SFDIMKA P2GPIPOL P2GPIIMK P2WDICFG P2EN

P3PLBPOLA P3PLBIMKA P3SFDPOLA P3SFDIMKA P3GPIPOL P3GPIIMK P3WDICFG P3EN

P4PLBPOLA P4PLBIMKA P4SFDPOLA P4SFDIMKA P4GPIPOL P4GPIIMK P4WDICFG P4EN

P5PLBPOLA P5PLBIMKA P5SFDPOLA P5SFDIMKA P5GPIPOL P5GPIIMK P5WDICFG P5EN

P6PLBPOLA P6PLBIMKA P6SFDPOLA P6SFDIMKA P6GPIPOL P6GPIIMK P6WDICFG P6EN

P7PLBPOLA P7PLBIMKA P7SFDPOLA P7SFDIMKA P7GPIPOL P7GPIIMK P7WDICFG P7EN

P8PLBPOLA P8PLBIMKA P8SFDPOLA P8SFDIMKA P8GPIPOL P8GPIIMK P8WDICFG P8EN

P9PLBPOLA P9PLBIMKA P9SFDPOLA P9SFDIMKA P9GPIPOL P9GPIIMK P9WDICFG P9EN

P1PLBPOLB P1PLBIMKB P1SFDPOLB P1SFDIMKB P1PDBTIM

P2PLBPOLB P2PLBIMKB P2SFDPOLB P2SFDIMKB P2PDBTIM

P3PLBPOLB P3PLBIMKB P3SFDPOLB P3SFDIMKB P3PDBTIM

P4PLBPOLB P4PLBIMKB P4SFDPOLB P4SFDIMKB P4PDBTIM

P5PLBPOLB P5PLBIMKB P5SFDPOLB P5SFDIMKB P5PDBTIM

P6PLBPOLB P6PLBIMKB P6SFDPOLB P6SFDIMKB P6PDBTIM

P7PLBPOLB P7PLBIMKB P7SFDPOLB P7SFDIMKB P7PDBTIM

P8PLBPOLB P8PLBIMKB P8SFDPOLB P8SFDIMKB P8PDBTIM

P9PLBPOLB P9PLBIMKB P9SFDPOLB P9SFDIMKB P9PDBTIM

P1PDOCFG

P2PDOCFG

P3PDOCFG

P4PDOCFG

P5PDOCFG

P6PDOCFG

P7PDOCFG

P8PDOCFG

P9PDOCFG

FLT/STS

GPI/WDI

UPDCFG

PDEN

MANID

DEVID

REVID

MARK1

MARK2 GPI1CFG

GPI2CFG

GPI3CFG

GPI4CFG

WDICFG

ERRMASK1

ERRMASK2

E

BSFD1/2

H/PSFD1

PSFD2/3

A

B

C

D

BS1OVTH

HSOVTH

PS2OVTH

PS4OVTH

BS1OVHYST BS1UVTH

BS1UVHYST BS1SEL

HSUVHYST HSSEL

BS2OVTH

PS1OVTH

PS3OVTH

UVSTAT

BS2OVHYST BS2UVTH

PS1OVHYST PS1UVTH

PS3OVHYST PS3UVTH

BS2UVHYST BS2SEL

PS1UVHYST PS1SEL

PS3UVHYST PS3SEL

HSOVHYST

HSUVTH

PS2OVHYST PS2UVTH

PS4OVHYST PS4UVTH

PS2UVHYST PS2SEL

PS4UVHYST PS4SEL

PSFD4/

FLT/STS

OVSTAT

SFDSTAT

GWSTAT

LATF1

LATF2

PDOSTAT1

PDOSTAT2

E

F

Rev. B | Page 48 of 52

ADM1060

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

A0

GPI1

GPI2

GPI3

GPI4

1

2

28

27

26

25

A1

SDA

3

SCL

4

VDDCAP

GND

VCCP

VH

5

24 WDI

6

PDO9

23

22

21

20

19

18

17

16

15

ADM1060

TOP VIEW

(Not to Scale)

7

PDO8

PDO7

PDO6

PDO5

PDO4

PDO3

PDO2

PDO1

8

VP1

9

VP2

10

11

12

13

14

VP3

VP4

VB1

VB2

Figure 38. Pin Configuration

Table 58. Pin Function Descriptions

1

Mnemonic

A0

Function

Logic Input. Controls the seventh bit (LSB) of the 7-bit Serial Bus Address.

Logic Input. Controls the sixth bit of the 7-bit Serial Bus Address.

Serial Bus Data I/O Pin. Open-Drain output. Requires 2.2 kΩ pull-up resistor.

Open-Drain Serial Bus Clock Pin. Requires 2.2 kΩ pull-up resistor.

2

A1

3

SDA

4

SCL

5

VDDCAP

V_DDBypass Capacitor Pin. A capacitor from this pin to GND stabilizes the V_DDArbitrator. A 1 µF capacitor is

recommended for this function.

6

7

GND

Ground. Connect to common of power supplies.

VCCP

Reservoir Capacitor for Central Charge Pump. This provides the first stage in the tripler circuits used to

produce 12 V of gate drive on PDOs 1 to 4. A 1 µF capacitor is recommended for this function.

8

VH

High Voltage Supply Input. Two input ranges. A supply of between 2 V and 6 V or between 4.8 V and 14.4 V

can be applied to this pin. The V_DDarbitrator will select this supply to power the ADM1060 if it is the highest

supply supervised.

9–12

13–14

15–23

VP1–4

VB1–2

PDO1–9

Positive Only Supply Inputs. Three input ranges. A supply of between 0.6 V and 1.8 V, 1 V and 3 V, or 2 V and

6 V can be applied to this pin. The V_DDarbitrator will select one of these supplies to power the ADM1060 if it is

the highest supply supervised.

Bipolar Supply Inputs. Two modes. Two input ranges in positive mode. One input range in negative mode. A

supply of between –6 V and –2 V can be applied to this pin when set in negative mode. A supply of between

1 V and 3 V or between 2 V and 6 V can be applied to this pin when set in positive mode.

Programmable Driver Output Pin. All nine can be programmed as logic outputs with multiple pull-up options

to V_DDor VPn. PDOs 1 to 4 can also provide a charge-pump generated gate drive for external

N-channel FETs.

24

WDI

Watchdog Input. Used to monitor a processor clock and asserts a fault condition if the clock fails to transition

from low-to-high or high-to-low within a programmed timeout period (up to 18 sec).

25–28

GPI4–1

General-Purpose Logic Input. TTL compatible logic. Can be used as, for example, a manual reset, a chip en-

able pin, or an input for a control logic signal that may be used to initiate the power-up/power-down

sequence of the supplies under control.

Rev. B | Page 49 of 52

ADM1060

OUTLINE DIMENSIONS

Figure 39. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features proprie-

tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of

functionality.

Ordering Guide

Model

Temperature Range

–40°C to +85°C

Package Description

28-lead TSSOP

Package Option

RU-28

ADM1060ARU

ADM1060ARU–REEL

ADM1060ARU–REEL7

EVAL–ADM1060EB¹

–40°C to +85°C

28-lead TSSOP

RU-28

–40°C to +85°C

28-lead TSSOP

RU-28

Evaluation Board

¹Contact factory for availability of the evaluation board.

For general ADM1060 support, send email to: ADM1060.support@analog.com

Rev. B | Page 50 of 52

ADM1060

NOTES

Rev. B | Page 51 of 52

ADM1060

NOTES

©

registered trademarks are the property of their respective owners.

C03470–0–12/03(B)

Rev. B | Page 52 of 52


型号：	ADM1060ARUZ
厂家：	ADI
描述：	Multi Power Supply Sequencer & Supervisor
文件：	总53页 (文件大小：512K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADM1060ARUZ [ADI]

相关型号：

ADM1060ARUZ-REEL7

ADM1062

ADM1062-1069

ADM1062ACP

ADM1062ACPZ

ADM1062ACPZ-REEL7

ADM1062ASU

ADM1062ASUZ

ADM1062ASUZ-REEL7

ADM1063

ADM1063ACP

ADM1063ACP-REEL7