ADM1185ARMZ [ADI]
Quad Voltage Monitor and Sequencer; 四电压监视和音序器
| 型号： | ADM1185ARMZ |
| 厂家： | 
ADI |
| 描述： | Quad Voltage Monitor and Sequencer |
| 文件： | 总12页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Voltage Monitor and Sequencer
ADM1185
Preliminary Technical Data
FEATURES
Powered from 2.7V to 5.5V on the VCC pin
FUNCTIONAL BLOCK DIAGRAM
Monitors Four Supplies via 0.8% Accurate Comparators
VCC
Four inputs can be programmed for voltage levels with
resistor dividers
Three Open-Drain Enable Outputs
Open-Drain Power Good Output
10-pin MSOP Package
ADM1185
POWER AND
REFERENCE
GENERATOR
REF=0.6V
OUT1
VIN1
REF=0.6V
APPLICATIONS
Monitor and Alarm Functions
Power Supply Sequencing
Telecommunication and Datacommunication Equipment
PC/Servers
OUT2
OUT3
VIN2
VIN3
REF=0.6V
REF=0.6V
REF=0.6V
LOGIC
GENERAL DESCRIPTION
VIN4
The ADM1185 is an integrated four channel voltage monitoring
device. A 2.7V to 5.5V power supply is required on the VCC pin
to power the device.
PWRGD
Four precision comparators monitor four voltage rails. All
comparators have a 0.6V reference with a worst-case accuracy
of 0.8%. Resistor networks external to the VIN1-VIN4 pins set
the trip points.
GND
Figure 1.
There are four open-drain outputs on the device. A digital core
interprets the comparator outputs and asserts the outputs as
appropriate.
APPLICATIONS DIAGRAM
3.3V IN
2.5V OUT
1.8V OUT
1.2V OUT
IN
Regulator1
VCC
2.5V OUT
1.8V OUT
VIN1
VIN2
EN
OUT
OUT1
OUT2
IN
VIN3
VIN4
OUT3
Regulator2
EN
OUT
ADM1185
IN
GND
PWRGD
Regulator3
1.2V OUT
EN
OUT
POWER
GOOD
Figure 2.
Rev. PrK June 2006
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2006 Analog Devices, Inc. All rights reserved.
ADM1185
Preliminary Technical Data
TABLE OF CONTENTS
REVISION HISTORY
Rev. PrK | Page 2 of 12
Preliminary Technical Data
ADM1185
ADM1185—SPECIFICATIONS
VVCC = 2.7V to 5.5V, TA = -40°C to +85°C
Table 1.
Parameter
Min
Typ
Max
Units
Conditions
VCC Pin
Operating Voltage Range, VVCC
Supply Current, IVCC
2.7
5.5
100
V
µA
30
VIN1-VIN4 Pins
Input Current, IVINLEAK
Input Rising Threshold, VTHR
Input Rising Hysteresis, VHYST (=VTHR -VTHF
OUT1-OUT3, PWRGD Pins
-100
0.5952
100
nA
V
mV
VVINx = 0.7V
0.6000 0.6048
9
)
Output low voltage, VOUTL
0.4
0.4
1
V
V
µA
V
VVCC = 2.7 V, ISINK = 2mA
VVCC = 1 V, ISINK =100µA
Leakage Current, IALERT
VVCC that guarantees outputs valid
-1
1
All outputs will be guaranteed to be either
low or giving a valid output level from VVCC
= 1V.
VIN1 to OUT1 Delay
100
100
190
190
280
280
ms
ms
VVIN1 Rising
VIN4 to PWRGD Delay
VVIN4 Rising, condition only valid at certain
operational states, refer to state diagram
High-to-Low Propagation Delay
Low-to-High Propagation Delay
30
30
µs
µs
VVCC =3.3V, see TPC1
VVCC =3.3V, see TPC1
Rev. PrK | Page 3 of 12
ADM1185
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only. Functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions may affect device reliability.
Ambient temperature = 25°C, unless otherwise noted.
Parameter
Rating
VCC Pin
VIN1-VIN4 Pin
OUT1-OUT3, PWRGD Pins
Power Dissipation
Storage Temperature
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
TBD
−65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
300°C
150°C
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrK | Page 4 of 12
Preliminary Technical Data
PIN CONFIGURATIONS
ADM1185
10
9
1
2
Vcc
GND
VIN1
VIN2
VIN3
VIN4
ADM1185
TOP VIEW
OUT1
8
OUT2
3
(NOT TO SCALE)
7
6
4
5
OUT3
PWRGD
Figure 3. Pin Configurations
PIN FUNCTIONAL DESCRIPTIONS
Table 3.
Pin No. Name
Description
1
2
GND
VIN1
Chip Ground Pin.
Non-inverting input of comparator 1. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
3
4
5
6
VIN2
Non-inverting input of comparator 2. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Non-inverting input of comparator 3. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Non-inverting input of comparator 4. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN4 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this
pin. After power-up (after PWRGD asserts) this output will be driven low if any of the voltages on the VIN1-
VIN4 pins falls below 0.6V.
VIN3
VIN4
PWRGD
7
8
9
OUT3
OUT2
OUT1
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN3 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low
if the voltage on VIN1 falls below 0.6V.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN2 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low
if the voltage on VIN1 falls below 0.6V.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN1 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this
pin. After power-up (after PWRGD asserts) this output will be driven low if the voltage on VIN1 falls below
0.6V.
10
VCC
Positive supply input pin. The operating supply voltage range is 2.7 V to 5.5 V.
Rev. PrK | Page 5 of 12
ADM1185
Preliminary Technical Data
TYPICAL PERFORMANCE CURVES
v(pad)
800
Output
Low
Voltage
(mV)
Voltage
(mV)
775
750
725
700
675
650
625
600
575
550
525
500
475
450
425
400
375
350
325
300
275
250
225
200
175
150
125
100
75
2mA. 85degC/SLOW
50
25
0
.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Duration (us)
Supply Voltage (V)
TPC 2. Output Low Voltage vs. Supply Voltage
TPC 1. Maximum transient duration Without Causing an Output Pulse vs.
Output Comparator Overdrive
Rev. PrK | Page 6 of 12
Preliminary Technical Data
Functional Description
The operation of the ADM1185 is explained in this section in
the context of the device in a voltage monitoring and
sequencing application (figure 4, above). In this application, the
ADM1185 will monitor four separate voltage rails, turn on
three regulators in a predefined sequence and generate a power
good signal to turn on a controller when all power supplies are
up and stable.
ADM1185
The assertion of OUT1 will turn on Regulator1. The 2.5V
output of this regulator will begin to rise. This will be detected
by input VIN2 (with a similar resistor divider scheme as shows
in figure 5). When VIN2 sees the 2.5V rail rise above its UV
point it will assert output OUT2, turning on Regulator2. A
capacitor can be placed on the VIN2 pin to slow the rise of the
voltage on this pin- this effectively sets a time delay between the
2.5V rail powering up and the next Regulator being enabled.
The same scheme is implemented with the other input and
output pins. Every rail that is turned on via an output pin
OUT(n) is monitored via input pin VIN(n+1).
The final comparator inside the VIN4 pin detects the final
supply turning on, which is 1.2V in this case. All of the output
pins (OUT1-OUT3) are logically ANDed together to generate a
system power good signal (PWRGD). There is an internal
190ms delay associated with the assertion of the PWRGD
output.
POWER ON SEQUENCING AND MONITORING
The main supply (in this case 3.3V) powers up the device via
the VCC pin as the voltage rises. A supply voltage of 2.7V to
5.5V is needed to power the device.
The VIN1 pin is monitoring the main 3.3V supply. An external
resistor divider will scale this voltage down for monitoring at
the VIN1 pin. The resistor ratio is chosen so that the VIN1
voltage is 0.6V when the main voltage rises to the preferred
level at start-up (some voltage below the nominal 3.3V level). In
this case, R1 is 4.6K and R2 is 1.2K so that a voltage level of
2.9V will correspond to 0.6V on the non-inverting input of the
first comparator.
Table 4 below is a truth table that steps through the power on
sequence of the outputs. Any associated internal time delays are
also shown.
V
VOLTAGE MONITORING AFTER POWER ON
Once PWRGD is asserted the logical core latches into a
different mode of operation. During the initial power up phase
each output is directly dependant on an input (i.e. VIN3
asserting causes OUT3 to assert). When power up is complete
this function is redundant.
3.3V
2.9V
0V
t
ADM1185
4.6K
Once in the PWRGD state the following behavior can be
observed:
VIN1
2.9V supply
gives 0.6V
at VIN1 pin
TO LOGIC
CORE
1.2K
•
If the main 3.3V supply that is monitored via VIN1
faults in the power good state then the PWRGD
output is deasserted to warn the downstream
controller and all of the outputs OUT1-OUT3 are
immediately turned off, disabling all locally generated
supplies.
0.6V
Figure 4.Setting the undervoltage threshold with an external resistor divider
•
If a supply monitored by VIN2-VIN4 fails the
PWRGD output is deasserted to warn the controller
but the other outputs are not deasserted.
OUT1 is an open drain active high output. In this application,
OUT1 is connected to the enable pin of a regulator. Before the
voltage on VIN1 has reached 0.6V this output is switched to
ground, disabling regulator 1. (Note that all outputs are driven
to ground as long as there is 1V on the VCC pin of the
ADM1185). When the main system voltage reaches 2.9V VIN1
will detect 0.6V and this will cause OUT1 to assert after a
190ms delay. When this occurs the open drain output will
switch high and the external pull-up resistor will pull the
voltage on the regulator 1 enable pin above its turn-on
threshold, turning on the output of regulator 1.
Table 5 and table 6 are truth tables that highlight the behavior of
the ADM1185 under various fault situations during normal
operation (i.e. in the mode of operation after PWRGD has
asserted).
Rev. PrK | Page 7 of 12
ADM1185
Preliminary Technical Data
3.3V IN
2.5V OUT
1.8V OUT
1.2V OUT
IN
Regulator1
VCC
2.5V OUT
VIN1
VIN2
EN
OUT
OUT1
OUT2
IN
VIN3
VIN4
OUT3
Regulator2
1.8V OUT
1.2V OUT
EN
OUT
ADM1185
IN
GND
PWRGD
Regulator3
EN
OUT
POWER
GOOD
Figure 5. Applications Diagram showing ADM1185 in a voltage monitoring and sequencing application
State1
Start
IN1=OK
(Delay=100ms min)
OUT1
On
State2
IN2=OK
IN1=FAULT
IN1=FAULT
OUT1,2
On
State3
State4
IN3=OK
OUT1,2,3
On
IN4=OK
(Delay=100ms min)
IN1=FAULT
IN1=FAULT
PWRGD
State5
IN2.IN3.IN3=FAULT
Figure 6. Flow Diagram highlighting the different modes of operation o the logical core
State Name OUT1 OUT2 OUT3 OUT4
Next Event
Next State
State
Reset*
Out1 On
Out1,2 On
Out1,2,3 On
PowerGood
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
IN1 High for 190ms
IN1 and IN2 High for 30us
IN1 and IN3 High for 30us
All High for 190ms
IN2 or IN3 or IN4 Low for
30us
Out1 On
Out1,2 On
Out1,2,3 On
PowerGood
Out1,2,3 On
1
2
3
4
5
IN1 Low for 30 us
Start
Table 4. Truth table
Rev. PrK | Page 8 of 12
Preliminary Technical Data
ADM1185
VIN1
VT(rising)
VT(falling)
=0.6V
VIN1
VT(rising)
tPROP
tPROP
OUT1
OUT2
OUT3
OUT1
OUT2
OUT3
190ms
190ms
tPROP
PWRGD
PWRGD
190ms
190ms
NOTE* The rising threshold on the VIN1-VIN4 pins will be slightly
higher than 0.6V as there is some hysteresis on this pin.
NOTE* The rising threshold on the VIN1-VIN4 pins will be slightly
higher than 0.6V as there is some hysteresis on this pin.
Figure 6. Power-up Waveforms
Figure 7. Waveforms showing reaction to a temporary low glitch on the
main supply
Rev. PrK | Page 9 of 12
ADM1185
Preliminary Technical Data
CASCADING MULTIPLE DEVICES
Multiple ADM1185 devices can be cascaded in situations where
a large number of supplies must be monitored and/or
sequenced. There are numerous configurations for
interconnecting devices. The most suitable configuration will
depend on the application. Figures 8, 9 and 10 show some
methods for cascading multiple ADM1185 devices.
3.3V
3.3V
ADM1185-A
VCC
Reg1
EN1
VIN1
VIN2
OUT1
OUT2
3.3V
V1
Reg2
V1
EN2
V2
VIN3
VIN4
V2
V3
Reg3
OUT3
EN3
V3
GND
PWRGD
Note: Supplies
scaled down with
resistor dividers
3.3V
ADM1185-B
VCC
Reg4
EN4
VIN1
VIN2
VIN3
OUT1
OUT2
V4
V5
Reg5
V4
V5
V6
EN5
Reg6
OUT3
EN6
V6
VIN4
GND
PWRGD
POWER GOOD
Figure 8. Cascading multiple ADM1185 devices, option 1
Rev. PrK | Page 10 of 12
Preliminary Technical Data
ADM1185
3.3V
3.3V
ADM1185-A
VCC
Reg1
EN1
VIN1
OUT1
OUT2
3.3V
V1
V2
Reg2
V1
V2
VIN2
EN2
VIN3
VIN4
Reg3
OUT3
EN3
V3
3.3V
GND
PWRGD
Note: Supplies
scaled down with
resistor dividers
3.3V
ADM1185-B
VCC
Reg4
EN4
V3
VIN1
VIN2
VIN3
OUT1
OUT2
V4
V5
Reg5
V4
V5
V6
EN5
Reg6
OUT3
EN6
V6
VIN4
GND
PWRGD
POWER GOOD
Figure 9. Cascading multiple ADM1185 devices, option 2
3.3V
3.3V
ADM1185-A
VCC
Reg1
EN1
VIN1
VIN2
VIN3
OUT1
OUT2
3.3V
V1
V2
Reg2
V1
V2
EN2
Reg3
OUT3
EN3
V3
VIN4
GND
3.3V
PWRGD
Note: Supplies
scaled down with
resistor dividers
3.3V
ADM1185-B
VCC
VIN1
VIN2
OUT1
OUT2
3.3V
Reg4
EN4
V3
V5
V4
V5
Reg5
EN5
VIN3
VIN4
OUT3
V6
GND
PWRGD
POWER GOOD
Figure 10. Cascading multiple ADM1185 devices, option 3
Rev. PrK | Page 11 of 12
ADM1185
Preliminary Technical Data
OUTLINE DIMENSIONS
0.122 (3.10)
0.114 (2.90)
10
6
5
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
1
PIN
1
0.0197 (0.50)
BSC
0.120 (3.05)
0.120 (3.05)
0.112 (2.85)
0.112 (2.85)
0.037 (0.94)
0.031 (0.78)
0.043 (1.10)
MAX
6o
0o
SEATING
PLANE
0.006 (0.15) 0.012 (0.30)
0.002 (0.05) 0.006 (0.15)
0.028 (0.70)
0.016 (0.40)
0.009 (0.23)
0.005 (0.13)
Figure 9. 10-Lead MSOP Package
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1185ARMZ1
Temperature Range
-40°C to +85°C
Package Description
Package Outline
MSOP-10
RM-10
Z=PB-free part
Rev. PrK | Page 12 of 12
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