ADM3483EARZ-REEL7 [ADI]
3.3 V, 【15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers; 3.3 V ， 【 15千伏ESD保护，半双工和全双工， RS - 485 / RS -422收发器
| 型号： | ADM3483EARZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 3.3 V, 【15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers |
| 文件： | 总20页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 V, ± ±1 ꢀV ꢁESD-Proteotꢂ, ꢃHalD Hꢄꢂ
FuaaDSupatx, RED481/RED422 TPHꢄsetivtPs
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
V
TIA/EIA RS-485/RS-422 compliant
15 kV ESD protection on RS-485 input/output pins
Data rates
CC
ADM3483E/
ADM3486E
ADM3483E/ADM3488E: 250 kbps
ADM3486E: 2.5 Mbps
ADM3490E/ADM3491E: 12 Mbps
Half- and full-duplex options
R
RO
RE
DE
A
B
DI
D
Up to 32 nodes on the bus
Receiver open-circuit, fail-safe design
Low power shutdown current
GND
(ADM3483E/ADM3486E/ADM3491E only)
Outputs high-Z when disabled or powered off
Common-mode input range: −7 V to +12 V
Thermal shutdown and short-circuit protection
Industry-standard 75176 pinout
8-lead and 14-lead narrow SOIC packages
Figure 1.
V
CC
ADM3488E/
ADM3490E
A
B
R
RO
DI
APPLICATIONS
Power/energy metering
Telecommunications
EMI-sensitive systems
Industrial control
Z
Y
D
GND
Figure 2.
Local area networks
V
CC
GENERAL DESCRIPTION
The ADM3483E/ADM3486E/ADM3488E/ADM3490E/
ADM3491E are 3.3 V, low power data transceivers with
1ꢀ ꢁV EꢂD protection suitable for full- and half-duplex
communication on multipoint bus transmission lines. They
are designed for balanced data transmission, and they
comply with TIA/EIA standards Rꢂ48ꢀ and Rꢂ-422. The
ADM3483E/ADM3486E are half-duplex transceivers that
share differential lines and have separate enable inputs for
the driver and receiver. The full-duplex ADM3488E/
ADM3490E/ADM3491E transceivers have dedicated
differential line driver outputs and receiver inputs. The
ADM3491E also features separate enable inputs for the
driver and receiver.
ADM3491E
A
B
R
RO
RE
DE
Z
Y
DI
D
GND
Figure 3.
The devices have a 12 ꢁΩ receiver input impedance,
which allows up to 32 transceivers on a bus. Because only
one driver should be enabled at any time, the output of a
disabled or powered-down driver is tristated to avoid
overloading the bus.
(continued on Page 3)
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Driver Timing Specifications...................................................... 5
Receiver Timing Specifications .................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Test Circuits and Switching Characteristics.................................. 9
Typical Performance Characteristics ........................................... 11
Circuit Description......................................................................... 14
Devices Without Receiver/Driver Enable―ADM3488E/
ADM3490E ................................................................................. 14
Low Power Shutdown Mode—ADM3483E/ADM3486E/
ADM3491E ................................................................................. 14
Driver Output Protection.......................................................... 14
Propagation Delay...................................................................... 14
Line Length vs. Data Rate ......................................................... 14
15 kꢀ ESD Protection ............................................................. 15
Human Body Model .................................................................. 15
Typical Applications................................................................... 15
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Devices with Receiver/Driver Enable—ADM3483E/
ADM3486E/ADM3491E ........................................................... 14
REVISION HISTORY
10/06—Rev. 0 to Rev. A
Added ADM3483E and ADM3488E ...............................Universal
Changes to Figure 1 and Figure 2................................................... 1
Inserted Table 3................................................................................. 5
Changes to Figure 4 and Figure 5................................................... 8
Inserted Figure 28 and Figure 29.................................................. 13
Changes to Figure 31 and Figure 32............................................. 16
Changes to Figure 34...................................................................... 17
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 18
8/06—Revision 0: Initial Version
Rev. A | Page 2 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
GꢁNꢁRAL SꢁECRI-TION
(continued from Page 1)
Excessive power dissipation caused by bus contention
or by output shorting is prevented with a thermal shut-
down circuit.
The driver outputs of the ADM3483E/ADM3486E/
ADM3488E are slew rate limited, in order to reduce EMI
and data errors caused by reflections from improperly
terminated buses. The receiver has a fail-safe feature that
ensures a logic high output when the inputs are floating.
The parts are fully specified over the industrial temperature range
and are available in 8-lead and 14-lead narrow ꢂOIC pacꢁages.
Table 1. Selection Table
Guaranteed Data
Rate (Mbps)
Supply
Voltage (V)
Half/Full Slew Rate
Driver/Receiver
Enable
15 kV ESD Protection
on Bus Pins
Part No.
Duplex
Half
Half
Full
Limited
Pin Count
ADM3483E
ADM3486E
ADM3488E
ADM3490E
ADM3491E
0.25
2.5
0.25
12
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
8
8
8
8
Full
No
12
Full
No
14
Rev. A | Page 3 of 20
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
SPECIFICATIONS
VCC = 3.3 V ꢀ.3 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2. ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Parameter
Symbol Min
Typ
Max Unit
Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage
VOD
2.0
1.5
1.5
V
V
V
V
V
V
mA
mA
RL = 100 Ω (RS-422) (see Figure 7)
RL = 54 Ω (RS-485) (see Figure 7)
RL = 60 Ω (RS-485) (see Figure 8)
RL = 54 Ω or 100 Ω (see Figure 7)
RL = 54 Ω or 100 Ω (see Figure 7)
RL = 54 Ω or 100 Ω (see Figure 7)
VOUT = −7 V
Δ|VOD| for Complementary Output States1
Common-Mode Output Voltage
Δ|VOC| for Complementary Output States1
∆VOD
VOC
∆VOC
IOSD
0.2
3
0.2
Short-Circuit Output Current
−250
−20
250
20
VOUT = 12 V
Output Leakage (Y, Z) (ADM3491E Only)
Normal Mode
IO
μA
μA
μA
μA
DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
VOUT = 12 V
DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
VOUT = −7 V
DE = 0 V, RE = VCC, VCC = 0 V or 3.6 V,
VOUT = 12 V
DE = 0 V, RE = VCC, VCC = 0 V or 3.6 V,
VOUT = −7 V
Shutdown Mode
1
−1
Logic Inputs
Input High Voltage
Input Low Voltage
Logic Input Current
VIH
VIL
IIN1
2.0
V
DE, DI, RE
DE, DI, RE
DE, DI, RE
0.8
2
V
μA
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Input Hysteresis
Input Resistance (A, B)
Input Current (A, B)
VTH
∆VTH
RIN
−0.2
12
0.2
1.0
V
−7 V < VCM < +12 V
VCM = 0 V
−7 V < VCM < +12 V
50
mV
kΩ
mA
mA
IIN2
DE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V
DE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
−0.8
VCC − 0.4
8
RO Logic Output
Output High Voltage
Output Low Voltage
Short-Circuit Output Current
Tristate Output Leakage Current
POWER SUPPLY
VOH
VOL
IOSR
IOZR
V
V
mA
μA
IOUT = −1.5 mA, VID = 200 mV (see Figure 9)
IOUT = 2.5 mA, VID = 200 mV (see Figure 9)
0 V < VRO < VCC
0.4
60
1
VCC = 3.6 V, 0 V < VOUT < VCC
Voltage Range
Supply Current
VCC
ICC
3.0
3.6
2.2
V
mA
1.1
No load, DI = 0 V or VCC, DE = VCC,
RE = 0 V or VCC
0.95
0.002
1.9
1
mA
μA
No load, DI = 0 V or VCC, DE = 0 V,
RE = 0 V
Shutdown Current
ISHDN
DE = 0 V, RE = VCC, DI = 0 V or VCC
ESD PROTECTION
A, B, Y, Z Pins
All Pins Except A, B, Y, Z Pins
15
4
kV
kV
Human body model
Human body model
1 Δ|VOD| and Δ|VOC| are the changes in VOD and VOC, respectively, when DI input changes state.
Rev. A | Page 4 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
DRIVER TIMING SPECIFICATIONS
VCC = 3.3 V, TA = 2ꢀ°C.
Table 3. ADM3483E/ADM3488E
Parameter
Symbol
Min
250
600
400
Typ
Max
Unit
kbps
ns
Test Conditions/Comments
MAXIMUM DATA RATE
DIFFERENTIAL OUTPUT DELAY
DIFFERENTIAL OUTPUT TRANSITION TIME
PROPAGATION DELAY
tDD
tTD
900
740
1400
1200
RL = 60 Ω (see Figure 10)
RL = 60 Ω (see Figure 10)
ns
From Low to High Level
From High to Low Level
|tPLH − tPHL| PROPAGATION DELAY SKEW1
ENABLE/DISABLE TIMING (ADM3483E ONLY)
Enable Time to Low Level
tPLH
tPHL
tPDS
700
700
930
930
50
1500
1500
ns
ns
ns
RL = 27 Ω (see Figure 11)
RL = 27 Ω (see Figure 11)
RL = 27 Ω (see Figure 11)
tPZL
tPZH
tPLZ
tPHZ
tPSL
tPSH
900
600
50
50
1.9
2.2
1300
800
80
80
2.7
3.0
ns
ns
ns
ns
μs
μs
RL = 110 Ω (see Figure 13)
RL = 110 Ω (see Figure 12)
RL = 110 Ω (see Figure 13)
RL = 110 Ω (see Figure 12)
RL = 110 Ω (see Figure 13)
RL = 110 Ω (see Figure 12)
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
Enable Time from Shutdown to Low Level
Enable Time from Shutdown to High Level
1 Measured on |tPLH (Y) − tPHL (Y)| and |tPLH (Z) − tPHL (Z)|.
VCC = 3.3 V, TA = 2ꢀ°C.
Table 4. ADM3486E
Parameter
Symbol
Min
2.5
20
Typ
Max
Unit
Mbps
ns
Test Conditions/Comments
MAXIMUM DATA RATE
DIFFERENTIAL OUTPUT DELAY
DIFFERENTIAL OUTPUT TRANSITION TIME
PROPAGATION DELAY
tDD
tTD
42
28
70
60
RL = 60 Ω (see Figure 10)
RL = 60 Ω (see Figure 10)
15
ns
From Low to High Level
From High to Low Level
|tPLH − tPHL| PROPAGATION DELAY SKEW1
tPLH
tPHL
tPDS
20
20
42
42
−6
75
75
12
ns
ns
ns
RL = 27 Ω (see Figure 11)
RL = 27 Ω (see Figure 11)
RL = 27 Ω (see Figure 11)
ENABLE/DISABLE TIMING
Enable Time to Low Level
tPZL
tPZH
tPLZ
tPHZ
tPSL
tPSH
52
52
40
40
700
700
100
100
80
80
1000
1000
ns
ns
ns
ns
ns
ns
RL = 110 Ω (see Figure 13)
RL = 110 Ω (see Figure 12)
RL = 110 Ω (see Figure 13)
RL = 110 Ω (see Figure 12)
RL = 110 Ω (see Figure 13)
RL = 110 Ω (see Figure 12)
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
Enable Time from Shutdown to Low Level
Enable Time from Shutdown to High Level
1 Measured on |tPLH (Y) − tPHL (Y)| and |tPLH (Z) − tPHL (Z)|.
Rev. A | Page 5 of 20
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
VCC = 3.3 V, TA = 25°C.
Table 5. ADM3490E/ADM3491E
Parameter
Symbol
Min
12
1
Typ
15
Max
Unit
Mbps
ns
Test Conditions/Comments
MAXIMUM DATA RATE
DIFFERENTIAL OUTPUT DELAY
DIFFERENTIAL OUTPUT TRANSITION TIME
PROPAGATION DELAY
tDD
tTD
22
35
25
RL = 60 Ω (see Figure 10)
RL = 60 Ω (see Figure 10)
3
11
ns
From Low to High Level
From High to Low Level
|tPLH − tPHL| PROPAGATION DELAY SKEW1
ENABLE/DISABLE TIMING (ADM3491E ONLY)
Enable Time to Low Level
tPLH
tPHL
tPDS
7
7
23
23
35
35
±±
ns
ns
ns
RL = 27 Ω (see Figure 11)
RL = 27 Ω (see Figure 11)
RL = 27 Ω (see Figure 11)
−1.4
tPZL
tPZH
tPLZ
tPHZ
tPSL
tPSH
42
42
35
35
650
650
90
90
±0
±0
900
900
ns
ns
ns
ns
ns
ns
RL = 110 Ω (see Figure 13)
RL = 110 Ω (see Figure 12)
RL = 110 Ω (see Figure 13)
RL = 110 Ω (see Figure 12)
RL = 110 Ω (see Figure 13)
RL = 110 Ω (see Figure 12)
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
Enable Time from Shutdown to Low Level
Enable Time from Shutdown to High Level
1 Measured on |tPLH (Y) − tPHL (Y)| and |tPLH (Z) − tPHL (Z)|.
RECEIVER TIMING SPECIFICATIONS
VCC = 3.3 V, TA = 25°C.
Table 6. ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Parameter
Symbol Min Typ Max Unit
Test Conditions/Comments
PROPAGATION DELAY
From Low to High Level
tRPLH
ADM34±6E/ADM3490E/ADM3491E
ADM34±3E/ADM34±±E
25
25
62
75
90
120
ns
ns
VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
From High to Low Level
tRPHL
ADM34±6E/ADM3490E/ADM3491E
ADM34±3E/ADM34±±E
25
25
62
75
90
120
ns
ns
VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
|tRPLH − tRPHL| PROPAGATION DELAY SKEW
ADM34±6E/ADM3490E/ADM3491E
ADM34±3E/ADM34±±E
tRPDS
+6
±10
ns
ns
VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
+12 ±20
ENABLE/DISABLE TIMING (ADM34±3E/ADM34±6E/
ADM3491E ONLY)
Enable Time to Low Level
Enable Time to High Level
tRPZL
tRPZH
tRPLZ
tRPHZ
tRPSL
tRPSH
tSHDN
25
25
25
25
50
50
45
45
ns
ns
ns
ns
CL = 15 pF (see Figure 15)
CL = 15 pF (see Figure 15)
CL = 15 pF (see Figure 15)
CL = 15 pF (see Figure 15)
CL = 15 pF (see Figure 15)
CL = 15 pF (see Figure 15)
Disable Time from Low Level
Disable Time from High Level
Enable Time from Shutdown to Low Level
Enable Time from Shutdown to High Level
Time to Shutdown1
720 1400 ns
720 1400 ns
190 300
±0
ns
1 The transceivers are put into shutdown mode by bringing the high and the DE low. If the inputs are in this state for less than ±0 ns, the parts are guaranteed not to
RE
enter shutdown. If the parts are in this state for 300 ns or more, the parts are guaranteed to enter shutdown.
Rev. A | Page 6 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
ABEOLUTꢁ MAXIMUM RATINGE
TA = 2ꢀ°C, unless otherwise noted.
ꢂtresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Parameter
Rating
−0.3 V to +6 V
VCC to GND
Digital Input/Output Voltage (DE, RE, DI) −0.3 V to +6 V
Receiver Output Voltage (RO)
−0.3 V to (VCC + 0.3 V)
Driver Output (A, B, Y, Z)/Receiver Input
(A, B) Voltage
Driver Output Current
−8 V to +13 V
250 mA
ESD CAUTION
Operating Temperature Range
Storage Temperature Range
θJA Thermal Impedance
8-Lead SOIC_N
−40°C to +85°C
−65°C to +150°C
158°C/W
120°C/W
260°C
14-Lead SOIC_N
Lead Temperature, Soldering (20 sec)
Rev. A | Page 7 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
-IN CONFIGURATIONE ANS FUNCTION SꢁECRI-TIONE
NC
RO
1
2
3
4
5
6
7
14
13
12
11
10
9
V
V
CC
CC
RE
A
ADM3491E
TOP VIEW
(Not to Scale)
DE
B
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
V
1
2
3
4
8
7
6
5
A
B
Z
DI
Z
CC
CC
ADM3483E/
ADM3486E
ADM3488E/
ADM3490E
B
RO
DI
GND
GND
Y
A
TOP VIEW
(Not to Scale)
8
NC
TOP VIEW
(Not to Scale)
GND
GND
Y
NC = NO CONNECT
Figure 4. ADM3483E/ADM3486E
Pin Configuration
Figure 5. ADM3488E/ADM3490E
Pin Configuration
Figure 6. ADM3491E
Pin Configuration
Table 8. Pin Function Descriptions
ADM3483E/
ADM3486E
Pin No.
ADM3488E/
ADM3490E
Pin No.
ADM3491E
Pin No.
Mnemonic Description
Receiver Output. If A > B by 200 mV, RO is high; if A < B by 200 mV,
RO is low.
1
2
2
RO
2
N/A
3
RE
Receiver Output Enable. A low level enables the receiver output. A high
level places it in a high impedance state. If RE is high and DE is low, the
device enters a low power shutdown mode.
3
4
N/A
3
4
5
DE
DI
Driver Output Enable. A high level enables the driver differential A and B
outputs. A low level places it in a high impedance state. If RE is high and DE
is low, the device enters a low power shutdown mode.
Driver Input. With a half-duplex part when the driver is enabled, a logic low
on DI forces A low and B high; a logic high on DI forces A high and B low.
With a full-duplex part when the driver is enabled, a logic low on DI forces Y
low and Z high; a logic high on DI forces Y high and Z low.
5
N/A
6
N/A
N/A
7
N/A
8
4
5
N/A
8
6
N/A
7
1
6, 7
9
N/A
12
10
N/A
11
GND
Y
A
A
Z
B
B
VCC
NC
Ground.
Noninverting Driver Output.
Noninverting Receiver Input A and Noninverting Driver Output A.
Noninverting Receiver Input A.
Inverting Driver Output.
Inverting Receiver Input B and Inverting Driver Output B.
Inverting Receiver Input B.
Power Supply, 3.3 V 0.3 V. Bypass VCC to GND with a 0.1 μF capacitor.
No Connect. Not internally connected. Can be connected to GND.
13, 14
1, 8
N/A
N/A
Rev. A | Page 8 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
TꢁET CIRCUITE ANS EWITCꢃING CꢃARACTꢁRIETICE
V
OM
Y
R
= 27ꢀ
L
R /2
L
S1
V
OD
OUT
2
D
V
R /2
L
OC
C
= 15pF
1
L
GENERATOR
50ꢀ
Z
V
CC
Figure 7. Driver Differential Output Voltage and
Common-Mode Output Voltage
V
+ V
OL
OH
V
=
≈ 1.5V
OM
2
375Ω
1
2
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
C
INCLUDES PROBE AND STRAY CAPACITANCE.
V
=
CM
–7V TO +12V
D
V
R
L
OD
3V
0V
V
CC
IN
1.5V
1.5V
375Ω
Figure 8. Driver Differential Output Voltage with
Varying Common-Mode Voltage
tPLH
tPHL
V
V
OH
OL
Y
V
V
V
V
OM
OM
OUT
tPHL
tPLH
R
V
ID
V
V
OH
OL
0
Z
OUT
I
I
OM
OM
V
V
OH
OH
(–)
OL
(+)
OL
Figure 11. Driver Propagation Delays
Figure 9. Receiver Output Voltage High and Output Voltage Low
S1
C
L
OUT
= 110ꢀ
0V OR 3V
D
R
60Ω
=
L
OUT
D
2
= 50pF
R
C
L
L
1
GENERATOR
50Ω
V
1
CC
GENERATOR
50ꢀ
2
C
= 15pF
L
V
+ V
OL
OH
V
=
≈ 1.5V
OM
2
1
2
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
C
INCLUDES PROBE AND STRAY CAPACITANCE.
1
2
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
C
INCLUDES PROBE AND STRAY CAPACITANCE.
+3V
0V
IN
+1.5V
+1.5V
3V
0V
1.5V
1.5V
IN
tDD
90%
tDD
tPZH
tPHZ
≈ +2V
≈ –2V
90%
50%
10%
50%
10%
V
OH
OUT
0.25V
OUT
V
OM
tTD
tTD
0V
Figure 10. Driver Differential Output Delay and Transition Times
Figure 12. Driver Enable and Disable Times (tPZH, tPSH, tPHZ
)
Rev. A | Page 9 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
V
CC
R
= 110ꢀ
L
S1
OUT
OUT
0V OR 3V
D
V
ID
R
1
GENERATOR
2
C
= 50pF
50ꢀ
L
2
C
= 15pF
L
1
GENERATOR
50ꢀ
1.5V
0V
V
CC
V
=
OM
2
1
2
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
1
2
O
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
C
INCLUDES PROBE AND STRAY CAPACITANCE.
C
INCLUDES PROBE AND STRAY CAPACITANCE.
3V
0V
3V
0V
IN
1.5V
1.5V
1.5V
1.5V
IN
tPSL
tPLZ
tRPLH
tRPHL
V
V
CC
OUT
V
V
CC
OM
0.25V
V
V
OM
OUT
OM
OL
0V
Figure 13. Driver Enable and Disable Times (tPZL, tPSL, tPLZ
)
Figure 14. Receiver Propagation Delays
S1
S2
S3
+1.5V
–1.5V
V
CC
1kꢀ
V
ID
R
2
C
L
1
GENERATOR
50ꢀ
1
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
2
C
INCLUDES PROBE AND STRAY CAPACITANCE.
+3V
+3V
0V
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
+1.5V
IN
+1.5V
IN
0V
V
tRPZL
tRPSL
tRPZH
tRPSH
V
OH
CC
OUT
OUT
+1.5V
+1.5V
0V
V
OL
+3V
0V
+3V
0V
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
+1.5V
+1.5V
IN
IN
tRPHZ
tRPLZ
V
V
OH
CC
OL
OUT
OUT
+0.25V
0V
V
+0.25V
Figure 15. Receiver Enable and Disable Times
Rev. A | Page 10 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
TY-ICAL -ꢁRFORMANCꢁ CꢃARACTꢁRIETICE
25
20
15
10
5
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I
= 2.5mA
RO
0
–40
10
60
85
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE (V)
Figure 16. Output Current vs. Receiver Output Low Voltage
Figure 19. Receiver Output Low Voltage vs. Temperature
–18
100
90
80
70
60
50
40
30
20
10
0
–16
–14
–12
–10
–8
–6
–4
–2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT HIGH VOLTAGE (V)
DIFFERENTIAL OUTPUT VOLTAGE (V)
Figure 17. Output Current vs. Receiver Output High Voltage
Figure 20. Driver Output Current vs. Differential Output Voltage
2.6
3.30
3.25
3.20
3.15
3.10
3.05
3.00
R
= 54ꢀ
I
= –1.5mA
L
RO
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
–50
–25
0
25
50
75
–50
–25
0
25
50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Receiver Output High Voltage vs. Temperature
Figure 21. Driver Differential Output Voltage vs. Temperature
Rev. A | Page 11 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
120
100
80
60
40
20
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2
4
6
8
10
12
–50
–25
0
25
50
75
OUTPUT LOW VOLTAGE (V)
TEMPERATURE (°C)
Figure 22. Output Current vs. Driver Output Low Voltage
Figure 25. Shutdown Current vs. Temperature
120
100
80
60
40
20
0
DI
3
Y
Z
CH1
CH2
CH1 1.0V
CH3 2.0V
ꢀ
ꢀ
CH2 1.0V
ꢀ
IT 400ps/pt A CH3
M20ns 1.25GS/s
1.44V
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
OUTPUT HIGH VOLTAGE (V)
Figure 23. Output Current vs. Driver Output High Voltage
Figure 26. ADM3490E/ADM3491E Driver Propagation Delay
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
V
– V
A
B
M1
RO
3
CH3 2.0V
ꢀ
M200ns 250MS/s
4ns/pt
A CH2
1.24V
–40
–10
20
50
80
MATH1 2.01V 200ns
TEMPERATURE (°C)
Figure 24. Supply Current vs. Temperature
Figure 27. ADM3490E/ADM3491E Receiver Propagation Delay,
Driven by External RS-485 Device
Rev. A | Page 12 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
DI
3
V
– V
B
A
Y
Z
1
RO
M
CH1 500mV ꢀ CH2 500mV ꢀ M2.0µs 25.0MS/s 40.0ns/pt
CH3 5.0V ꢀ CH3 2.4V
CH1 2.00V
MATH 2.00V 20.0ms
M20.0ms
A
CH1
40.0mV
A
Figure 28. ADM3483E/ADM3488E Driver Propagation Delay
Figure 29. ADM3483E/ADM3488E Receiver Propagation Delay
Rev. A | Page 13 of 20
ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
CIRCUIT DESCRIPTION
The ADM34xxE are low power transceivers for RS-485 and RS422
Table 12. Receiving Truth Table
communications. The ADM3483E/ADM3488E operate at data
rates up to 250 kbps. The ADM3486E operates at data rates up
to 2.5 Mbps, and the ADM3490E/ADM3491E transmit at up to
12 Mbps. The ADM3488E/ADM3490E/ADM3491E are full-
duplex transceivers, and the ADM3483E/ADM3486E are half
Receiving Input
Receiving Output
A – B
RO
1
≥ +0.2 V
≤ −0.2 V
0
Inputs open
1
RE
duplex. Driver enable (DE) and receiver enable ( ) pins are
included on the ADM3483E/ADM3486E/ADM3491E. When
disabled, the driver and receiver outputs are high impedance.
LOW POWER SHUTDOWN MODE—ADM3483E/
ADM3486E/ADM3491E
DEVICES WITH RECEIVER/DRIVER ENABLE—
ADM3483E/ADM3486E/ADM3491E
The ADM3483E/ADM3486E/ADM3491E are put into a low
RE
power shutdown mode by bringing both
high and DE low.
The devices do not shut down unless both the driver and the
receiver are disabled (high impedance). In shutdown mode, the
devices typically draw less than 1 μA of supply current. For
these devices, the tPSH and the tPSL enable times assume the part
was in the low power shutdown mode; the tPZH and the tPZL
enable times assume the receiver or the driver was disabled, but
the part was not shut down.
Table 9. Transmitting Truth Table
Transmitting Inputs
Transmitting Outputs
A1, Y2
RE
DE
DI
B1, Z2
Mode
X3
X3
0
1
1
0
0
1
0
X3
X3
1
0
0
1
Normal
Normal
Normal
Shutdown
High-Z4
High-Z4
High-Z4
High-Z4
1
DRIVER OUTPUT PROTECTION
1 ADM3483E and ADM3486E only.
2 ADM3491E only.
The ADM34xxE family implements two ways to prevent
excessive output current and power dissipation caused by faults
or by bus contention. A current limit on the output stage
provides immediate protection against short circuits over the
whole common-mode voltage range (see the Typical
Performance Characteristics section). In addition, a thermal
shutdown circuit forces the driver outputs into a high
impedance state if the die temperature rises excessively.
3 X = don’t care.
4 High-Z = high impedance.
Table 10. Receiving Truth Table
Receiving Inputs
RE DE1 DE2 A – B
Receiving Output
RO
Mode
0
0
0
1
0
0
0
0
X3
X3
X3
X3
≥ +0.2 V
≤ −0.2 V
Inputs open
X3
1
0
1
Normal
Normal
Normal
Shutdown
PROPAGATION DELAY
High-Z4
Figure 11, Figure 14, Figure 26, and Figure 27 show the typical
propagation delays. Skew time is simply the difference between
the low-to-high and the high-to-low propagation delays. Small
driver/receiver skew times help maintain a symmetrical mark-
space ratio (50% duty cycle).
1 ADM3483E and ADM3486E only.
2 ADM3491E only.
3 X = don’t care.
4 High-Z = high impedance.
DEVICES WITHOUT RECEIVER/DRIVER ENABLE―
ADM3488E/ADM3490E
The receiver skew time, |tPRHL – tPRHL|, is under 10 ns (20 ns for
the ADM3483E/ADM3488E). The driver skew time is 8 ns for
the ADM3490E/ADM3491E, 12 ns for the ADM3486E, and
typically under 50 ns for the ADM3483E/ADM3488E.
Table 11. Transmitting Truth Table
Transmitting Input
DI
1
0
Transmitting Outputs
Z
0
1
Y
1
0
LINE LENGTH VS. DATA RATE
The RS-485/RS-422 standard covers line lengths up to 4000 feet.
For line lengths greater than 4000 feet, Figure 34 illustrates an
example of a line repeater.
Rev. A | Page 14 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
R1
R2
HIGH
VOLTAGE
GENERATOR
15 kV ESD PROTECTION
DEVICE
UNDER
TEST
Two coupling methods are used for EꢂD testing: con-
tact discharge and air-gap discharge. Contact discharge
calls for a direct connection to the unit being tested. Air-
gap discharge uses a higher test voltage but does not maꢁe
direct contact with the test unit. With air-gap discharge,
the discharge gun is moved toward the unit under test,
developing an arc across the air gap, therefore the term air-
gap discharge. This method is influenced by humidity,
temperature, barometric pressure, distance, and rate of
closure of the discharge gun. The contact discharge
method, while less realistic, is more repeatable and is
gaining acceptance and preference over the air-
gap method.
C1
ESD TEST METHOD
R2
C1
HUMAN BODY MODEL 1.5kꢀ 100pF
ESD ASSOC. STD 55.1
100%
90%
Although very little energy is contained within an EꢂD pulse,
the extremely fast rise time, coupled with high voltages, can
cause failures in unprotected semiconductors. Catastrophic
destruction can occur immediately as a result of arcing or
heating. Even if catastrophic failure does not occur immediately,
the device can suffer from parametric degradation that can
result in degraded performance. The cumulative effects of
continuous exposure can eventually lead to complete failure.
36.8%
10%
TIME
t
tDL
tRL
Figure 30. Human Body Model and Current Waveform
TYPICAL APPLICATIONS
Input/output lines are particularly vulnerable to EꢂD damage.
ꢂimply touching or connecting an input/output cable can result
in a static discharge that can damage or completely destroy the
interface product connected to the input/output port. It is
extremely important, therefore, to have high levels of EꢂD
protection on the input/output lines.
The ADM3483E/ADM3486E/ADM3491E transceivers are
designed for bidirectional data communications on multipoint
bus transmission lines. The ADM3488E/ADM3490E full-duplex
transceiver is designed to be used in a daisy-chain networꢁ
topology or in a point-to-point application (see Figure 32). The
ADM3483E/ADM3486E are half-duplex Rꢂ-48ꢀ transceivers
that can be used in a multidrop bus configuration, as shown in
Figure 31. The ADM3488E/ADM3490E/ADM3491E can also
be used as a line repeater, for use with cable lengths longer than
4000 feet, as shown in Figure 34. To minimize reflections, the
line must be terminated at both ends in its characteristic
impedance, and stub lengths off the main line should be ꢁept as
short as possible.
The EꢂD discharge can induce latch-up in the device under test,
so it is important that EꢂD testing on the input/output pins be
carried out while device power is applied. This type of testing is
more representative of a real-world input/output discharge,
which occurs when the equipment is operating normally.
The transmitter outputs and receiver inputs of the ADM34xxE
family are characterized for protection to a 1ꢀ ꢁV limit using
the human body model.
HUMAN BODY MODEL
Figure 30 shows the human body model and the current wave-
form it generates when discharged into a low impedance. This
model consists of a 100 pF capacitor charged to the EꢂD voltage
of interest, which is then discharged into the test device
through a 1.ꢀ ꢁΩ resistor.
Rev. A | Page 15 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
ADM3483E/
ADM3486E
ADM3483E/
ADM3486E
R
R
RO
RO
A
A
B
RE
RE
DE
DI
R
R
T
T
DE
DI
B
D
D
A
B
A
B
ADM3483E/
ADM3486E
ADM3483E/
ADM3486E
R
R
D
D
RO RE DE DI
RO RE DE DI
NOTES
1. MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 32.
2. R IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
T
Figure 31. ADM3483E/ADM3486E Typical Half-Duplex RS-485 Network
MASTER
SLAVE
ADM3488E/
ADM3490E
ADM3488E/
ADM3490E
A
Y
DI
R
D
RO
DI
B
Z
Z
B
D
R
RO
Y
A
Figure 32. ADM3488E/ADM3490E Full-Duplex Point-to-Point Applications
Rev. A | Page 16 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
MASTER
SLAVE
ADM3491E
ADM3491E
DE
A
B
Y
Z
R
R
D
T
RO
RE
DE
DI
DI
B
Z
Y
D
R
R
RO
RE
T
A
A
B
R
A
B
R
Y
Y
Z
Z
SLAVE
SLAVE
D
D
ADM3491E
ADM3491E
RO RE DE DI
RO RE DE DI
NOTES
1. MAXIMUM NUMBER OF NODES: 32.
2. R IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
T
Figure 33. ADM3491E Full-Duplex RS-485 Network
ADM3488E/
ADM3490E/
ADM3491E
A
RO
RE
R
R
DATA IN
R
T
B
DE
DI
Z
Y
D
DATA OUT
T
NOTES
1. R IS EQUAL TO THE CHARACTERISTIC
T
IMPEDANCE OF THE CABLE USED.
2. RE AND DE PINS ON ADM3491E ONLY.
Figure 34. Line Repeater for ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 17 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
OUTLINꢁ SIMꢁNEIONE
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 35. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 36. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Temperature
Range
Model
ADM3483EARZ1
Package Description
Package Option Ordering Quantity
–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N)
R-8
ADM3483EARZ-REEL71 –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N)
R-8
R-8
R-8
R-8
R-8
R-8
R-8
1,000
1,000
1,000
1,000
1,000
ADM3486EARZ1
ADM3486EARZ-REEL71 –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N)
ADM3488EARZ1
–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N)
ADM3488EARZ-REEL71 –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N)
ADM3490EARZ1
–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N)
ADM3490EARZ-REEL71 –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N)
–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N)
ADM3491EARZ1
–40°C to +85°C 14-Lead Standard Small Outline Package (SOIC_N) R-14
ADM3491EARZ-REEL71 –40°C to +85°C 14-Lead Standard Small Outline Package (SOIC_N) R-14
1 Z = Pb-free part.
Rev. A | Page 18 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
NOTꢁE
Rev. A | Page 19 of 20
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ
NOTꢁE
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06284-0-10/06(A)
Rev. A | Page 20 of 20
相关型号：
©2020 ICPDF网 联系我们和版权申明