ADM7151ARDZ-04 [ADI]
800 mA Ultralow Noise, High PSRR, RF Linear Regulator;
| 型号： | ADM7151ARDZ-04 |
| 厂家： | 
ADI |
| 描述： | 800 mA Ultralow Noise, High PSRR, RF Linear Regulator 光电二极管 输出元件 调节器 |
| 文件： | 总25页 (文件大小：1178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
800 mA Ultralow Noise,
High PSRR, RF Linear Regulator
ADM7151
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
ADM7151-04
Input voltage range: 4.5 V to 16 V
Maximum output current: 800 mA
Adjustable output from 1.5 V to 5.1 V
Low noise
V
= 6.2V
V
= 5.0V
IN
OUT
VIN
VOUT
REF
C
10µF
C
OUT
10µF
IN
ON
EN
C
1µF
REF
OFF
V
1.0 μV rms total integrated noise from 100 Hz to 100 kHz
1.6 μV rms total integrated noise from 10 Hz to 100 kHz
Noise spectral density: 1.7 nV√Hz from 10 kHz to 1 MHz
Power supply rejection ratio (PSRR) at 400 mA load
>90 dB from 1 kHz to 100 kHz, VOUT = 5 V
>60 dB at 1 MHz, VOUT = 5 V
BYP
BYP
C
BYP
1µF
R1
V
= 1.5V × (R1 + R2)/R2
OUT
REF_SENSE
GND
R2
1kΩ < R2 < 200kΩ
V
REG
VREG
C
REG
10µF
Dropout voltage: 0.6 V at VOUT = 5 V, 800 mA load
Initial voltage accuracy: 1ꢀ
Figure 1. ADM7151-04 with VOUT = 5 V
Voltage accuracy over line, load and temperature: 2ꢀ
Quiescent current (IGND): 4.3 mA at no load
Low shutdown current: 0.1 μA
Stable with a 10 μF ceramic output capacitor
8-lead LFCSP package and 8-lead SOIC package
APPLICATIONS
Regulated power noise sensitive applications
RF mixers, phase-locked loops (PLLs), voltage-controlled
oscillators (VCOs), and PLLs with integrated VCOs
Clock distribution circuits
Ultrasound and other imaging applications
High speed RF transceivers
High speed, 16-bit or greater ADCs
Communications and infrastructure
Cable digital-to-analog converter (DAC) drivers
but also providing excellent thermal performance for applications
requiring up to 800 mA of output current in a small, low profile
footprint.
GENERAL DESCRIPTION
The ADM7151 is a low dropout (LDO) linear regulator that
operates from 4.5 V to 16 V and provides up to 800 mA of output
current. Using an advanced proprietary architecture, it provides
high power supply rejection (>90 dB from 1 kHz to 1 MHz),
ultralow noise (1.7 nV√Hz from 10 kHz to 1 MHz), and excellent
line and load transient response with a 10 μF ceramic output
capacitor. The output voltage can be set to any voltage between
1.5 V and 5.1 V with two resistors.
100k
C
C
C
C
= 1µF
BYP
BYP
BYP
BYP
= 10µF
= 100µF
= 1mF
10k
1k
The ADM7151 is available in two models that optimize power
dissipation and PSRR performance as a function of input and
output voltage. See Table 6 and Table 7 for selection guides.
100
10
The ADM7151 regulator output noise is 1.0 μV rms from
100 Hz to 100 kHz, and the noise spectral density is 1.7 nV/√Hz
from 10 kHz to 1 MHz.
1
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
The ADM7151 is available in 8-lead, 3 mm × 3 mm LFCSP and
8-lead SOIC packages, making it not only a very compact solution,
Figure 2. Noise Spectral Density (NSD) vs. Frequency for Various CBYP
Rev. A
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ADM7151
Data Sheet
TABLE OF CONTENTS
Features........................................................................................... 1
Theory of Operation.................................................................... 15
Applications Information............................................................ 16
Model Selection....................................................................... 16
Capacitor Selection.................................................................. 16
Enable (EN) and Undervoltage Lockout (UVLO) ................ 18
Start-Up Time.......................................................................... 19
REF, BYP, and VREG Pins....................................................... 19
Current-Limit and Thermal Overload Protection................ 19
Thermal Considerations......................................................... 19
Printed Circuit Board Layout Considerations....................... 22
Outline Dimensions.................................................................... 23
Ordering Guide........................................................................ 24
Applications................................................................................... 1
Typical Application Circuit........................................................... 1
General Description...................................................................... 1
Revision History............................................................................ 2
Specifications................................................................................. 3
Input and Output Capacitor, Recommended Specifications.. 4
Absolute Maximum Ratings......................................................... 5
ThermalData............................................................................. 5
Thermal Resistance................................................................... 5
ESD Cautio n............................................................................... 5
Pin Configurations and Function Descriptions .......................... 6
Typical Performance Characteristics............................................ 7
REVISION HISTORY
4/15—Rev. 0 to Rev. A
Change to Figure 4..........................................................................6
Change to Figure 39......................................................................12
9/13—Revision0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADM7151
SPECIFICATIONS
VIN = 4.5 V, VOUT = 1.5 V, V REF = VREF_SENSE (unity gain), VEN = VIN, IOUT = 10 mA, CIN = COUT = CREG = 10 µF, CREF = CBYP = 1 µF. TA = 25°C
for typicalspecifications. TJ = −40°C to +125°C for minimum/maximum specifications,unless otherwise noted.
Table 1.
Parameter
Symbol
VIN
Test Conditions/Comments
Min
Typ Max
Unit
V
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
4.5
16
IGND
IOUT = 0 µA
IOUT = 800 mA
4.3
8.6
0.1
1.6
1.0
1.7
7.0
12
3
mA
mA
SHUTDOWN CURRENT
OUTPUT NOISE
IIN-SD
VEN = GND
µA
OUTNOISE
10 Hz to 100 kHz, independent of output voltage
100 Hz to 100 kHz, independent ofoutput voltage
10 kHz to 1 MHz, independent of output voltage
µV rms
µV rms
nV/√Hz
NOISE SPECTRAL DENSITY
POWER SUPPLY REJECTION RATIO
ADM7151-04
NSD
PSRR
1 kHz to 100 kHz, VIN = 6.2 V, VOUT = 5 V at 800 mA
1 MHz, VIN = 6.2 V, VOUT = 5 V at 800 mA
1 kHz to 100 kHz, VIN = 6.2 V, VOUT = 5 V at 400 mA
1 MHz, VIN = 6.2 V, VOUT = 5 V at 400 mA
1 kHz to 100 kHz, VIN = 5.2 V, VOUT = 4 V at 800 mA
1 MHz, VIN = 5.2 V, VOUT = 4 V at 800 mA
1 kHz to 100 kHz, VIN = 5.2 V, VOUT = 4 V at 400 mA
1 MHz, VIN = 5.2 V, VOUT = 4 V at 400 mA
VOUT = VREF
84
53
94
67
91
50
94
58
dB
dB
dB
dB
dB
dB
dB
dB
ADM7151-02
VOUT VOLTAGE ACCURACY
Voltage Accuracy
VOUT
IOUT = 10 mA
1 mA < IOUT < 800 mA, over line, load and
temperature
−1
−2
+1
+2
%
%
VOUT REG U L ATION
Line Regulation
ΔVOUT/ΔVIN
ΔVOUT/ΔIOUT
ILIMIT
VIN = 4.5 V to 16 V
IOUT = 1 mA to 800 mA
−0.01
1.0
+0.01 %/V
Load Regulation1
0.5
1.0
%/A
CURRENT-LIMIT THRESHOLD
VREF Current Limit Threshold
VOUT Current Limit Threshold2
DROPOUT VOLTAGE3
20
mA
A
1.3
1.6
VDROPOUT
IOUT = 400 mA, VOUT = 5 V
IOUT = 800 mA, VOUT = 5 V
0.30 0.60
0.60 1.20
V
V
PULL-DOWN RESISTANCE
VOUT Pull-Down Resistance
VREG Pull-Down Resistance
VREF Pull-Down Resistance
VBYP Pull-Down Resistance
START-UP TIME4
VOUT-PULL
VREG -PULL
VREF-PULL
VBYP-PULL
VEN = 0 V, VOUT = 1 V
VEN = 0 V, VREG = 1 V
VEN = 0 V, VREF = 1 V
VEN = 0 V, VBYP = 1 V
VOUT = 5 V
600
34
800
500
Ω
kΩ
Ω
Ω
VOUT Start-Up Time
VREG Start-Up Time
VREF Start-Up Time
tS TA R T -UP
tREG -S TA R T -UP
tREF-S TA R T -UP
2.8
1.0
1.8
ms
ms
ms
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
UNDERVOLTAGE THRESHOLDS
Input Voltage Rising
TSSD
TJ rising
155
15
°C
°C
TSSD-HYS
UVLORISE
UVLOFA L L
UVLOHYS
TJ = −40°C to +125°C
TJ = −40°C to +125°C
4.49
240
V
V
mV
Input Voltage Falling
Hysteresis
3.85
Rev. A | Page 3 of 24
ADM7151
Data Sheet
Parameter
VREG 5 UNDERVOLTAGETHRESHOLDS
VREG Rise
Symbol
Test Conditions/Comments
Min
2.55
3.2
Typ Max
Unit
VREGUVLORISE TJ = −40°C to +125°C
3.1
V
VREG Fall
Hysteresis
VREGUVLOFA L L TJ = −40°C to +125°C
V
mV
VREGUVLOHYS
4.5 V ≤ VIN ≤ 16 V
ENHIGH
ENLOW
ENHYS
IEN-LKG
210
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Logic Hysteresis
EN Input Leakage Current
V
V
mV
µA
0.8
1.0
VIN = 5 V
225
0.1
VEN = VIN or GND
1 Based on an end-point calculation using 1 mA and 800 mA loads. See Figure 6 and Figure 13 for typical load regulation performance for loads less than 1 mA.
2 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V.
3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to achieve the nominal output voltage. Dropout applies only for
output voltages above 4.5 V.
4 Start-up time is defined as the time between the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value.
5 The output voltage is turned off until the VREG UVLO rise threshold is crossed. The VREG output is turned off until the input voltage UVLO rising threshold is crossed.
INPUT AND OUTPUT CAPACITOR, RECOMMENDEDSPECIFICATIONS
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
CAPACITANCE
Minimum Input1
TA = −40°C to +125°C
CIN
7.0
7.0
7.0
0.1
0.7
µF
µF
µF
µF
µF
Minimum Regulator1
Minimum Output1
Minimum Bypass
Minimum Reference
CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR)
CREG , COUT, CIN, CREF
CREG
COUT
CBYP
CREF
RESR
TA = −40°C to +125°C
0.001
0.001
0.2
2.0
Ω
Ω
CBYP
1 The minimum input, regulator, and output capacitance must be greater than 7.0 µF over the full range of operating conditions. The full range of operating conditions
in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are
recommended; however, Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. A | Page 4 of 24
Data Sheet
ADM7151
ABSOLUTEMAXIMUM RATINGS
Junction to ambient thermalresistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction to ambient thermalresistanceis highly dependent on
the applicationandboardlayout. In applicationswhere high
maximumpower dissipation exists, close attention to thermal
board design is required. The value of θJA mayvary, depending on
PCB material, layout, and environmental conditions.The specified
values of θJA are based on a 4-layer, 4in. × 3 in. circuit board.
See JESD51-7 and JESD51-9for detailed information on the
board construction.
Table 3.
Parameter
VIN to GND
VREG to GND
Rating
−0.3 V to +18 V
−0.3 V to VIN, or +6 V
(whichever is less)
−0.3 V to VREG, or +6 V
(whichever is less)
VOUT to GND
VOUT to BYP
EN to GND
0.3 V
−0.3 V to18 V
−0.3 V to VREG, or +6 V
(whichever is less)
BYP to GND
ΨJB is the junction to board thermalcharacterization parameter
with units of°C/W. ΨJB of the package is basedon modelingandthe
calculation using a 4-layer board. TheJESD51-12, Guidelines for
Reportingand UsingElectronic Package Thermal Information,
states that thermalcharacterization parameters arenot the same
as thermalresistances. ΨJB measures the component power
flowing through multiple thermalpathsrather than a single
path as in thermalresistance (θJB). Therefore, ΨJB thermalpaths
include convection from the top of the package as wellas
radiation from the package, factorsthat makeΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the boardtemperature(TB) and power
dissipation (PD) using the formula
−0.3 V to VREG, or +6 V
(whichever is less)
REF to GND
REF_SENSE to GND
Storage Temperature Range
Junction Temperature
−0.3 V to +6 V
−65°C to +150°C
150°C
Operating AmbientTemperatureRange –40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damageto the product. This is a
stress rating only; functionaloperation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditionsfor extended periods may
affect product reliability.
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12for more detailedinformation
about ΨJB.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADM7151 can be damaged when the junction
temperature limits are exceeded.Monitoring ambient temperature
does not guarantee thatTJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermalresistance, the maximumambient temperaturemay
have to be derated.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst-caseconditions, that
is, a device soldered in a circuitboardfor surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
θJC
ΨJB
Unit
8-Lead LFCSP
8-Lead SOIC
36.7
36.9
23.5
27.1
13.3
18.6
°C/W
°C/W
In applications with moderate power dissipation and low
printed circuit board (PCB)thermalresistance, the maximum
ambient temperaturecan exceed the maximumlimit as long as
the junction temperature is within specification limits. The
junction temperature(TJ)of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction toambient thermalresistance of the
package (θJA).
ESD CAUTION
Maximum junction temperature (TJ) is calculated from the
ambient temperature(TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
Rev. A | Page 5 of 24
ADM7151
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VREG
VOUT
BYP
1
2
3
4
8
7
6
5
VIN
EN
VREG
VOUT
BYP
1
2
3
4
8
7
6
5
VIN
ADM7151
EN
TOP VIEW
ADM7151
REF
(Not to Scale)
TOP VIEW
REF
GND
REF_SENSE
(Not to Scale)
GND
REF_SENSE
NOTES
NOTES
1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE.
EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS
ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.
CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON
THE BOARD TO ENSURE PROPER OPERATION.
1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE.
EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS
ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.
CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON
THE BOARD TO ENSURE PROPER OPERATION.
Figure 4. 8-Lead SOIC Pin Configuration
Figure 3. 8-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
VREG
Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 10 μF or greater capacitor. Do not connect a
load to ground.
2
3
4
5
6
VOUT
BYP
GND
Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor.
Low Noise Bypass Capacitor. Connect a 1 μF capacitor to GND to reduce noise. Do not connect a load to ground.
Ground Connection.
REF_SENSE External Resistor Divider Used to Set the Output Voltage. VOUT = VREF × (R1 + R2)/R2, where VREF = 1.5 V.
REF
Low Noise Reference Voltage Output. Bypass REF to GND with a 1 μF capacitor. Short REF_SENSE to REF for fixed
output voltages. Do not connect a load to ground.
7
EN
Enable. Drive EN high to turn on the regulator and drive EN low to turn off the regulator. For automatic startup,
connect EN to VIN.
8
EP
VIN
EP
Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor.
Exposed Pad on the Bottom of the Package. Exposed pad enhances thermal performance and is electrically
connected to GND inside the package. Connect the exposed pad to the ground plane on the board to ensure
proper operation.
Rev. A | Page 6 of 24
Data Sheet
ADM7151
TYPICAL PERFORMANCECHARACTERISTICS
VIN = VOUT + 1.2 V or VIN = 4.5 V, whichever is greater, EN = VIN, IOUT = 10 mA, CIN = COUT = CREG = 10 µF, CREF = CBYP = 1 µF, TA = 25°C,
unless otherwise noted.
4.04
4.03
4.02
4.01
4.00
3.99
3.98
3.97
3.96
10
9
8
7
6
5
4
3
2
1
0
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
–40
–5
25
85
125
–40
–5
25
85
125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 5. Output Voltage (VOUT) vs. Junction Temperature (TJ), ADM7151-02,
VOUT = 4 V
Figure 8. Ground Current vs. Junction Temperature (TJ), ADM7151-02,
VOUT = 4 V
4.04
4.03
4.02
4.01
4.00
3.99
3.98
3.97
3.96
10
9
8
7
6
5
4
3
2
1
0
1
10
100
1000
1
10
100
1000
I
(mA)
I
(mA)
LOAD
LOAD
Figure 6. Output Voltage (VOUT) vs. Load Current (ILOAD), ADM7151-02,
VOUT = 4 V
Figure 9. Ground Current vs. Load Current (ILOAD), ADM7151-02, VOUT = 4 V
4.04
10
9
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
4.03
4.02
4.01
4.00
3.99
3.98
3.97
3.96
8
7
6
5
4
3
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
2
1
0
5
6
7
8
9
10
11
(V)
12
13
14
15
16
5
6
7
8
9
10
11
(V)
12
13
14
15
16
V
V
IN
IN
Figure 7. Output Voltage (VOUT) vs. Input Voltage (VIN), ADM7151-02,
VOUT = 4 V
Figure 10. Ground Current vs. Input Voltage (VIN), ADM7151-02, VOUT = 4 V
Rev. A | Page 7 of 24
ADM7151
Data Sheet
10
5.00
4.99
4.98
4.97
4.96
4.95
4.94
4.93
4.92
4.91
4.90
V
V
V
V
V
= 6.2V
= 6.5V
= 7.0V
= 10V
= 16V
IN
IN
IN
IN
IN
1
0.1
0.01
0.001
0.0001
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
–40
–5
25
85
125
6
8
10
12
14
16
TEMPERATURE (°C)
V
(V)
IN
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
Figure 14. Output Voltage (VOUT) vs. Input Voltage (VIN), ADM7151-04,
VOUT = 5 V
5.00
4.99
4.98
4.97
4.96
4.95
4.94
10
9
8
7
6
5
4
4.93
3
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
4.92
2
4.91
1
4.90
0
–40
–5
25
85
125
–40
–5
25
85
125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 12. Output Voltage (VOUT) vs. JunctionTemperature (TJ), ADM7151-04,
VOUT = 5 V
Figure 15. Ground Current vs. Junction Temperature (TJ), ADM7151-04,
VOUT = 5 V
5.00
4.99
4.98
4.97
4.96
4.95
4.94
4.93
4.92
4.91
4.90
10
9
8
7
6
5
4
3
2
1
0
1
10
100
1000
1
10
100
1000
I
(mA)
I
(mA)
LOAD
LOAD
Figure 13. Output Voltage (VOUT) vs. Load Current (ILOAD), ADM7151-04,
VOUT = 5 V
Figure 16. Ground Current vs. Load Current (ILOAD), ADM7151-04,
VOUT = 5 V
Rev. A | Page 8 of 24
Data Sheet
ADM7151
10
12
10
8
9
8
7
6
5
6
4
4
LOAD = 1mA
3
2
1
0
I
I
I
I
I
I
= 5mA
GND
GND
GND
GND
GND
GND
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
= 10mA
= 100mA
= 200mA
= 400mA
= 800mA
2
0
6
8
10
12
14
16
4.6
4.8
5.0
5.2
5.4
(V)
5.6
5.8
6.0
V
(V)
V
IN
IN
Figure 17. Ground Current vs. Input Voltage (VIN), ADM7151-04, VOUT = 5 V
Figure 20. Ground Current vs. Input Voltage (VIN) in Dropout, ADM7151-04,
VOUT = 5 V
0
700
600
500
400
300
200
100
0
LOAD = 800mA
–10
–20
LOAD = 400mA
LOAD = 200mA
LOAD = 100mA
LOAD = 10mA
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
1
10
100
1k
10k
100k
1M
10M
1
10
100
1000
FREQUENCY (Hz)
I
(mA)
LOAD
Figure 18. Dropout Voltage vs. Load Current (ILOAD), ADM7151-04, VOUT = 5 V
Figure 21. Power Supply RejectionRatio (PSRR) vs. Frequency, ADM7151-02,
VOUT = 4 V
5.2
5.0
4.8
4.6
4.4
0
LOAD = 800mA
–10
–20
LOAD = 400mA
LOAD = 200mA
LOAD = 100mA
LOAD = 10mA
–30
–40
–50
–60
–70
–80
V
V
V
V
V
V
= 5mA
DROPOUT
DROPOUT
DROPOUT
DROPOUT
DROPOUT
DROPOUT
= 10mA
= 100mA
= 200mA
= 400mA
= 800mA
–90
4.2
4.0
–100
–110
–120
4.6
4.8
5.0
5.2
5.4
(V)
5.6
5.8
6.0
1
10
100
1k
10k
100k
1M
10M
V
IN
FREQUENCY (Hz)
Figure 19. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,
ADM7151-04, VOUT = 5 V
Figure 22. Power Supply RejectionRatio (PSRR) vs. Frequency, ADM7151-04,
VOUT = 5 V
Rev. A | Page 9 of 24
ADM7151
Data Sheet
0
0
–20
600mV
1.0V
1.1V
1.2V
1.3V
1.4V
10Hz
100Hz
1kHz
100kHz
1MHz
10MHz
–10
–20
700mV
800mV
900mV
10kHz
–30
–40
–40
–50
–60
–60
–70
–80
–80
–90
–100
–110
–120
–100
–120
1
10
100
1k
10k
100k
1M
10M
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
FREQUENCY (Hz)
HEADROOM (V)
Figure 23. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various
Headroom Voltages, ADM7151-02, VOUT = 4 V, 400 mA Load
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
ADM7151-02, VOUT = 4 V, 400 mA Load
0
0
–20
–40
–60
600mV
700mV
800mV
900mV
1.0V
1.1V
1.2V
1.4V
1.6V
1.8V
–10
–20
–30
–40
–50
–60
–70
–80
–80
10Hz
100Hz
1kHz
–90
–100
–110
–120
10kHz
100kHz
1MHz
–100
10MHz
–120
1
10
100
1k
10k
100k
1M
10M
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
FREQUENCY (Hz)
HEADROOM (V)
Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various
Headroom Voltages, ADM7151-04, VOUT = 5 V, 400 mA Load
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
ADM7151-02, VOUT = 4 V, 800 mA Load
0
0
–20
–40
–60
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
–20
–40
10MHz
–60
–80
–80
10Hz
–100
–120
–140
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
–100
–120
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
0.3
0.5
0.7
0.9
1.1
1.3
1.5
HEADROOM (V)
HEADROOM (V)
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
ADM7151-02, VOUT = 4 V, 100 mA Load
Figure 28. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
ADM7151-04, VOUT = 5 V, 100 mA Load
Rev. A | Page 10 of 24
Data Sheet
ADM7151
0
2.0
1.6
1.2
0.8
0.4
0
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
–20
10MHz
–40
100Hz TO 100kHz
–60
–80
–100
–120
0.6
0.8
1.0
1.2
1.4
1.6
1.8
10
100
1000
HEADROOM (V)
LOAD CURRENT (mA)
Figure 29. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
ADM7151-04, VOUT = 5 V, 400 mA Load
Figure 32. RMS Output Noise vs. Load Current (ILOAD), 100 Hz to 100 kHz,
ADM7151-04, VOUT = 5 V
0
2.0
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
–20
–40
10MHz
1.6
10Hz TO 100kHz
1.2
0.8
0.4
0
–60
–80
–100
–120
0.7
0.9
1.1
1.3
1.5
1.7
10
100
1000
HEADROOM (V)
LOAD CURRENT (mA)
Figure 30. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
ADM7151-04, VOUT = 5 V, 800 mA Load
Figure 33. RMS Output Noise vs. Load Current (ILOAD), 10 Hz to 100 kHz,
ADM7151-02, VOUT = 4 V
2.0
2.0
1.6
1.2
1.6
10Hz TO 100kHz
1.2
0.8
0.4
0
100Hz TO 100kHz
0.8
0.4
0
10
100
1000
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 31. RMS Output Noise vs. Load Current (ILOAD), 10 Hz to 100 kHz,
ADM7151-04, VOUT = 5 V
Figure 34. RMS Output Noise vs. Load Current (ILOAD), 100 Hz to 100 kHz,
ADM7151-02, VOUT = 4 V
Rev. A | Page 11 of 24
ADM7151
Data Sheet
10
100k
10k
1k
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
1
100
10
0.1
1k
1
0.1
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 35. Output Noise Spectral Density, 1 kHz to 10 MHz, ILOAD = 10 mA
Figure 38. Output Noise Spectral Density at Different Load Currents,
0.1 Hz to 1 MHz
100k
100k
C
C
C
C
C
C
C
= 1µF
BYP
BYP
BYP
BYP
BYP
BYP
BYP
= 4.7µF
= 10µF
= 22µF
= 47µF
= 100µF
= 470µF
10k
1k
10k
1k
100
10
1
100
10
1
0.1
1
10
100
1k
10k
100k
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 36. Output Noise Spectral Density, 0.1 Hz to 10 kHz, ILOAD = 10 mA
Figure 39. Output Noise Spectral Density vs. at Different CBYP
,
Load Current = 10 mA
1k
T
LOAD = 800mA
LOAD = 400mA
LOAD = 200mA
LOAD = 100mA
LOAD = 10mA
100
1
2
10
1
0.1
10
B
B
W
CH1 500mA Ω
CH2 20mV
M20µs
A
CH1
200mA
W
100
1k
10k
100k
1M
10M
T
10.40%
FREQUENCY (Hz)
Figure 37. Output Noise Spectral Density at Different Load Currents,
10 Hz to 10 MHz
Figure 40. Load Transient Response, ILOAD = 1 mA to 800 mA,
OUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT
V
Rev. A | Page 12 of 24
Data Sheet
ADM7151
T
T
1
1
2
2
B
B
W
B
B
CH1 1.0V
CH2 2.0mV Ω
M10µs
10.0%
A
CH1
1.14V
CH1 500mA Ω
CH2 10mV
M4µs
W
A
CH1
200mA
W
W
T
T
11.0%
Figure 44. Line Transient Response, 2 V Input Step, ILOAD = 800 mA,
VOUT = 1.8 V, VIN = 4.5 V, CH1 = VIN, CH2 = VOUT
Figure 41. Load Transient Response, ILOAD = 10 mA to 800 mA,
VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT
T
T
1
1
2
2
B
B
W
B
B
CH1 1.0V
CH2 2.0mV Ω
M10µs
10.0%
A
CH3
1.14V
CH1 200mA Ω
CH2 10mV
M2µs
W
A
CH1
460mA
W
W
T
T
11.0%
Figure 45. Line Transient Response, 2 V Input Step, ILOAD = 800 mA,
VOUT = 3.3 V, VIN = 4.5 V, CH1 = VIN, CH2 = VOUT
Figure 42. Load Transient Response, ILOAD = 100 mA to 600 mA,
VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT
T
T
1
1
2
2
B
B
W
B
B
CH1 1.0V
CH2 2.0mV Ω
M10µs
10.0%
A
CH3
1.14V
CH1 50.0mA Ω
CH2 2.0mV
M4µs
W
A
CH1
50.0mA
W
W
T
T
10.0%
Figure 46. Line Transient Response, 2 V Input Step, ILOAD = 800 mA,
VOUT = 5 V, VIN = 6.2 V, CH1 = VIN, CH2 = VOUT
Figure 43. Load Transient Response, ILOAD = 1 mA to 100 mA,
VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT
Rev. A | Page 13 of 24
ADM7151
Data Sheet
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
V
V
EN
REG
REF
OUT
–0.5
0
1
2
3
4
5
6
7
8
9
10
TIME (ms)
Figure 47. VOUT, VREF, VREG Start-Up Times After VEN Rising,
VOUT = 3.3 V, VIN = 5 V
Rev. A | Page 14 of 24
Data Sheet
ADM7151
THEORY OF OPERATION
ADM7151-04
The ADM7151 is an adjustable, ultralow noise, high power
supply rejection ratio (PSRR) linear regulator targeting radio
frequency (RF) applications. The input voltage range is 4.5 V to
16 V, and it can deliver up to 800 mA of output current. Typical
shutdown current consumption is 0.1 μA at room temperature.
V
= 6.2V
ON
V
= 5.0V
IN
OUT
VIN
VOUT
C
10µF
C
OUT
10µF
IN
EN
REF
C
1µF
REF
OFF
V
BYP
BYP
C
BYP
1µF
Optimized for use with 10 μF ceramic capacitors, the ADM7151
provides excellent transient performance.
R1
V
= 1.5V × (R1 + R2)/R2
OUT
REF_SENSE
GND
R2
1kΩ < R2 < 200kΩ
V
REG
VREG
ACTIVE
RIPPLE
FILTER
C
10µF
REG
VIN
VOUT
SHORT CIRCUIT,
THERMAL
Figure 49. Typical Adjustable Output Voltage Application Schematic
VREG
BYP
PROTECT
GND
The R2 value must be greater than 1 kΩ to prevent excessive
loading of the reference voltage appearing on the REF pin. To
minimize errors in the output voltage caused by the REF_SENSE
pin input current, the R2 value must be less than 200 kΩ. For
example, when R1 and R2 each equal 200 kΩ, the output
voltage is 3.0 V. The output voltage error introduced by the
REF_SENSE pin input current is 10 mV or 0.33%, assuming a
maximum REF_SENSE pin input current of 100 nA at 125°C.
OTA
REFERENCE
E/A
REF_SENSE
REF
SHUTDOWN
EN
Figure 48. Adjustable Output Voltage Internal Block Diagram
Internally, the ADM7151 consists of a reference, an error amplifier,
a feedback voltage divider, and a P-channel MOSFET pass
transistor. Output current is delivered via the PMOS pass
device, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. If the
feedback voltage is lower than the reference voltage, the gate
of the PMOS device is pulled lower, allowing more current to
pass and increasing the output voltage. If the feedback voltage
is higher than the reference voltage, the gate of the PMOS
device is pulled higher, allowing less current to pass and
decreasing the output voltage.
The ADM7151 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. When EN is high, VOUT
turns on, and when EN is low, VOUT turns off. For automatic
startup, EN can be tied to VIN.
VIN
18V
VREG
6V
REF
REF_SENSE
BYP
6V
6V
OUT
By heavily filtering the reference voltage, the ADM7151 is able
to achieve 1.7 nV/√Hz output typical from 10 kHz to 1 MHz.
Because the error amplifier is always in unity gain, the output
noise is independent of the output voltage.
EN
18V
6V
6V
6V
6V
6V
18V
GND
To maintain very high PSRR over a wide frequency range, the
ADM7151 architecture uses an internal active ripple filter. This
stage isolates the low output noise LDO from noise on VIN.
The result is that the ADM7151 PSRR is significantly higher
over a wider frequency range than any single stage LDO.
Figure 50. Simplified ESD Protection Block Diagram
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 50).
The ADM7151 output voltage can be adjusted between 1.5 V
and 5.1 V and is available in two models that optimize the input
voltage and output voltage ranges to keep power dissipation as
low as possible without compromising PSRR performance. The
output voltage is determined by an external voltage divider
according to the following equation:
V
OUT = 1.5 V × (1 + R1/R2)
Rev. A | Page 15 of 24
ADM7151
Data Sheet
APPLICATIONS INFORMATION
MODEL SELECTION
Input and VREG Capacitor
Connecting a 10 μF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance are encountered.
The ADM7151 is available in two models to allow the user to
select the best combination of power dissipation and PSRR
performance for a given application.
To maintain the best possible stability and PSRR performance,
connect a 10 μF capacitor from VREG to GND. When more
than 10 μF of output capacitance is required, increase the input
and VREG capacitors to match it.
CAPACITOR SELECTION
Output Capacitor
The ADM7151 is designed for operation with ceramic capacitors
but functions with most commonly used capacitors as long as
care is taken with regard to the effective series resistance (ESR)
value. The ESR of the output capacitor affects the stability of the
LDO control loop. A minimum of 10 μF capacitance with an
ESR of 0.2 Ω or less is recommended to ensure the stability of
the ADM7151. Output capacitance also affects transient
response to changes in load current. Using a larger value of
output capacitance improves the transient response of the
ADM7151 to large changes in load current. Figure 51 shows the
transient responses for an output capacitance value of 10 μF.
REF Capacitor
The REF capacitor is necessary to stabilize the reference amplifier.
Connect a capacitor of at least 1 μF between REF and GND.
T
1
2
B
B
CH1 500mA Ω
CH2 10mV
M4µs
11.0%
A
CH1
200mA
W
W
T
Figure 51. Output Transient Response, VOUT = 5 V, COUT = 10 μF
Table 6. Model Selection Guide for PSRR
PSRR (dB) at 800 mA, 1.2 V Headroom
PSRR (dB) at 400 mA, 1 V Headroom
Model
VOUT Range (V)
1.5 to 4.0
1.5 to 5.1
10 kHz
91
84
100 kHz
91
84
1 MHz
50
53
10 kHz
94
94
100 kHz
94
94
1 MHz
58
67
ADM7151-02
ADM7151-04
Table 7. Model Selection Guide for Input Voltage
Minimum VIN at 800 mA Load
VOUT Range (V) VOUT < 3.3 V VOUT < 5 V VOUT ≥ 3.3 V VOUT ≥ 5 V
Minimum VIN at 400 mA Load
Model
VOUT < 3.3 V VOUT < 5V VOUT ≥ 3.3 V VOUT ≥ 5 V
ADM7151-02 1.5 to 4.0
ADM7151-04 1.5 to 5.1
4.5 V
N/A1
N/A1
VOUT + 1.2 V
N/A1
N/A1
VOUT + 1.2 V N/A1
4.5 V
N/A1
6 V
VOUT + 1.0 V
N/A1
N/A1
VOUT + 1.0 V
6.2 V
1 N/A = not applicable.
Rev. A | Page 16 of 24
Data Sheet
ADM7151
X5R or X7R dielectrics with a voltage rating of 6.3 V to 50 V
BYP Capacitor
are recommended.However, Y5V and Z5U dielectrics are not
recommendeddue to their poortemperatureand dcbias
characteristics.
The BYPcapacitor is necessary to filter the reference buffer. A
1 µF capacitor is typically connected between BYPand GND.
Capacitors as smallas 0.1µF can be used; however, the output
noise voltage of the LDO increases as a result.
Figure 54 depicts the capacitance vs. dc bias voltage of a 1206,
10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is
strongly influenced by the capacitor size and voltagerating.In
general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperaturevariationof the X5R
dielectric is ~ 15% over the −40°C to +85°C temperaturerange
and is not a function of package or voltage rating.
12
In addition, the BYP capacitor can be increased to reduce the
noise below 1kHzat the expense of increasing the start-up time
of the LDO. Very large values of CBYP significantly reduce the
noise below 10Hz. Tantalum capacitors are recommended for
capacitorslarger than about 33µF. A 1 µF ceramic capacitor in
parallelwith the larger tantalum capacitor is required to retain
good noise performance at higher frequencies.
100k
C
C
C
C
C
C
C
C
= 1µF
BYP
BYP
BYP
BYP
BYP
BYP
BYP
BYP
10
8
= 4.7µF
= 10µF
= 22µF
= 47µF
= 100µF
= 470µF
= 1mF
10k
1k
100
10
1
6
4
2
0
0
2
4
6
8
10
DC BIAS VOLTAGE (V)
0.1
1
10
100
1k
10k
100k
1M
Figure 54. Capacitance vs. DC Bias Voltage
FREQUENCY (Hz)
Figure 52. Noise Spectral Density vs. Frequency, CBYP = 1 µF to 1 mF
Use Equation 1to determine the worst-case capacitance
accounting for capacitorvariation overtemperature,component
tolerance, and voltage.
10k
1Hz
3Hz
10Hz
100Hz
400Hz
30Hz
300Hz
1kHz
C
EFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
(1)
1k
100
10
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitortemperature coefficient.
TOL is the worst-case component tolerance.
In this example, theworst-case temperature coefficient (TEMPCO)
over −40°C to +85°Cis assumedtobe15% foran X5R dielectric.
The tolerance of the capacitor(TOL) is assumed to be 10%, and
CBIAS is 9.72 µF at 5 V, as shown in Figure 54.
1
Substituting these valuesin Equation 1yields
1
10
100
1000
C
(µF)
BYP
CEFF = 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF
Figure 53. Noise Spectral Density vs. CBYP for Different Frequencies
Therefore,the capacitor chosen in this example meetsthe
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
Capacitor Properties
Any good quality ceramiccapacitors can be used with the
ADM7151 as long as they meet the minimum capacitance
and maximum ESR requirements. Ceramiccapacitorsare
manufactured with a variety of dielectrics, each with different
behavior overtemperatureand applied voltage. Capacitorsmust
have a dielectricadequate to ensurethe minimumcapacitance
over the necessary temperaturerangeand dcbias conditions.
To guarantee theperformanceof the ADM7151, it is imperative
that the effects of dcbias, temperature, and tolerances on the
behavior of the capacitors be evaluated foreach application.
Rev. A | Page 17 of 24
ADM7151
Data Sheet
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
ENABLE (EN) AND UNDERVOLTAGE LOCKOUT
(UVLO)
The ADM7151 uses the EN pin to enable and disablethe VOUT
pin under normal operating conditions. As shown in Figure 55,
when a rising voltage on EN crosses the upper threshold,
VOUT turns on. When a falling voltage on EN crosses the lower
threshold, VOUT turnsoff. The hysteresis varies as a function
of the input voltage. For example, theEN hysteresis is
approximately 200 mV with an input voltage of 4.5V.
3.5
–40°C
+25°C
+125°C
3.0
2.5
6
8
10
12
14
16
V
(V)
IN
Figure 57. Typical EN Fall Threshold vs. Input Voltage (VIN) for Various
Temperatures
2.0
VOUT_EN_FALL
The ADM7151 also incorporates an internal undervoltage
lockout circuit to disable the output voltage when the input
voltage is less than the minimum input voltagerating of the
regulator. The upper and lower thresholdsare internally fixed
with approximately 300 mV of hysteresis.
1.5
VOUT_EN_RISE
1.0
0.5
3.5
0
1.0
1.1
1.2
1.3
(V)
1.4
1.5
1.6
V
EN
3.0
Figure 55. Typical VOUT Response to EN Pin Operation, VOUT = 3.3 V, VIN = 5 V
2.5
3.2
VOUT_VIN_FALL
2.0
3.0
2.8
2.6
1.5
VOUT_VIN_RISE
–40°C
1.0
2.4
2.2
2.0
+125°C
+25°C
0.5
0
4.0
4.1
4.2
4.3
4.4
4.5
1.8
1.6
1.4
V
(V)
IN
Figure 58. Typical UVLO Hysteresis, VOUT = 3.3 V
Figure 58 shows the typicalhysteresis of the UVLOfunction.
This hysteresis prevents on/off oscillations that can occur due to
noise on the input voltage as it passes through the threshold
points.
6
8
10
12
14
16
V
(V)
IN
Figure 56. Typical EN Rise Threshold vs. Input Voltage (VIN) for Various
Temperatures
Rev. A | Page 18 of 24
Data Sheet
ADM7151
output load reaches 1.3A (typical). When the output load
exceeds 1.3A, the output voltageis reduced to maintain a
constant current limit.
START-UP TIME
The ADM7151 uses an internal soft start to limit the inrush
current when the outputis enabled.The start-up time for a 5 V
output is approximately3ms from the time the EN active threshold
is crossed to when the output reaches90% of its finalvalue.
Thermal overload protection is included, which limits the
junction temperatureto a maximumof 155°C (typical). Under
extreme conditions(that is, high ambient temperatureand/or
high power dissipation)when the junction temperature starts to
rise above 155°C, the output is turned off,reducing the output
current to zero. When the junction temperaturedrops below
140°C, the output is turned on again, and output current is
restoredto its operating value.
The rise time of theoutput voltage(10%to 90%)is approximately
0.0012 × CBYP seconds
where CBYP is in microfarads.
6
ENABLE
C
C
C
= 1µF
= 4.7µF
= 10µF
BYP
BYP
BYP
5
4
3
2
1
0
Considerthe case where a hard shortfrom VOUTto GND occurs.
At first, the ADM7151 current limits, so that only 1.3 A is
conducted into the short. If self heating of the junction is great
enough to cause its temperatureto rise above 155°C, thermal
shutdown activates, turning off the outputand reducing the
output current to zero. As the junction temperaturecools and
drops below 140°C, the output turnson and conducts 1.3 A into
the short, again causing the junction temperature to rise above
155°C. This thermaloscillation between 140°C and 155°C
causes a current oscillation between 1.3 A and 0 mA that
continues as long as the short remains at the output.
0
0.002 0.004 0.006 0.008 0.010 0.012 0.014 0.016 0.018 0.020
TIME (Seconds)
Current-limit and thermallimit protections are intended to
protect the device against accidentaloverloadconditions. For
reliable operation, device powerdissipation mustbe externally
limited so that the junction temperaturedoesnot exceed150°C.
Figure 59. Typical Start-Up Behavior with CBYP = 1 µF to 10 µF
6
5
4
3
2
THERMAL CONSIDERATIONS
In applications with low input to output voltagedifferential, the
ADM7151 doesnotdissipate much heat.However,in applications
with high ambient temperatureand/orhigh input voltage, the
heat dissipated in the package can becomelarge enough that it
causes the junction temperature ofthe die to exceedthe maximum
junction temperatureof 150°C.
1
0
ENABLE
When the junction temperatureexceeds 155°C, the converter
enters thermalshutdown. It recovers only after the junction
temperature decreasesbelow140°C to prevent any permanent
damage. Therefore,thermalanalysis for the chosen application
is important to guarantee reliable performance over all conditions.
The junction temperatureof the die is the sum of the ambient
temperature of the environment and the temperaturerise of the
package due to the power dissipation,as shown in Equation 2.
C
C
C
= 10µF
= 47µF
= 330µF
BYP
BYP
BYP
0
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
TIME (Seconds)
Figure 60. Typical Start-Up Behavior with CBYP = 10 µF to 330 µF
REF, BYP, AND VREGPINS
REF, BYP, and VREG are internally generated voltagesthat
require externalbypass capacitorsfor proper operation. Do not,
under any circumstances, connect any loadsto thesepins
because doing so compromisesthe noise and PSRR performance
of the ADM7151. Using larger values of CBYP, CREF, and CREG is
acceptable but can increase the start-up time, as described in
the Start-Up Time section.
To guarantee reliableoperation, the junction temperatureof the
ADM7151 must not exceed 150°C. To ensure thatthe junction
temperature stays below this maximumvalue, the user must be
aware of the parameters that contribute to junction temperature
changes. These parametersinclude ambient temperature, power
dissipation in the powerdevice,andthermal resistancesbetween
the junction and ambient air (θJA). The θJA number is dependent
on the packageassemblycompoundsthatareused and theamount
of copper used to solderthe package GND pin and exposed pad
to the PCB.
CURRENT-LIMIT ANDTHERMAL OVERLOAD
PROTECTION
The ADM7151 is protected againstdamage dueto excessive
power dissipation by current and thermaloverloadprotection
circuits. The ADM7151 is designed to current limit when the
Rev. A | Page 19 of 24
ADM7151
Data Sheet
Table 8shows typicalθJA values of the 8-lead SOIC and 8-lead
LFCSPpackages for various PCBcoppersizes.
Figure 61 to Figure 66 showjunction temperature calculations for
different ambient temperatures, powerdissipation, and areas of
PCB copper.
Table 9shows the typicalΨJB values of the 8-lead SOIC and
8-l e a d L F C S P.
155
145
135
125
115
105
95
Table 8. Typical θJA Values
θJA (°C/W)
Copper Size (mm2)
251
8-Lead LFCSP
165.1
8-Lead SOIC
165
100
500
125.8
68.1
126.4
69.8
85
75
1000
6400
56.4
57.8
65
42.1
43.6
55
45
35
25
2
6400mm
2
500mm
1 Device soldered to minimum size pin traces.
2
25mm
T
MAX
Table 9. Typical ΨJB Values
Package
J
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
TOTAL POWER DISSIPATION (W)
ΨJB (°C/W)
8-Lead LFCSP
8-Lead SOIC
15.1
17.9
Figure 61. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 25°C
The junction temperatureof the ADM7151 is calculated from
the following equation:
160
150
140
130
120
110
100
90
TJ = TA + (PD × θJA)
(2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND
where:
VIN and VOUT are thinput and outputvoltages, respectively.
LOAD is the load current.
GND is the groune d current.
)
(3)
80
2
6400mm
70
2
500mm
I
I
2
25mm
60
50
T
MAX
J
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
TOTAL POWER DISSIPATION (W)
Power dissipation due to groundcurrent is quite small and can
be ignored. Therefore,the junctiontemperature equation simplifies
to the following:
Figure 62. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 50°C
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(4)
155
145
135
125
115
105
95
As shownin Equation4, for a givenambienttemperature,input to
output voltagedifferential, and continuousload current, there
exists a minimum coppersize requirement forthe PCB to ensure
that the junction temperaturedoesnot rise above 150°C.
The heat dissipation fromthe packagecan be improvedby
increasingtheamount of copper attached tothepinsand exposed
pad of the ADM7151. Adding thermal planes underthe package
also improves thermal performance. However,aslistedin Table 8, a
point of diminishing returns is eventually reached, beyond
which an increase in the copper area doesnot yield significant
reduction in the junction to ambient thermalresistance.
85
75
65
2
6400mm
2
500mm
2
25mm
T
MAX
J
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
TOTAL POWER DISSIPATION (W)
Figure 63. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 85°C
Rev. A | Page 20 of 24
Data Sheet
ADM7151
155
145
135
125
115
102
95
Thermal Characterization Parameter (ΨJB)
When the board temperatureis known, use the thermal
characterization parameter, ΨJB, to estimatethe junction
temperature rise (see Figure 67 and Figure 68). Maximum
junction temperature(TJ) is calculated from the board
temperature (TB) and power dissipation (PD) using the following
formula:
85
75
TJ = TB + (PD × ΨJB)
(5)
65
55
The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP
package and 17.9°C/W for the 8-lead SOIC package.
2
6400mm
2
45
500mm
2
25mm
35
160
T
MAX
J
25
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
TOTAL POWER DISSIPATION (W)
140
120
100
80
Figure 64. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 25°C
160
150
140
130
120
110
100
90
60
T
T
T
T
T
= 25°C
= 50°C
= 65°C
= 85°C
MAX
B
B
B
B
J
40
20
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0
TOTAL POWER DISSIPATION (W)
80
2
Figure 67. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP
6400mm
70
2
500mm
2
25mm
60
50
160
140
120
100
80
T
MAX
J
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
TOTAL POWER DISSIPATION (W)
Figure 65. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 50°C
155
145
135
125
115
105
95
60
T
T
T
T
T
= 25°C
= 50°C
= 65°C
= 85°C
MAX
B
B
B
B
J
40
20
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
TOTAL POWER DISSIPATION (W)
85
75
65
2
Figure 68. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC
6400mm
2
500mm
2
25mm
T
MAX
1.8
J
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.0
TOTAL POWER DISSIPATION (W)
Figure 66. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 85°C
Rev. A | Page 21 of 24
ADM7151
Data Sheet
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Place the bypass capacitors for VREG
,
VREF, and VBYP close to the respective pins and GND. Use of an
0805, 0603, or 0402 size capacitor achieves the smallest possible
footprint solution on boards where area is limited.
Figure 70. Example 8-Lead SOIC PCB Layout
Figure 69. Example 8-Lead LFCSP PCB Layout
Rev. A | Page 22 of 24
Data Sheet
ADM7151
OUTLINEDIMENSIONS
2.44
2.34
2.24
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
EXPOSED
PAD
1.70
1.60
1.50
AREA
0.50
0.40
0.30
0.20 MIN
4
1
PIN 1
TOP VIEW
BOTTOM VIEW
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 71. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
5.00
4.90
4.80
3.098
0.356
5
4
6.20
6.00
5.80
8
1
4.00
3.90
3.80
2.41
0.457
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
BOTTOM VIEW
45°
1.27 BSC
3.81 REF
TOP VIEW
SECTION OF THIS DATA SHEET.
1.65
1.25
1.75
1.35
0.50
0.25
0.25
0.17
0.10 MAX
0.05 NOM
SEATING
PLANE
8°
0°
0.51
0.31
1.04 REF
COPLANARITY
0.10
1.27
0.40
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 72. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-2)
Dimensions shown in millimeters
Rev. A | Page 23 of 24
ADM7151
Data Sheet
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage Range(V)
1.5 to 4.0
1.5 to 4.0
Package Description
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Evaluation Board
Package Option
Branding
LNN
LNN
ADM7151ACPZ-02-R2
ADM7151ACPZ-02-R7
ADM7151ARDZ-02
ADM7151ARDZ-02-R7
ADM7151ACPZ-04-R2
ADM7151ACPZ-04-R7
ADM7151ARDZ-04
ADM7151ARDZ-04-R7
ADM7151CP-02-EVALZ
CP-8-11
CP-8-11
RD-8-2
RD-8-2
CP-8-11
CP-8-11
RD-8-2
RD-8-2
1.5 to 4.0
1.5 to 4.0
1.5 to 5.1
LNP
LNP
1.5 to 5.1
1.5 to 5.1
1.5 to 5.1
1.5 to 4.0
1 Z = RoHS Compliant Part.
©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11480-0-4/15(A)
Rev. A | Page 24 of 24
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