ADMCF340BST [ADI]
DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End; DashDSPTM 64引脚闪存混合信号DSP增强型模拟前端
| 型号： | ADMCF340BST |
| 厂家： | 
ADI |
| 描述： | DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End |
| 文件： | 总40页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
DashDSP 64-Lead Flash Mixed-Signal DSP
a
with Enhanced Analog Front End
ADMCF340
TARGET APPLICATIONS
Memory Configuration
Refrigerator and Air Conditioner Compressors,
Washing Machines
Industrial Variable Speed Drives, HVAC
512 ꢀ 16-Bit Data Memory RAM
512 ꢀ 24-Bit Program Memory RAM
4K ꢀ 24-Bit Program Memory ROM
4K ꢀ 24-Bit Total Program FLASH Memory
Three Independent FLASH Memory Sectors
3584 ꢀ 24-Bit, 256 ꢀ 24-Bit, 256 ꢀ 24-Bit
Low Cost Pin-Compatible ROM Option
16-Bit Watchdog Timer
MOTOR TYPES
Permanent Magnet Synchronous Motors (PMSM),
Brushless DC Motors (BDCM), AC Induction Motors
(ACIM), Switched Reluctance Motors (SRM)
Programmable 16-Bit Internal Timer with Prescaler
Two Double Buffered Serial Ports with SPI Mode
Support
Integrated Power On Reset Function
Three Phase 16-Bit PWM Generation Unit
16-Bit Center-Based PWM Generator
Programmable PWM Pulsewidth
Edge Resolution of 50 ns
FEATURES
20 MHz Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatibility
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Programmable Narrow Pulse Deletion
153 Hz Minimum Switching Frequency
Double/Single Update Mode Control
Individual Enable and Disable for Each PWM
Output
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
High Frequency Chopping Mode for
Transformer-Coupled Gate Drives
(continued on page 8)
FUNCTIONAL BLOCK DIAGRAM
MOTOR CONTROL PERIPHERALS
MEMORY BLOCK
3
ADC SUBSYSTEM
10
ADSP-21xx BASE
ARCHITECTURE
PROGRAM PROGRAM
ROM
FLASH
I
AMP
AND TRIP
SENSE
DATA
ADDRESS
4K ꢀ 24
4K ꢀ 24
6
V
DATA
MEMORY
512 ꢀ 16
ANALOG
INPUTS
PROGRAM
RAM
512 ꢀ 24
REF
GENERATORS
PROGRAM
SEQUENCER
2.5V
16-BIT
THREE-
PHASE
PWM
DAG 1 DAG 2
SHA
TIMERS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
SHIFTER
SERIAL PORT
2 ꢀ 16-BIT
AUX
WATCH-
TIMER
PIO
25
POR
DOG
ALU MAC
SPORT 0
SPORT 1
PWM
TIMER
2
7
DashDSP is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accu-
rate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents
or other rights of third parties that may result from its use. No
license is granted by implication or otherwise under any patent
or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
ADMCF340
(VDD = 5%, GND = 0 V, TA = –40ꢁC to +85ꢁC, CLKIN = 10 MHz, unless
ANALOG-TO-DIGITAL CONVERTER otherwise noted.)
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Signal Input
0.3
3.5
12
4
V
VAUX0, VAUX1, VAUX2
Resolution1
Bits
Bits
mV
ns
µA
µA
Linearity Error2
3
0
600
Zero Offset3
–32
–10
+7
Comparator Delay
ADC High Level Input Current2
ADC Low Level Input Current2
10
VIN = 3.5 V
VIN = 0.0 V
NOTES
1Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.
22.44 kHz sample frequency, VAUX0, VAUX1, VAUX2
3Extrapolated point outside of operating range. 2.44 kHz sample frequency
Specifications subject to change without notice.
ISENSE AMPLIFIER–TRIP
Parameter
Min
Typ
Max
Unit
Conditions/Comments
ISENSE Signal Operating Range
–400
–2.6
+400
–2.34
5.5
mV
%
%
%
Bits
V
%
dB
dB
dB
dB
µA
kΩ
mV
mV
µs
I
SENSE Gain
–2.51
VIN = –400 mV to +400 mV
VIN = –400 mV to +400 mV
VIN = –400 mV to +400 mV
ISENSE Gain Channel Matching
I
I
SENSE Gain Stability1
SENSE Linearity2
0.8
9
1.87
2.1
51
54
–40
–53
8
1.68
ISENSE Internal Offset Voltage2
2.1
I
I
SENSE Internal Offset Stability2
SENSE Signal-to-Noise Ratio (SNR)3
ISENSE Signal-to-Noise Ratio Less Distortion
(SNR)3
I
SENSE Total Harmonic Distortion3
ISENSE Input Current
SENSE Input Resistance
–200
+10
VIN = –400 mV to +400 mV
I
11.5
TRIP Threshold Low
–690
430
–430
690
TRIP Threshold High
TRIP Minimum Pulsewidth4
5
NOTES
1Variation of gain with VDD and temperature
2VIN = –400 mV to +400 mV.
3fIN = 1 kHz sine wave, VIN = –400 mV to +400 mV, fS = 4 kHz.
4High or low trip threshold
CURRENT SOURCE1
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Programming Resolution
Tuned Current2
3
109
Bits
µA
91
100
NOTES
1For ADC calibration
20.3 V to 3.5 V ICONST voltage
REV. 0
–2–
ADMCF340
VOLTAGE REFERENCE
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Voltage Level (VREF
Drift
)
2.44
2.50
110
2.55
V
–40°C to +85°C
ppm/°C
Specifications subject to change without notice.
POWER-ON RESET
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Reset Threshold
Hysteresis
Reset Active Timeout Period
3.20
3.65
100
3.2*
4.10
V
mV
ms
*216 CLKOUT cycles
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
Conditions/Comments
VIL
VIH
VIL
VIH
VOL
VOL
VOH
IIL
IIL
IIH
IIH
IIH
Low Level Input Voltage
0.8
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
mA
mA
High Level Input Voltage
2
Low Level Input Voltage1
1.75
High Level Input Voltage
2.60
Low Level Output Voltage2
Low Level Output Voltage3
High Level Output Voltage
Low Level Input Current RESET Pin4
Low Level Input Current
0.4
0.8
IOL = 2 mA
IOL = 2 mA
IOH = 0.5 mA
VIN = 0 V
4
–100
–10
VIN = 0 V
High Level Input Current RESET Pin4
30
100
10
VIN = VDD
VIN = VDD
VIN = VDD
VIN = VDD
VIN = 0 V
VDD = 5.25 V
VDD = 5.25 V
High Level Input Current5
High Level Input Current
IOZH
IOZL
IDD
IDD
High Level Three-State Leakage Current6
Low Level Three-State Leakage Current6
Supply Current (Idle)7
100
–10
55
135
Supply Current (Dynamic)7
NOTES
1PWMPOL and PWMSR Pins only
2Output pins PORTA0–PORTA8, PORTB0–PORTB15, AH, AL, BH, BL, CH, CL
3XTAL Pin
4Internal pull-up, RESET
5Internal pull-down, PWMTRIP, PORTA0–PORTA8, PORTB0–PORTB15
6Three stateable pins, DT1, RFS1, TFS1, SCLK1
7Outputs not switching
Specifications subject to change without notice.
REV. 0
–3–
ADMCF340
TIMING PARAMETERS
Parameter
Min
Max
Unit
Clock Signals
Signal TCK is defined as 0.5 tCKIN. The ADMCF340 uses an input clock with
a frequency equal to half the instruction rate; a 10 MHz input clock (which is
equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz).
When TCK values are within the range of 0.5 tCKIN period, they should be
substituted for all relevant timing parameters to obtain specification value as
in the following example:
tCKH = 0.5 TCK −10 ns = 0.5 × 50 ns −10 ns = 15 ns
Timing Requirements:
tCKIN
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
100
20
20
150
20
ns
ns
ns
Switching Characteristics:
tCKL
CLKOUT Width Low
0.5 TCK – 10
0.5 TCK – 10
0
ns
ns
ns
tCKH
tCKOH
CLKOUT Width High
CLKIN High to CLKOUT High
Control Signals
Timing Requirement:
tRSP
RESET Width Low
5 TCK
*
ns
ns
PWM Shutdown Signals
Timing Requirement:
tPWMTPW PWMTRIP Width Low
TCK
*Applies after power-up sequence is complete.
Specifications subject to change without notice.
tCKIN
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
Figure 1. Clock Signals
REV. 0
–4–
ADMCF340
TIMING PARAMETERS
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
tSCK
tSCS
tSCH
tSCP
SCLK Period
100
15
20
ns
ns
ns
ns
DR/TFS/RFS Setup before SCLK Low
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
40
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
0.25 TCK 0.25 TCK + 20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCDE
tSCDV
tRH
30
30
30
0
0
0
tRD
tSCDH
tSCDD
tTDE
tTDV
tRDV
SCLK High to DT Disable
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
25
30
RFS (Multichannel, Frame Delay Zero) to DT Valid
Specifications subject to change without notice.
CLKOUT
SCLK
tCC
tCC
tSCK
tSCP
tSCS tSCH
tSCP
DR
RFS
TFS
IN
IN
tRD
tRH
RFS
TFS
OUT
OUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
(ALTERNATE
FRAME MODE)
tRDV
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
Figure 2. Serial Port Timing
REV. 0
–5–
ADMCF340
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Supply Voltage (VDD
) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Supply Voltage (AVDD) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280°C
*Stresses greater than those listed may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
63 62 61
58 57
55 54
52
64
60 59
56
53
51
50 49
1
2
48
AGND
AV
DD
PIN 1
IDENTIFIER
DGND1
47 DV
1
DD
3
46
45
44
43
42
41
40
39
38
37
36
35
34
33
XTAL
RESET
PB6
CH
4
NC
5
CLKIN
NC
6
PB7
PB8
CL
7
PB5
8
PB4
ADMCF340
9
TOP VIEW
PB9
PB10
BH
PA0/DR0
PB3
(Not to Scale)
10
11
12
13
14
15
16
PB2
PB11
PB12
BL
PA1/DT0
PB1
PB0
NC
PA2/RFS0
NC
NC
18 19 20
23 24 25
29 30 31 32
26 27 28
17
21 22
NC = NO CONNECT
ORDERING GUIDE
Temperature
Range
Instruction
Rate
Package
Description
Package
Option
Model
ADMCF340BST
–40°C to +85°C
20 MHz
64-Lead Thin Plastic Quad Flatpack
(LQFP)
ST-64
ADMCF340-EVALKIT
N/A
N/A
Development Tool Kit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADMCF340 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–6–
ADMCF340
PIN FUNCTION DESCRIPTIONS
Pin
No.
Pin
Type
Pin
No.
Pin
Type
Mnemonic
Mnemonic
1
2
3
4
5
6
7
8
AGND
DGND1
RESET
PB6
CH
PB7
PB8
CL
PB9
PB10
BH
PB11
PB12
BL
NC
NC
GND
GND
D_IN
D_I/O
D_OUT
D_I/O
D_I/O
D_OUT
D_I/O
D_I/O
D_OUT
D_I/O
D_I/O
D_OUT
No Connect
No Connect
No Connect
D_OUT
D_I/O
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
PA2/RFS0
PB0
PB1
PA1/DT0
PB2
PB3
PA0/DR0
PB4
PB5
NC
CLKIN
NC
XTAL
DVDD
AVDD
PWMTRIP
V3
ISENSE3
V2
ISENSE2
No Connect
D_I/O
D_I/O
D_I/O
D_I/O
D_I/O
D_I/O
D_I/O
D_I/O
D_I/O
No Connect
D_I/O
No Connect
A_OUT
SUP
SUP
D_IN
A_IN
A_IN
A_IN
A_IN
A_IN
A_IN
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
NC
AH
PB13
PB14
AL
PB15
D_I/O
D_OUT
D_I/O
V1
PA8/(AUX0/CLKOUT)
PA7/(AUX1/PWMSYNC) D_I/O
D_I/O
ISENSE1
VAUX4
VAUX0
VAUX5
VAUX1
VAUX6
VAUX2
VAUX7
ICONST
NC
A_IN
A_IN
A_IN
A_IN
A_IN
A_IN
A-IN
A_OUT
No Connect
DVDD
2
SUP
PWMSR
DGND2
PA6/DR1
PA5/(FL1/DT1)
PA4/(SCLK1/SCLK0)
PWMPOL
D_IN
GND
D_I/O
D_I/O
D_I/O
D-IN
D_I/O
PA3/TFS0
PA is the abbreviation of PORTA; PB is the abbreviation of PORTB.
REV. 0
–7–
ADMCF340
(continued from page 1)
tional units, data address generators, and a program sequencer.
The computational units comprise an ALU, a multiplier/accumu-
lator (MAC), and a barrel shifter. There are special instructions
for bit manipulation, multiplication (x squared), biased rounding,
and global interrupt masking. The system peripherals are the
power-on reset circuit (POR), the watchdog timer, and two
synchronous serial ports. The serial ports are configurable,
and double buffered, with hardware support for UART, SCI,
and SPI port emulation. The ADMCF340 provides 512 × 24-bit
program memory RAM, 4K × 24-bit program memory ROM,
4K × 24-bit program FLASH memory, and 512 × 16-bit data
memory RAM. The user code will be stored and executed from
the flash memory. The program and data memory RAM can be
used for dynamic data storage or can be loaded through the
serial port from an external device as in other ADMCxx family
parts. The program memory ROM contains a monitor function
as well as useful routines for erasing, programming, and verifying
the flash memory.
External PWMTRIP Pin
Switched Reluctance Motor Mode Selection Pin
PWM Polarity Selection Pin
Integrated 13-Channel ADC Subsystem
Three Bipolar ISENSE Inputs with Programmable
Sample and Hold Amplifier and Overcurrent
Protection (Usable as Three Dedicated Analog Inputs)
Three Simultaneous Converting Voltage Inputs
Seven Muxed Auxiliary Analog Inputs
Internal Voltage Reference (2.5 V)
Acquisition Synchronized to PWM Switching
Frequency
25-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 16-Bit Auxiliary PWM Timers
Synthesized Analog Output
The motor control peripherals of the ADMCF340 provide a 12-bit
analog data acquisition system with 13 analog input channels,
three dedicated ISENSE functions (combining internal amplifi-
cation, sampling, and overcurrent PWM shutdown features),
and an internal voltage reference. In addition, a three-phase,
16-bit, center-based PWM generation unit can be used to produce
high accuracy PWM signals with minimal processor overhead. The
ADMCF340 also contains two 16-bit auxiliary PWM timers
and 25 lines of programmable digital I/O.
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operation Modes
Independent Mode/Offset Mode
GENERAL DESCRIPTION
The ADMCF340 is a low cost, single-chip DSP-based controller
suitable for permanent magnet synchronous, ac induction, switched
reluctance, and brushless dc motors. The ADMCF340 integrates
a 20 MHz, fixed-point DSP core with a complete set of motor control
and system peripherals that permit fast, efficient development of
motor controllers.
Several functions such as the auxiliary PWM and the serial com-
munication ports are multiplexed with the nine PORT A (9, PIO)
programmable input/output (PIO) pins. The other 16 pro-
grammable digital I/O are dedicated. The pin functions can
be independently selected to allow maximum flexibility for
different applications.
The DSP core of the ADMCF340 is completely code compatible
with the ADSP-21xx DSP family and combines three computa-
INSTRUCTION
REGISTER
FLASH
PROGRAM
MEMORY
4K ꢀ 24
PM ROM
DM RAM
512 ꢀ 16
4K ꢀ 24
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
PROGRAM
SEQUENCER
PM RAM
512 ꢀ 24
14
14
PMA BUS
DMA BUS
PMD BUS
DMD BUS
24
BUS
EXCHANGE
16
CONTROL
LOGIC
TIMER
INPUT REGS
ALU
INPUT REGS
INPUT REGS
SHIFTER
MAC
TRANSMIT REG
COMPANDING
CIRCUITRY
RECEIVE REG
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
16
SERIAL
PORT
R BUS
6
Figure 3. DSP Core Block Diagram
–8–
REV. 0
ADMCF340
DSP CORE ARCHITECTURE OVERVIEW
Program memory can store both instructions and data, permitting
the ADMCF340 to fetch two operands in a single cycle—one from
program memory and one from data memory. The ADMCF340
can fetch an operand from on-chip program memory and the next
instruction in the same cycle. The ADMCF340 writes data from its
16-bit registers to the 24-bit program memory using the PX Register
to provide the lower eight bits. When it reads data (not instructions)
from 24-bit program memory to a 16-bit data register, the lower
eight bits are placed in the PX Register.
Figure 3 is an overall block diagram of the DSP core of the
ADMCF340. The flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle (50 ns with a 10 MHz
CLKIN) the DSP core can:
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
The ADMCF340 can respond to a number of distinct DSP core
and peripheral interrupts. The DSP interrupts comprise a serial port
receive interrupt, a serial port transmit interrupt, a timer inter-
rupt, and two software interrupts. Additionally, the motor control
peripherals include two PWM interrupts and a PIO interrupt.
This all takes place while the processor continues to:
•
Receive and transmit through the serial ports
Decrement the interval timer
Generate three-phase PWM waveforms for a power inverter
Generate two signals using the 16-bit auxiliary PWM timers
Acquire four analog signals
•
•
•
•
•
The serial port (SPORT0 ) provides a complete synchronous
serial interface with optional companding in hardware and a wide
variety of framed and unframed data transmit and receive modes of
operation. SPORT0 and SPORT1 can generate an internal
programmable serial clock or accept an external serial clock.
Decrement the watchdog timer
The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC), and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision com-
putations. The ALU performs a standard set of arithmetic and
logic operations as well as providing support for division primitives.
The MAC performs single-cycle multiply, multiply/add, and
multiply/subtract operations with 40 bits of accumulation. The
shifter performs logical and arithmetic shifts, normalization,
denormalization, and derive-exponent operations. The shifter
can be used to implement numeric format control efficiently,
including floating-point representations. The internal result (R)
bus directly connects the computational units so that the output
of any unit may be the input of any unit on the next cycle.
A programmable interval counter is also included in the DSP core
and can be used to generate periodic interrupts. A 16-bit count
register (TCOUNT) is decremented every n processor cycle,
where n – 1 is a scaling value stored in the 8-bit TSCALE Register.
When the value of the counter reaches zero, an interrupt is
generated and the count register is reloaded from a 16-bit period
register (TPERIOD).
The ADMCF340 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Each instruction is executed in a single 50 ns processor
cycle (for a 10 MHz CLKIN). The ADMCF340 assembly language
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development. For further information on the DSP core, refer to
the ADSP-2100 Family User’s Manual, Third Edition, with
particular reference to the ADSP-2171.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps and
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMCF340 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
SERIAL PORTS
The ADMCF340 incorporates two synchronous serial ports
(SPORT1 and SPORT0) for serial communication and multi-
processor communication. SPORT1 is primarily intended for
the interfacing of the debugging tools and/or code booting from
an external serial memory.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro-
gram memory. Each DAG maintains and updates four address
pointers (I registers). Whenever the pointer is used to access
data (indirect addressing), it is post-modified by the value in
one of four modify (M) registers. A length value may be associated
with each pointer (L registers) to implement automatic modulo
addressing for circular buffers. The circular buffering feature is
also used by the serial ports for automatic data transfers to and
from on-chip memory. DAG1 generates only data memory address
and provides an optional bit-reversal capability. DAG2 may
generate either program or data memory addresses but has no
bit-reversal capability. Efficient data transfer is achieved with
the use of five internal buses:
The following is a brief list of capabilities of the ADMCF340
SPORTs.
•
•
•
SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
SPORTs can use an external serial clock or generate their
own serial clock internally.
SPORTs have independent framing for the receive and transmit
sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame synchronization signals are active high or inverted, with
either of two pulsewidths and timings.
•
•
•
•
•
Program memory address (PMA) bus
Program memory data (PMD) bus
Data memory address (DMA) bus
Data memory data (DMD) bus
Result (R) bus
•
•
SPORTs support serial data-word lengths from three bits to
16 bits and provide optional A-law and m-law companding
according to ITU (formerly CCITT) recommendation G.711.
SPORTs’ receive and transmit sections can generate unique
interrupts on completing a data-word transfer.
REV. 0
–9–
ADMCF340
•
SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data-word. An interrupt
is generated after a data buffer transfer.
INTERRUPT OVERVIEW
The ADMCF340 can respond to 34 different interrupt sources
with minimal overhead, seven of which are internal DSP core
interrupts and 27 are from the motor control peripherals. The seven
DSP core interrupts are SPORT1 receive (or IRQ0) and transmit
(or IRQ1), SPORT0 receive and transmit, the internal timer,
and two software interrupts. The motor control peripheral
interrupts are the 25 programmable I/Os and two from the PWM
(PWMSYNC pulse and PWMTRIP). All motor control interrupts
are multiplexed into the DSP core through the peripheral IRQ2
interrupt. The interrupts are internally prioritized and individually
maskable. A detailed description of the entire interrupt system of
the ADMCF340 is presented later, following a more detailed
description of each peripheral block.
•
SPORT0 has one pin, SCLK0, shared with SPORT1. Dur-
ing a boot phase (SPORT1 Boot Mode enabled by a bit in
the MODECTRL Register), the serial clock of SPORT1 is
externally available. The serial clock of SPORT0 is exter-
nally available when the SPORT1 is configured in UART
Mode.
•
SPORT0 can be configured as SPI port (master mode only).
Refer to Table XI for more information. The clock phase and
polarity are programmable through the MODECTRL Register.
Refer to Table XI for pin configuration.
•
•
SPORT0 has a multichannel interface to selectively receive
and transmit a 24-word or 32-word time division multiplexed
serial bitstream.
MEMORY MAP
The ADMCF340 has two distinct memory types: program
and data. In general, program memory contains user code and
coefficients, while the data memory is used to store variables and
data during program execution. Three kinds of program memory are
provided on the ADMCF340: RAM, ROM, and FLASH. The
motor control peripherals are memory mapped into a region of the
data memory space starting at 0x2000. The complete program and
data memory maps are given in Tables II and III, respectively.
SPORT1 is the default port for program/data memory boot
loading and for the development tools interface. The DT1/FL1
Pin can be configured as the SROM/E2 prom reset signal.
The ADMCF340 is available in a 64-lead LQFP package.
PIN FUNCTION DESCRIPTION
Table I. Pin List
Table II. Program Memory Map
Memory
Pin Group
Name
# of Input/
Pins Output Function
Address Range
Type
Function
PWMPOL
PWMSR
1
1
I
I
PWM Polarity
0x0000–0x002F
0x0030–0x01FF
0x0200–0x07FF
0x0800–0x17FF
0x1800–0x1FFF
0x2000–0x20FF
RAM
RAM
Internal Vector Table
User Program Memory
Reserved
Reserved Program Memory
Reserved
User Program Memory
Sector 0
User Program Memory
Sector 1
User Program Memory
Sector 2
PWM Switched
Reluctance Mode
Processor Reset Input
Serial Port 1 Pins
(DT1/FL1, DR1)
Serial Port 0 Pins
(DT0, DR0, RFS0,
TFS0, SCLK1/
SCLK02)
Processor Clock
Output
External Clock or
Quart Crystal
RESET
1
2
I
I/O
SPORT11
ROM
SPORT01
5
I/O
FLASH
FLASH
FLASH
0x2100–0x21FF
0x2200–0x2FFF
0x3000–0x3FFF
CLKOUT1
11
2
I/O
I/O
Reserved
CLKIN, XTAL
Connection Point
Digital I/O Port Pins
Digital I/O Port Pins
Auxiliary PWM
Outputs
PWM Outputs
PWM Trip Signal
ISENSE Inputs
Analog Inputs
Auxiliary Analog Inputs
ADC Constant
Current Source
Power Supply
Ground
Table III. Data Memory Map
Memory
PORTA0–PORTA81
9
I/O
I/O
O
PORTB0–PORTB15 16
AUX0–AUX11
2
Address Range
Type
Function
0x0000–0x1FFF
0x2000–0x20FF
0x2100–0x37FF
0x3800–0x39FF
0x3A00–0x3BFF
0x3C00–0x3FFF
Reserved
Memory Mapped Registers
Reserved
User Data Memory
Reserved
AH-CL
PWMTRIP
V1 to V3
ISENSE1 to ISENSE3
VAUX0-VAUX7
ICONST
6
1
3
3
7
1
O
I
I
I
I
RAM
RAM
Memory Mapped Registers
O
VDD
GND
3
3
I
I
NOTES
1Multiplexed pins, individually selectable through PORTA_SELECT and
PORTA_DATA Registers.
2SCLK1/SCLK0 multiplexed signals. Selectable through MODECTRL
Register Bit 4.
REV. 0
–10–
ADMCF340
FLASH MEMORY SUBSYSTEM
flash memory before clearing the boot-from-flash code, thus
ensuring the security of the user program. If security is not a
concern, the auto_erase_reg routine can be used to clear the
boot-from-flash code while leaving the user program intact.
The ADMCF340 has 4K × 24-bit of user-programmable, nonvola-
tile flash memory. A flash programming utility is provided with the
development tools that performs the basic device programming
operations: erase, program, and verify.
Refer to the ADMCF34x DSP Motor Controller Developers’
Reference Manual for further instructions and an example of
using the boot-from-flash code.
The flash memory array is portioned into three asymmetrically
sized sectors of 256 words, 256 words, and 3,584 words, labeled
Sector 0, Sector 1, and Sector 2, respectively. These sectors are
mapped into external program memory address space.
FLASH PROGRAM BOOT SEQUENCE
On power-up or reset, the processor begins instruction execution
at Address 0x0800 of internal program ROM. The ROM monitor
program that is located there checks the boot-from-flash code. If
that code is set, the processor jumps to location 0x2200 in external
flash program memory, where it expects to find the user’s
application program.
Four flash memory interface registers are connected to the DSP.
These 16-bit registers are mapped into the register area of data
memory space. They are named Flash Memory Control Register
(FMCR), Flash Memory Address Register (FMAR), Flash
Memory Data Register Low (FMDRL), and Flash Memory Data
Register High (FMDRH). These registers are diagrammed later in
this data sheet. They are used by the flash memory programming
utility. The user program may read these registers but should not
modify them directly. The flash programming utility provides a
complete interface to the flash memory.
If the boot-from-flash code is not set, the monitor attempts to
boot from an external device as described in the ADMCF34x
DSP Motor Controller Developers’ Reference Manual.
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMCF340
with an external crystal.
Note: From the point of view of 2171 core, the flash memory
is placed externally. It means the core accesses them through
an external memory interface that multiplexes the program
memory and data memory buses into a single external bus.
Therefore, if more than one external transfer must be made in
the same instruction, there will be at least an overhead cycle
required. For more details, see Application Note ANF32X-65
Guidelines to Transfer Code from ADMCF32x to ADMC32x.
22pF
CLKOUT
XTAL
10MHz
CLKIN
22pF
ADMCF340
Special Flash Registers
RESET
The flash module has four nonvolatile 8-bit registers called Special
Flash Registers (SFRs) that are accessible independently of
the main flash array via the flash programming utility. These
registers are for general-purpose, nonvolatile storage. When
erased, the Special Flash Registers contain all “0s.” To read
Special Flash Registers from the user program, call the read_reg
routine contained in the ROM. Refer to the ADMCF34x DSP
Motor Controller Developers’ Reference Manual for an example.
Figure 4. Basic System Configuration
Clock Signals
The ADMCF340 can be clocked either by a crystal or a TTL
compatible clock signal. For normal operation, the CLKIN
input cannot be halted, changed during operation, or operated
below the specified minimum frequency. If an external clock is
used, it should be a TTL compatible signal running at half the
instruction rate. The signal is connected to the CLKIN pin of
the ADMCF340. In this mode, with an external clock signal,
the XTAL Pin must be left unconnected. The ADMCF340 uses
an input clock with a frequency equal to half the instruction
rate; a 10 MHz input clock yields a 50 ns processor cycle (which is
equivalent to 20 MHz). Normally, instructions are executed
in a single processor cycle. All device timing is relative to the
internal instruction rate that is indicated by the CLKOUT
signal when enabled.
Boot-from-Flash Code
A security feature is available in the form of a code that when set
causes the processor to execute the program in flash memory at
power-up or reset. In this mode, the flash programming utility
and debugger are unable to communicate with the ADMCF340.
Consequently, the contents of the flash memory can be neither
programmed nor read.
The boot-from-flash code may be set via the flash programming
utility when the user’s program is thoroughly tested and loaded
into flash program memory at Address 0x2200. The user’s pro-
gram must contain a mechanism for clearing the boot-from-flash
code if reprogramming the flash memory is desired. The only
way to clear boot-from-flash is from within the user program, by
calling the flash_init or auto_erase_reg routines that are included in the
ROM. The user program must be signaled in some way to call the
necessary routine to clear the boot-from-flash code. An example
would be to detect a high level on a PIO pin during startup initial-
ization and then call the flash_init or auto-erase-reg routine.
The flash_init routine will erase the entire user program in
Because the ADMCF340 includes an on-chip oscillator feedback
circuit, an external crystal may be used instead of a clock source,
as shown in Figure 2. The crystal should be connected across the
CLKIN and XTAL Pins with two capacitors (see Figure 2). A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used. A clock output signal (CLKOUT) is
generated by the processor at the processor’s cycle rate of twice
the input frequency.
REV. 0
–11–
ADMCF340
Reset
DSP Control Registers
The ADMCF340 DSP core and peripherals must be correctly
reset when the device is powered up to assure proper unitization.
The ADMCF340 contains an integrated power-on-reset (POR)
circuit that provides a complete system reset on power-up and
power-down. The POR circuit monitors the voltage on the
ADMCF340 VDD Pin and holds the DSP core and peripherals
The DSP core has a system control register, SYSCNTL, memory-
mapped at DM (0x3FFF). SPORT1 must be configured as a
serial port by setting Bit 10. SPORT0 and SPORT1 are enabled
by setting Bit 11 and Bit 12.
The DSP core has a wait state control register, MEMWAIT,
memory-mapped at DM (0x3FFE). The default value of this
register is 0xFFFF. For proper operation of the ADMCF340,
this register must always contain the value 0x8000. This value
sets the minimum access time to the program memory.
in reset while VDD is less than the threshold voltage level, VRST
.
When this voltage is exceeded, the ADMCF340 is held in reset
for an additional 216 DSP clock cycles (TRST in Figure 5). During
this time (TRST), the supply voltage must reach the recommended
operating condition. On power-down, when the voltage on the
VDD Pin falls below VRST –VHYST, the ADMCF340 will be
reset. Also, if the external RESET Pin is actively pulled low
at any time after power-up, a complete hardware reset of the
ADMCF340 is initiated.
The configurations of both the SYSCNTL and MEMWAIT Reg-
isters of the ADMCF340 are shown at the end of the data sheet.
THREE-PHASE PWM CONTROLLER
Overview
The PWM generator block of the ADMCF340 is a flexible,
programmable, three-phase PWM waveform generator that can
be programmed to generate the required switching patterns to
drive a three-phase voltage source inverter for ac induction motors
(ACIM) or permanent magnet synchronous motors (PMSM).
In addition, the PWM block contains special functions that
considerably simplify the generation of the required PWM
switching patterns for control of electronically commutated
motors (ECM), brushless dc motors (BDCM), or switched
reluctance motors (SRM).
V
RST
V
– V
HYST
RST
V
DD
T
RST
RESET
Figure 5. Power-On Reset Operation
The ADMCF340 sets all internal stack pointers to the empty
stack condition, masks all interrupts, clears the MSTAT Register,
and performs a full reset of all the motor control peripherals.
Following a power-up, it is possible to initiate a DSP core and
motor control peripheral reset by pulling the RESET Pin low.
The RESET signal must be the minimum pulsewidth specification,
tRSP. Following the reset sequence, the DSP core starts executing
code from the internal PM ROM located at 0x0800.
The six PWM output signals consist of three high side drive
signals (AH, BH, and CH) and three low side drive signals (AL,
BL, and CL). The switching frequency, dead time, and minimum
pulsewidths of the generated PWM patterns are programmable
using, respectively, the PWMTM, PWMDT, and PWMPD
registers. In addition, three registers (PWMCHA, PWMCHB,
and PWMCHC) control the duty cycles of the three pairs of
PWM signals.
PWM DUTY CYCLE
REGISTERS
PWM CONFIGURATION
REGISTERS
PWMTM (15...0)
PWMDT (9...0)
PWMCHA (15...0)
PWMCHB (15...0)
PWMCHC (15...0)
PWMPD (9...0)
PWMSYNCWT (7...0)
MODECTRL (6)
PWMSEG (8...0)
PWMGATE (9...0)
AH
AL
BH
THREE-PHASE
PWM TIMING
UNIT
OUTPUT
CONTROL
UNIT
GATE
DRIVE
UNIT
BL
CH
CL
SYNC
CLK
SYNC RESET
CLK
CLKOUT
PWMSYNC
TO INTERRUPT
CONTROLLER
PWMTRIP
PWMTRIP
OR
PWMSWT (0)
I
I
I
SENSE1
SENSE2
SENSE3
OVER
CURRENT
TRIP
PWM SHUTDOWN CONTROLLER
ANALOG BLOCK
Figure 6. Overview of the PWM Controller of the ADMCF340
–12–
REV. 0
ADMCF340
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG Register. In
addition, three control bits of the PWMSEG Register permit
crossover of the two signals of a PWM.
the status of PWMTRIP is available, as well as a status bit that
indicates whether operation is in the first half or the second half
of the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 6. The generation of the six output PWM signals on pins
AH to CL is controlled by four important blocks:
In crossover mode, the high side PWM signals are diverted to
the complementary low side output and low side signals are
diverted to the corresponding high side output.
•
The three-phase PWM timing unit, that is the core of the
PWM controller, generates three pairs of complemented and
dead-time-adjusted center-based PWM signals.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation
techniques: optical isolation using optocouplers, and transformer
isolation using pulse transformers. The PWM controller of the
ADMCF340 permits mixing of the output PWM signals with a
high frequency chopping signal to permit an easy interface to
such pulse transformers. The features of this gate-drive chopping
mode can be controlled by the PWMGATE Register. There is an
8-bit value within the PWMGATE Register that directly controls
the chopping frequency. In addition, high frequency chopping
can be independently enabled for the high side and the low side
outputs using separate control bits in the PWMGATE Register.
•
The output control unit allows the redirection of the outputs
of the three-phase timing unit for each channel to either the
high side or low side output. In addition, the output control
unit allows individual enabling/disabling of each of the six
PWM output signals.
•
•
The GATE drive unit provides the high chopping frequency
and its subsequent mixing with the PWM signals.
The PWM shutdown controller manages the three PWM
shutdown modes (via the PWMTRIP Pin, the analog block, or
the PWMSWT Register) and generates the correct RESET
signal for the Timing Unit.
The PWM generator is capable of operating in two distinct modes:
single update mode or double update mode. In single update
mode, the duty cycle values are programmable only once per
PWM period, so that the resultant PWM patterns are symmetrical
about the midpoint of the PWM period. In the double update mode,
a second updating of the PWM duty cycle values is implemented
at the midpoint of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in three-phase PWM inverters. This technique
also permits the closed-loop controller to change the average
voltage applied to the machine winding at a faster rate, allowing
wider closed-loop bandwidths to be achieved. The operating
mode of the PWM block (single or double update mode) is
selected by a control bit in MODECTRL Register.
•
The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, CLKOUT, and is capable of gener-
ating two interrupts to the DSP core. One interrupt is generated
on the occurrence of a PWMSYNC pulse, and the other is
generated on the occurrence of any PWM shutdown action.
Three-Phase Timing Unit
The 16-bit three-phase timing unit is the core of the PWM
controller and produces three pairs of pulsewidth modulated
signals with high resolution and minimal processor overhead.
There are four main configuration registers (PWMTM, PWMDT,
PWMPD, and PWMSYNCWT) that determine the fundamental
characteristics of the PWM outputs. In addition, the operating
mode of the PWM (single or double update mode) is selected by
Bit 6 of the MODECTRL Register. These registers, in conjunction
with the three 16-bit duty cycle registers (PWMCHA, PWMCHB,
and PWMCHC), control the output of the three-phase timing unit.
The PWM generator of the ADMCF340 also provides an internal
signal that synchronizes the PWM switching frequency to the A/D
operation. In single update mode, a PWMSYNC pulse is produced
at the start of each PWM period. In double update mode, an
additional PWMSYNC pulse is produced at the midpoint of each
PWM period. The width of the PWMSYNC pulse is programmable
through the PWMSYNCWT Register.
PWM Switching Frequency: PWMTM Register
The PWM switching frequency is controlled by the PWM
period register, PWMTM. The fundamental timing unit of
the PWM controller is TCK = 1/fCLKOUT where fCLKOUT is the
CLKOUT frequency (DSP instruction rate). Therefore, for a
20 MHz CLKOUT, the fundamental time increment is 50 ns.
The value written to the PWMTM Register is effectively the
number of TCK clock increments in half a PWM period. The
required PWMTM value is a function of the desired PWM
switching frequency (fPWM) and is given by:
The PWM signals produced by the ADMCF340 can be shut
off in a number of different ways. First, there is a dedicated
asynchronous PWM shutdown pin, PWMTRIP, which when
brought low, instantaneously places all six PWM outputs in the
OFF state. In addition, PWM shutdown is initiated when the
voltage on any of the three ISENSE input pins exceeds the trip
thresholds (high or low). Because these two hardware shutdown
mechanisms are asynchronous, and the associated PWM disable
circuitry does not use clocked logic, the PWM will shut down
even if the DSP clock is not running. The PWM system may also
be shut down from software by writing to the PWMSWT Register.
fCLKOUT
2 × fPWM
fCLKIN
fPWM
PWMTM =
=
Therefore, the PWM switching period, TS, can be written as:
TS = 2 × PWMTM ×TCK
Status information about the PWM system of the ADMCF340
is available to the user in the SYSSTAT Register. In particular,
REV. 0
–13–
ADMCF340
For example, for a 20 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (TS = 100 µs), the correct value
to load into the PWMTM Register is:
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks
the start of a new PWM cycle and is used to latch new values
from the PWM configuration registers (PWMTM, PWMDT,
PWMPD, and PWMSYNCWT) and the PWM duty cycle registers
(PWMCHA, PWMCHB, and PWMCHC) into the three-phase
timing unit. The PWMSEG Register is also latched into the
output control unit on the rising edge of the PWMSYNC pulse.
In effect, this means that the parameters of the PWM signals can
be updated only once per PWM period at the start of each cycle.
Thus, the generated PWM patterns are symmetrical about the
midpoint of the switching period.
20 ×106
PWMTM =
= 1000 = 0x3E8
2 ×10 ×103
The largest value that can be written to the 16-bit PWMTM
Register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:
20 × 106
fPWM,min
=
= 153 Hz
2 × 65,535
In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The rising
edge of this new PWMSYNC pulse is again used to latch new
values of the PWM configuration registers, duty cycle registers,
and the PWMSEG Register. As a result, it is possible to alter
both the characteristics (switching frequency, dead time, mini-
mum pulsewidth, and PWMSYNC pulsewidth) and the output
duty cycles at the midpoint of each PWM cycle. Consequently,
it is possible to produce PWM switching patterns that are no
longer symmetrical about the midpoint of the period (asym-
metrical PWM patterns).
for a CLKOUT frequency of 20 MHz.
PWM Switching Dead Time: PWMDT Register
The second important PWM block parameter that must be
initialized is the switching dead time. This is a short delay time
introduced between turning off one PWM signal (e.g., AH) and
turning on its complementary signal (e.g., AL). This short time
delay is introduced to permit the power switch being turned off to
completely recover its blocking capability before the comple-
mentary switch is turned on. This time delay prevents a potentially
destructive short circuit condition from developing across the dc
link capacitor of a typical voltage source inverter.
In the double update mode, operation in the first half or the
second half of the PWM cycle is indicated by Bit 3 of the
SYSSTAT Register. In double update mode, this bit is cleared
during operation in the first half of each PWM period (between
the rising edge of the original PWMSYNC pulse and the rising
edge of the new PWMSYNC pulse, which is introduced in
double update mode). Bit 3 of the SYSSTAT Register is set
during the second half of each PWM period. If required, a user
may determine the status of this bit during a PWMSYNC
interrupt service routine.
Dead time is controlled by the PWMDT Register. The dead
time is inserted into the three pairs of PWM output signals. The
dead time, TD, is related to the value in the PWMDT Register by:
PWMDT
TD = PWMDT × 2 ×TCK = 2 ×
fCLKOUT
Therefore, a PWMDT value of 0x00A (= 10) introduces a 1 µs
delay between the turn-off of any PWM signal (e.g., AH) and
the turn-on of its complementary signal (e.g., AL). The amount
of the dead time can therefore be programmed in increments of
2 TCK (or 100 ns for a 20 MHz CLKOUT). The PWMDT Register
is a 10-bit register. For a CLKOUT rate of 20 MHz its maximum
value of 0x3FF (= 1023) corresponds to a maximum programmed
dead time of:
The advantages of the double update mode are that lower
harmonic voltages can be produced by the PWM process and
wider control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service routine,
there is a larger computational burden on the DSP in the
double update mode.
TD max = 1023 × 2 ×TCK
= 1023 × 2 × 50 ×10−9 sec
= 102 µs
Width of the PWMSYNC Pulse: PWMSYNCWT Register
The PWM controller of the ADMCF340 produces an internal
PWM synchronization pulse at a rate equal to the PWM switching
frequency in single update mode and at twice the PWM frequency
in the double update mode. This PWMSYNC synchronizes the
operation of the PWM unit with the A/D converter system.
The width of this PWMSYNC pulse is programmable by the
PWMSYNCWT Register. The width of the PWMSYNC pulse,
The dead time can be programmed to zero by writing 0 to the
PWMDT Register.
PWM Operating Mode: MODECTRL and SYSSTAT Registers
The PWM controller of the ADMCF340 can operate in two
distinct modes: single update mode and double update mode.
The operating mode of the PWM controller is determined by
the state of Bit 6 of the MODECTRL Register. If this bit is
cleared, the PWM operates in the single update mode. Setting
Bit 6 places the PWM in the double update mode. By default,
following either a peripheral reset or power-on, Bit 6 of the
MODECTRL Register is cleared. This means that the default
operating mode is single update mode.
TPWMSYNC, is given by:
TPWMSYNC = TCK × PWMSYNCWT +1
(
)
REV. 0
–14–
ADMCF340
which means that the width of the pulse is programmable from TCK
to 256 TCK (corresponding to 50 ns to 12.8 µs for a CLKOUT
rate of 20 MHz). Following a reset, the PWMSYNCWT Register
contains 0x27 (= 39) so that the default PWMSYNC width is 2.0 µs.
Each switching edge is moved by an equal amount (PWMDT
× TCK) to preserve the symmetrical output patterns. The
PWMSYNC pulse, whose width is set by the PWMSYNCWT
Register, is also shown. Bit 3 of the SYSSTAT Register indicates
which half cycle is active. This can be useful in double update
mode, to be discussed later in this data sheet.
PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC
Registers
The duty cycles of the six PWM output signals are controlled by
the three duty cycle registers, PWMCHA, PWMCHB, and
PWMCHC. The integer value in the register PWMCHA controls
the duty cycle of the signals on AH and AL. PWMCHB controls
the duty cycle of the signals on BH and BL, and PWMCHC
controls the duty cycle of the signals on CH and CL. The duty cycle
registers are programmed in integer counts of the fundamental
time unit, TCK, and define the desired on-time of the high side
PWM signal produced by the three-phase timing unit over half the
PWM period. The switching signals produced by the three-phase
timing unit are also adjusted to incorporate the programmed dead
time value in the PWMDT Register.
The resultant on-times of the PWM signals shown in Figure 5
may be written as:
TAH = 2 ×(PWMCHA – PWMDT)×TCK
TAL = 2 ×(PWMTM – PWMCHA – PWMDT)×TCK
The corresponding duty cycles are:
TAH
TS
PWMCHA – PWMDT
dAH
=
=
PWMTM
TAL PWMTM – PWMCHA – PWMDT
dAL
=
=
The PWM is center-based. This means that in single update mode,
the resulting output waveforms are symmetrical and centered
in the PWMSYNC period. Figure 7 presents a typical PWM timing
diagram illustrating the PWM-related registers’ (PWMCHA,
PWMTM, PWMDT, and PWMSYNCWT) control over the
waveform timing in both half cycles of the PWM period. The
magnitude of each parameter in the timing diagram is determined by
multiplying the integer value in each register by TCK (typically
50 ns). It may be seen in the timing diagram how dead time is
incorporated into the waveforms by moving the switching edges
away from the original values set in the PWMCHA Register.
TS
PWMTM
Obviously, negative values of TAH and TAL are not permitted
because the minimum permissible value is zero, corresponding
to a 0% duty cycle. In a similar fashion, the maximum value is
TS, corresponding to a 100% duty cycle.
The output signals from the timing unit for operation in double
update mode are shown in Figure 8. This illustrates a completely
general case where the switching frequency, dead time, and duty
cycle are all changed in the second half of the PWM period. Of
course, the same value for any or all of these quantities could be
used in both halves of the PWM cycle. However, it can be seen
that there is no guarantee that symmetrical PWM signals will be
produced by the timing unit in this double update mode.
Additionally, it is seen that the dead time is inserted into the PWM
signals in the same way as in the single update mode.
PWMCHA PWMCHA
AH
2 ꢀ PWMDT
2 ꢀ PWMDT
AL
PWMCHA
PWMCHA
2
1
PWMSYNCWT + 1
PWMSYNC
AH
AL
SYSSTAT (3)
2 ꢀ PWMDT
2 ꢀ PWMDT
1
2
PWMTM
PWMTM
PWMSYNCWT + 1
1
PWMSYNCWT + 1
2
PWMSYNC
Figure 7. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode
SYSSTAT (3)
PWMTM
1
PWMTM
2
Figure 8. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode
REV. 0
–15–
ADMCF340
In general, the on-times of the PWM signals in double update
mode are defined by:
PWM signals similar to those illustrated in Figure 7 and Figure 8 can
be produced on the BH, BL, CH, and CL outputs by programming
the PWMCHB and PWMCHC Registers in a manner identical
to that described for PWMCHA.
TAH = (PWMCHA1 + PWMCHA2 – PWMDT1 – PWMDT2 ) × TCK
T
AL = (PWMTM1 + PWMTM2 – PWMCHA1 – PWMCHA2 –
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
Registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If during initialization, the PWMTM Register is written
before the PWMCHA, PWMCHB, and PWMCHC Registers, the
first PWMSYNC pulse (and interrupt if enabled) will be generated
(1.5 × TCK × PWMTM) seconds after the initial write to the
PWMTM Register in single update mode. In double update mode,
the first PWMSYNC pulse will be generated (TCK × PWMTM)
seconds after the initial write to the PWMTM Register in single
update mode.
PWMDT1 – PWMDT2) × TCK
TAH
TS
dAH
=
PWMCHA + PWMCHA
PWMTM1 + PWMTM2
1
2
=
PWMDT + PWMDT2
PWMTM1 + PWMTM2
1
−
Effective PWM Resolution
In single update mode, the same values of PWMCHA, PWMCHB,
and PWMCHC are used to define the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2 TCK (or 100 ns for a 20 MHz
CLKOUT) since incrementing one of the duty cycle registers by
one changes the resultant on-time of the associated PWM signals
by TCK in each half period (or 2 TCK for the full period).
TAL
TS
dAL
=
PWMTM + PWMTM + PWMCHA
(
)
1
2
1
=
PWMTM1 + PWMTM2
In double update mode, improved resolution is possible since
different values of the duty cycle registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of TCK. This corresponds to an effective
PWM resolution of TCK in double update mode (or 50 ns for a
20 MHz CLKOUT).
PWMCHA + PWMDT + PWMDT
(
)
2
1
2
–
PWMTM1 + PWMTM2
because of the completely general case in double update mode,
the switching period is given by:
T = PWNMTM + PWMTM × T
(
)
S
1
2
CK
Again, the values of TAH and TAL are constrained to lie between
zero and TS.
Table IV. Fundamental Characteristics of PWM Generation Unit of ADMCF340
16-BIT PWM TIMER
Parameter
Min
Typ
Max
Unit
Counter Resolution
16
100
50
Bits
ns
ns
µs
ns
µs
ns
Hz
µs
MHz
Edge Resolution (Single Update Mode)
Edge Resolution (Double Update Mode)
Programmable Dead Time Range
Programmable Dead Time Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
0
102
51
100
0
50
153
0.05
0.02
PWMSYNC Pulsewidth (TCRST
Gate Drive Chop Frequency Range
)
12.8
5
REV. 0
–16–
ADMCF340
The PWMSEG Register contains three crossover bits, one for each
pair of PWM outputs. Setting Bit 8 of the PWMSEG Register
enables the crossover mode for the AH/AL pair of PWM
signals; setting Bit 7 enables crossover on the BH/BL pair of
PWM signals; and setting Bit 6 enables crossover on the CH/CL
pair of PWM signals. If crossover mode is enabled for any pair
of PWM signals, the high side PWM signal from the timing unit
(for example, AH) is diverted to the associated low side output
of the output control unit so that the signal will ultimately
appear at the AL Pin. Of course, the corresponding low side
output of the timing unit is also diverted to the complementary
high side output of the output control unit so that the signal
appears at Pin AH. Following a reset, the three crossover bits
are cleared so that the crossover mode is disabled on all three
pairs of PWM signals.
Table V. Achievable PWM Resolution in Single and Double
Update Modes
Resolution Single Update Mode
Double Update Mode
(Bit)
PWM Frequency (kHz) PWM Frequency (kHz)
8
9
39.1
19.5
9.8
4.9
2.4
78.1
39.1
19.5
9.8
10
11
12
4.9
Minimum Pulsewidth: PWMPD Register
In many power converter switching applications, it is desirable
to eliminate PWM switching pulses shorter than a certain width.
It takes a finite time to both turn on and turn off modern power
semiconductor devices. Therefore, if the width of any of the
PWM pulses is shorter than some minimum value, it may be
desirable to completely eliminate the PWM switching for that
particular cycle.
The PWMSEG Register also contains six bits (Bits 0 to 5) that
can be used to individually enable or disable each of the six
PWM outputs. If the associated bit of the PWMSEG Register is
set, the corresponding PWM output is disabled regardless of the
value of the corresponding duty cycle register. This PWM output
signal will remain in the OFF state as long as the corresponding
enable/disable bit of the PWMSEG Register is set. The PWM
output enable function gates the crossover function. After a
reset, all six enable bits of the PWMSEG Register are cleared,
thereby enabling all PWM outputs by default.
The allowable minimum on-time for any of the six PWM outputs
for half a PWM period that can be produced by the PWM
controller may be programmed using the PWMPD Register.
The minimum on-time is programmed in increments of TCK so
that the minimum on-time produced for any half PWM period,
T
MIN, is related to the value in the PWMPD Register by:
In a manner identical to the duty cycle registers, the PWMSEG
is latched on the rising edge of the PWMSYNC signal so
that changes to this register only become effective at the start
of each PWM cycle in single update mode. In double update
mode, the PWMSEG Register can also be updated at the
midpoint of the PWM cycle.
TMIN = PWMPD × TCK
A PWMPD value of 0x002 defines a permissible minimum
on-time of 100 ns for a 20 MHz CLKOUT.
In each half cycle of the PWM, the timing unit checks the on-time
of each of the six PWM signals. If any of the times are found to be
less than the value specified by the PWMPD Register, the corre-
sponding PWM signal is turned OFF for the entire half period,
and its complementary signal is turned completely ON.
In the control of an ECM, only two inverter legs are switched at
any time, and often the high side device in one leg must be
switched ON at the same time as the low side driver in a second
leg. Therefore, by programming identical duty cycles for two
PWM channels (for example, let PWMCHA = PWMCHB) and
setting Bit 7 of the PWMSEG Register to crossover the BH/BL
pair of PWM signals, it is possible to turn ON the high side
switch of Phase A and the low side switch of Phase B at the
same time. In the control of an ECM, one inverter leg (Phase C
in this example) is disabled for a number of PWM cycles. This
disable may be implemented by disabling both the CH and CL
PWM outputs by setting Bits 0 and 1 of the PWMSEG Register.
This is illustrated in Figure 7, where it can be seen that both the
AH and BL signals are identical, because PWMCHA = PWMCHB,
and the crossover bit for Phase B is set. In addition, the other
four signals (AL, BH, CH, and CL) have been disabled by
setting the appropriate enable/disable bits of the PWMSEG
Register. For the situation illustrated in Figure 9, the appropriate
value for the PWMSEG Register is 0x00A7. In ECM operation,
because each inverter leg is disabled for a certain period of time,
the PWMSEG Register is changed based upon the position of
the rotor shaft (motor commutation).
Consider the example where PWMTM = 200, PWMCHA = 5,
PWMDT = 3, and PWMPD = 10 with a CLKOUT of 20 MHz,
while operating in single update mode. For this case, the PWM
switching frequency is 50 kHz and the dead time is 300 ns. The
minimum permissible on-time of any PWM signal over one-half
of any period is 500 ns. Clearly, for this example, the dead time
adjusted on-time of the AH signal for one-half a PWM period is
(5 – 3) × 50 ns = 100 ns. Because this is less than the minimum
permissible value, output AH of the timing unit will remain OFF
(0% duty cycle). Additionally, the AL signal will be turned ON
for the entire half period (100% duty cycle).
Output Control Unit: PWMSEG Register
The operation of the output control unit is managed by the 9-bit
read/write PWMSEG Register. This register sets two distinct
features of the output control unit that are directly useful in the
control of ECM or BDCM.
REV. 0
–17–
ADMCF340
PWMCHA = PWMCHB
TCHOP = 4 × GDCLK +1 ×T
(
)
]
CK
[
AH
2 ꢀ PWMDT
2 ꢀ PWMDT
fCLKOUT
AL
BH
BL
fCHOP
=
4 × GDCLK +1
(
)
]
[
The GDCLK value may range from 0 to 255, corresponding
to a programmable chopping frequency rate from 19.5 kHz to
5 MHz for a 20 MHz CLKOUT rate. The gate drive features
must be programmed before operation of the PWM controller
and typically are not changed during normal operation of the
PWM controller. Following a reset, by default, all bits of the
PWMGATE Register are cleared so that high frequency
chopping is disabled.
CH
CL
PWMTM
PWMTM
Figure 9. An example of PWM signals suitable for ECM
control. PWMCHA = PWMCHB, BH/BL are a crossover
pair. AL, BH, CH, and CL outputs are disabled. Operation
is in single update mode.
PWMCHA PWMCHA
2 ꢀ PWMDT
2 ꢀ PWMDT
Gate Drive Unit: PWMGATE Register
[4 ꢀ (GDCLK + 1) ꢀ tCK
]
The gate drive unit of the PWM controller adds features that
simplify the design of isolated gate drive circuits for PWM
inverters. If a transformer-coupled power device gate drive amplifier is
used, the active PWM signal must be chopped at a high frequency.
The PWMGATE Register allows the programming of this high
frequency chopping mode. The chopped active PWM signals
may be required for the high side drivers only, for the low side
drivers only, or for both the high side and low side switches.
Therefore, independent control of this mode for both high side
and low side switches is included with two separate control bits
in the PWMGATE Register.
PWMTM
PWMTM
Figure 10. Typical PWM signals with high frequency gate
chopping enabled on both high side and low side switches.
(GDCLK is the integer equivalent of the value in Bits 0 to
7 of the PWMGATE Register.)
PWM Polarity Control, PWMPOL Pin
The polarity of the PWM signals produced at the output pins
AH to CL may be selected in hardware by the PWMPOL Pin.
Connecting the PWMPOL Pin to DGND selects active LO PWM
outputs, such that a LO level is interpreted as a command to
turn on the associated power device. Conversely, connecting
the PWMPOL Pin to VDD selects active HI PWM and the asso-
ciated power devices are turned ON by a HI level at the PWM
outputs. There is an internal pull-up on the PWMPOL Pin, so
that if this pin becomes disconnected (or is not connected),
active HI PWM will be produced. The level on the PWMPOL
Pin may be read from Bit 2 of the SYSSTAT Register, where a
zero indicates a measured LO level at the PWMPOL Pin.
Typical PWM output signals with high frequency chopping
enabled on both high side and low side signals are shown in
Figure 10. Chopping of the high side PWM outputs (AH, BH,
and CH) is enabled by setting Bit 8 of the PWMGATE Register.
Chopping of the low side PWM outputs (AL, BL, and CL) is
enabled by setting Bit 9 of the PWMGATE Register. The high
chopping frequency is controlled by the 8-bit word (GDCLK)
written to Bits 0 to 7 of the PWMGATE Register. The period
and the frequency of this high frequency carrier are:
REV. 0
–18–
ADMCF340
SWITCHED RELUCTANCE MODE
voltage at any of the ISENSE pins exceeds the trip threshold
(high or low), PWMTRIP will be internally pulled low. The
negative edge of the internal PWMTRIP will generate a shut-
down in the same manner as a negative edge on pin PWMTRIP.
The PWM block of the ADMCF340 contains a switched reluc-
tance (SR) mode that is controlled by the PWMSR Pin. The
switched reluctance mode is enabled by connecting the PWMSR
Pin to DGND. In this SR Mode, the low side PWM signals
from the three-phase timing unit assume permanently ON
states, independent of the value written to the duty-cycle
registers. The duty cycles of the high side PWM signals from the
timing unit are still determined by the three duty cycle registers.
Using the crossover feature of the output control unit, it is possible
to divert the permanently ON PWM signals to either the high
side or low side outputs. This mode is necessary because in the
typical power converter configuration for switched or variable
reluctance motors, the motor winding is connected between the
two power switches of a given inverter leg. Therefore, in order
to build up current in the motor winding, it is necessary to turn
on both switches at the same time. Typical active LO PWM
signals during operation in SR Mode are shown in Figure 8 for
operation in double update mode. It is clear that the three low
side signals (AL, BL, and CL) are permanently ON and the
three high side signals are modulated in the usual manner so
that the corresponding high side power switches are switched
between the ON and OFF states. The SR Mode can only be
enabled by connecting the PWMSR Pin to GND. There are no
software means by which this mode can be enabled. There is
an internal pull-up resistor on the PWMSR Pin so that if this
pin is left unconnected or becomes disconnected the SR Mode is
disabled. Of course, the SR Mode is disabled when the PWMSR
In addition, it is possible through software to initiate a PWM
shutdown by writing to the 1-bit read/write PWMSWT Register
(0x2061). Writing to this bit generates a PWM shutdown in a
manner identical to the PWMTRIP or ISENSE pins. Following
a PWM shutdown, it is possible to determine if the shutdown
was generated from hardware or software by reading the same
PWMSWT Register. Reading this register also clears it.
Restarting the PWM after a fault condition is detected requires
clearing the fault and reinitializing the PWM. Clearing the fault
requires that PWMTRIP returns to a HI state. After the fault has
been cleared, the PWM can be restarted by writing to registers
PWMTM, PWMCHA, PWMCHB, and PWMCHC. After the fault
is cleared and the PWM Registers are initialized, internal timing of
the three-phase timing unit will resume, and the new duty cycle
values will be latched on the next rising edge of PWMSYNC.
PWM Registers
The configuration of the PWM Registers is described at the end
of the data sheet. The parameters of the PWM block are tabu-
lated in Table IV.
ADC OVERVIEW
The ADC of the ADMCF340 is based upon the single slope
conversion technique. This approach offers an inherently mono-
tonic conversion process within the noise and stability of its
components, and there will be no missing codes.
Pin is tied to VDD
.
PWM Shutdown
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down. Two methods of
sensing a fault condition are provided by the ADMCF340. For
the first method, a low level on the PWMTRIP Pin initiates
an instantaneous, asynchronous (independent of DSP clock)
shutdown of the PWM controller. This places all six PWM
outputs in the OFF state, disables the PWMSYNC pulse and
associated interrupt signal, and generates a PWMTRIP interrupt
signal. The PWMTRIP Pin has an internal pull-down resistor so
that even if the pin becomes disconnected, the PWM outputs will
be disabled. The state of the PWMTRIP Pin can be read from
Bit 0 of the SYSSTAT Register.
The single slope technique has been adopted on the ADMCF340
for four channels that are simultaneously converted. Refer to
Figure 11 for the functional schematic of the ADC. The main
inputs (V1, V2, and V3) are directly connected to the ADC
converter through three front end blocks. Figure 14 shows the
block diagram of a single front end block. Each front end block has
a bipolar current amplifier (gain = –2.5) designed to acquire the
voltage on a current-sensing resistor, whose voltage can be either
positive or negative with respect to the power supply ground rail.
The fourth channel has been configured with a serially connected
8-to-1 multiplexer. Table VI shows the multiplexer input selection
codes. One of these auxiliary multiplexed channels is used to acquire
the internal voltage reference (VREF) for calibration purpose.
The second method for detecting a fault condition is through the
ISENSE pins of the analog block of the ADMCF340. When the
REV. 0
–19–
ADMCF340
Single Slope ADC Operations
ICONST_TRIM
REG <2:0>
Comparing each ADC input to a reference ramp voltage and
timing the comparison of the two signals performs the conversion
process. The actual conversion point is the time point intersection
of the input voltage and the ramp voltage (VC) as shown in
Figure 12. This time is converted to counts by the 12-bit ADC
Timer Block and is stored in the ADC registers. The ramp
voltage used to perform the conversion is generated by driving a
fixed current into an off-chip capacitor, where the capacitor
voltage is:
FILTER
PWMTRIP
MODECTRL REG
<09..10..11>
ICONST
MODECTRL
REG <07>
VOLTAGE
CLK
CHANNEL1
V1
CURRENT
V1
COMP
VOLTAGE
CURRENT
CHANNEL2
CHANNEL3
V2
V3
V2
V3
COMP
COMP
V = I /C × t
(
)
C
VOLTAGE
CURRENT
Following reset, VC = 0 at t = 0. This reset and the start of the
conversion process are initiated by the PWMSYNC pulse, as
shown in Figure 12. The width of the PWMSYNC pulse is
controlled by the PWMSYNCWT Register and should be
programmed according to Figure 12 to ensure complete resetting.
VAUX0 (V)
VAUX1 (V)
VAUX2 (V)
12-BIT
ADC
VAUX0
VAUX1
VAUX2
TIMER
BLOCK
COMP
VAUX
8-1
VAUX4 (V)
VAUX5 (V)
VAUX6 (V)
VAUX7 (V)
VAUX4
VAUX5
VAUX6
VAUX7
MULTIPLEXER
In order to compensate for IC process manufacturing tolerances
(and to adjust for capacitor tolerances), the current source of the
ADMCF340 is software programmable. The software setting of the
magnitude of the ICONST current generator is accomplished by
selecting one of eight steps over approximately 20% current range.
ADC1
ADC2
ADC3
ADC
REGISTERS
VAUX3 (V)
ADCAUX
V
REF
MODECTRL REG <0..1>
ICONST
CAPACITOR
EXTERNALCHARGING
CAPACITOR
RESET
PWMSYNC (CONVST)
Figure 11. ADC Overview
Table VI. ADC Auxiliary Channel Selection
MODECTRL(5)
ADCMUX
MODECTRL(1)
ADCMUX1
MODECTRL(0)
ADCMUX0
Select
VAUX0
VAUX1
VAUX2
VAUX3 Calibration (VREF
VAUX4
VAUX5
VAUX6
VAUX7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
)
Table VII. Port A Multiplexing
PORTA Pin
First Alternate Function (Peripheral)
Second Alternate Function (Peripheral)
PORTA8
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
AUX0 (Auxiliary PWM Output)
AUX1 (Auxiliary PWM Output)
DR1 (Data Receive SPORT1)
FL1 (Flag Out SPORT1)
SCLK1 (Serial Clock SPORT1)
TFS0 (Transmit Frame Sync SPORT0)
RFS0 (Receive Frame Sync SPORT0)
DT0 (Data Transmit SPORT0)
DR0 (Data Receive SPORT0)
CLKOUT (System CLOCK)
PWMSYNC (PWM)
None
DT1 (Data Transmit SPORT1)
SCLK0 (Serial Clock SPORT0)
None
None
None
None
REV. 0
–20–
ADMCF340
20 MHz and PWMSYNC pulsewidth of 2.0 µs, the effective
resolution of the ADC block is tabulated for various PWM
switching frequencies in Table VIII.
V
C
V
CMAX
V1
Table VIII. ADC Resolution Examples
PWM
Frequency Max
MODECTRL[7] = 0
MODECTRL[7] = 1
Effective
Max
Effective
V
VIL
t
(kHz)
Count
Resolution
Count
Resolution
T
VIL
2.4
4
8
18
25
4095
2480
1230
535
12
4095
4095
2460
1070
760
12
12
>11
>10
>9
T
CRST
>11
>10
>9
T
– T
CRST
PWM
PWMSYNC
380
>8
COMPARATOR
OUTPUT
Programmable Current Source
The ADMCF340 has an internal current source that is used to
charge an external capacitor, generating the voltage ramp used for
conversion. The magnitude of the output of the current source circuit is
subject to manufacturing variations and can vary from one device to
the next. Therefore, the ADMCF340 includes a programmable
current source whose output can always be tuned to within 5% of
the target 100 µA. A 3-bit register, ICONST_TRIM, allows the
user to make this adjustment. The output current is proportional to
the value written to the register: 0x0 produces the minimum output,
and 0x7 produces the maximum output. The default value of
ICONST_TRIM after reset is 0x0.
Figure 12. Analog Input Block Operation
The ADC system consists of four comparators and a single
timer that may be clocked at either the DSP rate or half the
DSP rate, depending on the setting of the ADCCNT bit (Bit 7)
of the MODECTRL Register. When this bit is cleared, the
timer counts at a slower rate of CLKIN. When this bit is set, the
timer counts at CLKOUT or twice the rate of CLKIN. ADC1,
ADC2, ADC3, and ADCAUX are the registers that capture the
conversion times, which are the timer values when the associ-
ated comparator trips.
Suggested implementations of the calibration routine are pro-
vided through Application Notes and code that can be found by
visiting www.analog.com/motorcontrol.
100
Charging Capacitor Selection
The charging capacitor value is selected based on the sample
(PWM) frequency desired. Too small a capacitor value will re-
duce the available resolution of the ADC by having the ramp voltage
rise rapidly and convert too quickly, not utilizing all possible counts
available in the PWM cycle. Too large a capacitor may not convert in
the available PWM cycle returning 0x000. To select a charging capaci-
tor, use Figure 13, select the sampling frequency desired, determine
if the current source is to be tuned to a nominal 100 µA or left in
the default (0x0 code) trim state, then determine the proper charge
capacitor off the appropriate curve.
10
TUNED I
CONST
DEFAULT I
CONST
1
1
10
100
VOLTAGE
Figure 13. Timing Capacitor Selection
ADC Resolution
TRIP
The ADC is intrinsically linked to the PWM block through the
PWMSYNC pulse controlling the ADC conversion process.
Because of this link, the effective resolution of the ADC is a
function of both the PWM switching frequency and the rate at
which the ADC counter timer is clocked. For a CLKOUT
period of TCK and a PWM period of TPWM, the maximum count
of the ADC is given by:
TRIP REF HIGH
(TO PWMTRIP FILTER)
OVERCURRENT
COMPARATOR
TRIP REF LOW
VxL
(TO ADC)
CURRENT
SHA
–25x
PWMSYNC
CLOCKOUT
Max Count = min 4095, T
− TCRST / 2T
(
)
(
)
PWM
CK
SHA
STATE
for MODECTRL Bit 7 = 0
MACHINE
SHA TIMER
COUNTER
Max Count = min 4095, T
− TCRST / T
(
)
(
)
PWM
CK
ADC CONVERSION
STATUS BIT
(ADC REGISTER)
SHA TIMER
REGISTER
for MODECTRL Bit 7 = 1
Where TPWM is equal to the PWM period if operating in single
update mode, or it is equal to half that period if operating in
double update mode. For an assumed CLKOUT frequency of
MODECTRL REGISTER
CHANNEL SELECTION (I
/V)
SENSE
Figure 14. Analog Front End Block Diagram
REV. 0
–21–
ADMCF340
Analog Front End
The main analog inputs of the ADMCF340 (ISENSE1 through
cycle. Each channel has an independent amplifier, SHA, and
SHA timing unit/state machine. Figure 15 shows a conversion
sequence of a single channel.
I
SENSE3) are connected to the ADC converter through three
front end blocks. Figure 14 shows the block diagram of a single
analog front end.
At the beginning of the cycle N (rising edge of PWMSYNC
signal (1)), the Timer Counter is loaded with the value con-
tained in the SHA_CNT Register. After the Timer Counter has
been reloaded, it starts counting down at the CLKOUT rate; in
this phase the SHA state-machine forces the SHA in TRACK
(sample) status.
Each analog front end has two analog inputs: voltage and
current. A 2-to-1 multiplexer selects which input will be
converted; the multiplexer selection is determined by the
MODECTRL Register.
The current input (ISENSE) is amplified through a bipolar amplifier
(Gain –2.5). There is an output offset that matches the amplifier
output signal range to the input signal range of the A/D converter.
The amplifier has a built-in over current and open circuit protec-
tion. The over current protection shuts down the PWM block
when the voltage at any of the ISENSE pins exceeds the trip thresh-
old (high or low). The open-circuit protection shuts down the
PWM block when any of the ISENSE inputs is in high impedance
(for example the current sense resistor or the current transducer
is disconnected). The shut-down signals generated by the amplifi-
ers are then OR-ed and filtered in order to avoid spurious trip
caused by the switching of the power devices. The amplifier is
followed by a sample-and-hold amplifier (SHA). The SHA time
is user-programmable through the SHA Timer Register. The
sampling time is set as a delay from the rising edge of the
PWMSYNC signal and is calculated as:
When the counter reaches the value of 0x0000 (after the time
TSAMPLE from the rising edge of PWMSYNC), the SHA state-
machine forces the SHA in HOLD status.
The conversion of the sampled value is then taking place in the
cycle N + 1 (from (4) to (5)) in Figure 16 and the result of the
conversion is available on the ADC Register at the cycle N + 2
(rising edge of PWMSYNC (5)).
On cycle N + 2, the reload value of the Timer Counter exceeds the
period of the PWMSYNC signal. In this case the SHA state ma-
chine forces the SHA in HOLD status at the rising edge of
PWMSYNC of the next cycle (7). The conversion then takes place
on cycle N + 3 and the conversion result is available on the ADC
Register at the cycle N + 4 (rising edge of PWMSYNC (9)).
During the acquire phase (the PWMSYNC cycle during the
sampling of the input value) the conversion takes place. How-
ever, the value on the ADC Register is not considered valid.
This condition is signaled by the ADC by setting the LSB of the
ADC Register to high.
TSAMPLE = SHA_CNT + 2 × T
(
)
CK
The SHA Timer Counter has a minimum reload value of 0x0003,
which ensures a minimum settling time of the SHA output in
case the user is programming the SHA Timer Register to a value
smaller than 0x0003. This means that the sampling time is program-
mable from 5 TCK to 65535 TCK (corresponding to 250 ns to
3.28 ms for a CLKOUT rate of 20 MHz). The sampling time,
however, is limited to the rising edge of the following PWMSYNC
On cycle N + 4, at the rising edge of the PWMSYNC signal (9),
the Timer Counter is reloaded with a value smaller than the
PWMSYNC pulsewidth. In this case the SHA samples within
the PWMSYNC pulsewidth and the conversion takes place in
the same PWMSYNC cycle (from (10) to (11)).
1
2
3
4
5
6
7
8
9
10
11 12
CYCLE
N + 4
N + 5
N – 1
N
N + 1
N + 2
N + 3
PWMSYNC
VC
T
SAMPLE
T
SAMPLE
T
SAMPLE
SHA TIMER
COUNTER
T
SAMPLE
TRACK
H
SHA STATUS
ISENSE INPUT
X
T
H
T
H
T
H
S
S
S
S
DATA READY
SAMPLED ON
CYCLE N – 2
DATA READY
SAMPLED ON
CYCLE N
DATA READY DATA READY
SAMPLED ON SAMPLED ON
INVALID
LSB = 1
INVALID
LSB = 1
ADC REGISTER
CYCLE N + 2
CYCLE N + 4
Figure 15. ADC Conversion Sequence of a Current Input
–22–
REV. 0
ADMCF340
Table IX. Fundamental Characteristics of Auxiliary PWM Timer of ADMCF340
Parameter
Test Conditions
Min
Typ
Max
Unit
Resolution
PWM Frequency
16
Bits
MHz
10 MHz CLKIN
0.152
AUXILIARY PWM TIMERS
Overview
However in this mode, the AUXTM1 Register defines the offset
time from the rising edge of the signal on the AUX0 Pin to that
on the AUX1 Pin according to:
The ADMCF340 provides two variable frequency, variable duty
cycle, 16-bit, auxiliary PWM outputs that are available at the
AUX1 and AUX0 Pins. When enabled, these auxiliary PWM
outputs can be used to provide switching signals to other circuits in
a typical motor control system such as power factor corrected
front-end converters or other switching power converters. Alterna-
tively, by addition of a suitable filter network, the auxiliary PWM
output signals can be used as simple single-bit digital-to-analog
converters, which is shown in Figure 16. The auxiliary PWM
system of the ADMCF340 can operate in two different modes:
independent mode or offset mode. The operating mode of the
auxiliary PWM system is controlled by Bit 8 of the MODECTRL
Register. Setting Bit 8 of the MODECTRL Register places the
auxiliary PWM system in the independent mode. In this mode,
the two auxiliary PWM generators are completely independent
and separate switching frequencies and duty cycles may be
programmed for each auxiliary PWM output. In this mode, the
16-bit AUXTM0 Register sets the switching frequency of the
signal at the AUX0 output pin. Similarly, the 16-bit AUXTM1
Register sets the switching frequency of the signal at the AUX1
pin. The fundamental time increment for the auxiliary PWM
outputs is twice the DSP instruction rate (or 2 TCK) and the
corresponding switching periods are given by:
TOFFSET = 2 × AUXTM1+ 1 × T
(
)
CK
For correct operation in this mode, the value written to the
AUXTM1 Register must be less than the value written to the
AUXTM0 Register. Typical auxiliary PWM waveforms in offset
mode are shown in Figure 17(b). Again, duty cycles from 0% to
100% are possible in this mode.
In both operating modes, the resolution of the auxiliary PWM
system is 16 bits only at the minimum switching frequency
(AUXTM0 = AUXTM1 = 65535 in independent mode,
AUXTM0 = 65535 in offset mode). Obviously, as the switching
frequency is increased, the resolution is reduced.
Values can be written to the auxiliary PWM Registers at any
time. However, new duty cycle values written to the AUXCH0
and AUXCH1 Registers only become effective at the start of the
next cycle. Writing to the AUXTM0 or AUXTM1 Registers
causes the internal timers to be reset to 0 and new PWM cycles
to begin. By default following a reset, Bit 8 of the MODECTRL
Register is cleared, thus enabling offset mode. In addition, the
registers AUXTM0 and AUXTM1 default to 0xFFFF, corre-
sponding to the minimum switching frequency and zero offset.
The on-time registers AUXCH0 and AUXCH1 default to 0x0000.
TAUX 0 = 2 × AUXTM0 + 1 × T
(
)
CK
AUXPWM
R1
R2
C1
TAUX1 = 2 × AUXTM1+ 1 × T
(
)
CK
Since the values in both AUXTM0 and AUXTM1 can range
from 0 to 0xFFFF, the achievable switching frequency of the
auxiliary PWM signals may range from 152.59 Hz to 10 MHz
for a CLKOUT frequency of 20 MHz. The on-time of the two
auxiliary PWM signals is programmed by the two 16-bit AUXCH0
and AUXCH1 Registers, according to:
C2
R1 = R2 = 13kꢂ
C1 = C2 = 10nF
Figure 16. Auxiliary PWM Output Filter
Auxiliary PWM Interface, Registers and Pins
The registers of the auxiliary PWM system are summarized at
the end of the data sheet.
TON, AUX0 = 2 × AUXCH0 × T
(
)
CK
TON, AUX1 = 2 × AUXCH1 × T
(
)
CK
so that output duty cycles from 0% to 100% are possible. Duty
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in independent
mode are shown in Figure 17(a). When Bit 8 of the MODECTRL
Register is cleared, the auxiliary PWM channels are placed in
offset mode. In offset mode, the switching frequency of the two
signals on the AUX0 and AUX1 Pins are identical and controlled
by AUXTM0 in a manner similar to that previously described
for independent mode. In addition, the on times of both the
AUX0 and AUX1 signals are controlled by the AUXCH0 and
AUXCH1 Registers as before.
2 ꢀ (AUXTM0 + 1)
2 ꢀ AUXCH0
AUX0
2 ꢀ (AUXTM1 + 1)
2 ꢀ AUXCH1
AUX1
2 ꢀ AUXCH1
(a) Independent Mode
REV. 0
–23–
ADMCF340
When a pin is operating as PIO, its direction can be set through
the corresponding bit of the data direction register (PORTA_DIR
or PORTB_DIR).
2 ꢀ (AUXTM0 + 1)
2 ꢀ AUXCH0
AUX0
AUX1
Clearing any bit of the data direction register configures the
corresponding PIO as input while setting the bit configures the
PIO as output.
2 ꢀ (AUXTM0 + 1)
Following a power-on or reset, all bits or PORTA_DIR and
PORTB_DIR are cleared, configuring all the PIO lines as inputs.
2 ꢀ AUXCH1
The data of the PIOs is controlled by the data registers
(PORTA_DATA and PORTB_DATA). These registers can be
used to read data from those PIOs configured as input and write
data to those configured as outputs.
2 ꢀ (AUXTM1 + 1)
(b) Offset Mode
Figure 17. Typical Auxiliary PWM Signals (All Times in
Increments of TCK
)
Each PIO can be individually programmed to be an interrupt
source by setting the corresponding bit of the interrupt enable
register (PORTA_INTEN and PORTB_INTEN). To generate
an interrupt, the corresponding bit on the data register
(PORTA_DATA and PORTB_DATA) must change state
(high-to-low or low-to-high transition). The transition can be on
the corresponding pin (PIO configured as input) or by writing
into the corresponding bit of the data register (PIO configured as
output).
WATCHDOG TIMER
The ADMCF340 incorporates a watchdog timer that can perform
a full reset of the DSP and motor control peripherals in the event
of software error. The watchdog timer is enabled by writing a
timeout value to the 16-bit WDTIMER Register. The timeout
value represents the number of CLKIN cycles required for the
watchdog timer to count down to zero. When the watchdog timer
reaches zero, a full DSP core and motor control peripheral reset
is performed. In addition, Bit 1 of the SYSSTAT Register is set
so that after a watchdog reset, the ADMCF340 can determine
that the reset was due to the timeout of the watchdog timer
and not an external reset. Following a watchdog reset, Bit 1 of
the SYSSTAT Register may be cleared by writing zero to the
WDTIMER Register. This clears the status bit but does not
enable the watchdog timer.
Following a change of state on the data register on a PIO
configured as interrupt source the corresponding bit is set in
the flag register (PORTA_FLAG and PORTB_FLAG) and a
common PIO interrupt is generated.
Reading the flag register is possible to determine which PIO has
generated the interrupt. Reading the flag register automatically
clears all the bits of the register. Following a power-on or reset,
all bits of the interrupt enable registers are cleared (no interrupt
enabled).
On reset, the watchdog timer is disabled and is only enabled
when the first timeout value is written to the WDTIMER Register.
To prevent the watchdog timer from timing out, the user must write
to the WDTIMER Register at regular intervals (shorter than the
programmed WDTIMER period value). On all but the first write
to WDTIMER, the particular value written to the register is
unimportant, since writing to WDTIMER simply reloads the first
value written to this register.
Each PIO line has an internal pull-down resistor so that following
a power-on or reset all the PIO lines will be read as logic lows
if left unconnected.
Once a pin has been selected as PIO function, it can be set as
input, output, and interrupt source (either configured as
input or output).
PIO Registers
PROGRAMMABLE DIGITAL INPUT/OUTPUT
The ADMCF340 has 25 programmable digital input/output
(PIO) pins. These pins are organized in two separate ports:
PORTA (nine pins) and PORTB (16 pins).
The configuration of all registers of the PIO system is shown at
the end of the data sheet.
INTERRUPT CONTROL
The nine pins of PORTA are multiplexed with other on-chip
peripheral functions. PORTB has 16 pins that are dedicated to
the digital I/O function only.
The ADMCF340 can respond to 34 different interrupt sources
with minimal overhead. Seven of these interrupts are internal
DSP core interrupts and 27 are from the on-chip peripherals.
The seven DSP core interrupts are SPORT0 receive and trans-
mit, SPORT1 receive (or IRQ0 ) and transmit (or IRQ1), the
internal timer, and two software interrupts. The Motor Control
interrupts are the 25 PIOs and two from the PWM block
(PWMSYNC pulse and PWMTRIP). All the on-chip peripherals
interrupts are multiplexed into the DSP core via the peripheral
IRQ2 interrupt. They are also internally prioritized and individually
maskable. The start address in the interrupt vector table for the
ADMCF340 interrupt sources is shown in Table X. The interrupts
are listed from high priority to the lowest priority. The
PWMSYNC interrupt is triggered by a low-to-high transition on the
PWMSYNC pulse. The PWMTRIP interrupt is triggered on a high-
to-low transition on the PWMTRIP pin. A PIO interrupt is detected
on any change of state (high-to-low or low-to-high) on the PIO lines.
Each bit of PORTA can be individually selected as PIO or the
alternate function through PORTA_SELECT Register. Bit 0 of
PORTA_SELECT controls the operation of the PA0 Pin, Bit 1
controls the operation of PA1 and so on. Setting the appropriate
bit in the PORTA_SELECT Register causes the corresponding
pin to be configured as PIO. Clearing the bit selects the alternate
function of the corresponding pin. Following a power-on or reset,
all bits of PORTA_SELECT are set such that PIO functionality
is selected. The second alternate function of PA7 is selected by
Bit 14 of the PORTA_SELCT Register. The second alternate
function of PA8 is selected by Bit 15 of PORTA_SELECT
Register. The second alternate function of PA4 and PA5 is selected
by Bit 4 of MODECTRL Register (SPORT1 Mode: Boot/UART).
REV. 0
–24–
ADMCF340
The entire interrupt control system of the ADMCF340 is config-
ured and controlled by the IFC, IMASK, and ICNTL Registers of
the DSP core and the IRQFLAG Register for the PWMSYNC
and PWMTRIP interrupts and PORTA_FLAG Register for the
PIO interrupts.
the interrupt controller automatically jumps to the appropriate
location in the interrupt vector table. At this point, a JUMP
instruction to the appropriate ISR is required. Motor control
peripheral interrupts are slightly different. When a peripheral
interrupt is detected, a bit is set in the IRQFLAG Register for
PWMSYNC and PWMTRIP or in the PORTA_FLAG Register
for a PIO interrupt, and the IRQ2 line is pulled low until all
pending interrupts are acknowledged. The DSP software must
determine the source of the interrupts by reading IRQFLAG
register. If more than one interrupt occurs simultaneously, the
higher priority interrupt service routine is executed. Reading the
IRQFLAG Register clears the PWMTRIP and PWMSYNC bits
and acknowledges the interrupt, thus allowing further interrupts
when the ISR exits. A user’s PIO interrupt service routine must
read the PORTA_FLAG Register to determine which PIO port
is the source of the interrupt. Reading register PORTA_FLAG
clears all bits in the registers and acknowledges the interrupt,
thus allowing further interrupts after the ISR exits. The configu-
ration of all these registers is shown at the end of the data sheet.
Table X. Interrupt Vector Addresses
Interrupt Source
Interrupt Vector Address
PWMTRIP
Peripheral Interrupt (IRQ2)
PWMSYNC
0x002C (Highest Priority)
0x0004
0x000C
PIO
0x0008
Software Interrupt 1
Software Interrupt 0
SPORT0 Transmit Interrupt
SPORT0 Receive Interrupt
0x0018
0x001C
0x0010
0x0014
SPORT1 Transmit Interrupt (or IRQ1) 0x0020
SPORT1 Receive Interrupt (or IRQ0) 0x0024
Timer
0x0028 (Lowest Priority)
SYSTEM CONTROLLER
The system controller block of the ADMCF340 performs the
following functions:
Interrupt Masking
Interrupt masking (or disabling) is controlled by the IMASK
Register of the DSP core. This register contains individual bits
that must be set to enable the various interrupt sources. If any
peripheral interrupt is to be enabled, the IRQ2 interrupt enable
bit (Bit 9) of the IMASK Register must be set. The configura-
tion of the IMASK Register of the ADMCF340 is shown at the
end of the data sheet.
1. Manages the interface and data transfer between the DSP
core and the motor control peripherals
2. Handles interrupts generated by the motor control peripherals
and generates a DSP core interrupt signal IRQ2
3. Controls the ADC multiplexer select lines
Interrupt Configuration
4. Enables PWMTRIP and PWMSYNC interrupts
5. Controls the multiplexing of the SPORT1 and SPORT0 pins
6. Controls the PWM single/double update mode
The IFC and ICNTL Registers of the DSP core control and
configure the interrupt controller of the DSP core. The IFC
Register is a 16-bit register that may be used to force and/or clear
any of the eight DSP interrupts. Bits 0 to 7 of the IFC Register
may be used to clear the DSP interrupts while Bits 8 to 15 can
be used to force a corresponding interrupt. Writing to Bits 11
and 12 in IFC is the only way to create the two software interrupts.
The ICNTL Register is used to configure the sensitivity (edge or
level) of the IRQ0, IRQ1, and IRQ2 interrupts and to enable/
disable interrupt nesting. Setting Bit 0 of ICNTL configures the
IRQ0 as edge-sensitive, while clearing the bit configures it for
level-sensitive. Bit 1 is used to configure the IRQ1 interrupt and
Bit 2 is used to configure the IRQ2 interrupt. It is recommended
that the IRQ2 interrupt always be configured for level-sensitive
as this ensures that no peripheral interrupts are lost. Setting Bit 4
of the ICNTL Register enables interrupt nesting. The configura-
tion of both IFC and ICNTL Registers is shown at the end of
the data sheet.
7. Controls the ADC conversion time modes and the
SHA timers
8. Controls the auxiliary PWM operation mode
9. Contains a status register (SYSSTAT) that indicates the
state of the PWMTRIP Pin, the watchdog timer, and the
PWM timer
10. Performs a reset of the motor control peripherals and
control registers following a hardware, software, or watch-
dog initiated reset
SPORT1 and SPORT0 Control
The ADMCF340 has two serial ports: SPORT0 and SPORT1.
SPORT1 is available with a limited number of pins and is mainly
intended as a secondary port for Development Tools interfacing
and/or for Code Booting from an external serial memory.
Figure 18 shows the internal multiplexing of the SPORT0 and
SPORT1 signals. SPORT0 is intended as general-purpose
communication port. SPORT0 can support the following
operating modes: SPORT, UART, and SPI.
INTERRUPT OPERATION
Following a reset, the ROM code on the ADMCF340 must copy a
default interrupt vector table into program memory RAM from
address 0x0000 to 0x002F. Since each interrupt source has a
dedicated four word space in this vector table, it is possible to
code short interrupt service routines (ISR) in place. Alterna-
tively, it may be necessary to insert a JUMP instruction to the
appropriate start address of the interrupt service routine if more
memory is required for the ISR. When an interrupt occurs, the
program sequencer ensures that there is no latency (beyond
synchronization delay) when processing unmasked interrupts. In
the case of the Timer, SPORT0, SPORT1 and software interrupts,
SPORT1 Configuration
There are two operating modes for SPORT1: Boot Mode and
UART Mode. These modes are selectable through Bit 4 of
MODECTRL Register. With SPORT1 in Boot Mode, SPORT1
serial clock (SCLK1) is externally available through the SCLK1/
SCLK0 pin. The signal SCLK1 is used to drive the external
serial memory input clock.
REV. 0
–25–
ADMCF340
Also SPORT1 Flag signal (FL1) is externally available through
the FL1/DT1 Pin. This signal is used to drive the external serial
memory input reset.
SPORT0 can be configured to operate as master SPI interface.
The SPI Mode is set through Bit 14 of MODECTRL Register.
When SPORT0 is configured as SPI interface, the SPORT I/O
pins assume the configuration shown in Table XI.
With SPORT1 configured in UART Mode, the SPORT0 serial
clock (SCLK0) is externally available through the SCLK1/
SCLK0 Pin. The SPORT1 data transmit (DT1) is externally
available through the FL1/DT1 Pin.
The Slave Select Pin automatically generates the select signal at
each word transfer. This pin can also be used as a general purpose
I/O during the SPI transfer without affecting the SPORT operations.
SPORT0 Configuration
SPORT0 can be configured in the following modes:
The SPI clock polarity and phase are configurable through
Bits 13 and 12 of MODECTRL Register. The SPI transfer using
clock phase is shown in Figure 19 and Figure 20.
SPORT Mode
UART Mode
SPI Mode
SPORT0 can be configured for UART Mode. In this mode,
the DR0 and RFS0 signals of the internal serial port are
connected together.
MODECTRL REGISTER (04)
SPORT1 BOOT MODE/UART MODE
DT1/FL1
DR1
DT1
FL1
TFS1
DSP
CORE
SPORT1
RFS1
DR1
SCLK1
SCLK1/SCLK0
SCLK0
DT0
DT0
SPI
CONTROL
BLOCK
DR0
TFS0
DR0
DSP
CORE
SPORT0
TFS0
RFS0
RFS0
MODECTRL REGISTER (15)
SPORT0 SPORT MODE/UART MODE
ADMCF340
MODECTRL REGISTER (14..13..12)
SPORT0 SPI INTERFACE CONTROL
Figure 18. SPORT0 and SPORT1 Internal Multiplexing (Simplied Diagram)
REV. 0
–26–
ADMCF340
Table XI. SPORT0 Pin Assignment in SPI Mode
SPI Mode
SPORT I/O Signal
SPI MODE I/O
DT0 (Data Transmit)
DR0
TFS0
RFS0
SCLK0
MOSI (Master Output/Slave Input)
MISO (Master Input Slave Output)
SS (Slave Select)
Unused
SCK (Serial Clock)
Output
Input
Output
N/A
Output
SCK CYCLE #
1
2
3
4
5
N
SCK (POLARITY = 0)
SCK (POLARITY = 1)
SS
MOSI
MISO
SEE NOTE 1
SEE NOTE 2
NOTE
MSB
MSB
LSB
LSB
1. LSB OF PREVIOUSLY TRANSMITTED WORD
2. UNDEFINED
Figure 19. SPI Transfer Using Clock Phase CPHA = 0
SCK CYCLE #
1
2
3
4
5
N
SCK (POLARITY = 0)
SCK (POLARITY = 1)
SS
MOSI
MISO
SEE NOTE 1
SEE NOTE 2
MSB
MSB
LSB
LSB
NOTE
1. LSB OF PREVIOUSLY TRANSMITTED WORD
2. UNDEFINED
Figure 20. SPI Transfer Using Clock Phase CPHA = 1
REV. 0
–27–
ADMCF340
Table XII. Peripheral Register Map
Bits Used
Address
(HEX)
Name
Function
0x2000
0x2001
0x2002
0x2003
0x2004
0x2005
0x2006
0x2007
0x2008
0x2009
0x200A
0x200B
0x200C
0x200D
0x200E
0x200F
0x2010
0x2011
0x2012
0x2013
0x2014
0x2015
0x2016
0x2017
0x2018
0x2019 . . . 43
0x2044
0x2045
0x2046
0x2047
0x2048
0x2049
0x204A . . . 5F
0x2060
0x2061
0x2062 . . . 67
0x2068
0x2069
0x206A
0x206B
0x2070
0x2080
0x2081
0x2082
0x2083
0x2084 . . . FF
ADC1
ADC2
ADC3
ADCAUX
PORTA_DIR
PORTA_DATA
PORTA_INTEN
PORTA_FLAG
PWMTM
[15 . . . 4]
[15 . . . 4]
[15 . . . 4]
[15 . . . 4]
[8 . . . 0]
[8 . . . 0]
[8 . . . 0]
[8 . . . 0]
[15 . . . 0]
[9 . . . 0]
[9 . . . 0]
[9 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[8 . . . 0]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
ADC Results for V1/ISENSE
ADC Results for V2/ISENSE
1
2
ADC Results for V3/ISENSE3
ADC Results for VAUX
PA8...PA0 Pins Direction Setting
PA8...PA0 Pins Input/Output Data
PA8...PA0 Pins Interrupt Enable
PORTA Pins Interrupt Status
PWM Period
PWMDT
PWMPD
PWM Dead Time
PWM Pulse Deletion Time
PWM Gate Drive Configuration
PWM Channel A Pulsewidth
PWM Channel B Pulsewidth
PWM Channel C Pulsewidth
PWM Segment Select
AUX PWM Output 0
AUX PWM Output 1
Auxiliary PWM Frequency Value
Auxiliary PWM Frequency Value/Offset
Reserved
PWMGATE
PWMCHA
PWMCHB
PWMCHC
PWMSEG
AUXCH0
AUXCH1
AUXTM0
AUXTM1
MODECTRL
SYSSTAT
IRQFLAG
[8 . . . 0]
[3 . . . 0]
[1 . . . 0]
[15 . . . 0]
Mode Control Register
System Status
Interrupt Status
Watchdog Timer
WDTIMER
Reserved
PORTB_DIR
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
PB15...PB0 Pin Direction Setting
PB15...PB0 Data and Mode Control
PB15...PB0 Pin Interrupt Enable
PB15...PB0 Pin Interrupt Status
Reserved
PIO Mode Select
Reserved
PWMSYNC Pulsewidth
PWM S/W Trip Bit
Reserved
ICONST_TRIM
Sample and Hold Timer
Sample and Hold Timer
Sample and Hold Timer
Reserved
Flash Memory Control Register
Flash Memory Address Register
Flash Memory Data Register High
Flash Memory Data Register Low
Reserved
PORTB_DATA
PORTB_INTEN
PORTB_FLAG
PORTA_SELECT
[15 . . . 0]
PWMSYNCWT
PWMSWT
[7 . . . 0]
[0]
ICONST_TRIM
SHA1_TM
SHA2_TM
[2. . .0]
[15...0]
[15...0]
[15...0]
SHA3_TM
FMCR
FMAR
FMDRH
FMDRL
[15. . .0]
[11. . .0]
[13. . .0]
[15. . .0]
REV. 0
–28–
ADMCF340
Table XIII. DSP Core Registers
Bits
Address
Name
Function
0x3FFA
0x3FF9
0x3FF8
0x3FF7
0x3FF6
0x3FF5
0x3FF4
0x3FF3
0x3FF2
0x3FFF
0x3FFE
0x3FFD
0x3FFC
0x3FFB
0x3FFA . . . F3
0x3FF2
0x3FF1
0x3FF0
0x3FEF
SPORT0_Rx_Words1
SPORT0_Rx_Words0
SPORT0_Tx_Words1
SPORT0_Tx_Words0
SPORT0_Ctrl_Reg
SPORT0_Sclkdiv
SPORT0_Rfsdiv
SPORT0_Autobuf Ctrl
SPORT1_Ctrl_Reg
SYSCNTL
MEMWAIT
TPERIOD
TCOUNT
TSCALE
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[7 . . . 0]
Multichannel Receive Word Enables
Multichannel Receive Word Enables
Multichannel Transmit Word Enables
Multichannel Transmit Word Enables
Control Register
Serial Clock Divide Modulus
Receive Frame Sync Divide Modulus
Autobuffer Control Register
Control Register
System Control Register
Memory Wait State Control Register
Interval Timer Period Register
Interval Timer Count Register
Interval Timer Scale Register
Reserved
SPORT1_CTRL_REG
SPORT1_SCLKDIV
SPORT1_RFSDIV
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
SPORT1 Control Register
SPORT1 Clock Divide Register
SPORT1 Receive Frame Sync Divide
SPORT1 Autobuffer Control Register
SPORT1_AUTOBUF_CTRL
[15 . . . 0]
REV. 0
–29–
ADMCF340
FLASH MEMORY CONTROL REGISTER
15 14 13 12 11 10
9
8
7
6
5
4
3
0
2
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0x2080
BOOT-FROM-FLASH-CODE
FLASH MEMORY ADDRESS REGISTER
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x2081
ADDRESS 11 Ϸ 0
RESERVED
ALWAYS READ 0
FLASH MEMORY DATA REGISTER LOW (FMDRL)
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0
0
0x2083
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STATUS 5–0
DATA 7–0
RESERVED
ALWAYS READ 0
FLASH MEMORY DATA REGISTER HIGH (FMDRH)
15 14 13 12
11 10
9
8
7
6
5
4
3
2
0
1
0
0
0
0x2082
0
0
0
0
0
0
0
0
0
0
0
0
0
DATA 23–8
MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH.
Figure 21. Configuration of Flash Memory Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. 0
–30–
ADMCF340
PWMTM (R/W)
15
14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
DM (0x2008)
PWMTM
fCLKOUT
2 ꢀ PWMTM
fPWM
=
PWMDT (R/W)
15 14 13 12 11 10
9
0
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
DM (0x2009)
PWMDT
2 ꢀ PWMTM
=
T
SECONDS
D
fCLKOUT
PWMSEG (R/W)
15 14 13 12 11 10
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x200F)
0
0
0
0
0
0
0
0
0
0
A CHANNEL CROSSOVER
B CHANNEL CROSSOVER
CH OUTPUT DISABLE
CL OUTPUT DISABLE
BH OUTPUT DISABLE
0 = NO CROSSOVER
1 = CROSSOVER
C CHANNEL CROSSOVER
0 = ENABLE
1 = DISABLE
BL OUTPUT DISABLE
AH OUTPUT DISABLE
AL OUTPUT DISABLE
PWMSYNCWT (R/W)
15 14 13 12 11 10
9
8
7
6
5
1
4
0
3
0
2
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
DM (0x2060)
PWMSYNCWT
PWMSYNCWT + 1
fCLKOUT
T
=
PWMSYNC, ON
PWMSWT (R/W)
15 14 13 12 11 10
9
8
7
6
5
0
4
0
3
0
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DM (0x2061)
Figure 22. Configuration of PWM Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. 0
–31–
ADMCF340
PWMPD (R/W)
15
0
14 13 12 11 10
9
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x200A)
PWMPD
0
0
0
0
0
0
0
0
PWMPD
fCLKOUT
=
T
MIN
PWMGATE (R/W)
15 14 13 12 11 10
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x200B)
0
0
0
0
0
0
0
0
0
0
GDCLK
GATE DRIVE CHOPPING FREQUENCY
LOW SIDE GATE CHOPPING
HIGH SIDE GATE CHOPPING
fCLKOUT
0 = DISABLE
1 = ENABLE
=
fCHOP
4 ꢀ (GDCLK + 1)
PWMCHA (R/W)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DM (0x200C)
PWM CHANNEL A
DUTY CYCLE
PWMCHB (R/W)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DM (0x200D)
PWM CHANNEL B
DUTY CYCLE
PWMCHC (R/W)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DM (0x200E)
PWM CHANNEL C
DUTY CYCLE
Figure 23. Configuration of Additional PWM Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. 0
–32–
ADMCF340
PORTA_DIR (R/W)
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
15
0
14
0
13
0
12
0
11
0
10
0
DM (0x2004)
0
0
0
0
0 = INPUT
1 = OUTPUT
PA0-PA8
PORTB_DIR (R/W)
9
8
7
6
5
0
4
3
0
2
0
1
0
0
0
15
0
14
0
13
0
12
0
11
0
10
0
DM (0x2044)
(NOT USED IN ADMCF341)
0
0
0
0
0
0 = INPUT
1 = OUTPUT
PB0-PB15
PORTA_DATA (R/W)
9
8
7
6
5
4
0
3
0
2
0
1
0
15
14
13
12
11
0
10
0
DM (0x2005)
0
0
0
0
0
0
0
0
0
0
0
0 = LOW LEVEL
1 = HIGH LEVEL
PA0-PA8
PORTB_DATA (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
0
4
0
3
2
0
1
0
0
0
DM (0x2045)
(NOT USED IN ADMCF341)
0
0
0
0
0
0 = LOW LEVEL
1 = HIGH LEVEL
PB0-PA15
PORTA_SELECT (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
1
4
1
3
2
1
1
1
0
1
DM (0x2049)
0
1
1
1
1
0 = DR0
1 = PA0
0 = CLOCKOUT
1 = AUX0
0 = AUX0/CLOCKOUT
1 = PA8
0 = PWMSYNC
1 = AUX1
0 = DT0
1 = PA1
0 = AUX1/PWMSYNC
1 = PA7
0 = DR1
1 = PA6
0 = RFS0
1 = PA2
0 = DT1/FL1
1 = PA5
0 = TFS0
1 = PA3
0 = SCLK1/SCLK0
1 = PA4
Figure 24. Configuration of PIO Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. 0
–33–
ADMCF340
PORTA_INTEN (R/W)
15 14 13 12
11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
0
0
0
0
0
0
0
DM (0x2006)
0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE
PORTB_INTEN (R/W)
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
0
DM (0x2046)
(NOT USED IN ADMCF341)
0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE
PORTA_FLAG (R/W)
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
0
DM (0x2007)
0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE
PORTB_FLAG (R/W)
15 14 13 12
11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2047)
0
0
0
0
0
0
(NOT USED IN ADMCF341)
0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE
Figure 25. Configuration of Additional PIO Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
AUXCH0 (R/W)
15 14 13 12
11 10
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
DM (0x2010)
T
= 2 ꢀ (AUXCH0) ꢀ TCK
ON, AUX0
AUXCH1 (R/W)
15 14 13 12
11 10
9
8
7
6
5
0
4
3
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DM (0x2011)
T
= 2 ꢀ (AUXCH1) ꢀ TCK
ON, AUX1
AUXTM0 (R/W)
15 14 13 12
11 10
9
1
8
7
6
5
1
4
3
1
2
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
DM (0x2012)
p
AUX0 PERIOD = 2 ꢀ (AUXTM0 + 1) ꢀ TCK
AUXTM1 (R/W)
15 14 13 12
11 10
9
1
8
7
6
5
1
4
1
3
1
2
1
1
1
0
1
1
1
1
1
1
1
1
1
1
DM (0x2013)
AUX1 PERIOD = 2 ꢀ (AUXTM1) ꢀ TCK
OFFSET = 2 ꢀ (AUXTM1) ꢀ TCK
Figure 26. Configuration of Auxiliary PWM Register
Default bit values are shown; if no value is shown, the bit field is undefined at reset.
REV. 0
–34–
ADMCF340
ADC1 (R)
15 14 13 12
11 10
9
8
7
6
5
4
3
0
2
0
1
0
0
0
DM (0x2000)
0 = DATA READY
1 = NOT READY
CONVERSION
STATUS
ADC2 (R)
15 14 13 12
11 10
9
8
7
6
5
4
3
0
2
0
1
0
0
0
DM (0x2001)
0 = DATA READY
1 = NOT READY
CONVERSION
STATUS
ADC3 (R)
15 14 13 12
11 10
9
9
8
7
6
5
5
4
4
3
0
2
0
1
0
0
0
DM (0x2002)
0 = DATA READY
1 = NOT READY
CONVERSION
STATUS
ADCAUX (R)
8
15 14 13 12
11 10
7
6
3
0
2
0
1
0
0
0
DM (0x2003)
ICONST_TRIM (R/W)
15 14 13 12
11 10
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2068)
0
0
0
0
0
0
0
0
0
0
ICONST MIN = BITS 0–2 CLEARED.
ICONST MAX = BITS 0–2 SET.
SHA1_TM (R/W)
15
0
14
0
13
12
11
0
10
0
9
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
DM (0x2069)
0
0
0
0
0
0
SHA2 _TM (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x206A)
DM (0x206B)
SHA3 _TM (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
Figure 27. Configuration of ADC Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. 0
–35–
ADMCF340
MODECTRL (R/W)
15 14 13 12
11 10
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2015)
0
0
0
0
0
0
0
0
0
0
ADC MUX CONTROL*
SPORT 0
MODE SELECT
0 = SPORT MODE
1 = UART MODE
SPORT 0
SPI MODE
0 = SPORT
1 = SP1 MODE
PWMTRIP
INTERRUPT
0 = DISABLE
1 = ENABLE
0 = STANDARD
1 = REVERSE
SPI CLOCK
POLARITY
PWMSYNC
INTERRUPT
0 = DISABLE
1 = ENABLE
0 = PHA0
1 = PHA1
SPI CLOCK
PHASE
0 = BOOT MODE
1 = UART MODE
SPORT1 MODE
SELECT
0 = I
1 = VOLTAGE
SENSE
CHANNEL 3
SELECTION
ADC MUX
CONTROL
ADC MUX CONTROL*
0 = I
1 = VOLTAGE
SENSE
CHANNEL 2
SELECTION
0 = SINGLE UPDATE MODE
1 = DOUBLE UPDATE MODE
PWM UPDATE
MODE SELECT
0 = I
1 = VOLTAGE
SENSE
CHANNEL 1
SELECTION
0 = OFFSET MODE
1 = INDEPENDENT MODE
AUX PWM
MODE SELECT
0 = CLKIN RATE
1 = CLKOUT RATE
ADC
COUNTER
SYSSTAT (R)
15 14 13 12
11 10
9
0
8
7
6
0
5
0
4
3
2
1
1
0
DM (0x2016)
0
0
0
0
0
0
0
0
0
PWMTRIP
PIN STATUS
0 = LOW
1 = HIGH
0 = 1ST HALF OF PWM
CYCLE
1 = 2ND HALF OF PWM
CYCLE
0 = NORMAL
1 = WATCHDOG RESET
OCCURRED
PWM TIMER
STATUS
WATCHDOG
STATUS
IRQFLAG (R)
15 14 13 12
11 10
9
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2017)
0
0
0
0
0
0
0
0
0
PWMTRIP INTERRUPT
0 = NO INTERRUPT
1 = INTERRUPT OCCURRED
PWMSYNC INTERRUPT
WDTIMER (W)
15 14 13 12
11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2018)
0
0
0
0
0
0
Figure 28. Configuration of Status/Control Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset.
REV. 0
–36–
ADMCF340
Table XIV. Auxiliary Analog Input Selection
Selection
MODECTRL (5)
MODECTRL (1)
MODECTRL (0)
VAUX0 (1)
VAUX1 (1)
VAUX2 (1)
VREF (1)
VAUX4
VAUX5
VAUX6
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VAUX7
REV. 0
–37–
ADMCF340
ICNTL
2
4
0
3
0
1
1
0
1
0
DSP REGISTER
0 = DISABLE
1 = ENABLE
INTERRUPT NESTING
IRQ0 SENSITIVITY
IRQ1 SENSITIVITY
IRQ2 SENSITIVITY
0 = LEVEL
1 = EDGE
IFC
15 14 13 12 11 10
9
0
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DSP REGISTER
0
0
0
0
0
0
0
INTERRUPT FORCE
INTERRUPT CLEAR
IRQ2
TIMER
SPORT0 TRANSMIT
SPORT0 RECEIVE
SPORT1 RECEIVE OR IRQ0
SPORT1 TRANSMIT OR IRQ1
SOFTWARE 0
SOFTWARE 1
SOFTWARE 0
SOFTWARE 1
SPORT0 RECEIVE
SPORT0 TRANSMIT
SPORT1 TRANSMIT OR IRQ1
SPORT1 RECEIVE OR IRQ0
TIMER
IRQ2
IMASK (R/W)
15 14 13 12
11 10
9
0
8
7
6
5
0
4
3
0
2
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
DSP REGISTER
TIMER
PERIPHERAL (OR IRQ2)
SPORT1 RECEIVE
(OR IRQ0)
SPORT0 TRANSMIT
0 = DISABLE
(MASK)
1 = ENABLE
0 = DISABLE
(MASK)
1 = ENABLE
SPORT0 RECEIVE
SPORT1 TRANSMIT
(OR IRQ1)
SOFTWARE 1
SOFTWARE 0
Figure 29. Configuration of Interrupt Control Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. 0
–38–
ADMCF340
SYSCNTL (R/W)
15 14 13 12 11 10
9
8
7
6
5
1
4
1
3
1
2
1
1
1
0
1
DM (0x3FFF)
0
0
0
0
0
1
0
0
0
0
0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SERIAL PORT
SPORT1 CONFIGURE
MEMWAIT (R/W)
0 = DISABLED
1 = ENABLED
SPORT1 ENABLE
15 14 13 12
11 10
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
0
1
DM (0x3FFE)
1
1
1
1
1
1
1
Figure 30. Configuration of Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset.
REV. 0
–39–
ADMCF340
OUTLINE DIMENSIONS
64-Lead Thin Plastic Quad Flatpack [LQFP]
(ST-64)
Dimensions shown in millimeters and (inches)
16.25 (0.6398)
16.00 (0.6299) SQ
15.75 (0.6201)
1.60 (0.0630)
MAX
0.75 (0.0295)
0.60 (0.0236)
0.45 (0.0177)
64
49
1
48
SEATING
PLANE
12ꢁ
TYP
14.10 (0.5551)
14.00 (0.5512) SQ
13.90 (0.5472)
TOP VIEW
(PINS DOWN)
0.10 (0.0039)
MAX LEAD
COPLANARITY
16
33
10ꢁ
6ꢁ
2ꢁ
17
32
0.80 (0.0315) 0.35 (0.0138)
BSC
0.17 (0.0067)
MAX
1.45 (0.0571)
1.40 (0.0551)
1.35 (0.0531)
7ꢁ
0ꢁ
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–40–
REV. 0
相关型号：
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