ADN2525ACPZ-R2 [ADI]
10.7 Gbps Active Back-Termination, Differential Laser Diode Driver; 10.7 Gbps有源反向端接，差分激光二极管驱动器
| 型号： | ADN2525ACPZ-R2 |
| 厂家： | 
ADI |
| 描述： | 10.7 Gbps Active Back-Termination, Differential Laser Diode Driver |
| 文件： | 总16页 (文件大小：626K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10.7 Gbps Active Back-Termination,
Differential Laser Diode Driver
ADN2525
FEATURES
Up to 10.7 Gbps operation
GENERAL DESCRIPTION
The ADN2525 laser diode driver is designed for direct modula-
tion of packaged laser diodes having a differential resistance
ranging from 5 Ω to 50 Ω. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2525 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly mis-
terminated. The small package provides the optimum solution
for compact modules where laser diodes are packaged in low
pin-count optical subassemblies.
Very low power: 670 mW (IBIAS = 40 mA, IMOD = 40 mA)
Typical 24 ps rise/fall times
Full back-termination of output transmission lines
Drives TOSAs with resistances ranging from 5 Ω to 50 Ω
PECL-/CML-compatible data inputs
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Automatic laser shutdown (ALS)
3.3 V operation
Compact 3 mm × 3 mm LFCSP package
Voltage input control for bias and modulation currents
XFP-compliant bias current monitor
Optical evaluation board available
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The automatic
laser shutdown feature allows the user to turn on/off the bias
and modulation currents by driving the ALS pin with the
proper logic levels.
APPLICATIONS
SONET OC-192 optical transceivers
SDH STM-64 optical transceivers
10 Gb Ethernet optical transceivers
XFP/X2/XENPAK/XPAK/MSA 300 optical modules
SR and VSR optical links
The product is available in a space-saving 3 mm × 3 mm LFCSP
package specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VCC
ALS
VCC
ADN2525
VCC
IMODP
IMODN
50Ω
50Ω
IMOD 50Ω
GND
VCC
DATAP
DATAN
IBMON
IBIAS
800Ω
800Ω
200Ω
200Ω
200Ω
2Ω
MSET
GND
BSET
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADN2525
TABLE OF CONTENTS
Specifications..................................................................................... 3
Thermal Specifications ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Input Stage..................................................................................... 9
Bias Current .................................................................................. 9
Automatic Laser Shutdown (ALS) ........................................... 10
Modulation Current................................................................... 10
Load Mis-termination ............................................................... 12
Power Consumption .................................................................. 12
Applications Information.............................................................. 13
Typical Application Circuit ....................................................... 13
Layout Guidelines....................................................................... 13
Design Example.......................................................................... 14
Headroom Calculations ........................................................ 14
BSET and MSET Pin Voltage Calculation .......................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
3/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADN2525
SPECIFICATIONS
VCC = VCCMIN to VCCMAX, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted.
Typical values are specified at 25°C, IMOD = 40 mA.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
BIAS CURRENT (IBIAS)
Bias Current Range
10
100
mA
µA
V
Bias Current while ALS Asserted
Compliance Voltage1
100
ALS = high
0.6
0.6
VCC – 1.2
VCC – 0.8
IBIAS = 100 mA
IBIAS = 10 mA
V
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range
10
80
mA diff
mA diff
ps
RLOAD = 5 Ω to 50 Ω differential
ALS = high
Modulation Current while ALS Asserted
Rise Time (20% to 80%)2, 3
0.5
32.5
32.5
0.9
12
24
Fall Time (20% to 80%),
Random Jitter,
2
3
24
ps
2
3
0.4
7.2
−10
−14
ps rms
ps p-p
dB
Deterministic Jitter3, 4
Differential |S22|
5 GHz < F < 10 GHz, Z0 = 50 Ω differential
F < 5 GHz, Z0 = 50 Ω differential
dB
Compliance Voltage
1
VCC − 1.1
VCC + 1.1
V
DATA INPUTS (DATAP, DATAN)
Input Data Rate
10.7
1.6
Gbps
V p-p diff
dB
NRZ
Differential Input Swing
Differential |S11|
0.4
85
Differential ac-coupled
F < 10 GHz, Z0 = 100 Ω differential
Differential
−16.8
100
Input Termination Resistance
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain
BSET Input Resistance
115
Ω
75
100
120
mA/V
Ω
800
1000
1200
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain
MSET Input Resistance
70
88
110
mA/V
Ω
See Figure 29
800
1000
1200
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio
10
µA/mA
Accuracy of IBIAS to IBMON Ratio
−5.0
−4.0
−2.5
−2
+5.0
+4.0
+2.5
+2
%
%
%
%
10 mA ≤ IBIAS < 20 mA, RIBMON = 1 kΩ
20 mA ≤ IBIAS < 40 mA, RIBMON = 1 kΩ
40 mA ≤ IBIAS < 70 mA, RIBMON = 1 kΩ
70 mA ≤ IBIAS < 100 mA, RIBMON = 1 kΩ
AUTOMATIC LASER SHUTDOWN (ALS)
VIH
2.4
V
VIL
0.8
+20
200
10
V
IIL
−20
0
µA
µA
µs
IIH
ALS Assert Time
Rising edge of ALS to fall of IBIAS and IMOD below
10% of nominal; see Figure 2
ALS Negate Time
10
µs
Falling edge of ALS to rise of IBIAS and IMOD above
90% of nominal; see Figure 2
POWER SUPPLY
VCC
3.07
3.3
39
3.53
45
V
5
ICC
mA
mA
VBSET = VMSET = 0 V
6
ISUPPLY
157
176
VBSET = VMSET = 0 V. ISUPPLY = ICC + IMODP + IMODN
1 Refers to the voltage between the pin for which the compliance voltage is specified and GND.
2 The pattern used is composed by a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.
3 Measured using the high speed characterization circuit shown in Figure 3.
4 The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.
5 Only includes current in the ADN2525 VCC pins.
6 Includes current in ADN2525 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.
Rev. 0 | Page 3 of 16
ADN2525
THERMAL SPECIFICATIONS
Table 2.
Parameter
Min
2.6
65
Typ
5.8
Max
10.7
79.4
125
Unit
°C/W
°C/W
°C
Conditions/Comments
Thermal resistance from junction to bottom of exposed pad.
Thermal resistance from junction to top of package.
θJ-PAD
θJ-TOP
72.2
IC Junction Temperature
ALS
NEGATE TIME
ALS
t
IBIAS
AND IMOD
90%
10%
t
ALS
ASSERT TIME
Figure 2. ALS Timing Diagram
VEE
VEE
VEE
GND
10Ω
1kΩ
TP2
VBSET
10nF
TP1
GND
GND
BSET IBMON IBIAS GND
GND
VCC
VCC
GND
BIAS TEE
GND
50Ω
ADN2525
Z
= 50Ω
Z
= 50Ω
= 50Ω
Z
Z
= 25Ω
Z
Z
= 50Ω
0
0
0
0
10nF
35Ω
ADAPTER ATTENUATOR
ADAPTER ATTENUATOR
J2
DATAP
IMODP
GND
GND
= 50Ω
GND
GND
= 50Ω
GND
OSCILLOSCOPE
70Ω
35Ω
Z
Z
= 25Ω
0
0
0
0
10nF
J3
DATAN
VCC
IMODN
50Ω
GND
GND
GND
GND GND
GND
BIAS TEE
GND
VCC
GND
GND
MSET NC1
ALS GND
VMSET
BIAS TEE: Picosecond Pulse Labs Model 5542-219
Adapter: Pasternack PE-9436 2.92mm female-to-female adapter
Attenuator: Pasternack PE-7046 2.92mm 20dB attenuator
GND
VEE
10nF
VEE
VEE
J5
J8
22µF
GND GND
GND
Figure 3. High Speed Characterization Circuit
Rev. 0 | Page 4 of 16
ADN2525
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Min
Max
Unit
V
V
V
V
°C
°C
°C
Supply Voltage, VCC to GND
IMODP, IMODN to GND
DATAP, DATAN to GND
All Other Pins
Junction Temperature
Storage Temperature
−0.3
+4.2
4.75
VCC − 1 .5
VCC − 1.8
−0.3
VCC − 0.4
VCC + 0.3
150
+150
240
−65
Soldering Temperature
(Less than 10 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 16
ADN2525
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 BSET
11 IBMON
10 IBIAS
MSET
NC
1
2
3
4
PIN 1
INDICATOR
ADN2525
ALS
GND
TOP VIEW
9
GND
Figure 4. Pin Configuration
Note: The exposed pad on the bottom of the package must be connected to the VCC or GND plane.
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
MSET
NC
ALS
GND
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Input
N/A
Input
Modulation Current Control Input
No Connect—Leave Floating
Automatic Laser Shutdown
Negative Power Supply
Power
Power
Output
Output
Power
Power
Output
Output
Input
Power
Input
Input
Power
Power
VCC
Positive Power Supply
IMODN
IMODP
VCC
Modulation Current Negative Output
Modulation Current Positive Output
Positive Power Supply
Negative Power Supply
Bias Current Output
Bias Current Monitoring Output
Bias Current Control Input
Positive Power Supply
Data Signal Positive Input
Data Signal Negative Input
Positive Power Supply
GND
IBIAS
IBMON
BSET
VCC
DATAP
DATAN
VCC
Exposed Pad
Pad
Connect to GND or VCC
Rev. 0 | Page 6 of 16
ADN2525
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3 V, unless otherwise noted.
28.0
27.5
27.0
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
9
8
7
6
5
4
3
2
1
0
0
20
40
60
80
100
0
20
40
60
80
100
DIFFERENTIAL MODULATION CURRENT (mA)
DIFFERENTIAL MODULATION CURRENT (mA)
Figure 5. Rise Time vs. IMOD
Figure 8. Deterministic Jitter vs. IMOD
350
300
250
200
150
100
50
27.5
27.0
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
IBIAS = 100mA
IBIAS = 50mA
IBIAS = 10mA
0
0
20
40
60
80
100
0
20
40
60
80
100
DIFFERENTIAL MODULATION CURRENT (mA)
DIFFERENTIAL MODULATION CURRENT (mA)
Figure 9. Total Supply Current vs. IMOD
Figure 6. Fall Time vs. IMOD
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
–5
–10
–15
–20
–25
–30
–35
–40
0
20
40
60
80
100
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
DIFFERENTIAL MODULATION CURRENT (mA)
FREQUENCY (GHz)
Figure 7. Random Jitter vs. IMOD
Figure 10. Differential |S11|
Rev. 0 | Page 7 of 16
ADN2525
0
(ACQ LIMIT TEST) WAVEFORMS: 1000
–5
–10
–15
–20
–25
–30
–35
–40
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
Figure 14. Electrical Eye Diagram
(10.7 Gbps, PRBS31, IMOD = 80 mA)
Figure 11. Differential |S22
|
16
14
12
10
8
6
4
2
0
23
24
25
26
27
28
29
30
RISE TIME (ps)
Figure 15. Filtered SONET OC192 Optical Eye Diagram (for reference)
(PRBS31 Pattern, Pav = −2 dBm, ER = 7 dB,
Figure 12. Worst-Case Rise Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85°C)
17% Mask Margin, NEC NX8341UJ TOSA)
16
14
12
10
8
6
4
2
0
23
24
25
26
27
28
29
30
FALL TIME (ps)
Figure 13. Worst-Case Fall Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85°C)
Figure 16. Filtered 10G Ethernet Optical Eye
(PRBS31 Pattern, Pav = −2 dBm, ER = 5 dB,
41% Mask Margin, NEC NX8341UJ TOSA)
Rev. 0 | Page 8 of 16
ADN2525
THEORY OF OPERATION
As shown in Figure 1, the ADN2525 consists of an input stage
and two voltage controlled current sources for bias and modula-
tion. The bias current is available at the IBIAS pin. It is controlled
by the voltage at the BSET pin, and can be monitored at the
IBMON pin. The differential modulation current is available at
the IMODP and IMODN pins. It is controlled by the voltage at
the MSET pin. The output stage implements the active back-
match circuitry for proper transmission line matching and
power consumption reduction. The ADN2525 can drive a load
having differential resistance ranging from 5 Ω to 50 Ω. The
excellent back-termination in the ADN2525 absorbs signal
reflections from the TOSA end of the output transmission lines,
enabling excellent optical eye quality to be achieved even when
the TOSA end of the output transmission lines is significantly
mis-terminated.
The ADN2525 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the common-
mode voltages of the data signal source and the input stage of
the driver (see Figure 18). The ac-coupling capacitors should
have an impedance less than 50 Ω over the required frequency
range. Generally this is achieved using 10 nF to 100 nF capacitors.
ADN2525
50Ω
50Ω
C
C
DATAP
DATAN
DATA SIGNAL SOURCE
Figure 18. AC-Coupling the Data Source to the
ADN2525 Data Inputs
INPUT STAGE
The input stage of the ADN2525 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in Figure 17.
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor as shown in Figure 19.
VCC
VCC
ADN2525
R
R
DATAP
VCC
50Ω
I
BMON
BIAS
BSET
IBMON
IBIAS
800Ω
200Ω
VCC
I
50Ω
DATAN
200Ω
2Ω
GND
Figure 17. Equivalent Circuit of the Input Stage
Figure 19. Voltage-to-Current Converter Used to Generate IBIAS
The DATAP and DATAN pins are terminated internally with a
100 Ω differential termination resistor. This minimizes signal
reflections at the input, which could otherwise lead to degrada-
tion in the output eye diagram. It is not recommended to drive
the ADN2525 with single-ended data signal sources.
The voltage-to-current conversion factor is set at 100 mA/V by
the internal resistors, and the bias current is monitored using a
current mirror with a gain equal to 1/100. By connecting a 1 kΩ
resistor between IBMON and GND, the bias current can be
monitored as a voltage across the resistor. A low temperature
coefficient precision resistor must be used for the IBMON
resistor (RIBMON). Any error in the value of RIBMON due to toler-
ances, or drift in its value over temperature, contributes to the
overall error budget for the IBIAS monitor voltage. If the IBMON
voltage is being connected to an ADC for A/D conversion,
RIBMON should be placed close to the ADC to minimize errors
due to voltage drops on the ground plane.
Rev. 0 | Page 9 of 16
ADN2525
The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 20, Figure 21, and Figure 22.
two bias current levels (10 mA and 100 mA), but it can be
calculated for any bias current by using the following equation:
VCC
V
COMPLIANCE_MAX(V) = VCC(V) − 0.75 − 4.4 × IBIAS(A)
VCC
BSET
See the Applications Information section for example headroom
calculations.
800Ω
200Ω
The function of the inductor L is to isolate the capacitance of
the IBIAS output from the high frequency signal path. For
recommended components, see Table 5.
Figure 20. Equivalent Circuit of the BSET Pin
AUTOMATIC LASER SHUTDOWN (ALS)
IBIAS
VCC
2kΩ
The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Table 4.
VCC
100Ω
Table 4.
ALS Logic State
IBIAS and IMOD
Disabled
2Ω
High
Low
Enabled
Figure 21. Equivalent Circuit of the IBIAS Pin
Floating
Enabled
VCC
VCC
500Ω
The ALS pin is compatible with 3.3 V CMOS and TTL logic
levels. Its equivalent circuit is shown in Figure 24.
VCC
VCC
100Ω
50kΩ
100Ω
ALS
VCC
2kΩ
IBMON
Figure 24. Equivalent Circuit of the ALS Pin
Figure 22. Equivalent Circuit of the IBMON Pin
MODULATION CURRENT
The recommended configuration for BSET, IBIAS, and IBMON
is shown in Figure 23.
The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter using an
operational amplifier and a bipolar transistor as shown in
Figure 25.
TO LASER CATHODE
L
IBIAS
IBIAS
ADN2525
VCC
BSET
IBMON
IMODP
IMOD 50Ω
R
IBMON
1kΩ
GND
VBSET
IMODN
FROM INPUT STAGE
Figure 23. Recommended Configuration for BSET, IBIAS, and IBMON Pins
MSET
800Ω
The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range. See the Specifications
table. The maximum compliance voltage is specified for only
200Ω
ADN2525
GND
Figure 25. Generation of Modulation Current on the ADN2525
Rev. 0 | Page 10 of 16
ADN2525
This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and gained up by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins.
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value as shown
in Figure 29.
210
200
190
180
170
The output stage also generates the active back-termination,
which provides proper transmission line termination. Active
back-termination uses feedback around an active circuit to
synthesize a broadband termination resistance. This provides
excellent transmission line termination, while dissipating less
power than a traditional resistor passive back-termination. The
equivalent circuits for MSET, IMODP, and IMODN are shown
in Figure 26 and Figure 27.
160
MAXIMUM
150
140
TYPICAL
130
120
MINIMUM
110
100
90
80
70
60
VCC
VCC
MSET
0
5
10
15
20
25
30
35
40
45
50
55
800Ω
200Ω
DIFFERENTIAL LOAD RESISTANCE
Figure 29. MSET Voltage to Modulation Current Ratio vs.
Differential Load Resistance
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to generate
the required modulation current range (see the example in the
Applications Information section).
Figure 26. Equivalent Circuit of the MSET Pin
VCC
25Ω
VCC
25Ω
IMODN
IMODP
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
80 mA modulation currents through the differential load, the
output stage of the ADN2525 (IMODP, IMODN pins) must be
ac-coupled to the load. The voltages at these pins have a dc
component equal to VCC, and an ac component with single-
3.3Ω
3.3Ω
Figure 27. Equivalent Circuit of the IMODP and IMODN Pins
ended peak-to-peak amplitude of IMOD × 25 Ω. This is the
case even if the load impedance is less than 50 Ω differential,
since the transmission line characteristic impedance sets the
peak-to-peak amplitude. For proper operation of the output stage,
the voltages at the IMODP and IMODN pins must be between
the compliance voltage specifications for this pin over supply,
temperature, and modulation current range as shown in
Figure 30. See the Applications Information section for
example headroom calculations.
The recommended configuration of the MSET, IMODP, and
IMODN pins is shown in Figure 28. See Table 5 for recom-
mended components.
IBIAS
VCC
ADN2525
L
L
Z
= 25Ω
= 25Ω
Z
Z
= 25Ω
= 25Ω
0
0
0
0
C
C
VIMODP, IMODN
IMODP
TOSA
Z
VCC + 1.1V
MSET
IMODN
GND
VMSET
NORMAL OPERATION REGION
VCC
L
L
VCC VCC
VCC – 1.1V
Figure 28. Recommended Configuration for the
MSET, IMODP, and IMODN Pins
Figure 30. Allowable Range for the Voltage at
IMODP and IMODN
Rev. 0 | Page 11 of 16
ADN2525
THERMAL COMPOUND
MODULE CASE
LOAD MIS-TERMINATION
Due to its excellent S22 performance, the ADN2525 can drive
differential loads that range from 5 Ω to 50 Ω. In practice, many
TOSAs have differential resistance less than 50 Ω. In this case,
with 50 Ω differential transmission lines connecting the
ADN2525 to the load, the load end of the transmission lines are
mis-terminated. This mis-termination leads to signal reflections
back to the driver. The excellent back-termination in the
ADN2525 absorbs these reflections, preventing their reflection
back to the load. This enables excellent optical eye quality to be
achieved, even when the load end of the transmission lines is
significantly mis-terminated. The connection between the load
and the ADN2525 must be made with 50 Ω differential (25 Ω
single-ended) transmission lines so that the driver end of the
transmission lines is properly terminated.
T
TOP
DIE
PACKAGE
T
THERMO-COUPLE
J
T
PAD
PCB
COPPER PLANE
VIAS
Figure 31. Typical Optical Module Structure
The following procedure can be used to estimate the IC
junction temperature:
T
TOP = Temperature at top of package in °C.
POWER CONSUMPTION
T
PAD = Temperature at package exposed paddle in °C.
TJ = IC junction temperature in °C.
The power dissipated by the ADN2525 is given by
P = Power dissipation in W.
V
⎛
⎜
⎞
MSET
θ
θ
J-TOP = Thermal resistance from IC junction to package top.
J-PAD = Thermal resistance from IC junction to package exposed
pad.
P =VCC ×
+ ISUPPLY +V
× IBIAS
⎟
IBIAS
13.5
⎝
⎠
where:
VCC is the power supply voltage.
IBIAS is the bias current generated by the ADN2525.
MSET is the voltage applied to the MSET pin.
SUPPLY is the sum of the current that flows into the VCC,
IMODP, and IMODN pins of the ADN2525 when
IBIAS = IMOD = 0 expressed in amps (see Table 1).
T
TOP
T
θJ-TOP
TOP
V
I
P
θJ-PAD
T
PAD
T
PAD
V
IBIAS is the average voltage on the IBIAS pin.
Figure 32. Electrical Model for Thermal Calculations
Considering VBSET/IBIAS = 10 as the conversion factor from
TTOP and TPAD can be determined by measuring the temperature
at points inside the module as shown in Figure 31. The thermo-
couples should be positioned to obtain an accurate measurement
of the package top and paddle temperatures. Using the model
shown in Figure 32, the junction temperature can be calculated
using the following formula:
V
BSET to IBIAS, the dissipated power becomes
V
VBSET
⎛
⎜
⎞
⎟
MSET
P = VCC ×
+ ISUPPLY
+
×VIBIAS
13.5
10
⎝
⎠
To ensure long-term reliable operation, the junction tempera-
ture of the ADN2525 must not exceed 125°C, as specified in
Table 2. For improved heat dissipation, the module’s case can be
used as heat sink as shown in Figure 31. A compact optical
module is a complex thermal environment, and calculations of
device junction temperature using the package θJA (junction-to-
ambient thermal resistance) do not yield accurate results.
P ×
θJ−PAD × θJ−TOP
+ TTOP × θJ−PAD + TPAD × θJ−TOP
TJ =
θJ−PAD + θJ−TOP
where θJ-TOP and θJ-PAD are given in Table 2 and P is the power
dissipated by the ADN2525.
Rev. 0 | Page 12 of 16
ADN2525
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
LAYOUT GUIDELINES
Figure 33 shows the typical application circuit for the ADN2525.
The dc voltages applied to the BSET and MSET pins control the
bias and modulation currents. The bias current can be monitored
as a voltage drop across the 1 kΩ resistor connected between
the IBMON pin and GND. The ALS pin allows the user to turn
on/off the bias and modulation currents, depending on the logic
level applied to the pin. The data signal source must be connected
to the DATAP and DATAN pins of the ADN2525 using 50 Ω
transmission lines. The modulation current outputs, IMODP
and IMODN, must be connected to the load (TOSA) using 50 Ω
differential (25 Ω single-ended) transmission lines. Table 5
shows recommended components for the ac-coupling interface
between the ADN2525 and TOSA. For up-to-date component
recommendations, contact your sales representative.
Due to the high frequencies at which the ADN2525 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Controlled impedance transmission
lines must be used for the high speed signal paths. The length
of the transmission lines must be kept to a minimum to reduce
losses and pattern-dependent jitter. The PCB layout must be
symmetrical, both on the DATAP, DATAN inputs, and on the
IMODP, IMODN outputs, to ensure a balance between the
differential signals. All VCC and GND pins must be connected
to solid copper planes by using low inductance connections.
When the connections are made through vias, multiple vias can
be connected in parallel to reduce the parasitic inductance.
Each GND pin must be locally decoupled with high quality
capacitors. If proper decoupling cannot be achieved using a
single capacitor, the user can use multiple capacitors in parallel
for each GND pin. A 20 µF tantalum capacitor must be used as
general decoupling capacitor for the entire module. For
guidelines on the surface-mount assembly of the ADN2525,
consult the Amkor Technology® application note “Application
Notes for Surface Mount Assembly of Amkor’s
Table 5.
Component
Value
36 Ω
200 Ω
100 nF
Description
R1, R2
R3, R4
C3, C4
0603 size resistor
0603 size resistor
0603 size capacitor,
Phycomp 223878615649
MicroLeadFrame® (MLF) Packages.”
L2, L3, L6, L7
L1, L4, L5, L8
82 nH
10 µH
0402 size inductor,
Murata LQW15AN82NJ0
0603 size inductor,
Murata LQM21FN100M70L
VCC
GND
R5
GND
1kΩ
C5
10nF
BSET
TP1
L1
L2
L8
L7
R1
R4
VCC
BSET IBMON IBIAS GND
VCC
= 50Ω
VCC
VCC
VCC
Z
Z
Z
Z
= 25Ω
Z
Z
= 25Ω
= 25Ω
0
0
0
0
DATAP
DATAN
DATAP
IMODP
C1
C4
C3
GND
= 25Ω
ADN2525
TOSA
= 50Ω
0
0
DATAN
VCC
IMODN
VCC
C2
GND
L3
L6
VCC
VCC
MSET NC1 ALS GND
VCC
L4
R2 L5
R3
C6
10nF
MSET
+3.3V
VCC
C7
20µF
GND
ALS
VCC
VCC
GND
Figure 33. Typical ADN2525 Application Circuit
Rev. 0 | Page 13 of 16
ADN2525
DESIGN EXAMPLE
This design example covers
Assuming VLB = 0 V and IMOD = 60 mA, the minimum voltage
at the modulation output pins is equal to
•
•
Headroom calculations for IBIAS, IMODP, and IMODN pins.
VCC − (IMOD × 25)/2 = VCC − 0.75
Calculation of the typical voltage required at the BSET and
MSET pins in order to produce the desired bias and
modulation currents.
VCC − 0.75 > VCC − 1.1 V, which satisfies the requirement.
The maximum voltage at the modulation output pins is equal to
VCC + (IMOD × 25)/2 = VCC + 0.75
This design example assumes that the resistance of the TOSA is
25 Ω, the forward voltage of the laser at low current is VF = 1 V,
IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V.
VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement.
Headroom Calculations
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
BSET and MSET Pin Voltage Calculation
Considering the typical application circuit shown in Figure 33,
the voltage at the IBIAS pin can be written as
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2525 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET
voltage to IBIAS gain specified in Table 1. Assuming that IBIAS
= 40 mA and the typical IBIAS/VBSET ratio of 100 mA/V, the
BSET voltage is given by
VIBIAS = VCC − VF − (IBIAS × RTOSA) − VLA
where:
VCC is the supply voltage.
VF is the forward voltage across the laser at low current.
R
TOSA is the resistance of the TOSA.
IBIAS(mA) 40
V
V
LA is the dc voltage drop across L5, L6, L7, and L8.
LB is the dc voltage drop across L1, L2, L3, and L4.
VBSET
=
=
= 0.4 V
100 mA/V 100
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Table 1.
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
Assuming that the voltage drop across the 25 Ω transmission
lines is negligible and that VLA =0 V, VF = 1 V, IBIAS = 40 mA,
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
V
IBIAS = 3.3 − 1 − (0.04 × 25) = 1.3 V
IMOD
VMSET
=
K
VIBIAS = 1.3 V > 0.6 V, which satisfies the requirement.
where K is the MSET voltage to IMOD ratio.
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by the
following equation:
The value of K depends on the actual resistance of the TOSA.
It can be read using the plot shown in Figure 29. For a TOSA
resistance of 25 Ω, the typical value of K = 120 mA/V. Assuming
that IMOD = 60 mA and using the preceding equation, the
MSET voltage is given by
V
COMPLIANCE_MAX = VCC − 0.75 − 4.4 × IBIAS(A)
For this example:
V
V
COMPLIANCE_MAX = VCC – 0.75 − 4.4 × 0.04 = 2.53 V
IBIAS = 1.3 V < 2.53 V, which satisfies the requirement.
IMOD(mA) 60
VMSET
=
=
= 0.5 V
120 mA/V 120
To calculate the headroom at the modulation current pins
(IMODP, IMODN), the voltage has a dc component equal to
VCC due to the ac-coupled configuration and a swing equal to
IMOD × 25 Ω. For proper operation of the ADN2525, the
voltage at each modulation output pin should be within the
normal operation region shown in Figure 30.
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These
can be obtained from the minimum and maximum curves in
Figure 29.
Rev. 0 | Page 14 of 16
ADN2525
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1 INDICATOR
1.65
13
12
16
1
0.45
*
1.50 SQ
1.35
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PA D
(BOTTOM VIEW)
4
9
0.50
BSC
8
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding
ADN2525ACPZ-WP1
−40°C to +85°C
16-Lead Lead Frame Chip Scale Package,
50-Piece Waffle Pack
16-Lead Lead Frame Chip Scale Package,
500-Piece Reel
16-Lead Lead Frame Chip Scale Package,
7” 1500-Piece Reel
CP-16-3
F06
ADN2525ACPZ-R21
−40°C to +85°C
−40°C to +85°C
CP-16-3
CP-16-3
F06
F06
ADN2525ACPZ-REEL71
1 Z = Pb-free part.
Rev. 0 | Page 15 of 16
ADN2525
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05077–0–3/05 (0)
Rev. 0 | Page 16 of 16
相关型号：
ADN2530YCPZ-500R7
SPECIALTY INTERFACE CIRCUIT, PQCC16, 3 X 3 MM, LEAD FREE, MO-220VEED-2,LFCSP-16
ROCHESTER
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