ADN2526ACPZ-R2 [ADI]
11.3 Gbps Active Back-Termination, Differential Laser Diode Driver; 11.3 Gbps有源反向端接，差分激光二极管驱动器
| 型号： | ADN2526ACPZ-R2 |
| 厂家： | 
ADI |
| 描述： | 11.3 Gbps Active Back-Termination, Differential Laser Diode Driver |
| 文件： | 总16页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
11.3 Gbps Active Back-Termination,
Differential Laser Diode Driver
ADN2526
FEATURES
GENERAL DESCRIPTION
3.3 V operation
Up to 11.3 Gbps operation
Typical 24 ps rise/fall times
The ADN2526 laser diode driver is designed for direct modula-
tion of packaged laser diodes that have a differential resistance
ranging from 5 Ω to 50 Ω. The active back-termination in the
ADN2526 absorbs signal reflections from the TOSA end of the
output transmission lines, enabling excellent optical eye quality to
be achieved even when the TOSA end of the output transmission
lines is significantly misterminated. ADN2526 is an SFP+ MSA-
compliant device, and its small package and enhanced ESD
protection provide the optimum solution for compact modules
where laser diodes are packaged in low pin-count optical
subassemblies.
Full back-termination of output transmission lines
Drives TOSAs with resistances ranging from 5 Ω to 50 Ω
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Voltage input control for bias and modulation currents
Data inputs sensitivity: 150 mV p-p diff
Automatic laser shutdown (ALS)
Cross point adjustment (CPA)
XFP-compliant bias current monitor
SFP+ MSA compliant
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with control
voltages, the user has the flexibility to implement various
average optical power and extinction ratio control schemes,
including closed-loop or look-up table control. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with a
LVTTL logic source.
Optical evaluation board available
Compact 3 mm × 3 mm LFCSP
APPLICATIONS
SONET OC-192 and SDH STM-64 optical transceivers
10 Gb Fibre Channel transceivers
10 Gb Ethernet optical transceivers
SFP+/XFP/X2/XENPAK/XPAK/MSA 300 optical modules
The product is available in a space-saving 3 mm × 3 mm LFCSP
specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VCC
CPA
ALS
VCC
ADN2526
VCC
IMODP
IMODN
50Ω
50Ω
50Ω
IMOD
VCC
GND
DATAP
DATAN
CROSS
POINT
ADJUST
IBMON
IBIAS
800Ω
800Ω
200Ω
200Ω
200Ω
2Ω
MSET
VEE
BSET
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
ADN2526
TABLE OF CONTENTS
Features .............................................................................................. 1
Automatic Laser Shutdown (ALS) ........................................... 11
Modulation Current................................................................... 11
Load Mistermination................................................................. 12
Crosspoint Adjustment.............................................................. 13
Power Sequence.......................................................................... 13
Power Consumption .................................................................. 13
Applications Information.............................................................. 14
Typical Application Circuit....................................................... 14
Layout Guidelines....................................................................... 14
Design Example.......................................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Thermal Specifications ................................................................ 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 10
Input Stage................................................................................... 10
Bias Current ................................................................................ 10
REVISION HISTORY
8/09—Rev. 0 to Rev. A
Changes to θJ-PAD Maximum Value (Table 2)................................. 4
Changes to Figure 5 and Figure 6................................................... 8
1/09—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADN2526
SPECIFICATIONS
VCC = VCCMIN to VCCMAX, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted. Typical values are specified at
TA = 25°C, IMOD1
D
= 40 mA, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
BIAS CURRENT (IBIAS)
Bias Current Range
Bias Current While ALS Asserted
Compliance Voltage2
10
100
300
VCC
VCC
mA
μA
V
ALS = high
IBIAS = 100 mA
IBIAS = 10 mA
0.6
0.6
V
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range
Modulation Current While ALS Asserted
Rise Time (20% to 80%)3, 4
Fall Time (20% to 80%)3, 4
Random Jitter3, 4
10
80
mA diff
mA diff
ps
RLOAD = 5 Ω to 50 Ω differential
ALS = high
0.5
32.5
32.5
0.9
12
24
24
0.4
7.2
2
ps
ps rms
ps p-p
ps
Deterministic Jitter3, 5
Includes pulse width distortion
PWD = (|THIGH – TLOW|)/2
Pulse Width Distortion3, 4
5
Differential |S22|
−10
−14
dB
dB
5 GHz < f < 10 GHz, Z0 = 50 Ω differential
f < 5 GHz, Z0 = 50 Ω differential
Compliance Voltage2
DATA INPUTS (DATAP, DATAN)
Input Data Rate
Differential Input Swing
Differential |S11|
Input Termination Resistance
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain
BSET Input Resistance
VCC − 1.1
0.15
VCC + 1.1
V
11.3
1.6
Gbps
NRZ
V p-p diff Differential, ac-coupled
dB
Ω
−16.8
100
f < 10 GHz, Z0 = 100 Ω differential
Differential
90
1000
mA/V
Ω
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain
MSET Input Resistance
50
78
1000
100
mA/V
Ω
See Figure 29
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio
10
μA/mA
Accuracy of IBIAS to IBMON Ratio
−5.0
−4.0
−2.5
−2
+5.0
+4.0
+2.5
+2
%
%
%
%
10 mA ≤ IBIAS < 20 mA, RIBMON = 1 kΩ
20 mA ≤ IBIAS < 40 mA, RIBMON = 1 kΩ
40 mA ≤ IBIAS < 70 mA, RIBMON = 1 kΩ
70 mA ≤ IBIAS < 100 mA, RIBMON = 1 kΩ
AUTOMATIC LASER SHUTDOWN (ALS)
VIH
2.0
V
VIL
IIL
IIH
0.8
+30
200
2
V
−30
0
μA
μA
μs
ALS Assert Time
Rising edge of ALS to falling edge of IBIAS and
IMOD below 10% of nominal, see Figure 2
ALS Negate Time
10
μs
Falling edge of ALS to rise of IBIAS and IMOD
above 90% of nominal, see Figure 2
Rev. A | Page 3 of 16
ADN2526
Parameter
POWER SUPPLY
VCC
Min
Typ
Max
Unit
Test Conditions/Comments
3.0
3.3
46
74
1.88
50
3.6
55
95
V
6
ICC
ISUPPLY
mA
mA
V
VBSET = VMSET = 0 V
7
VBSET = VMSET = 0 V; ISUPPLY = ICC + IMODP + IMODN
In NC mode (refer to Table 4)
From an optical eye in NC mode
CPA
Cross Point
%
1 IMOD is the total modulation current sink capability for a differential driver. IMOD = IMODP + IMODN, the dynamic current sank by the IMODP and IMODN pins.
2 Refers to the voltage between the pin for which the compliance voltage is specified and VEE.
3 The pattern used is a repetitive sequence of eight 1s followed by eight 0s at 11.3 Gbps.
4 Measured using the high speed characterization circuit shown in Figure 3.
5 The pattern used is K28.5 (00111110101100000101) at a 11.3 Gbps rate.
6 Only includes current in the VCC pins.
7 Without laser diode loaded.
THERMAL SPECIFICATIONS
Table 2.
Parameter
Min
2.6
65
Typ
5.8
72.2
Max
10.7
79.4
125
Unit
°C/W
°C/W
°C
Conditions/Comments
θJ-PAD
θJ-TOP
Thermal resistance from junction to bottom of exposed pad
Thermal resistance from junction to top of package
IC Junction Temperature
ALS
NEGATE TIME
ALS
t
IBIAS
AND IMOD
90%
10%
t
ALS
ASSERT TIME
Figure 2. ALS Timing Diagram
Rev. A | Page 4 of 16
ADN2526
VEE
VEE
VEE
GND
1kΩ
TP2
10Ω
VBSET
TP1
10nF
GND
GND
BSET IBMON IBIAS VEE
GND
BIAS
VCC
VCC
GND
GND
TEE
50Ω
ADN2526
Z
= 50Ω
Z
= 50Ω
= 50Ω
Z
Z
= 25Ω
Z
Z
= 50Ω
0
0
0
0
10nF
35Ω
ADAPTER ATTENUATOR
ADAPTER ATTENUATOR
J2
J3
DATAP
IMODP
GND
GND
= 50Ω
GND
GND
= 50Ω
GND
OSCILLOSCOPE
70Ω
35Ω
Z
0
Z
= 25Ω
0
0
0
10nF
DATAN
IMODN
50Ω
GND
GND
GND
GND
GND
BIAS
TEE
GND
VCC
VCC
VEE
GND
GND
MSET CPA ALS
GND
VMSET
BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219
ADAPTER: PASTERNACK PE-9436 2.92mm FEMALE-TO-FEMALE ADAPTER
ATTENUATOR: PASTERNACK PE-7046 2.92mm 20dB ATTENUATOR
GND
VEE
10nF
22µF
VEE
VEE
J5
VCPA
J8
VEE
GND GND
GND
Figure 3. High Speed Characterization Circuit
Rev. A | Page 5 of 16
ADN2526
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VEE connected to supply ground.
Table 3.
Parameter
Rating
Supply Voltage, VCC to VEE
IMODP, IMODN to VEE
DATAP, DATAN to VEE
All Other Pins
HBM ESD on IMODP, IMODN
HBM ESD on All Other Pins
Junction Temperature
Storage Temperature Range
−0.3 V to +4.2 V
1.1 V to 4.75 V
VCC − 1.8 V to VCC − 0.4 V
−0.3 V to VCC + 0.3 V
200 V
1 kV
150°C
−65°C to +150°C
300°C
ESD CAUTION
Soldering Temperature
(Less Than 10 sec)
Rev. A | Page 6 of 16
ADN2526
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
12 BSET
11 IBMON
10 IBIAS
MSET
CPA
ALS
1
2
3
4
ADN2526
TOP VIEW
(Not to Scale)
VEE
9 VEE
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECTED TO VCC OR THE GND PLANE.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
MSET
CPA
I/O1 Description
1
2
AI
AI
DI
P
Modulation Current Control Input.
Adjustable Cross Point. Defaults to not connected (NC) mode (floating).
Automatic Laser Shutdown.
Negative Power Supply. Normally connected to system ground.
Positive Power Supply.
3
4
ALS
VEE
5
VCC
P
6
7
8
IMODN
IMODP
VCC
AI
AI
P
Modulation Current Sink, Negative.
Modulation Current Sink, Positive.
Positive Power Supply.
9
VEE
P
Negative Power Supply. Normally connected to system ground.
Bias Current Sink.
Bias Current Monitoring Output.
Bias Current Control Input.
Positive Power Supply.
Data Signal Positive Input.
10
11
12
13
14
15
16
IBIAS
IBMON
BSET
AI
AO
AI
P
AI
AI
P
VCC
DATAP
DATAN
VCC
Data Signal Negative Input.
Positive Power Supply.
17 (EPAD) Exposed Pad (EPAD)
P
The exposed pad on the bottom of the package must be connected to VCC or the GND plane.
1 AI = analog input, DI = digital input, P = power, AO = analog output.
Rev. A | Page 7 of 16
ADN2526
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3 V, unless otherwise noted.
27.0
9
8
7
6
5
4
3
2
1
0
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
0
20
40
60
80
100
0
20
40
60
80
100
IMOD (mA)
IMOD (mA)
Figure 5. Rise Time vs. IMOD
Figure 8. Deterministic Jitter vs. IMOD
27.0
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
IBIAS = 100
IBIAS = 50
IBIAS = 10
0
20
40
60
80
100
0
10
20
30
40
50
60
70
80
90
100
IMOD (mA)
IMOD (mA)
Figure 6. Fall Time vs. IMOD
Figure 9. Total Supply Current vs. IMOD
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
–5
–10
–15
–20
–25
–30
–35
–40
0
20
40
60
80
100
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
IMOD (mA)
Figure 7. Random Jitter vs. IMOD
Figure 10. Differential |S11|
Rev. A | Page 8 of 16
ADN2526
0
–5
–10
–15
–20
–25
–30
–35
–40
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
Figure 11. Differential |S22|
Figure 14. Electrical Eye Diagram
(11.3 Gbps, PRBS31, IMOD = 80 mA)
16
14
12
10
8
6
4
2
0
23
24
25
26
27
28
29
30
RISE TIME (ps)
Figure 12. Worst-Case Rise Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85°C)
Figure 15. Filtered SONET OC192 Optical Eye Diagram (for Reference)
16
14
12
10
8
6
4
2
0
23
24
25
26
27
28
29
30
FALL TIME (ps)
Figure 16. Filtered 10 Gb Ethernet Optical Eye
Figure 13. Worst-Case Fall Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85°C)
Rev. A | Page 9 of 16
ADN2526
THEORY OF OPERATION
ADN2526
As shown in Figure 1, the ADN2526 consists of an input stage
and two voltage-controlled current sources for bias and modula-
tion. The bias current, which is available at the IBIAS pin, is
controlled by the voltage applied at the BSET pin and can be
monitored at the IBMON pin. The differential modulation
current, which is available at the IMODP and IMODN pins, is
controlled by the voltage applied to the MSET pin. The output
stage implements the active back-match circuitry for proper
transmission line matching and power consumption reduction.
The ADN2526 can drive a load having differential resistance
ranging from 5 Ω to 50 Ω. The excellent back-termination in
the ADN2526 absorbs the signal reflections from the TOSA
end, enabling excellent optical eye quality, even though the
TOSA is significantly misterminated.
50Ω
50Ω
C
C
DATAP
DATAN
DATA SIGNAL SOURCE
Figure 18. AC-Coupling the Data Source to the ADN2526 Data Inputs
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor, as shown in Figure 19.
VCC
INPUT STAGE
ADN2526
R
R
The input stage of the ADN2526 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in Figure 17.
I
BMON
BIAS
BSET
IBMON
IBIAS
800Ω
200Ω
I
VCC
DATAP
200Ω
2Ω
VCC
50Ω
GND
Figure 19. Voltage-to-Current Converter Used to Generate IBIAS
The voltage-to-current conversion factor is set at 100 mA/V by
the internal resistors, and the bias current is monitored using a
current mirror with a gain equal to 1/100. By connecting a 1 kΩ
resistor between IBMON and VEE, the bias current can be moni-
tored as a voltage across the resistor. A low temperature coefficient
precision resistor must be used for the IBMON resistor (RIBMON).
Any error in the value of RIBMON that is due to tolerances or to drift
in its value over temperature contributes to the overall error
budget for the IBIAS monitor voltage. If the IBMON voltage is
connected to an ADC for analog-to-digital conversion, RIBMON
should be placed close to the ADC to minimize errors due to
voltage drops on the ground plane.
50Ω
DATAN
Figure 17. Equivalent Circuit of the Input Stage
The DATAP and DATAN pins are terminated internally with a
100 Ω differential termination resistor. This minimizes signal
reflections at the input, which can otherwise lead to degradation in
the output eye diagram. It is not recommended to drive the
ADN2526 with single-ended data signal sources.
The ADN2526 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the common-
mode voltages of the data signal source and the input stage of
the driver (see Figure 18). The ac-coupling capacitors should
have an impedance much less than 50 Ω over the required
frequency range. Generally, this is achieved using 10 nF to 100 nF
capacitors.
The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 20, Figure 21, and Figure 22.
VCC
VCC
BSET
800Ω
In SFP+ MSA applications, the DATAP and DATAN pins need
to be connected to the SFP+ connector directly. This connection
requires enhanced ESD protection to support the SFP+ module
hot plug-in application.
200Ω
Figure 20. Equivalent Circuit of the BSET Pin
Rev. A | Page 10 of 16
ADN2526
IBIAS
VCC
2kΩ
Table 5. ALS Functions
ALS Logic State
VCC
IBIAS and IMOD
Disabled
Enabled
High
Low
100Ω
Floating
Enabled
2Ω
The ALS pin is compatible with 3.3 V CMOS and LVTTL logic
levels. Its equivalent circuit is shown in Figure 24.
Figure 21. Equivalent Circuit of the IBIAS Pin
VCC
VCC
VCC
VCC
500Ω
100Ω
40kΩ
ALS
2kΩ
Figure 24. Equivalent Circuit of the ALS Pin
100Ω
MODULATION CURRENT
VCC
The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter using an
operational amplifier and a bipolar transistor, as shown in
Figure 25.
IBMON
Figure 22. Equivalent Circuit of the IBMON Pin
The recommended configuration for BSET, IBIAS, and IBMON
is shown in Figure 23.
TO LASER CATHODE
VCC
L
IBIAS
IMODP
IBIAS
50Ω
IMOD
ADN2526
IMODN
BSET
IBMON
IBMON
g
× V
O
FROM INPUT STAGE
m
R
1kΩ
GND
MSET
V
BSET
800Ω
V
Figure 23. Recommended Configuration for the BSET, IBIAS, and IBMON Pins
O
The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range (see Table 1). The
maximum compliance voltage is specified for only two bias
current levels (10 mA and 100 mA), but it can be calculated for
any bias current by
200Ω
ADN2526
GND
Figure 25. Generation of Modulation Current on the ADN2526
This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and amplified by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins.
V
COMPLIANCE_MAX (V) = VCC (V) − 0.75 − 4.4 × IBIAS
(1)
The output stage also generates the active back-termination,
which provides proper transmission line termination. Active
back-termination uses feedback around an active circuit to
synthesize a broadband termination resistance. This provides
excellent transmission line termination, while dissipating less
power than a traditional resistor passive back-termination.
A small portion of the modulation current flows in the virtual
50 Ω active back-termination resistor. All of the preset IMOD
modulation current, the range specified in Table 1, flows into
the external load. The equivalent circuits for MSET, IMODP, and
IMODN are shown in Figure 26 and Figure 27. The two 25 Ω
resistors in Figure 27 are not actual resistors. They represent the
active back-termination resistance.
See the Applications Information section for examples of
headroom calculations.
The function of the inductor, L, is to isolate the capacitance of
the IBIAS output from the high frequency signal path. For
recommended components, see Table 7.
AUTOMATIC LASER SHUTDOWN (ALS)
The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Table 5.
Rev. A | Page 11 of 16
ADN2526
VCC
VCC
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to generate
the required modulation current range (see the example in the
Applications Information section).
MSET
800Ω
200Ω
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
80 mA modulation currents through the differential load, the
output stage of the ADN2526 (the IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins have
a dc component equal to VCC and an ac component with
single-ended, peak-to-peak amplitude of IMOD × 25 Ω. This is
the case even if the load impedance is less than 50 Ω differential,
because the transmission line characteristic impedance sets the
peak-to-peak amplitude. For proper operation of the output stage,
the voltages at the IMODP and IMODN pins must be between
the compliance voltage specifications for these pins over supply,
temperature, and modulation current range, as shown in Figure 30.
See the Applications Information section for examples of
headroom calculations.
Figure 26. Equivalent Circuit of the MSET Pin
VCC
25Ω
VCC
25Ω
IMODN
IMODP
3.3Ω
3.3Ω
Figure 27. Equivalent IMODP and IMODN Pins, As Seen From Laser Side
The recommended configuration of the MSET, IMODP,
and IMODN pins is shown in Figure 28. See Table 7 for the
recommended components.
IMODP, IMODN
IBIAS
VCC
ADN2526
L
L
VCC + 1.1V
Z
Z
= 25Ω
= 25Ω
Z
Z
= 25Ω
= 25Ω
0
0
0
C
C
IMODP
NORMAL OPERATION REGION
VCC
TOSA
0
MSET
IMODN
VEE
VCC – 1.1V
V
MSET
L
L
VCC VCC
Figure 28. Recommended Configuration for the MSET, IMODP, and IMODN Pins
Figure 30. Allowable Range for the Voltage at IMODP and IMODN
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in Figure 29.
LOAD MISTERMINATION
Due to its excellent S22 performance, the ADN2526 can drive
differential loads that range from 5 Ω to 50 Ω. In practice, many
TOSAs have differential resistance less than 50 Ω. In this case, with
50 Ω differential transmission lines connecting the ADN2526 to
the load, the load end of the transmission lines are misterminated.
This mistermination leads to signal reflections back to the driver.
The excellent back-termination in the ADN2526 absorbs these
reflections, preventing their reflection back to the load. This
enables excellent optical eye quality to be achieved, even when
the load end of the transmission lines is significantly mistermi-
nated. The connection between the load and the ADN2526 must
be made with 50 Ω differential (25 Ω single-ended) transmission
lines so that the driver end of the transmission lines is properly
terminated.
220
210
200
190
180
170
MAXIMUM
160
150
140
TYPICAL
MINIMUM
130
120
110
100
90
80
70
60
50
40
0
10
20
30
40
50
60
DIFFERENTIAL LOAD RESISTANCE (Ω)
Figure 29. MSET Voltage-to-Modulation Current Ratio vs.
Differential Load Resistance
Rev. A | Page 12 of 16
ADN2526
junction-to-ambient thermal resistance (θJA) do not yield
accurate results.
CROSSPOINT ADJUSTMENT
The optical eye cross point is adjustable between 35% and 65%
using the cross point adjust (CPA) control input. The equivalent
circuit for the CPA pin is shown in Figure 31. In a default CPA
setting, leave CPA unconnected (maintain pin-to-pin compatibil-
ity with the ADN2525). The internal bias circuit presents about
1.9 V at the CPA pin and the eye cross point is set to 50%. To set
the cross point at various points, apply an external voltage to the
CPA pin.
THERMAL COMPOUND
MODULE CASE
T
TOP
DIE
T
THERMOCOUPLE
J
PACKAGE
T
PAD
PCB
COPPER PLANE
VIAS
7kΩ
7kΩ
Figure 32. Typical Optical Module Structure
7kΩ
The parameters in Table 6 can be used to estimate the IC
junction temperature.
VCC
Table 6. Definitions
Parameter Description
CPA
Unit
Figure 31. Equivalent Circuit for CPA Pin
TTOP
TPAD
TJ
P
θJ-TOP
Temperature at the top of the package
Temperature at the package exposed paddle °C
IC junction temperature
Power dissipation
Thermal resistance from the IC junction to
the package top
°C
POWER SEQUENCE
°C
W
°C/W
To ensure reliable operation, the recommended power-up
sequence is: the supply rail to ADN2526 first, then the BSET
pin, followed by the MSET pin, and, finally, the CPA pin.
θJ-PAD
Thermal resistance from the IC junction to
the package exposed paddle
°C/W
To turn off the ADN2526, the operation is reversed: shut down
CPA first, then MSET, followed by BSET, and, last, the supply rail.
TTOP and TPAD can be determined by measuring the temperature
at points inside the module, as shown in Figure 32. The thermo-
couples should be positioned to obtain an accurate measurement
of the package top and paddle temperatures. Using the model
shown in Figure 33, the junction temperature can be calculated by
POWER CONSUMPTION
The power dissipated by the ADN2526 is given by
V
13.5
⎛
⎜
⎞
⎠
MSET
P =VCC ×
+ ISUPPLY +VIBIAS × IBIAS
⎟
⎝
P ×
θJ −PAD ×θJ −TOP
+TTOP ×θJ −PAD +TPAD ×θJ−TOP
where:
VCC is the power supply voltage.
MSET is the voltage applied to the MSET pin.
SUPPLY is the sum of the currents that flow into VCC, IMODP,
and IMODN, which are sank by the ADN2526 when VBSET
TJ =
θ J−PAD +θJ−TOP
V
I
where:
J-TOP and θJ-PAD are given in Table 2.
P is the power dissipated by the ADN2526.
θ
=
V
MSET = 0 V, expressed in amps (see Table 1).
T
TOP
V
IBIAS is the average voltage presented on the IBIAS pin.
IBIAS is the bias current sank by the ADN2526.
T
θJ-TOP
TOP
Considering VBSET/IBIAS = 10 mV/mA as the conversion factor
from VBSET to IBIAS, the dissipated power becomes
P
θJ-PAD
V
VBSET
⎛
⎜
⎞
⎟
MSET
P =VCC ×
+ ISUPPLY
+
×VIBIAS
13.5
10
⎝
⎠
T
PAD
To ensure long-term reliable operation, the junction tempera-
ture of the ADN2526 must not exceed 125°C, as specified in
Table 2. For improved heat dissipation, the SFP+ module case
can work as a heat sink, as shown in Figure 32. A compact
optical module is a complex thermal environment, and
calculations of device junction temperature using the package
Figure 33. Electrical Model for Thermal Calculations
Rev. A | Page 13 of 16
ADN2526
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2526 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Well controlled transmission line
impedance must be used for the high speed signal paths. The
length of the transmission lines must be kept to a minimum to
reduce losses and pattern-dependent jitter. The PCB layout
must be symmetrical, on both the DATAP and DATAN inputs
and the IMODP and IMODN outputs, to ensure a balance
between the differential signals. All VCC and VEE pins must be
connected to solid copper planes by using low inductance
connections. When the connections are made through vias,
multiple vias should be used in parallel to reduce the parasitic
inductance. Each VEE pin must be locally decoupled with high
quality capacitors. If proper decoupling cannot be achieved
using a single capacitor, the user can use multiple capacitors in
parallel for each VEE pin. A 20 μF tantalum capacitor must be
used as a general decoupling capacitor for the entire module. For
guidelines on the surface-mount assembly of the ADN2526, see
the Amkor Technology® Application Notes for Surface Mount
Assembly of Amkor’s MicroLeadFrame® (MLF®) Packages.
Figure 34 shows the typical application circuit for the ADN2526.
The dc voltages applied to the BSET and MSET pins control the
bias and modulation currents. The bias current can be monitored
as a voltage drop across the 1 kΩ resistor connected between
the IBMON pin and GND. The ALS pin allows the user to turn
on or turn off the bias and modulation currents, depending on
the logic level applied to the pin. The data signal source must be
connected to the DATAP and DATAN pins of the ADN2526
using 50 Ω transmission lines. The modulation current outputs,
IMODP and IMODN, must be connected to the load (TOSA)
using 50 Ω differential (25 Ω single-ended) transmission lines.
It is recommended that the components shown in Table 7 be
used between the ADN2526 and the TOSA for an example ac
coupling circuit. For up-to-date component recommendations,
contact your local Analog Devices, Inc., sales representative.
Working with a TOSA laser sample, the circuit in Figure 34
delivers optical performance shown in Figure 15 and Figure 16.
For additional applications information and optical eye perfor-
mance of other laser samples, contact your local Analog Devices
sales representative.
Table 7. Recommended Components for AC-Coupling
Component
Value
Description
R1, R2
R3, R4
C3, C4
L2, L3
36 Ω
0603 size resistor
0603 size resistor
0603 size capacitor, Phycomp 223878615649
0402 size inductor, Murata LQW15AN20NJ0
200 Ω
100 nF
20 nH
L6, L7
L1, L4, L5, L8
0402 size ferrite Murata BLM15HG102SN1
10 μH 0603 size inductor, Murata LQM21FN100M70L
VCC
GND
R5
1kΩ
GND
C5
10nF
BSET
TP1
L1
R1 L8
R4
VCC
BSET IBMON IBIAS VEE
VCC
= 50Ω
VCC
VCC
VCC
L2
L7
Z
Z
Z
Z
= 25Ω
Z
Z
= 25Ω
= 25Ω
0
0
0
0
DATAP
DATAN
DATAP
IMODP
C1
C4
GND
= 25Ω
TOSA
ADN2526
= 50Ω
0
0
DATAN
VCC
IMODN
VCC
C2
C3
L6
GND
L3
VCC
VCC
MSET CPA ALS VEE
VCC
L4
R2 L5
R3
C6
10nF
MSET
3.3V
VCC
C7
GND
CPA ALS
VCC
VCC
200µF
GND
Figure 34. Typical Application Circuit
Rev. A | Page 14 of 16
ADN2526
V
LB is the dc voltage drop across L1, L2, L3, and L4. Assuming
DESIGN EXAMPLE
This design example covers:
that VLB = 0 V and IMOD = 60 mA, the minimum voltage at the
modulation output pins is equal to
•
Headroom calculations for the IBIAS, IMODP, and
IMODN pins.
VCC − (IMOD × 25)/2 = VCC − 0.75
VCC − 0.75 > VCC − 1.1 V, which satisfies the requirement.
The maximum voltage at the modulation pins is equal to
VCC + (IMOD × 25)/2 = VCC + 0.75
•
Calculation of the typical voltage required at the BSET and
MSET pins to produce the desired bias and modulation
currents.
This design example assumes that the resistance of the TOSA is
25 Ω, the forward voltage of the laser at low current is VF = 1 V,
IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V.
VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement.
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2526 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET voltage
to IBIAS gain specified in Table 1. Assuming that IBIAS = 40 mA
and the typical IBIAS/VBSET ratio of 100 mA/V, the BSET voltage
is given by
Considering the typical application circuit shown in Figure 34,
the voltage at the IBIAS pin can be written as
VIBIAS = VCC − VF − (IBIAS × RTOSA) − VLA
where:
VCC is the supply voltage.
VF is the forward voltage across the laser at low current.
IBIAS (mA)
100 mA/V
40
100
VBSET
=
=
= 0.4 V
R
TOSA is the resistance of the TOSA.
LA is the dc voltage drop across L5, L6, L7, and L8.
V
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Table 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
Assuming that the voltage drop across the 25 Ω transmission
lines is negligible and that VLA = 0 V, VF = 1 V, and IBIAS =
40 mA
IMOD
K
VMSET
=
VIBIAS = 3.3 − 1 − (0.04 × 25) = 1.3 V
where K is the MSET voltage to IMOD ratio.
VIBIAS = 1.3 V > 0.6 V, which satisfies the requirement.
The value of K depends on the actual resistance of the TOSA.
It can be read using the plot shown in Figure 29. For a TOSA
resistance of 25 Ω, the typical value of K is equal to 120 mA/V.
Assuming that IMOD = 60 mA and using the preceding
equation, the MSET voltage is given by
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
V
COMPLIANCE_MAX = VCC − 0.75 − 4.4 × IBIAS
For this example,
VCOMPLIANCE_MAX = VCC – 0.75 − 4.4 × 0.04 = 2.53 V
IBIAS = 1.3 V < 2.53 V, which satisfies the requirement.
To calculate the headroom at the modulation current pins
(2)
IMOD (mA)
120 mA/V
60
120
VMSET
=
=
= 0.5 V
V
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These
can be obtained from the minimum and maximum curves in
Figure 29.
(IMODP and IMODN), the voltage has a dc component equal
to VCC, due to the ac-coupled configuration, and a swing equal
to IMOD × 25 Ω. For proper operation of the ADN2526, the
voltage at each modulation output pin should be within the
normal operation region shown in Figure 30.
Rev. A | Page 15 of 16
ADN2526
OUTLINE DIMENSIONS
0.50
0.40
0.30
0.60 MAX
3.00
BSC SQ
PIN 1
INDICATOR
BOTTOM VIEW
*
1.65
1.50 SQ
1.35
13
12
16
1
0.45
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
8
0.50
BSC
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADN2526ACPZ1
ADN2526ACPZ-R21
ADN2526ACPZ-R71
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-16-3
CP-16-3
Branding
F0C
F0C
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ, 7”Tape & Reel, 250-Piece Reel
16-Lead LFCSP_VQ, 7”Tape & Reel, 1,500-Piece Reel
CP-16-3
F0C
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07511-0-8/09(A)
Rev. A | Page 16 of 16
相关型号：
ADN2530YCPZ-500R7
SPECIALTY INTERFACE CIRCUIT, PQCC16, 3 X 3 MM, LEAD FREE, MO-220VEED-2,LFCSP-16
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