ADN2806ACPZ [ADI]
622 Mbps Clock and Data Recovery IC; 622 Mbps的时钟和数据恢复IC
| 型号： | ADN2806ACPZ |
| 厂家： | 
ADI |
| 描述： | 622 Mbps Clock and Data Recovery IC |
| 文件： | 总20页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
622 Mbps Clock and Data Recovery IC
ADN2806
FEATURES
GENERAL DESCRIPTION
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Patented clock recovery architecture
No reference clock required
The ADN2806 provides the receiver functions for clock and
data recovery, and data retiming for 622 Mbps NRZ data. The
ADN2806 automatically locks to 622 Mbps data without the
need for an external reference clock or programming. In the
absence of input data, the output clock drifts no more than
5%. All SONET jitter requirements are met, including jitter
transfer, jitter generation, and jitter tolerance. All specifications
are quoted for −40°C to +85°C ambient temperature, unless
otherwise noted.
Loss-of-lock indicator
I2C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 359 mW typical
5 mm × 5 mm, 32-lead LFCSP, Pb free
This device, together with a PIN diode, TIA preamplifier, and a
lim amp can implement a highly integrated, low cost, low power
fiber optic receiver.
APPLICATIONS
BPON ONT
SONET OC-12
WDM transponders
Regenerators/repeaters
Test equipment
The ADN2806 is available in a compact 5 mm × 5 mm,
32-lead LFCSP.
Broadband cross-connects and routers
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REFCLKN
(OPTIONAL)
LOL
CF1
CF2 VCC
VEE
LOOP
FILTER
FREQUENCY
DETECT
PIN
NIN
PHASE
SHIFTER
PHASE
DETECT
LOOP
FILTER
BUFFER
VCO
VREF
DATA
RE-TIMING
2
ADN2806
2
DATAOUTP/
DATAOUTN
CLKOUTP/
CLKOUTN
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADN2806
TABLE OF CONTENTS
Features .............................................................................................. 1
Jitter Specifications......................................................................... 10
Theory of Operation ...................................................................... 11
Functional Description.................................................................. 13
Frequency Acquisition............................................................... 13
Input Buffer Amplifier............................................................... 13
Lock Detector Operation .......................................................... 13
SQUELCH Modes...................................................................... 13
I2C Interface ................................................................................ 14
Reference Clock (Optional)...................................................... 15
Applications Information.............................................................. 17
PCB Design Guidelines ............................................................. 17
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Jitter Specifications....................................................................... 3
Output and Timing Specifications............................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Timing Characteristics..................................................................... 6
Pin Configuration and Function Descriptions............................. 7
I2C Interface Timing and Internal Register Description............. 8
REVISION HISTORY
2/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADN2806
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DATA INPUTS—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
DATA INPUTS—AC CHARACTERISTICS
Data Rate
@ PIN or NIN, dc-coupled
PIN − NIN
DC-coupled
1.8
0.2
2.3
2.8
2.0
2.8
V
V
V
2.5
622
−15
Mbps
dB
S11
@ 622 MHz
Output Clock Range
Input Resistance
Absence of input data
Differential
622 5ꢀ
100
MHz
Ω
Input Capacitance
0.65
pF
LOSS-OF-LOCK (LOL) DETECT
VCO Frequency Error for LOL Assert
VCO Frequency Error for LOL Deassert
LOL Response Time
With respect to nominal
With respect to nominal
OC-12
1000
250
200
ppm
ppm
μs
ACQUISITION TIME
Lock to Data Mode
OC-12
2.0
20.0
ms
ms
Optional Lock to REFCLK Mode
DATA RATE READBACK ACCURACY
Fine Readback
In addition to REFCLK accuracy
OC-12
100
3.3
ppm
V
POWER SUPPLY VOLTAGE
3.0
3.6
POWER SUPPLY CURRENT
Locked to 622.08 Mbps
109
mA
°C
OPERATING TEMPERATURE RANGE
–40
+85
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer Bandwidth
Jitter Peaking
OC-12
OC-12
75
0
130
0.03
kHz
dB
Jitter Generation
OC-12, 12 kHz to 5 MHz
0.001
0.011
0.003
0.026
UI rms
UI p-p
Jitter Tolerance
OC-12, 223 − 1 PRBS
30 Hz1
300 Hz1
100
44
2.5
1.0
UI p-p
UI p-p
UI p-p
UI p-p
25 kHz
250 kHz1
1 Jitter tolerance of the ADN2806 at these jitter frequencies is better than what the test equipment is able to measure.
Rev. 0 | Page 3 of 20
ADN2806
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
LVDS OUTPUT CHARACTERISTICS
(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)
Output Voltage High
Output Voltage Low
VOH (see Figure 3)
VOL (see Figure 3)
VOD (see Figure 3)
VOS (see Figure 3)
Differential
1475
mV
mV
mV
mV
Ω
925
250
1125
Differential Output Swing
Output Offset Voltage
Output Impedance
320
1200
100
400
1275
LVDS Outputs’Timing
Rise Time
Fall Time
Setup Time
Hold Time
20ꢀ to 80ꢀ
80ꢀ to 20ꢀ
TS (see Figure 2), OC-12
TH (see Figure 2), OC-12
LVCMOS
115
115
800
800
220
220
840
840
ps
ps
ps
ps
760
760
I2C INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
VIH
VIL
0.7 VCC
−10.0
V
V
μA
V
0.3 VCC
+10.0
0.4
VIN = 0.1 VCC or VIN = 0.9 VCC
VOL, IOL = 3.0 mA
See Figure 10
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHIGH
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
TR/TF
tSU;STO
600
1300
600
600
100
300
20 + 0.1 Cb1
600
1300
Data Hold Time
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time Between a Stop and a Start
REFCLK CHARACTERISTICS
Input Voltage Range
300
tBUF
Optional lock to REFCLK mode
@ REFCLKP or REFCLKN
VIL
0
V
VIH
VCC
100
V
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
mV p-p
MHz
ppm
10
160
100
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
VIH
2.0
V
Input Low Voltage
Input High Current
Input Low Current
VIL
0.8
5
V
μA
μA
IIH, VIN = 2.4 V
IIL, VIN = 0.4 V
−5
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
VOH, IOH = −2.0 mA
VOL, IOL = +2.0 mA
2.4
V
V
0.4
1 Cb = total capacitance of one bus line in picofarads. If used with Hs-mode devices, faster fall times are allowed.
Rev. 0 | Page 4 of 20
ADN2806
ABSOLUTE MAXIMUM RATINGS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF =
0.47 μF, unless otherwise noted.
Table 4.
Parameter
Supply Voltage (VCC)
Minimum Input Voltage (All Inputs)
Maximum Input Voltage (All Inputs)
Maximum Junction Temperature
Storage Temperature Range
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
4.2 V
VEE − 0.4 V
VCC + 0.4 V
125°C
−65°C to +150°C
THERMAL CHARACTERISTICS
Thermal Resistance
32-lead LFCSP, 4-layer board with exposed paddle soldered to
VEE, θJA = 28°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 20
ADN2806
TIMING CHARACTERISTICS
CLKOUTP
T
H
T
S
DATAOUTP/
DATAOUTN
Figure 2. Output Timing
DIFFERENTIAL CLKOUTP/N, DATAOUTP/N
V
OH
V
|V
|
OS
OD
V
OL
Figure 3. Differential Output Specifications
5mA
R
LOAD
100Ω
V
DIFF
100Ω
5mA
SIMPLIFIED LVDS
OUTPUT STAGE
Figure 4. Differential Output Stage
Rev. 0 | Page 6 of 20
ADN2806
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TEST1 1
VCC 2
VREF 3
NIN 4
PIN 5
NC 6
24 VCC
23 VEE
22 NC
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE
PIN 1
INDICATOR
ADN2806*
TOP VIEW
(Not to Scale)
NC 7
VEE 8
NC=NO CONNECT
* THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
TEST1
VCC
Type1
Description
1
2
Connect to VCC.
P
Power for Limiting Amplifier, LOS.
Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
No Connect
3
4
5
6
VREF
NIN
PIN
NC
AO
AI
AI
7
NC
No Connect
8
9
VEE
NC
P
GND for Limiting Amplifier, LOS.
No Connect
10
11
12
REFCLKP
REFCLKN
VCC
DI
DI
P
Differential REFCLK Input. 10 MHz to 160 MHz.
Differential REFCLK Input. 10 MHz to 160 MHz.
VCO Power.
13
VEE
P
VCO GND.
14
15
16
17
CF2
CF1
LOL
VEE
AO
AO
DO
P
Frequency Loop Capacitor.
Frequency Loop Capacitor.
Loss-of-Lock Indicator. LVTTL active high.
FLL Detector GND.
18
VCC
P
FLL Detector Power.
19
20
21
SADDR5
SCK
SDA
DI
DI
DI
Slave Address Bit 5.
I2C Clock Input.
I2C Data Input.
22
23
24
NC
VEE
VCC
No Connect
P
P
Output Buffer, I2C GND.
Output Buffer, I2C Power.
25
26
27
28
29
30
31
32
CLKOUTN
CLKOUTP
SQUELCH
DATAOUTN
DATAOUTP
VEE
VCC
TEST2
Pad
DO
DO
DI
DO
DO
P
Differential Recovered Clock Output. LVDS.
Differential Recovered Clock Output. LVDS.
Disable Clock and Data Outputs. Active high. LVTTL.
Differential Recovered Data Output. LVDS.
Differential Recovered Data Output. LVDS.
Phase Detector, Phase Shifter GND.
Phase Detector, Phase Shifter Power.
Connect to VCC.
P
Exposed Pad
P
Connect to GND.
1 Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Rev. 0 | Page 7 of 20
ADN2806
I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
R/W
SLAVE ADDRESS [6...0]
A5
CTRL.
1
0
0
0
0
0
X
MSB = 1 SET BY
PIN 19
0 = WR
1 = RD
Figure 6. Slave Address Configuration
S
SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S)
DATA A(S)
P
Figure 7. I2C Write Data Transfer
S
SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S)
S
SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M)
DATA A(M) P
S = START BIT
P = STOP BIT
A(M) = LACK OF ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
Figure 8. I2C Read Data Transfer
START BIT
STOP BIT
SLAVE ADDRESS
SUB ADDRESS
DATA
SDA
SCK
A6
A5
A7
A0
D7
D0
S
P
WR
ACK
ACK
ACK
SLADDR[4...0]
SUB ADDR[6...1]
DATA[6...1]
Figure 9. I2C Data Transfer Timing
tF
tSU;DAT
tHD;STA
tBUF
tR
SDA
SCK
tSU;STO
tR
tF
tLOW
tHIGH
tHD;STA
tSU;STA
S
S
P
S
tHD;DAT
Figure 10. I2C Port Timing Diagram
Rev. 0 | Page 8 of 20
ADN2806
Table 6. Internal Register Map1
Reg
Name
FREQ0
FREQ1
FREQ2
MISC
R/W Addr D7
D6
D5
D4
D3
D2
D1
D0
LSB
LSB
LSB
x
R
R
R
R
0x0
0x1
0x2
0x4
MSB
MSB
0
MSB
x
x
x
Static LOL
LOL status
Data rate
measurement
complete
x
CTRLA
CTRLB
W
W
0x8
0x9
FREF range
Data rate/DIV_FREF ratio
Measure data rate
0
Lock to reference
0
Config Reset
System
reset
0
Reset
0
LOL
MISC[4]
MISC[2]
CTRLC
W
0x11
0
0
0
0
0
x
SQUELCH mode
Output boost
1 All writeable registers default to 0x00.
Table 7. Miscellaneous Register, MISC
Static LOL
D4
LOL Status
D3
Data Rate Measurement Complete
D2
D7
D6
D5
D1
D0
x
x
x
0 = Waiting for next LOL
1 = Static LOL until reset
0 = Locked
1 = Acquiring
0 = Measuring data rate
1 = Measurement complete
x
x
Table 8. Control Register, CTRLA1
FREF Range
Data Rate/Div_FREF Ratio
Measure Data Rate
D1
Lock to Reference
D0
0 = Lock to input data
1 = Lock to reference clock
D7
0
D6
0
D5
0
D4
1
D3
0
D2
1
19.44 MHz
38.88 MHz
77.76 MHz
155.52 MHz
32
32
32
32
Set to 1 to measure data rate
0
1
0
1
0
1
1
0
0
1
0
1
1
1
0
1
0
1
1 Where DIV_FREF is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Config LOL
D7
Reset MISC[4]
D6
System Reset
D5
Reset MISC[2]
D3
D4
D2
D1
D0
0 = LOL pin normal operation
1 = LOL pin is static LOL
Write a 1 followed
by 0 to reset MISC[4] 0 to reset ADN2806
Write a 1 followed by Set to 0 Write a 1 followed
by 0 to reset MISC[2]
Set to 0 Set to 0 Set to 0
Table 10. Control Register, CTRLC
SQUELCH Mode
D1
Output Boost
D0
D7
D6
D5
D4
D3
D2
Set to 0
Set to 0 Set to 0
Set to 0
Set to 0 Set to 0
0 = Squelch data outputs and 0 = Default output swing
clock outputs
1 = Squelch data outputs or
clock outputs
1 = Boost output swing
Rev. 0 | Page 9 of 20
ADN2806
JITTER SPECIFICATIONS
The ADN2806 CDR is designed to achieve the best bit-
error-rate (BER) performance and to exceed the jitter
transfer, generation, and tolerance specifications proposed
for SONET/SDH equipment defined in the Telcordia
Technologies specification.
0.1
SLOPE = –20dB/DECADE
ACCEPTABLE
RANGE
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
fC
JITTER FREQUENCY (kHz)
Figure 11. Jitter Transfer Curve
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
Jitter Tolerance
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see Figure 12).
ADN2806 performance with respect to those specifications.
Jitter Generation
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For SONET devices, the jitter generated
must be less than 0.01 UI rms and less than 0.1 UI p-p.
15.00
SLOPE = –20dB/DECADE
Jitter Transfer
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal vs. the frequency.
This parameter measures the amount of jitter on an input signal
that can be transferred to the output signal (see Figure 11). This
amount is limited.
1.50
0.15
f0
f1
f2
f3
f4
JITTER FREQUENCY (kHz)
Figure 12. SONET Jitter Tolerance Mask
Rev. 0 | Page 10 of 20
ADN2806
THEORY OF OPERATION
The ADN2806 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops, which share a common control voltage.
A high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, composed of the VCO,
tracks the low frequency components of input jitter. The initial
frequency of the VCO is set by yet a third loop that compares
the VCO frequency with the input data frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
controls the VCO by the fine-tuning control.
psh
e(s)
X(s)
INPUT
DATA
d/sc
o/s
1/n
Z(s)
RECOVERED
CLOCK
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
JITTER TRANSFER FUNCTION
Z(s)
X(s)
1
=
cn
do
n psh
2
s
+ s
+ 1
o
TRACKING ERROR TRANSFER FUNCTION
2
e(s)
X(s)
s
=
d psh do
2
s
+ s +
c
cn
Figure 13. PLL/DLL Architecture
The delay and phase loops together track the phase of the input
data signal. For example, when the clock lags the input data, the
phase detector drives the VCO to a higher frequency and
increases the delay through the phase shifter; both of these
actions serve to reduce the phase error between the clock and
the data. The faster clock picks up phase, whereas the delayed
data loses phase. Because the loop filter is an integrator, the
static phase error is driven to 0°.
JITTER PEAKING
IN ORDINARY PLL
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path;
therefore, it does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phase-
locked loop is caused by the presence of this zero in the closed-
loop transfer function. Because this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.
ADN2806
Z(s)
X(s)
o
d psh
c
n psh
FREQUENCY (kHz)
Figure 14. Jitter Response vs. Conventional PLL
The delay and phase loops contribute to overall jitter accom-
modation. At low frequencies of input jitter on the data signal,
the integrator in the loop filter provides high gain to track large
jitter amplitudes with small phase error. In this case, the VCO is
frequency modulated, and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider
tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors; therefore, the phase shifter remains close to the
center of its range and thus contributes little to the low
frequency jitter accommodation.
The delay and phase loops together simultaneously provide
wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 13 shows that
the jitter transfer function, Z(s)/X(s), provides excellent second-
order low-pass filtering. Note that the jitter transfer has no zero,
unlike an ordinary second-order phase-locked loop. This means
that the main PLL loop has virtually no jitter peaking (see
Figure 14), making this circuit ideal for signal regenerator
applications, where jitter peaking in a cascade of regenerators
can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function can be
optimized to accommodate a significant amount of wideband
jitter, because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
Rev. 0 | Page 11 of 20
ADN2806
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at one extreme of its tuning range. The size of
the VCO tuning range, therefore, has only a small effect on the
jitter accommodation. The delay-locked loop control voltage is
now larger; therefore, the phase shifter takes on the burden of
tracking the input jitter. The phase shifter range, in UI, can be
seen as a broad plateau on the jitter tolerance curve. The phase
shifter has a minimum range of 2 UI at all data rates.
The gain of the loop integrator is small for high jitter
frequencies; therefore, larger phase differences are needed to
increase the loop control voltage enough to tune the range of
the phase shifter. However, large phase errors at high jitter
frequencies cannot be tolerated. In this region, the gain of the
integrator determines the jitter accommodation. Because the
gain of the loop integrator declines linearly with frequency,
jitter accommodation is lower with higher jitter frequency. At
the highest frequencies, the loop gain is very small, and little
tuning of the phase shifter can be expected. In this case, jitter
accommodation is determined by the eye opening of the input
data, the static phase error, and the residual loop jitter
generation. The jitter accommodation is roughly 0.5 UI in this
region. The corner frequency between the declining slope and
the flat region is the closed-loop bandwidth of the delay-locked
loop, which is roughly 1.0 MHz at 622 Mbps.
Rev. 0 | Page 12 of 20
ADN2806
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
LOL Detector Operation Using a Reference Clock
In REFCLK mode, a reference clock is used as an acquisition aid
to lock the ADN2806 VCO. Lock-to-reference mode is enabled
by setting CTRLA[0] to 1. The user also needs to write to the
CTRLA[7, 6] and CTRLA[5:2] bits to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss-of-lock signal, which appears on Pin 16, LOL, is deasserted
when the VCO is within 250 ppm of the desired frequency. This
enables the D/PLL, which pulls the VCO frequency in the
remaining amount with respect to the input data and acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss-of-lock signal is reasserted and
control returns to the frequency loop, which reacquires with
respect to the reference clock. The LOL pin remains asserted
until the VCO frequency is within 250 ppm of the desired
frequency. This hysteresis is shown in Figure 15.
The ADN2806 acquires frequency from the data. The lock
detector circuit compares the frequency of the VCO and the
frequency of the incoming data. When these frequencies differ
by more than 1000 ppm, LOL is asserted. This initiates a frequency
acquisition cycle. When the VCO frequency is within 250 ppm
of the data frequency, LOL is deasserted.
Once LOL is deasserted, the frequency-locked loop is turned
off. The PLL/DLL pulls the VCO frequency in the rest of the
way until the VCO frequency equals the data frequency.
The frequency loop requires a single external capacitor between
CF1 and CF2, Pin 14 and Pin 15. A 0.47 μF 20%, X7R ceramic
chip capacitor with <10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 μF capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 μF capacitor should be greater than 300 MΩ.
INPUT BUFFER AMPLIFIER
The input buffer has differential inputs (PIN/NIN), which are
internally terminated with 50 Ω to an on-chip voltage reference
(VREF = 2.5 V typically). The minimum differential input level
required to achieve a BER of 10−10 is 200 mV p-p.
Static LOL Mode
The ADN2806 implements a static LOL feature that indicates if
a loss-of-lock condition has ever occurred. This feature remains
asserted, even if the ADN2806 regains lock, until the static LOL
bit is manually reset. The I2C register bit, MISC[4], is the static
LOL bit. If there is ever an occurrence of a loss-of-lock condition,
this bit is internally asserted to logic high. The MISC[4] bit remains
high even after the ADN2806 has reacquired lock to a new data
rate. This bit can be reset by writing a 1 followed by 0 to I2C
Register Bit CTRLB[6]. Once reset, the MISC[4] bit remains
deasserted until another loss-of-lock condition occurs.
LOCK DETECTOR OPERATION
The lock detector on the ADN2806 has three modes of
operation: normal mode, REFCLK mode, and static LOL mode.
Normal Mode
In normal mode, the ADN2806 is a CDR that locks onto a
622 Mbps data rate without the use of a reference clock as an
acquisition aid. In this mode, the lock detector monitors the
frequency difference between the VCO and the input data
frequency and deasserts the loss of lock signal, which appears
on Pin 16, LOL, when the VCO is within 250 ppm of the data
frequency. This enables the D/PLL, which pulls the VCO
frequency in the remaining amount and acquires phase lock.
Once locked, if the input frequency error exceeds 1000 ppm
(0.1%), the loss-of-lock signal is reasserted and control returns
to the frequency loop, which begins a new frequency
Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph. The CTRLB[7]
bit defaults to 0. In this mode, the LOL pin operates in the
normal operating mode, that is, it is asserted only when the
ADN2806 is in acquisition mode and deasserts when the
ADN2806 has reacquired lock.
acquisition. The LOL pin remains asserted until the VCO locks
onto a valid input data stream to within 250 ppm frequency
error. This hysteresis is shown in Figure 15.
SQUELCH MODES
Two modes for the SQUELCH pin are available with the
ADN2806: squelch data outputs and clock outputs mode and
squelch data outputs or clock outputs mode. Squelch data outputs
and clock outputs mode is selected when CTRLC[1] is 0 (default
mode). In this mode, when the SQUELCH input, Pin 27, is driven
to a TTL high state, both the data outputs (DATAOUTN and
DATAOUTP) and the clock outputs (CLKOUTN and CLKOUTP)
are set to the zero state to suppress downstream processing. If
the squelch function is not required, Pin 27 should be tied to VEE.
LOL
1
–1000
–250
0
250
1000
f
ERROR
VCO
(ppm)
Figure 15. Transfer Function of LOL
Rev. 0 | Page 13 of 20
ADN2806
Squelch data outputs or clock outputs mode is selected when
CTRLC[1] is 1. In this mode, when the SQUELCH input is
driven to a high state, the DATAOUTN and DATAOUTP pins
are squelched. When the SQUELCH input is driven to a low
state, the CLKOUTN and CLKOUTP pins are squelched. This is
especially useful in repeater applications, where the recovered
clock may not be needed.
The ADN2806 acts as a standard slave device on the bus. The data
on the SDA pin is eight bits long, supporting the 7-bit addresses
plus the R/W bit. The ADN2806 has eight subaddresses to enable
the user-accessible internal registers (see Table 6 through Table
10). It, therefore, interprets the first byte as the device address
and the second byte as the starting subaddress. Auto-increment
mode is supported, allowing data to be read from or written to
the starting subaddress and each subsequent address without
manually addressing the subsequent subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without updating all registers.
I2C INTERFACE
The ADN2806 supports a 2-wire, I2C-compatible serial bus
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCK), carry information to and from any device
connected to the bus. Each slave device is recognized by a
unique address. The ADN2806 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is factory programmed to 1. B5 of the slave
address is set by Pin 19, SADDR5. Slave Address Bits [4:0] are
defaulted to all 0s. The slave address consists of the seven MSBs
of an 8-bit word. The LSB of the word either sets a read or write
operation (see Figure 6). Logic 1 corresponds to a read operation,
while Logic 0 corresponds to a write operation.
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCK high period, the
user should issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADN2806 does not
issue an acknowledge and returns to the idle condition. If the
user exceeds the highest subaddress while reading back in auto-
increment mode, then the highest subaddress register contents
continue to be output until the master device issues a no acknow-
ledge. This indicates the end of a read. In a no-acknowledge
condition, the SDATA line is not pulled low on the ninth pulse.
See Figure 7 and Figure 8 for sample write and read data transfers
and Figure 9 for a more detailed timing diagram.
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establish-
ing a start condition, defined by a high-to-low transition on
SDA while SCK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCK lines, waiting for
the start condition and correct transmitted address. The R/W
bit determines the direction of the data. Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
Additional Features Available via the I2C Interface
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new
frequency acquisition while keeping the ADN2806 in its
previously programmed operating mode, as set in Registers
CTRL[A], CTRL[B], and CTRL[C].
Rev. 0 | Page 14 of 20
ADN2806
There are two mutually exclusive uses, or modes, of the
REFERENCE CLOCK (OPTIONAL)
reference clock. The reference clock can be used either to help
the ADN2806 lock onto data or to measure the frequency of the
incoming data to within 0.01%. The modes are mutually
exclusive because in the first use the user knows exactly what
the data rate is and wants to force the part to lock onto only that
data rate, and in the second use the user does not know what
the data rate is and wants to measure it.
A reference clock is not required to perform clock and data
recovery with the ADN2806; however, support for an optional
reference clock is provided. The reference clock can be driven
differentially or in a single-ended fashion. If the reference
clock is not being used, REFCLKP should be tied to VCC, and
REFCLKN can be left floating or tied to VEE (the inputs are
internally terminated to VCC/2). See Figure 16 through Figure
18 for sample configurations.
Lock-to-reference mode is enabled by writing a 1 to I2C Register
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing a 1 to I2C Register Bit CTRLA[1]. Writing a 1 to both of
these bits at the same time causes an indeterminate state and is
not supported.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended, low
voltage TTL input, providing maximum system flexibility.
Phase noise and duty cycle of the reference clock are not
critical, and 100 ppm accuracy is sufficient.
Using the Reference Clock to Lock onto Data
In this mode, the ADN2806 locks onto a frequency derived
from the reference clock according to
ADN2806
Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7, 6]
REFCLKP
10
BUFFER
The user must provide a reference clock that is a function of the
data rate. By default, the ADN2806 expects a reference clock of
19.44 MHz. Other options are 38.88 MHz, 77.76 MHz, and
155.52 MHz, which are selected by programming CTRLA[7, 6].
CTRLA[5:2] should be programmed to [0101] for all cases.
11
REFCLKN
100kΩ 100kΩ
VCC/2
Figure 16. Differential REFCLK Configuration
Table 11. CTRLA Settings
VCC
CTRLA[7, 6]
Range (MHz)
CTRLA[5:2]
0101
0101
0101
0101
Ratio
25
ADN2806
REFCLKP
CLK
00
01
10
11
19.44
38.88
77.76
155.52
OSC
25
OUT
BUFFER
25
25
REFCLKN
100kΩ 100kΩ
For example, if the reference clock frequency is 38.88 MHz and the
input data rate is 622.08 Mbps, CTRLA[7, 6] is set to [01] to
produce a divided-down reference clock of 19.44 MHz, and
CTRLA[5:2] is set to [0101], that is, 5, because
VCC/2
Figure 17. Single-Ended REFCLK Configuration
VCC
622.08 Mbps/19.44 MHz = 25
ADN2806
10
REFCLKP
BUFFER
In this mode, if the ADN2806 loses lock for any reason, it relocks
onto the reference clock and continues to output a stable clock.
11
NC
REFCLKN
While the ADN2806 is operating in lock-to-reference mode,
a 0 to 1 transition should be written into the CTRLA[0] bit to
initiate a lock-to-reference clock command.
100kΩ 100kΩ
VCC/2
Figure 18. No REFCLK Configuration
Rev. 0 | Page 15 of 20
ADN2806
3. Read back MISC[2]. If it is 0, the measurement is not
complete. If it is 1, the measurement is complete and the
data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2806 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to within 0.01% (100 ppm) accuracy.
The accuracy error of the reference clock is added to the accuracy
of the ADN2806 data rate measurement. For example, if a 100 ppm
accuracy reference clock is used, the total accuracy of the measure-
ment is within 200 ppm.
4. Read back the data rate from FREQ2[6:0], FREQ1[7:0], and
FREQ0[7:0].
The data rate can be determined by
fDATARATE
=
FREQ
[22.0
]
× fREFCLK
/2(14 + SEL _ RATE)
)
where:
The reference clock can range from 10 MHz to 160 MHz.
By default, the ADN2806 expects a reference clock between
10 MHz and 20 MHz. If the reference clock is between 20 MHz
and 40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz,
the user must configure the ADN2806 for the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7, 6]. Using the reference clock to determine the frequency
of the incoming data does not affect the manner in which the
part locks onto data. In this mode, the reference clock is used
only to determine the frequency of the data.
FREQ[22:0] is the reading from FREQ2[6:0] (MSB byte,
FREQ1[7:0], and FREQ0[7:0] (LSB byte).
f
DATARATE is the data rate (Mbps).
f
REFCLK is the REFCLK frequency (MHz).
SEL_RATE is the setting from CTRLA[7, 6].
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, because the reference frequency falls into the
20 MHz to 40 MHz range, setting CTRLA[7, 6] to [01],.
Assume for this example that the input data rate is 622.08 Mb/s
(OC12). After following Step 1 through Step 4, the value that is
read back on FREQ[22:0] = 0x9B851, which is equal to 637 × 103.
Plugging this value into the equation yields
Prior to reading back the data rate using the reference clock, the
CTRLA[7, 6] bits must be set to the appropriate frequency
range with respect to the reference clock being used. A fine data
rate readback is then executed as follows:
637e3 × 32e6/2(14 + 1) = 622.08 Mbps
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Step 2 through Step 4 to read back the new data rate.
1. Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2806. This bit is level
sensitive and can perform subsequent frequency measurements
without being reset.
2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].
This initiates a new data rate measurement.
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
Table 12.
D22
D21 ... D17
FREQ2[6:0]
D16
D15
D14 ... D9
FREQ1[7:0]
D8
D7
D6 ... D1
FREQ0[7:0]
D0
Rev. 0 | Page 16 of 20
ADN2806
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
If connections to the supply and ground are made through
vias, the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buffers. Refer to Figure 19 for the
recommended connections.
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using plugged vias so that solder does not leak
through the vias during reflow.
By placing the power supply and GND planes adjacent to each
other and using close spacing between the planes, excellent high
frequency decoupling can be realized. The capacitance is given
by
CPLANE = 0.88εr A/d
pF
)
where:
εr is the dielectric constant of the PCB material.
A is the area of the overlap of power and GND planes (cm2).
d is the separation between planes (mm).
Use of a 22 μF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they
should be placed between ADN2806 supply pins VCC and VEE,
as close as possible to the ADN2806 VCC pins.
For FR-4, εr = 4.4 and d = 0.25 mm; therefore,
C
PLANE ~ 15 pF/cm2.
50Ω TRANSMISSION LINES
VCC
+
DATAOUTP
DATAOUTN
CLKOUTP
CLKOUTN
22µF
0.1µF
1nF
VCC
1nF
0.1µF
TEST1
VCC
VEE
NC
SDA
SCK
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCC
VREF
NIN
PIN
NC
NC
VEE
EXPOSED PAD
TIED OFF TO
VEE PLANE
WITH VIAS
2
I C CONTROLLER
0.1µF
1nF
0.1µF
µC
2
I C CONTROLLER
SADDR5
VCC
VCC
VEE
1nF
0.1µF
1.6µF
1.6µF
50Ω
LIM
50Ω
µC
0.47µF ±20%
>300MΩ INSULATION RESISTANCE
VCC
0.1µF
1nF
Figure 19. Typical ADN2806 Applications Circuit
Rev. 0 | Page 17 of 20
ADN2806
Transmission Lines
Choosing AC Coupling Capacitors
Minimizing reflections in the ADN2806 requires use of 50 Ω
transmission lines for all pins with high frequency input and
output signals, including PIN, NIN, CLKOUTP, CLKOUTN,
DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN,
if a high frequency reference clock is used, such as 155 MHz). It
is also necessary for the PIN/NIN input traces to be matched in
length and for the CLKOUTP/CLKOUTN and
AC coupling capacitors at the input (PIN, NIN) and output
(DATAOUTP, DATAOUTN) of the ADN2806 can be optimized
for the application. When choosing the capacitors, the time
constant formed with the two 50 Ω resistors in the signal path
must be considered. When a large number of consecutive
identical digits (CIDs) are applied, the capacitor voltage can
droop due to baseline wander (see Figure 21), causing pattern-
dependent jitter (PDJ).
DATAOUTP/DATAOUTN output traces to be matched in
length to avoid skew between the differential traces.
The user must determine how much droop is tolerable and
choose an ac coupling capacitor based on that amount of droop.
The amount of PDJ can then be approximated based on the
capacitor selection. The actual capacitor value selection can
require some trade-offs between droop and PDJ.
The high speed inputs, PIN and NIN, are internally terminated
with 50 Ω to an internal reference voltage (see Figure 20).
A 0.1 μF is recommended between VREF, Pin 3, and GND to
provide an ac ground for the inputs.
As with any high speed, mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
For example, assuming that 2% droop can be tolerated, the
maximum differential droop is 4%. Normalizing to V p-p:
Droop = ΔV = 0.04 V = 0.5 V p-p (1 − e−t/τ); therefore, τ = 12t
ADN2806
C
IN
LIM
50Ω
PIN
where:
τ is the RC time constant (C is the ac coupling capacitor, R =
100 Ω seen by C).
t is the total discharge time, which is equal to nT, where n is the
number of CIDs, and T is the bit period.
C
IN
50Ω
NIN
50Ω 50Ω
3kΩ
VREF
2.5V
0.1µF
The capacitor value can then be calculated by combining the
equations for τ and t:
Figure 20. ADN2806 AC-Coupled Input Configuration
C = 12 nT/R
Soldering Guidelines for Lead Frame Chip Scale Package
The lands on the 32-lead LFCSP are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This
ensures that the solder joint size is maximized. The bottom of
the chip scale package has a central exposed pad. The pad on
the PCB should be at least as large as this exposed pad. The user
must connect the exposed pad to VEE using plugged vias so
that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
Once the capacitor value is selected, the PDJ can be
approximated as
PDJpspp = 0.5 tr(1 − e(−nT/RC))/0.6
where:
PDJpspp is the amount of pattern-dependent jitter allowed
(<0.01 UI p-p typical).
tr is the rise time, which is equal to 0.22/BW,
where BW ~ 0.7 (bit rate).
Note that this expression for tr is accurate only for the inputs.
The output rise time for the ADN2806 is ~100 ps regardless of
the data rate.
Rev. 0 | Page 18 of 20
ADN2806
ADN2806
C
C
LIM
V1
IN
V2
PIN
C
C
OUT
+
DATAOUTP
DATAOUTN
50Ω
CDR
BUFFER
V
REF
IN
V1b
V2b
50Ω
NIN
–
OUT
1
2
3
4
V1
V1b
V2
VREF
V2b
VTH
V
DIFF
V
= V2–V2b
DIFF
VTH = ADN2806 THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2AND V2b DISCHARGE TO THE
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2806.
THE QUANTIZER CAN RECOGNIZE BOTH HIGHAND LOW STATES AT THIS POINT.
Figure 21. Example of Baseline Wander
Rev. 0 | Page 19 of 20
ADN2806
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
EXPOSED
PAD
(BOTTOM VIEW)
3.45
3.30 SQ
3.15
TOP
VIEW
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 22. 32-Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ADN2806ACPZ1
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ, Tape-Reel, 500 pieces
32-Lead LFCSP_VQ, Tape-Reel, 1500 pieces
Evaluation Board
CP-32-3
CP-32-3
CP-32-3
ADN2806ACPZ-500RL71
ADN2806ACPZ-RL71
EVAL-ADN2806EB
1 Z = Pb-free part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05831–0–2/06(0)
Rev. 0 | Page 20 of 20
相关型号：
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