ADN2848ACP-32 [ADI]
3 V Dual-Loop 50 Mbps to 1.25 Gbps Laser Diode Driver; 3 V双回路50 Mbps到1.25 Gbps的激光二极管驱动器
| 型号： | ADN2848ACP-32 |
| 厂家： | 
ADI |
| 描述： | 3 V Dual-Loop 50 Mbps to 1.25 Gbps Laser Diode Driver |
| 文件： | 总12页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 V Dual-Loop 50 Mbps to 1.25 Gbps
Laser Diode Driver
a
ADN2848
FEATURES
GENERAL DESCRIPTION
50 Mbps to 1.25 Gbps Operation
Single 3.3 V Operation
The ADN2848 uses a unique control algorithm to control both
the average power and extinction ratio of the laser diode, LD,
after initial factory setup. External component count and PCB
area are low as both power and extinction ratio control are
fully integrated. Programmable alarms are provided for laser fail
(end of life) and laser degrade (impending fail).
Bias Current Range 2 mA to 100 mA
Modulation Current Range 5 mA to 80 mA
Monitor Photo Diode Current 50 ꢀA to 1200 ꢀA
50 mA Supply Current at 3.3 V
Closed-Loop Control of Power and Extinction Ratio
Full Current Parameter Monitoring
Laser Fail and Laser Degrade Alarms
Automatic Laser Shutdown, ALS
Optional Clocked Data
Supports FEC Rates
32-Lead (5 mm × 5 mm) LFCSP Package
APPLICATIONS
SONET OC-1/3/12
SDH STM-0/1/4
Fibre Channel
Gigabit Ethernet
FUNCTIONAL BLOCK DIAGRAM
V
CC
V
CC
IMODN
LD
V
CC
IMODP
MPD
IMPD
DATAP
DATAN
CLKP
CLKN
I
MOD
CONTROL
PSET
I
BIAS
I
BIAS
ASET
GND
GND
ERSET
ADN2848
GND
ERCAP
PAVCAP
LBWSET
GND
GND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(VCC = 3.0 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted.1
ADN2848–SPECIFICATIONS Typical values as specified at 25ꢁC.)
Parameter
Min
Typ
Max
Unit
Conditions/Comments
LASER BIAS (BIAS)
Output Current IBIAS
Compliance Voltage
IBIAS During ALS
ALS Response Time
CCBIAS Compliance Voltage
2
1.2
100
VCC
0.1
5
mA
V
mA
ꢀs
V
IBIAS < 10% of nominal
1.2
VCC
MODULATION CURRENT (IMODP, IMODN)
Output Current IMOD
Compliance Voltage
5
1.5
80
mA
V
mA
ps
ps
ps
VCC
0.1
170
170
1.5
I
MOD During ALS
Rise Time2
80
80
1
Fall Time2
Random Jitter2
Pulsewidth Distortion2
RMS
IMOD = 40 mA
15
ps
MONITOR PD (MPD)
Current
Compliance Voltage
50
1200
1.65
ꢀA
V
Average Current
Average Current
POWER SET INPUT (PSET)
Capacitance
Monitor Photodiode Current into RPSET Resistor
Voltage
80
1200
1.3
pF
ꢀA
V
50
1.1
1.2
1.2
EXTINCTION RATIO SET INPUT (ERSET)
Allowable Resistance Range
Voltage
1.2
1.1
25
1.3
kΩ
V
ALARM SET (ASET)
Allowable Resistance Range
Voltage
1.2
1.1
25
1.3
kΩ
V
%
1.2
5
Hysteresis
CONTROL LOOP
Time Constant
Low Loop Bandwidth Selection
LBWSET = GND
LBWSET = VCC
0.22
2.25
s
s
DATA INPUTS (DATAP, DATAN, CLKP, CLKN)3
V p-p (Single-Ended, Peak-to-Peak)
Input Impedance (Single-Ended)
tSETUP4 (see Figure 1)
100
500
mV
Ω
Data and Clock Inputs Are
AC-Coupled
50
50
100
ps
tHOLD4 (see Figure 1)
ps
LOGIC INPUTS (ALS, LBWSET, CLKSEL)
VIH
VIL
2.4
2.4
V
V
0.8
0.8
ALARM OUTPUTS (Internal 30 kΩ Pull-Up)
VOH
VOL
V
V
IBMON, IMMON, IMPDMON
IMMON Division Ratio
IMPDMON
100
1
A/A
A/A
V
Compliance Voltage
0
VCC – 1.2
3.6
SUPPLY
5
ICC
50
3.3
mA
V
IBIAS = IMOD = 0
6
VCC
3.0
NOTES
1Temperature range is as follows: –40°C to +85°C.
2Measured into a 25 Ω load using a 0-1 pattern at 622 Mbps.
3When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin.
4Guaranteed by design and characterization. Not production tested.
5ICCMIN for power calculation on page 6 is the typical ICC given.
6All VCC pins should be shorted together.
Specifications subject to change without notice.
–2–
REV. 0
ADN2848
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C, unless otherwise noted.)
ORDERING GUIDE
Temperature
Range
Package
Description
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 V
Digital Inputs
Model
(ALS, LBWSET, CLKSEL) . . . . . . . . . –0.3 V to VCC + 0.3 V
IMODN, IMODP . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 1.2 V
Operating Temperature Range
ADN2848ACP-32
ADN2848ACP-32-RL
ADN2848ACP-32-RL7 –40°C to +85°C 32-Lead LFCSP
–40°C to +85°C 32-Lead LFCSP
–40°C to +85°C 32-Lead LFCSP
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . 150°C
32-Lead LFCSP Package
Power Dissipation2 . . . . . . . . . . . . . . . . (TJ max – TA)/θJA W
HOLD
tH
SETUP
tS
θ
JA Thermal Impedance3 . . . . . . . . . . . . . . . . . . . . . 32°C/W
Lead Temperature (Soldering for 10 sec) . . . . . . . . . . 300°C
NOTES
DATAP/DATAN
CLKP
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2Power consumption formulae are provided on Page 6.
Figure 1. Setup and Hold Time
3θJA is defined when device is soldered in a 4-layer board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADN2848 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–3–
ADN2848
PIN CONFIGURATION
V
2 25
16 CLKN
15 CLKP
14 GND1
13 DATAP
12 DATAN
CC
IMODN 26
GND2 27
IMODP 28
GND2 29
GND2 30
ADN2848
TOP VIEW
11 V
1
CC
I
31
10 PAVCAP
9 ERCAP
BIAS
CCBIAS 32
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Function
1
2
LBWSET
ASET
Loop Bandwidth Select
Alarm Threshold Set Pin
3
4
ERSET
PSET
Extinction Ratio Set Pin
Average Optical Power Set Pin
5
IMPD
Monitor Photodiode Input
6
7
IMPDMON
GND4
Mirrored Current from Monitor Photodiode—Current Source
Supply Ground
8
VCC
4
Supply Voltage
9
ERCAP
PAVCAP
Extinction Ratio Loop Capacitor
Average Power Loop Capacitor
Supply Voltage
Data Negative Differential Terminal
Data Positive Differential Terminal
Supply Ground
Data Clock Positive Differential Terminal, Used if CLKSEL = VCC
Data Clock Negative Differential Terminal, Used if CLKSEL = VCC
Clock Select (Active = VCC), Used if Data Is Clocked into Chip
DEGRADE Alarm Output
FAIL Alarm Output
Automatic Laser Shutdown
Supply Voltage
Supply Ground
Modulation Current Mirror Output—Current Source
Bias Current Mirror Output—Current Source
Supply Voltage
Modulation Current Negative Output, Connect via Matching Resistor to VCC
Supply Ground
Modulation Current Positive Output, Connect to Laser Diode
Supply Ground
Supply Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VCC
1
DATAN
DATAP
GND1
CLKP
CLKN
CLKSEL
DEGRADE
FAIL
ALS
VCC
3
GND3
IMMON
IBMON
VCC
2
IMODN
GND2
IMODP
GND2
GND2
IBIAS
Laser Diode Bias Current Output
Extra Laser Diode Bias When AC-Coupled—Current Sink
CCBIAS
–4–
REV. 0
ADN2848
GENERAL
Note that IERSET and IPSET will change from device to device;
however, the control loops will determine the actual values.
It is not required to know the exact values for LI or MPD
optical coupling.
Laser diodes have current-in to light-out transfer functions as
shown in Figure 2. Two key characteristics of this transfer func-
tion are the threshold current, ITH, and slope in the linear region
beyond the threshold current, referred to as slope efficiency, LI.
Loop Bandwidth Selection
For continuous operation, the user should hardwire the LBWSET
pin high and use 1 µF capacitors to set the actual loop band-
width. These capacitors are placed between the PAVCAP and
ERCAP pins and ground. It is important that these capaci-
tors are low leakage multilayer ceramics with an insulation
resistance greater than 100 GΩ or a time constant of 1,000 sec,
whichever is less.
P1
ER =
P0
P1 + P0
P
=
AV
2
P1
ꢂP
P
AV
ꢂP
ꢂI
LI =
ꢂI
P0
Operation
Mode
Recommended Recommended
LBWSET PAVCAP
ERCAP
I
CURRENT
TH
Continuous
50 Mbps to
1.25 Gbps
High
1 µF
1 µF
Figure 2. Laser Transfer Function
Control
Optimized
for 1.25 Gbps
Low
47 nF
47 nF
A monitor photodiode, MPD, is required to control the LD.
The MPD current is fed into the ADN2848 to control the power
and extinction ratio, continuously adjusting the bias current and
modulation current in response to the laser’s changing threshold
current and light-to-current slope efficiency.
Setting LBSET low and using 47 nF capacitors results in a
shorter loop time constant (a 10× reduction over using 1 µF
capacitors and keeping LBWSET high).
The ADN2848 uses automatic power control, APC, to maintain
a constant average power over time and temperature.
Alarms
The ADN2848 is designed to allow interface compliance to
ITU-T-G958 (11/94) section 10.3.1.1.2 (transmitter fail) and
section 10.3.1.1.3 (transmitter degrade). The ADN2848 has two
active high alarms, DEGRADE and FAIL. A resistor between
ground and the ASET pin is used to set the current at which these
alarms are raised. The current through the ASET resistor is a ratio
of 100:1 to the FAIL alarm threshold. The DEGRADE alarm will
be raised at 90% of this level.
The ADN2848 uses closed-loop extinction ratio control to
allow optimum setting of extinction ratio for every device. Thus
SONET/SDH interface standards can be met over device
variation, temperature, and laser aging. Closed-loop modulation
control eliminates the need to either overmodulate the LD or
include external components for temperature compensation.
This reduces research and development time and second
sourcing issues caused by characterizing LDs.
Example:
Average power and extinction ratio are set using the PSET and
ERSET pins, respectively. Potentiometers are connected
between these pins and ground. The potentiometer RPSET is
used to change the average power. The potentiometer RERSET is
used to adjust the extinction ratio. Both PSET and ERSET are
kept 1.2 V above GND.
IFAIL = 50 mA so IDEGRADE = 45 mA
IFAIL 50 mA
IASET
=
=
= 500 ꢀA
100
1.2V
100
1.2
*RASET
=
=
= 2.4 kꢁ
IASET 500ꢀA
For an initial setup, RPSET and RERSET potentiometers may be
calculated using the following formulas.
*The smallest valid value for RASET is 1.2 kΩ, since this corresponds to the IBIAS
maximum of 100 ꢀA.
1.2V
IAV
RPSET
=
(Ω)
The laser degrade alarm, DEGRADE, is provided to give a
warning of imminent laser failure if the laser diode degrades
further or environmental conditions continue to stress the LD,
such as increasing temperature.
1.2V
RERSET
(Ω)
IMPD _ CW ER −1
×
× PAV
The laser fail alarm, FAIL, is activated when the transmitter can
no longer be guaranteed to be SONET/SDH compliant. This
occurs when one of the following conditions arise:
PCW
ER +1
where:
I
P
AV is the average MPD current.
CW is the dc optical power specified on the laser data sheet.
•
•
The ASET threshold is reached.
The ALS pin is set high. This shuts off the modulation and
bias currents to the LD, resulting in the MPD current drop-
ping to zero. This gives closed-loop feedback to the system
that ALS has been enabled.
I
P
MPD_CW is the MPD current at that specified PCW.
AV is the average power required.
ER is the desired extinction ratio (ER = P1/P0).
DEGRADE will be raised only when the bias current exceeds
90% of ASET current.
REV. 0
–5–
ADN2848
Monitor Currents
CCBIAS
IBMON, IMMON, and IMPDMON are current controlled
current sources from VCC. They mirror the bias, modulation,
and MPD current for increased monitoring functionality. An
external resistor to GND gives a voltage proportional to the
current monitored.
When the laser is used in ac-coupled mode, the CCBIAS and
the IBIAS pins should be tied together (see Figure 7). In dc-
coupled mode, CCBIAS should be tied to VCC
.
Automatic Laser Shutdown
The ADN2848 ALS allows compliance to ITU-T-G958 (11/94),
section 9.7. When ALS is logic high, both bias and modulation
currents are turned off. Correct operation of ALS can be con-
firmed by the FAIL alarm being raised when ALS is asserted.
Note that this is the only time that DEGRADE will be low
while FAIL is high.
If the monitoring function IMPDMON is not required, the
IMPD pin must be grounded and the monitor photodiode
output must be connected directly to the PSET pin.
Data and Clock Inputs
Data and clock inputs are ac-coupled (10 nF capacitors recom-
mended) and terminated via a 100 Ω internal resistor between
DATAP and DATAN and also between the CLKP and CLKN
pins. There is a high impedance circuit to set the common-
mode voltage, which is designed to allow for maximum input
voltage headroom over temperature. It is necessary that ac
coupling be used to eliminate the need for matching between
common-mode voltages.
Alarm Interfaces
The FAIL and DEGRADE outputs have an internal 30 kΩ pull-
up resistor that is used to pull the digital high value to VCC
.
However, the alarm output may be overdriven with an external
resistor allowing alarm interfacing to non-VCC levels. Non-VCC
alarm output levels must be below the VCC used for the
ADN2848.
Power Consumption
The ADN2848 die temperature must be kept below 125oC. The
LFCSP package has an exposed paddle. The exposed paddle
should be connected in such a manner that it is at the same
potential as the ADN2848 ground pins. The θJA for the package
is shown under the Absolute Maximum Ratings. Power con-
sumption can be calculated using
ADN2848
DATAP
(TO FLIP-FLOPS)
DATAN
50ꢃ 50ꢃ
V
REG
R
I
CC = ICCMIN + 0.3 IMOD
R = 2.5kꢃ, DATA
R = 3kꢃ, CLK
P = VCC ꢂ ICC + (IBIAS ꢂ VBIAS_PIN) + IMOD (VMODP_PIN
+
VMODN_PIN)/2
400ꢀATYP
T
DIE = TAMBIENT + θJA ꢂ P
Thus, the maximum combination of IBIAS + IMOD must be calcu-
lated. Where:
Figure 3. AC Coupling of Data Inputs
ICCMIN
= 50 mA, the typical value of ICC provided on Page 2
For input signals that exceed 500 mV p-p single-ended, it is
necessary to insert an attenuation circuit as shown in Figure 4.
with IBIAS = IMOD = 0
T
T
DIE = die temperature
AMBIENT = ambient temperature
ADN2848
R1
R2
DATAP/CLKP
DATAN/CLKN
V
V
V
BIAS_PIN = voltage at IBIAS pin
R
R3
IN
MODP_PIN = average voltage at IMODP pin
MODN_PIN = average voltage at IMODN pin
Laser Disode Interfacing
NOTETHAT R = 100ꢃ =THE DIFFERENTIAL
IN
Many laser diodes designed for 1.25 Gbps operation are pack-
aged with an internal resistor to bring the effective impedance
up to 25 Ω in order to minimize transmission line effects. In
high current applications, the voltage drop across this resistor,
combined with the laser diode forward voltage, makes direct
connection between the laser and the driver impractical in a 3 V
system. AC coupling the driver to the laser diode removes this
headroom constraint.
INPUT IMPEDANCE OFTHE ADN2848
Figure 4. Attenuation Circuit
–6–
REV. 0
ADN2848
V
CC
Caution must be used when choosing component values for ac
coupling to ensure that the time constant (L/R and RC, see
Figure 7) are sufficiently long for the data rate and expected
number of CIDs (consecutive identical digits). Failure to do this
could lead to pattern dependent jitter and vertical eye closure.
For designs with low series resistance, or where external
components become impractical, the ADN2848 supports direct
connection to the laser diode (see Figure 6). In this case, care
must be taken to ensure that the voltage drop across the laser
diode does not violate the minimum compliance voltage on the
IMODP pin.
V
CC
V
CC
IMPD
ADN2848
ADN2850
SDI
IMODP
I
BIAS
TX
RX
SDO
PSET
DAC1
DAC2
ERSET
CLK
CLK
CS
CS
Optical Supervisor
The PSET and ERSET potentiometers may be replaced with a
dual-digital potentiometer, the ADN2850 (see Figure 5). The
ADN2850 provides an accurate digital control for the average
optical power and extinction ratio and ensures excellent stability
over temperature.
DATAP
DATAN
IDTONE
Figure 5. Application Using the ADN2850 Dual 10-Bit
Digital Potentiometer with Extremely Low Temperature
Coefficient as an Optical Supervisor
FAIL
DEGRADE
ALS
1kꢃ
1.5kꢃ
1.5kꢃ
24
17
25
16
10nF
V
2
CLKN
CLKN
V
CC
CC
IMODN
GND2
IMODP
GND2
GND2
CLKP
CLKP
V
CC
*
10nF
GND1
10nF
MPD
LD
*
DATAP
DATAN
DATAP
*
ADN2848
DATAN
*
10nF
1ꢀF
V
1
CC
I
PAVCAP
ERCAP
BIAS
10ꢀH
CCBIAS
1ꢀF
V
CC 32
9
V
s SHOULD HAVE BYPASS CAPACITORS AS CLOSE
CC
AS POSSIBLETOTHE ACTUAL SUPPLY PINS ONTHE
ADN2848 ANDTHE LASER DIODE USED.
CONSERVATIVE DECOUPLINGWOULD INCLUDE 100pF
CAPACITORS IN PARALLELWITH 10nF CAPACITORS.
1
8
**
**
1.5kꢃ
V
CC
LD = LASER DIODE
MPD = MONITOR PHOTODIODE
10nF
10nF
10nF
10nF
10ꢀF
GND
NOTES
DESIGNATES COMPONENTSTHAT NEEDTO BE OPTIMIZED FORTHETYPE OF LASER USED.
** FOR DIGITAL PROGRAMMING,THE ADN2850 ORTHE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
*
Figure 6. DC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked
REV. 0
–7–
ADN2848
FAIL
DEGRADE
V
CC
ALS
1kꢃ
*
*
*
*
*
1.5kꢃ
1.5kꢃ
*
24
17
25
16
10nF
V
2
CLKN
V
CLKN
CLKP
CC
CC
IMODN
CLKP
GND1
10nF
10nF
GND2
IMODP
GND2
GND2
MPD
LD
*
DATAP
DATAN
DATAP
DATAN
*
*
ADN2848
*
10nF
V
1
CC
1ꢀF
I
PAVCAP
ERCAP
BIAS
10ꢀH
CCBIAS
1ꢀF
32
9
V
s SHOULD HAVE BYPASS CAPACITORS AS CLOSE
CC
AS POSSIBLETOTHE ACTUAL SUPPLY PINS ONTHE
ADN2848 ANDTHE LASER DIODE USED.
1
8
CONSERVATIVE DECOUPLINGWOULD INCLUDE 100pF
CAPACITORS IN PARALLELWITH 10nF CAPACITORS.
**
**
1.5kꢃ
V
CC
LD = LASER DIODE
MPD = MONITOR PHOTODIODE
10nF
10nF
10nF
10nF
10ꢀF
GND
NOTES
DESIGNATES COMPONENTSTHAT NEEDTO BE OPTIMIZED FORTHETYPE OF LASER USED.
** FOR DIGITAL PROGRAMMING,THE ADN2850 ORTHE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
*
Figure 7. AC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked
Figure 8. A 1.244 Mbps Optical Eye. Temperature at 25ꢃC.
Figure 9. A 1.244 Mbps Optical Eye. Temperature at 85ꢃC.
Average Power = 0 dBm, Extinction Ratio = 10 dBm, PRBS
31 Pattern, 1 Gb Ethernet Mask. Eye Obtained Using a
DFB Laser.
Average Power = 0 dBm, Extinction Ratio = 10 dB, PRBS
31 Pattern, 1 Gb Ethernet Mask. Eye Obtained Using a
DFB Laser.
–8–
REV. 0
ADN2848
OUTLINE DIMENSIONS
32-Lead Frame Chip Scale Package [LFCSP]
(CP-32)
Dimensions shown in millimeters
5.00
BSC SQ
0.60 MAX
PIN 1
0.60 MAX
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
2.25
1.70 SQ
0.75
4.75
BSC SQ
TOP
VIEW
BOTTOM
VIEW
0.50
0.40
0.30
17
16
8
9
3.50
REF
0.70 MAX
0.65 NOM
12ꢁ MAX
0.05 MAX
0.02 NOM
1.00
0.30
0.23
0.18
0.90
0.80
COPLANARITY
0.08
0.25 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
REV. 0
–9–
–10–
–11–
–12–
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