ADN2892ACPZ-RL7 [ADI]
3.3 V, 4.25 Gbps, Limiting Amplifier; 3.3 V ， 4.25 Gbps的速率，限幅放大器
| 型号： | ADN2892ACPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | 3.3 V, 4.25 Gbps, Limiting Amplifier |
| 文件： | 总16页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 V, 4.25 Gbps,
Limiting Amplifier
Data Sheet
ADN2892
FEATURES
GENERAL DESCRIPTION
Input sensitivity: 3.5 mV p-p
70 ps rise/fall times
The ADN2892 is a 4.25 Gbps limiting amplifier with integrated
loss of signal (LOS) detection circuitry and a received signal
strength indicator (RSSI). This part is optimized for Fibre
Channel (FC) and Gigabit Ethernet (GbE) optoelectronic
conversion applications. The ADN2892 has a differential input
sensitivity of 3.5 mV p-p and accepts up to a 2.0 V p-p
CML outputs: 750 mV p-p differential
Bandwidth selectable for multirate 1×/2×/4× FC modules
Optional LOS output inversion
Programmable LOS detector: 3.5 mV to 35 mV
Rx signal strength indicator (RSSI)
differential input overload voltage. The ADN2892 has current
mode logic (CML) outputs with controlled rise and fall times.
SFF-8472-compliant average power measurement
Single-supply operation: 3.3 V
The ADN2892 has a selectable low-pass filter with a −3 dB
cutoff frequency of 1.5 GHz. By setting BW_SEL to Logic 0, the
filter can limit the relaxation oscillation of a low cost CD laser
used in a legacy 1 Gbps FC transmitter. The limited BW also
reduces the rms noise and in turn improves the receiver optical
sensitivity for a lower data rate application, such as 1× FC and
GbE.
Low power dissipation: 160 mW
Available in space-saving, 3 mm × 3 mm, 16-lead LFCSP
Extended temperature range: −40°C to +95°C
SFP reference design available
APPLICATIONS
1×, 2×, and 4× FC transceivers
SFP/SFF/GBIC optical transceivers
GbE transceivers
By monitoring the bias current through a photodiode, the on-
chip RSSI detector measures the average power received with
2% typical linearity over the entire valid input range of the
photodiode. The on-chip RSSI detector facilitates SFF-8472-
compliant optical transceivers by eliminating the need for
external RSSI detector circuitry.
Backplane receivers
Additional features include a programmable loss-of-signal
(LOS) detector and output squelch. The ADN2892 is available
in a 3 mm × 3 mm, 16-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
AVCC AVEE
BW_SEL
SQUELCH
DRVEE
DRVCC
ADN2892
50W
50W
OUTP
OUTN
PIN
NIN
ADN2882
LPF
50W
50W
V+
10kW
3.5kW
LOS
V
REF
PD_VCC
RSSI/LOS
DETECTOR
ADuC7020
RSSI_OUT
PD_CATHODE
THRADJ
LOS_INV
Figure 1. RSSI Function Capable—Applications Setup Block Diagram
Rev. A
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Technical Support
www.analog.com
ADN2892
Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Squelch Mode ............................................................................. 10
BW_SEL (Bandwidth Selection) Mode................................... 10
LOS_INV (Lose of Signal_Invert) Mode ................................ 10
Applications..................................................................................... 11
PCB Design Guidelines ............................................................. 11
Pad Coating and Pb-Free Soldering ........................................ 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Limiting Amplifier ..................................................................... 10
Loss-of-Signal (LOS) Detector ................................................. 10
Received Signal Strength Indicator (RSSI).............................. 10
REVISION HISTORY
7/13—Rev. 0 to Rev. A
Change to Output Voltage Swing Parameter, Table 1...................3
Changes to Figure 2...........................................................................6
Updated Outline Dimensions........................................................13
Changes to Ordering Guide ...........................................................13
4/05—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
ADN2892
SPECIFICATIONS
Test Conditions: VCC = 2.9 V to 3.6 V, VEE = 0 V, TA = −40°C to +95°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
QUANTIZER DC CHARACTERISTICS
Input Voltage Range
Input Common Mode
Peak-to-Peak Differential Input Range
Input Sensitivity
Input Offset Voltage
Input RMS Noise
Input Resistance
VCC − 1.2
2.1
VCC − 0.2
2.7
2.0
V
V
At PIN or NIN, dc-coupled
DC-coupled
PIN − NIN, ac-coupled
PIN − NIN, BER ≤ 1 × 10−10
V p-p
mV p-p
µV
µV rms
Ω
6.6
1.0
3.5
100
235
50
Single-ended
Input Capacitance
QUANTIZER AC CHARACTERISTICS
Input Data Rate
0.65
pF
4.25
Gbps
dB
Small Signal Gain
51
Differential
S11
S22
Random Jitter
Deterministic Jitter
Low Frequency Cutoff
Power Supply Rejection
LOSS OF SIGNAL DETECTOR (LOS)
LOS Assert Level
−10
−10
3.0
10
30
45
dB
dB
ps rms
ps p-p
kHz
dB
Differential, f < 4.25 GHz
Differential, f < 4.25 GHz
Input ≥ 10 mV p-p, 4× FC, K28.7 pattern
Input ≥ 10 mV p-p, 4× FC, K28.5 pattern
3.9
21.0
100 kHz < f < 10 MHz
2.9
22.4
2.5
3.5
35
5.0
5.0
950
62
4.8
55.0
mV p-p
mV p-p
dB
dB
ns
RTHRADJ = 100 kΩ
RTHRADJ = 1 kΩ
1.0 Gbps, PRBS 223 − 1
4× FC, PRBS 223 − 1
DC-coupled
Electrical Hysteresis
2.8
LOS Assert Time
LOS Deassert Time
ns
DC-coupled
RSSI
Input Current Range
5
1000
µA
RSSI Output Linearity
Gain
Offset
2
1.0
145
%
5 µA ≤ IIN ≤ 1000 µA
IRSSI/IPD_CATHODE
mA/mA
nA
V
Compliance Voltage (At PD_CATHODE)
VCC − 0.4
VCC − 0.9
IPD_CATHODE = 5 µA
IPD_CATHODE = 1000 µA
V
BW_SEL (BANDWIDTH SELECTION)
Channel Bandwidth
1.5
GHz
−3 dB cutoff frequency of the on-chip,
two-pole, low-pass filter, when BW_SEL = 0
POWER SUPPLIES
VCC
ICC
2.9
3.3
48
3.6
54
V
mA
°C
OPERATING TEMPERATURE RANGE
CML OUTPUT CHARACTERISTICS
Output Impedance
Output Voltage Swing
Output Rise and Fall Time
−40
+25
+95
TMIN to TMAX
50
750
70
Ω
Single-ended
Differential
20% to 80%
600
940
103
mV p-p
ps
Rev. A | Page 3 of 16
ADN2892
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS (SQUELCH, LOS_INV, AND
BW_SEL)
VIH, Input High Voltage
2.0
V
VIL, Input Low Voltage
Input Current (SQUELCH, LOS_INV)
0.8
39
V
µA
IINH, VIN = 2.4 V, 100 kΩ pull-down,
on-chip resistor
Input Current (BW_SEL)
−38
µA
IINL, VIN = 0.0 V, 100 kΩ pull-up,
on-chip resistor
LOGIC OUTPUTS (LOS)
VOH, Output High Voltage
2.4
V
V
Open drain output, 4.7 kΩ − 10 kΩ
pull-up resistor to VCC
Open drain output, 4.7 kΩ − 10 kΩ
pull-up resistor to VCC
VOL, Output Low Voltage
0.4
Rev. A | Page 4 of 16
Data Sheet
ADN2892
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Power Supply Voltage
Minimum Voltage
(All Inputs and Outputs)
Maximum Voltage
(All Inputs and Outputs)
Storage Temperature
Operating Temperature Range
Production Soldering Temperature
Junction Temperature
4.2 V
VEE − 0.4 V
VCC + 0.4 V
−65°C to +150°C
−40°C to +95°C
J-STD-20
THERMAL RESISTANCE
125°C
θJA is specified for 4-layer PCB with exposed paddle soldered
to GND.
Table 3.
Package Type
θJA
Unit
3 mm × 3 mm, 16-lead LFCSP
28
°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 16
ADN2892
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 DRVCC
11 OUTP
10 OUTN
AVDD
PIN
1
2
3
4
ADN2892
TOP VIEW
NIN
(Not to Scale)
AVEE
9 DRVEE
NOTES
1. THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO
THE GND PLANE WITH FILLED VIAS.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
I/O Type1 Description
1
2
3
4
5
6
7
AVCC
PIN
NIN
AVEE
THRADJ
BW_SEL
LOS_INV
P
Analog Power Supply.
AI
AI
P
AO
DI
DI
Differential Data Input, Positive Port, 50 Ω On-Chip Termination.
Differential Data Input, Negative Port, 50 Ω On-Chip Termination.
Analog Ground.
LOS Threshold Adjust Resistor.
With one 100 kΩ on-chip, pull-up resistor, BW_SEL = 0 for 1×/2× FC, BW_SEL = 1 for 4× FC.
With one 100 kΩ on-chip, pull-down resistor, LOS_INV = 1 inverts the LOS output
to be active low for SFF.
8
9
LOS
DRVEE
OUTN
DO
P
DO
DO
P
DI
AO
P
LOS Detector Output, Open Collector.
Output Buffer Ground.
Differential Data Output, CML, Negative Port, 50 Ω, On-Chip Termination.
Differential Data Output, CML, Positive Port, 50 Ω, On-Chip Termination.
Output Buffer Power Supply.
Disable Outputs, 100 kΩ On-Chip, Pull-Down Resistor.
Average Current Output.
Power Input for RSSI Measurement.
10
11
12
13
14
15
16
OUTP
DRVCC
SQUELCH
RSSI_OUT
PD_VCC
PD_CATHODE AO
Photodiode Bias Voltage.
Exposed Pad Pad
P
Connect to Ground.
1 P = power; DI = digital input; DO = digital output; AI = analog input; and AO = analog output.
Rev. A | Page 6 of 16
Data Sheet
ADN2892
TYPICAL PERFORMANCE CHARACTERISTICS
0.06
0.05
0.04
0.03
0.02
0.01
0
+95°C
+25°C
–40°C
+25°C
DEASSERTION
–40°C
+95°C
ASSERTION
1k
10k
(W)
100k
50ps/DIV
R
TH
Figure 6. LOS Trip and Release vs. RTH at 4.25 Gbps
Figure 3. Eye of ADN2892 @ 25°C, 4.25 Gbps, and 10 mV Input
8
7
6
5
4
3
2
1
0
1GBPS
4.25GBPS
1k
10k
(W)
100k
50ps/DIV
R
TH
Figure 4. Eye of ADN2892 @ 95°C, 4.25 Gbps, and 10 mV Input
Figure 7. LOS Electrical Hysteresis vs. RTH at 25°C
16
14
12
10
8
6
4
2
200ps/DIV
0
5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6
ELECTRICAL HYSTERESIS (dB)
Figure 5. Eye of ADN2892 at 25°C, 1.063 Gbps, and 10 mV Input (BW_SEL = 0)
Figure 8. Sample Lot Distribution—Worst-Case Condition:
Conditions = 4.25 Gbps, 100 kΩ @ −40°C, 3.6 V
Rev. A | Page 7 of 16
ADN2892
Data Sheet
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
1200
1000
800
600
400
200
0
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
200
400
600
800
1000
RATE (Gbps)
PD_CATHODE CURRENT (PHOTODIODE CURRENT) (µA)
Figure 12. RSSI Output vs. Average Photodiode Current
Figure 9. Random Jitter vs. Data Rate
60
50
40
30
20
10
0
18
16
14
12
10
8
6
4
2
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
10
20
30
40
50
RATE (Gbps)
PD_CATHODE CURRENT (PHOTODIODE CURRENT) (µA)
Figure 10. Deterministic Jitter vs. Data Rate
Figure 13. RSSI Output vs. Average Photodiode Current (Zoomed)
–0.15
70
60
50
40
30
20
10
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–0.50
–0.55
–0.60
–0.65
–0.70
0
100k
0
100 200 300 400 500 600 700 800 900 1000
1M
10M
INPUT CURRENT (µA)
SUPPLY-NOISE FREQUENCY
Figure 14. PD_CATHODE Compliance Voltage vs.
Input Current RSSI (Refer to VCC)
Figure 11. PSRR vs. Supply-Noise Frequency
Rev. A | Page 8 of 16
Data Sheet
ADN2892
900
800
700
600
500
400
300
200
100
0
49.0
48.5
48.0
47.5
47.0
46.5
46.0
100
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. ADN2892 ICC Current vs. Temperature
Figure 15. RSSI Offset—Difference Between Measured RSSI Output and
PD_CATHODE (Input) Current of 5 µA
5.0
4.5
4.0
3.5
3.0
2.5
+100°C
2.0
1.5
1.0
0.5
0
+30°C
–40°C
0
200
400
600
800
1000
PD_CATHODE CURRENT (µA)
Figure 16. RSSI Linearity % vs. PD_CATHODE Current
Rev. A | Page 9 of 16
ADN2892
Data Sheet
THEORY OF OPERATION
LIMITING AMPLIFIER
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
Input Buffer
The ADN2892 has an on-chip, RSSI circuit. By monitoring the
current supplied to the photodiode, the RSSI circuit provides an
accurate, average power measurement. The output of the RSSI is
a current that is directly proportional to the average amount of
PIN photodiode current. Placing a resistor between the
RSSI_OUT pin and GND converts the current to a GND
referenced voltage. This function eliminates the need for
external RSSI circuitry for SFF-8472-compliant optical
receivers. For more information, see Figure 12 to Figure 16.
The ADN2892 limiting amplifier provides differential
inputs (PIN/NIN), each with a single-ended, on-chip 50 Ω
termination. The amplifier can accept either dc-coupled or
ac-coupled signals; however, an ac-coupled signal is
recommended. Using a dc-coupled signal, the amplifier
needs a nominal VCC − 0.7 V common-mode voltage and
0.5 V headroom. If the input common-mode voltage is 2.4 V,
the available headroom is reduced down to 0.3 V.
Connect the PD_VCC, PD_CATHODE, and RSSI_OUT pins to
AVCC to disable the RSSI feature.
The ADN2892 limiting amplifier is a high gain device. It is
susceptible to dc offsets in the signal path. The pulse width
distortion presented in the NRZ data or a distortion generated
by the TIA may appear as dc offset or a corrupted signal to the
ADN2892 inputs. An internal offset correction loop can
compensate for certain levels of offset.
SQUELCH MODE
Driving the SQUELCH input to logic high disables the limiting
amplifier outputs. Using LOS output to drive the SQUELCH
input, the limiting amplifier outputs stop toggling anytime a
signal input level to the limiting amplifier drops below the
programmed LOS threshold.
CML Output Buffer
The ADN2892 provides differential CML outputs, OUTP and
OUTN. Each output has an internal 50 Ω termination to VCC.
The SQUELCH pin has a 100 kΩ, internal pull-down resistor.
LOSS-OF-SIGNAL (LOS) DETECTOR
BW_SEL (BANDWIDTH SELECTION) MODE
The on-chip LOS circuit drives LOS to logic high when the
input signal level falls below a user-programmable threshold.
The threshold level can be set anywhere from 3.5 mV pp to 35
mV pp typical by a resistor connected between the THRADJ
pin and VEE. See Figure 6 and Figure 7 for the LOS threshold
vs. THRADJ. The ADN2892 LOS circuit has an electrical
hysteresis greater than 2.5 dB to prevent chatter at the LOS
signal. The LOS output is an open-collector output that must be
pulled up externally with a 4.7 kΩ to 10 kΩ resistor.
Driving the BW_SEL input signal to logic high, the amplifier
provides a 3.8 GHz bandwidth. Driving the BW_SEL input
signal to logic low, the amplifier accepts input signals through a
1.5 GHz, 2-pole, low-pass filter that improves receiving
sensitivity.
The low-pass filter reduces the possible relaxation oscillation of
low speed, low cost laser source by limiting the input signal
bandwidth.
The BW_SEL pin has a 100 kΩ, on-chip pull-up resistor. Setting
the BW_SEL pin open disables the low-pass filter.
LOS_INV (LOSE OF SIGNAL_INVERT) MODE
Some applications, such as SFF, need the LOS assertion and
deassertion voltage reversed. When the LOS_INV pin is pulled
to logic high, the LOS output assertion is pulled down to
electrical low.
The LOS_INV pin has a 100 kΩ on-chip, pull-down resistor.
Rev. A | Page 10 of 16
Data Sheet
ADN2892
APPLICATIONS
The exposed pad should connect to the GND plane using filled
vias so that solder does not leak through the vias during reflow.
Using filled vias in parallel under the package greatly reduces
the thermal resistance and enhances the reliability of the
connectivity of the exposed pad to the GND plane during
reflow.
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used to ensure
optimal performance.
Output Buffer Power Supply and Ground Planes
Pin 9 (DRVEE) and Pin 12 (DRVCC) are the power supply and
ground pins that provide current to the differential output
buffer. To reduce possible series inductance, Pin 9, which is the
ground return of the output buffer, should connect to ground
directly. If the ground plane is an internal plane and
To reduce power supply noise, a 10 μF electrolytic decoupling
capacitor between power and ground should be close to where
the 3.3 V supply enters the PCB. The other 0.1 μF and 1 nF
ceramic chip decoupling capacitors should be close to the VCC
and VEE pins to provide optimal supply decoupling and a
shorter current return loop.
connections to the ground plane are vias, multiple vias in
parallel to ground can reduce series inductance.
Similarly, to reduce the possible series inductance, Pin 12,
which supplies power to the high speed differential
OUTP/OUTN output buffer, should connect to the power plane
directly. If the power plane is an internal plane and connections
to the power plane are vias, multiple vias in parallel can reduce
the series inductance, especially on Pin 12. See Figure 18 for the
recommended connections.
VCC
C9
VCC
RSSI MEASUREMENT
TO ADC
R1
C10
0.1F
VCC
VCC
C8
C5
C6
16
15
14
13
C7
AVCC
PIN
DRVCC
1
2
3
4
12
11
10
9
ADN2892
C1
C2
OUTP C3
OUTN C4
DRVEE
CONNECT
EXPOSED
PAD TO
GND
TO HOST
BOARD
NIN
ADN2882
AVEE
5
6
7
8
C1–C4, C11: 0.01F X5R/X7R DIELECTRIC, 0201 CASE
C5, C7, C9, C10, C12: 0.1F X5R/X7R DIELECTRIC, 0402 CASE
C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE
R3
4.7k TO 10k
ON HOST BOARD
C12
R2
VCC
TO ADuC7020
Figure 18. Typical ADN2892 Applications Circuit
Rev. A | Page 11 of 16
ADN2892
Data Sheet
PCB Layout
Soldering Guidelines for the LFCSP
Figure 19 shows the recommended PCB layout. The 50 Ω
transmission lines are the traces that bring the high frequency
input and output signals (PIN, NIN, OUTP, and OUTN) from a
terminated source to a terminated load with minimum
reflection. To avoid a signal skew between the differential
traces, each differential PIN/NIN and OUTP/OUTN pair
should have matched trace lengths from a differential source to
a differential load. C1, C2, C3, and C4 are ac coupling
capacitors in series with the high speed, signal input/output
paths. To minimize the possible mismatch, the ac coupling
capacitor pads should be the same width as the 50 Ω
transmission line trace width. To reduce supply noise, a 1 nF
decoupling capacitor should be placed as close as possible to the
VCC pins on the same layer and not through vias. A 0.1 μF
decoupling capacitor can be placed on the bottom of the PCB
directly underneath the 1 nF capacitor. All high speed, CML
outputs have internal 50 Ω resistor termination between the
output pin and VCC. The high speed inputs, PIN and NIN, also
have the internal 50 Ω termination to an internal reference
voltage.
The lands on the 16-lead LFCSP are rectangular. The PCB pad
for these should be 0.1 mm longer than the package land length
and 0.05 mm wider than the package land width. The land
should be centered on the pad. This ensures that the solder joint
size is maximized. The bottom of the LFCSP has a central
exposed pad. The pad on the printed circuit board should be at
least as large as the exposed pad. Users must connect the
exposed pad to VEE using filled vias so that solder does not
leak through the vias during reflow. This ensures a solid
connection from the exposed pad to VEE.
PAD COATING AND PB-FREE SOLDERING
Table 5.
Pad Coating
Matt-Tin
Pb-Free Reflow Portfolio
J-STD-20B
As with any high speed, mixed-signal design, keep all high
speed digital traces away from sensitive analog nodes.
R1, C9, C10 ON BOTTOM
DVCC GND
TO ROSA
DOUBLE-VIAS TO REDUCE
INDUCTANCE TO SUPPLY
AND GND
AVCC
GND
PLACE C7 ON
BOTTOM OF BOARD
UNDERNEATH C8
PLACE C5 ON
BOTTOM OF BOARD
UNDERNEATH C6
1
EXPOSED PAD
C6
C8
C1
C3
PIN
NIN
OUTP
FILLED VIAS TO
GND
4mm
OUTN
C2
C4
TRANSMISSION LINES SAME
WIDTH AS AC COUPLING
CAPS TO REDUCE REFLECTIONS
DOUBLE-VIA TO GND
TO REDUCE INDUCTANCE
VIA TO C12, R2
ON BOTTOM
VIAS TO BOTTOM
Figure 19. Recommended ADN2892 PCB Layout (Top View)
Rev. A | Page 12 of 16
Data Sheet
ADN2892
OUTLINE DIMENSIONS
0.50
0.40
0.30
0.60 MAX
3.00
BSC SQ
PIN 1
INDICATOR
BOTTOM VIEW
*
1.65
1.50 SQ
1.35
13
12
16
0.45
1
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
8
0.50
BSC
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 20. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
–40°C to +95°C
–40°C to +95°C
–40°C to +95°C
Package Description
Package Option
CP-16-3
CP-16-3
Branding
F05
F05
ADN2892ACPZ-500RL7
ADN2892ACPZ-RL7
ADN2892ACPZ-RL
EVAL-ADN2892EBZ
16-Lead LFCSP_VQ, 500 pieces
16-Lead LFCSP_VQ, 1,500 pieces
16-Lead LFCSP_VQ,5,000 pieces
Evaluation Board
CP-16-3
F05
1 Z = RoHS-Compliant Part.
Rev. A | Page 13 of 16
ADN2892
NOTES
Data Sheet
Rev. A | Page 14 of 16
Data Sheet
NOTES
ADN2892
Rev. A | Page 15 of 16
ADN2892
NOTES
Data Sheet
©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04986-0-7/13(A)
Rev. A | Page 16 of 16
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