ADN2901XXX [ADI]
IC TRANSCEIVER, PBGA186, FBGA-186, ATM/SONET/SDH IC;
| 型号： | ADN2901XXX |
| 厂家： | 
ADI |
| 描述： | IC TRANSCEIVER, PBGA186, FBGA-186, ATM/SONET/SDH IC ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总16页 (文件大小：1333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
a
OC-192/STM-64 SONET/SDH Tranceiver
Preliminary Technical Data
ADN2901
FEATURES
APPLICATIONS
9.953 Gb/s SONET/SDH OC-192 Transceiver
ITU-T, Telcordia, and OIF compliant
Single 3.3 V power supply
SONET/SDH Add/Drop Multiplexers (ADM)
SONET/SDH Digital Cross-Connects
SONET/SDH Optical/Transponder Modules
ATM over SONET/SDH
Ultra low power, 1.6 W
Less than 1 ps RMS transmit jitter
Less than 30 ps transmit data rise and fall times
On-chip receive and transmit PLLs
CML data and clock serial interface with on-chip 50 Ω
termination
WDM/DWDM Systems
Section Repeaters
Terabit and Edge Routers
SONET/SDH Test Equipment
Serial Backplane Interface
16-bit parallel LVDS transmit and receive interface
Internal diagnostic and line loopback modes
Receiver Lock Detect and CDR
Matched impedance 186-pin flip-chip BGA
No heatsink or airflow required
0° C to 85° C operating range
OVERVIEW
The single chip transceiver, ADN2901, is capable of per-
forming data serialization and deserialization over SONET/
SDH networks at 9.953 Gb/s. The device consists of two inde-
pendent phase-locked-loops (PLLs) within the receiver and
transmitter blocks for clock recovery and clock synthesis, as
well as system timing circuitry for data management and clock
distribution. The device also features a receiver lock detect and
internal line loopback and diagnostic loopback modes for de-
bugging and maintenance purposes.
SiGe process technology
The ADN2901 transceiver typically dissipates 1.6 W of
power from a single 3.3 V supply. The clock and data through
the CML transmitter serial outputs and LVDS receiver parallel
outputs guarantee compliance to the jitter specifications , and
the bit error rate requirements per Telcordia and ITU-T stan-
dards. The ADN2901 is packaged in a 186 flip-chip BGA with
matched impedance plastic substrate.
16
ADN2894
LIMAMP
ADN2843
LDD
ADN2820
TIA
16
ADN2901
9.953 Gb/s
OC-192/STM64
ADN2901
9.953 Gb/s
OC-192/STM64
Transceiver
FRAMER
FRAMER
Transceiver
16
ADN2894
LIMAMP
16
ADN2820
TIA
ADN2843
LDD
Figure 1. System Block Diagram
REV. PrA
02/15/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
ADN2901
TRANSM ITTER
TxSYNC_RST
TxIN_P/N
16
16:1
Parallel-to-Serial
MUX
2:1
MUX
Phase
Alignment
TxOUT_P/N
LLB
TxCKOUT_P/N
1-to-16
Clock
Div ider
2:1
MUX
TxCKIN_P/N
TxCLK_SRC_P/N
Transmit PLL
2:1
MUX
and
Clock Multiplier
REFCLK
RECEIVER
1:16
Serial-to-Parallel
DEMUX
Output
Register
16
2:1
MUX
RxOUT_P/N
1-to-16
Clock
Div ider
DLB
2:1
MUX
RxCLK_P/N
Clock and Data
Recov ery PLL
RxIN_P/N
Decision
Block
RxDATVLD
BYPASS_AA
Acquisition-Aid
Rx_LOCKDET
Figure 2. ADN2901 Block Diagram
–2–
REV. PrA
PRELIMINARY TECHNICAL DATA
RECEIVER SPECIFICATIONS
ADN2901
PARAMETER
Conditions
Min
Typ
Max
Units
Receive Data Inputs
(RxIN_P, RxIN_N)
Data Frequency
9.953
Gb/s
mV
mV
GHz
dB
Ω
pF
Input Peak to Peak Differential1
RxIN_P - RxIN_N, AC Coupled
RxIN_P - RxIN_N, BER < 1e-10
50
1000
Input Sensitivity
Upper -3dB Bandwidth
S11
Input Resistance
Input Capacitance
50
TBD
TBD
50
@10GHz
Single-ended
TBD
Phase-Locked Loop Characteristics for all input data rates
Jitter Tolerance
2kHz
15
1.5
0.15
UIp-p
UIp-p
UIp-p
400kHz
4MHz
Receive Data Outputs
(RxOUT[15:0]_P, RxOUT[15:0]_N)
Data Frequency
622.08
Mb/s
mV
ps
Differential Voltage Swing1
Rise and Fall time
LVDS Differential
tr, tf
tCLK-Q (Figure 5)
400
600
300
200
110
RxCLK to RxOUT Output Delay
ps
Receive Clock Outputs
(RxCLK_P, RxCLK_N)
Clock Frequency
622.08
100
Mb/s
mV
%
Differential Voltage Swing1
Duty Cycle
LVDS Differential
tr, tf
400
45
600
55
150
Rise and Fall Time
ps
Notes:
1. See Figure 6
,
–3–
REV. PrA
PRELIMINARY TECHNICAL DATA
(TA = Tmin to Tmax, VDD = Vmin to Vmax, unless otherwise noted.)
ADN2901–SPECIFICATIONS
TRANSMITTER SPECIFICATIONS
PARAMETER
Conditions
Min
Typ
Max
Units
Transmit Data Inputs
(TxIN[15:0]_P, TxIN[15:0]_N)
Data Frequency
622.08
100
Mb/s
mV
Ω
Input Voltage Range1
Input Resistance
Timing
LVDS, Differential
Differential
400
600
Setup Time
Hold Time
ts-TxIN (See Figure 3)
ts-TxIN (See Figure 3)
200
200
ps
ps
Transmit Clock Inputs
(TxCKIN_P/N)
Clock Frequency
Input Voltage Range1
Input Resistance
Duty Cycle
622.08
100
Mb/s
mV
Ω
LVDS, Differential
Differential
400
45
600
55
%
Transmit Data Outputs
(TxOUT_P/N)
Data Frequency
Output Voltage Swing1
S22
9.953
TBD
30
Gb/s
mV
dB
Differential
tr, tf
1300
2000
Timing
Rise and Fall Time
ps
Transmit Clock Outputs
(TxCKOUT_P/N)
Data Frequency
9.953
GHz
mV
Output Voltage Swing1
Timing
Differential
660
45
1300
55
Duty Cycle
%
ps
ps
Rise and Fall Time
TxCKOUT to TxOUT Output Delay
Jitter
tr, tf
20
20
tTxCK-TxOUT (See Figure 4)
Jitter Transfer Bandwidth
Jitter Peaking
Jitter Generation
TBD
TBD
.03
kHz
dB
UIp-p
.005
UI rms
Transmit Clock/16 Outputs
(TxCLK_SRC_P, TxCLK_SRC_N)
Clock Frequency
622.08
400
190
Mb/s
mV
ps
Output Voltage Swing1
LVDS, differential
Rise and Fall Time
–4–
REV. PrA
PRELIMINARY TECHNICAL DATA
ADN2901
TxCKIN_P
tS-TxIN
tH-TxIN
TxIN_P
TxIN_N
Figure 3. Transmitter Input Timing
TxCKOUT_P
TxOUT_P/N
t
TxCK - T xOU T
Figure 4. Transmitter Output Timing
RxCLK_P
t CLK-Q
RxOUT_P/N
Figure 5. Receiver Output Timing
V(+)
V(-)
VSWING
V(+) - V (-)
VD = 2 X V
SWING
Figure 6. Differential Voltage Swing
–5–
REV. PrA
PRELIMINARY TECHNICAL DATA
(TA = Tmin to Tmax, VDD = Vmin to Vmax, unless otherwise noted.)
ADN2901–SPECIFICATIONS
PARAMETER
Conditions
Min
Typ
Max
Units
Reference Clock Requirements
REFCLK Frequency
Frequency Tolerance
Symmetry
622.08
MHz
ppm
%
ps
ps rms
-100
40
100
60
Rise and Fall Time
REFCLK Jitter
20% - 80%
50kHz to 80 MHz
320
0.25
0.8
LVTTL I/O DC Characteristics
Input Low Voltage
VIL
VIH
IIL
IIH
VOH
V
V
uA
uA
V
Input High Voltage
Input Low Current
Input High Current
Output High Voltage
2.0
-500
50
2.4
Output Low Voltage
VOL
0.5
V
LVDS I/O DC Characteristics
Input Voltage Range
single-ended
0
400
VDD
600
V
Differential Input Voltage Range
Threshold Hysteresis
Differential Input Resistance
Differential Output Voltage Swing
mV
mV
Ω
20
100
85
400
115
600
mV
CML Input DC Characteristics
Input Voltage Range
50Ω to VDD
VDD-1.0
25
50
VDD
500
1000
V
mV
mV
Input Voltage Swing
Input Voltage Swing
Single-ended
Differential
CML Output DC Characteristics
Output Low Voltage
50Ω to VDD
VOL-DAT, Data Outputs
VDD-1.1
VDD-0.1
1.3
VDD-0.9
VDD-0.3
660
VDD-0.75
VDD-0.06
2.0
VDD-0.63
VDD-0.15
1300
V
V
V
V
V
mV
Output High Voltage
Output Voltage Swing
Output Low Voltage
Output High Voltage
Output Voltage Swing
V
OH-DAT, Data Outputs
Differential Data Outputs
VOL-CLK, Clock Outputs
V
OH-CLK, Clock Outputs
Differential Clock Outputs
Recommended Operating Conditions
Ambient temperature Under Bias
Voltage on VDD w.r.t. GND
Voltage on LVTTL Inputs
Voltage on LVDS Inputs
IDD
0
85
deg C
V
V
V
mA
3.135
0
VDD-2
3.3
3.465
VDD
VDD
480
–6–
REV. PrA
PRELIMINARY TECHNICAL DATA
ADN2901
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
With
Respect
To
Temperature
Range
Package Package
Option Description
Model
Parameters
Min
Max
Units
ADN2901XXX
0 to +85
186 flip-chip BGA
VDD
VSS
VSS
VSS
VSS
-0.5
0
0
3.6
VDD
VDD+0.5
V
V
V
V
deg C
LVDS Inputs
LVTTL Inputs
LVTTL Outputs
Storage Temp
-0.5 VDD+0.5
-65 150
Package Information
Package Description
The ADN2901 comes in a multilayer BT substrate 186 BGA
with matched impedance on all high-speed differential I/Os.
The high-speed pins have been shielded to minimize crosstalk
and inter-symbol interference (ISI).The flip-chip packaging
technology is used to eliminate bond wire inductance and to
minimize pin-to-pin impedance variations.The backside of the
die is connected to a metal plate which is grounded and
provides backside biasing to the die. This plate also acts as a
heatsink.
Thermal Management
Due to the low power dissipation of the ADN2901, no special
thermal management is required.With a package ΘJA of less
than 24° C/W and a power dissipation of 1.6 W, no
heatsinking or airflow is required for this device to be used in
either commercial or industrial applications.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADN2901 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to over 50V of ESD. Therefore, proper ESD precautions are recommended to
avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. PrA
–7–
PRELIMINARY TECHNICAL DATA
ADN2901
VDD VDD
VDD
50 Ω
50 Ω
50 Ω
ZO = 50 Ω
CML
100Ω
ZI = 50 Ω
LVDS
50 Ω
VDD
Figure 9. CML Output Termination
Figure 7. LVDS Input Termination
9.953 Gb/s
Input
ZI = 50 Ω
RxIN_P
RxIN_N
50 Ω
ZO = 50 Ω
100 Ω
LVDS
CML
VDD
VTERM
50 Ω
ZI = 50 Ω
Figure 10. CML Differential Input Configuration
Figure 8. LVDS Output Termination
ZI = 50 Ω
9.953 Gb/s
Input
RxIN_P
50 Ω
50 Ω
CML
VTERM
RxIN_N
Figure 11. CML Single-Ended Input Configuration
–8–
REV. PrA
PRELIMINARY TECHNICAL DATA
ADN2901
Jitter Specifications
Jitter Tolerance
The ADN2901 transceiver is designed to achieve the best bit-
error-rate (BER) performance and has exceeded the jitter trans-
fer, generation, and tolerance specifications proposed for
SONET/SDH equipment defined in the Telcordia Technolo-
gies specification.
The jitter tolerance is defined as the peak-to-peak amplitude
of the sinusoidal jitter applied on the input signal that causes a
1 dB power penalty.This is a stress test intended to ensure no
additional penalty is incurred under the operating conditions.
(See Figure-13).
The following section briefly summarizes the specifications of
the jitter transfer, tolerance, and generation in accordance
with the Telcordia document (GR-253-CORE, Issue 3,
September 2000) for the optical interface at the equipment
level. The details of the jitter measurement technique and
results at the component level for the ADN2901 will be
described in the application notes.
15
Slope = -20 dB/decade
1.5
Jitter Generation
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For OC-192 devices, the bandpass filter
has a 50 kHz high-pass cutoff frequency with a roll-off of 20
dB/decade, and a low-pass cutoff frequency of at least 80
MHz.The jitter generated shall be less than 0.01 UI RMS, and
shall also be less than 0.1 UI pp.
0.15
20 K 400 K
Jitter Frequency (Hz )
4 M
10
2 K
Figure 13. Jitter Tolerance Curve, OC-192
Jitter Transfer
The jitter transfer function is the ratio of the jitter on the
output signal to the jitter applied on the input signal versus the
frequency.This parameter measures the limited amount of the
jitter on an input signal that can be transferred to the output
signal (See Figure-12).
0
Slope = -20 dB/decade
Acceptable
Range
8
Jitter Frequency (kHz)
Figure 12. Jitter Transfer Curve, OC-192
REV. PrA
–9–
PRELIMINARY TECHNICAL DATA
ADN2901
FUNCTIONAL DESCRIPTION
Lock Detect Circuitry
The single chip transceiver, ADN2901, is capable of perform-
ing data serialization and deserialization over SONET/SDH
transmitting at 9.953 Gb/s. A functional block diagram of the
ADN2901 is shown in Figure-2.
In the receiver block, the lock detect circuitry monitors the
serial data integrity. If the recovered clock is less than 500 ppm
from the REFCLK, the data inputs are not stuck at high or
low, and RxDATVLD is at high, then a lock condition is de-
tected which results in a high on the Rx_LOCKDET signal. If
any of the above conditions are not met, then the CDR will
lock to REFCLK. The Rx_LOCKDET signal will remain low
until the data clock is re-acquired. In case of signal loss or if an
invalid data condition is detected, the RxDATVLD input must
be forced low by an external source.
The receiver accepts 9.953 Gb/s scrambled NRZ serial data on
a CML interface and deserializes it to 16-bit parallel data. The
parallel data and clock (RxOUT_P/N and RxCLK_P/N) are
provided through an LVDS interface. The receiver block con-
sists of a clock/data recovery (CDR) PLL for recovering the
clock from the serial input data, a clock divider for the parallel
data clocking, a 1:16 serial-to-parallel DEMUX for data con-
version, a lock detect, and LVDS output buffers.
Serial-to-Parallel Converter
The 1:16 serial-to-parallel DEMUX receives the serial input
data at 9.953Gb/s and demultiplexes it into a 16-bit parallel
data outputs. The output is then aligned with the recovered
clock from the CDR circuitry. The data is then latched into the
output buffer by a 622.08MHz clock which is generated from
the 1/16 clock divider.The 16 bit parallel data (RxOUT_P/N) is
then latched out in synchronization with the rising edge of
RxCLK_P.
Input to the transmitter is a 16-bit parallel word through LVDS
interface at 622.08Mb/s, which is latched into a FIFO and
serialized into a single data stream (TxOUT_P/N). Also, a
9.953GHz clock output (TxCKOUT_P/N) is provided to
retime the output data. The transmitter block consists of a 16:1
parallel-to-serial MUX for data conversion, a clock synthesizer
PLL for generating the serial output clock frequency and main-
taining the stability of the synthesized clock, a timing generator
to provide the 1/16 clock rate of the serial clock, and differential
CML output buffers. The data and clock through the differen-
tial CML interfaces are designed with on-chip 50 Ω reverse
termination for matching impedance. The serial differential
outputs can be either AC or DC coupled and can also be used
as single-ended by terminating the unused output with a 50 Ω
to VDD.
Acquisition-Aid
The acquisition-aid block speeds up the acquisition time of the
phase detector in the receiver PLL by estimating the difference
in frequency between the 622.08MHz reference clock
(REFCLK) and an internal parallel clock, which is derived from
dividing the PLL clock by 16. If this difference is less than 500
ppm, and valid serial data is present at the input, then the PLL
switches from the synthesizer loop to the data phase tracking
loop.
The device also features internal Line Loop Back (receiver-to-
transmitter loop), and Diagnostic Loopback
(transmitter-to-receiver loop) for debugging and maintenance
purposes.
Diagnostic Loopback (DLB)
The DLB circuitry loops the transmitter parallel input data and
clock to the receiver output data and clock path. In normal
operation in which the DLB signal is low, the 16-bit parallel
output data and clock from the output register pass through the
receiver MUX and appear at RxOUT_P/N and RxCLK_P/N
respectively. When the DLB is high, the 16-bit parallel data
and clock (TxIN_P/N and TxCKIN_P/N) from the transmitter
block pass through the same MUX (Figure 2). Note that the
clock latches the data on the rising edge, and the transmitter-
to-receiver loop is at the parallel data rate.
RECEIVER BLOCK
High Speed Serial Data Input Interface
The received serial data (RxIN) can be provided as a differen-
tial or as a single-ended input (see Figures 10 and 11). Supplied
differentially, the inputs can be AC or DC coupled. If supplied
as a single-ended input, an external bias must be provided on
the VTERM pin and RxIN_P must be AC coupled in order to
eliminate any bias incompatibility between VTERM and the
RxIN_P input.
Clock and Data Recovery (CDR) PLL
The CDR block recovers the clock from the serial data input
and provides proper timing for the clock and data outputs. This
block contains a synthesizer tracking loop and a data phase
tracking loop. A synthesizer tracking loop locks the divided
down clock derived from the VCO frequency to a local refer-
ence clock running at 622.08MHz. Once it is determined that
the VCO frequency is locked to the reference clock and valid
serial data is present at the input, then the synthesizer loop is
switched off, and the data phase tracking loop is turned on. The
data phase tracking loop is designed in a manner such that,
once locked, the sampling edge of the VCO clock is automati-
cally aligned with the center of the input.
–10–
REV. PrA
PRELIMINARY TECHNICAL DATA
ADN2901
TRANSMITTER BLOCK
Manual Tx VCO Control and Automatic Search
The wide range of the transmitter PLL is divided into smaller
coarse tuning ranges. In the default mode, a low signal at the
TxVCO_MCTRL sets the Transmit PLL to automatic range
select, which is triggered by a single pulse at the TxVCO_RST
pin. Starting with the lowest frequency range, the Transmit
PLL searches for the proper range for the PLL to generate a
transmitting clock of 9.953 GHz.
Clock Synthesizer PLL
In transmitting operation, the 16-bit parallel data and clock are
serialized to generate a single data stream at 9.953Gb/s. The
transmitter PLL synthesizes a 9.953GHz clock from a reference
clock of 622.08MHz. It utilizes a phase frequency comparator
and a charge pump type of loop filter which guarantees a phase
lock under all operating conditions. This clock is then divided
by 16 and realigned by the timing generator to provide a system
clock for the parallel data.
The manual mode is setting TxVCO_MCTRL high and then
pulsing TxVCO_RST once. Subsequent pulsing of the
TxVCO_MCTRL increases the VCO frequency. This proce-
dure is continued until the desired frequency range is achieved.
The VCO frequency is incremented on a positive edge of each
pulse. This mode can be systematically controlled by a micro-
processor, if it is available.
Note that the crystal oscillator or other source providing the
REFCLK input to the PLL and clock multiplier must meet the
specifications listed in the spec table on page 6. This will pro-
vide the accuracy necessary for the transmitting serial clock and
data to meet SONET/SDH system requirements. For less de-
manding applications than SONET/SDH, lower accuracy clock
sources may be used.
A reset pulse, TxSYNC_RST, is used for phase alignment
between the 1/16 divided clock and the incoming parallel clock
if needed. The frequency of these clocks should be the same.
Parallel-to-Serial MUX
The parallel-to-serial converter has been optimized for maxi-
mum frequency with minimum power consumption by using a
tree structure. The input parallel data, TxIN_P/N, are latched
on the rising edge of the clock, TxCKIN_P/N.
1/16 Clock Divider
The transmitter also provides a TxCLK_SRC_P/N signal for a
downstream chip to be synchronized with the ADN2901 trans-
ceiver. The TxCLK_SRC_P/N signal is a divide-by-16 of the
transmitting serial clock TxCKOUT_P/N. This clock will en-
sure a stable frequency and phase relationship between the data
coming into and leaving the transmission system.
Line Loopback (LLB)
The LLB circuitry loops the receiver parallel output data and
clock (RxOUT_P/N and RxCLK_P/N) into the transmitter
input data and clock path. The LLB circuitry selects the source
of the data and clock which are then output on the TxOUT_P/
N and TxCKOUT_P/N pins. During normal operation, the
LLB signal is set low, and the 16-bit parallel transmit data and
clock (TxIN_P/N and TxCKIN_P/N) pass through the trans-
mitter 2:1 MUX. When LLB is high, the 16-bit parallel data
and clock from the receiver path, RxOUT_P/N and RxCLK_P/
N pass through the same MUX. Note that the clock latches
the data on the rising edge, and the receiver-to-transmitter loop
is at the parallel data rate.
REV. PrA
–11–
PRELIMINARY TECHNICAL DATA
ADN2901
VDD = 3.3 V
VSS = 0 V
VDD
VDD
50 Ω
VDD
TxCKIN_P
ZI = 50 Ω
50 Ω
50 Ω
100 Ω
TxCKIN_N
TxCKOUT_P
VDD
50 Ω
ZO = 50 Ω
TxIN[15:0]_P
ZI = 50 Ω
100 Ω
TxCKOUT_N
TxIN[15:0]_N
VDD
VDD
VDD
VDD
50 Ω
50 Ω
50 Ω
0.01 µf
TxOUT_P
10K Ω
VDD
50 Ω
REFCLK
ZO = 50 Ω
10K Ω
VSS
TxOUT_N
VDD
ADN2901
R
Rx_LOCKDET
RxCLK_P
ZI = 50 Ω
ZI = 50 Ω
RxIN_P
RxIN_N
VTERM
100 Ω
50 Ω
ZO = 50 Ω
100 Ω
100 Ω
RxCLK_N
50 Ω
Termination
Voltage
RxOUT[15:0]_P
RxOUT[15:0]_N
ZO = 50 Ω
Figure 14. Typical ADN2901 I/O Interface
–12–
REV. PrA
PRELIMINARY TECHNICAL DATA
ADN2901
Transmitter I/O Pins
Pin #
Mnemonic
Type
Description
L1
L2
L3
L4
M1
M2
M3
M4
N1
N2
N3
N4
P1
TxIN0_P
TxIN0_N
TxIN1_P
TxIN1_N
TxIN2_P
TxIN2_N
TxIN3_P
TxIN3_N
TxIN4_P
TxIN4_N
TxIN5_P
TxIN5_N
TxIN6_P
TxIN6_N
TxIN7_P
TxIN7_N
TxIN8_P
TxIN8_N
TxIN9_P
TxIN9_N
TxIN10_P
TxIN10_N
TxIN11_P
TxIN11_N
TxIN12_P
TxIN12_N
TxIN13_P
TxIN13_N
TxIN14_P
TxIN14_N
TxIN15_P
TxIN15_N
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
LVDS input
Parallel data input at 622.08Mb/s. TxIN0 is the LSB.
Parallel data input at 622.08Mb/s. TxIN0 is the LSB.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s.
Parallel data input at 622.08Mb/s. TxIN15 is the MSB.
Parallel data input at 622.08Mb/s. TxIN15 is the MSB.
P2
P3
P4
R1
R2
R3
R4
T1
T2
T3
T4
R5
T5
R6
T6
R7
T7
R8
T8
K3
K4
TxCKIN_P
TxCKIN_N
LVDS input
LVDS input
Parallel transmit data input clock at 622.08MHz.
Parallel transmit data input clock at 622.08MHz.
H1
J1
TxOUT_P
TxOUT_N
CML Output
CML Output
Differential transmit 9.953Gb/s serial data output stream.
Differential transmit 9.953Gb/s serial data output stream.
D1
E1
B1
A1
TxCKOUT_P
TxCKOUT_N
TxCLK_SRC_P
TxCLK_SRC_N
CML Output
CML Output
LVDS Output
LVDS Output
Differential transmit 9.953GHz serial output clock.
Differential transmit 9.953GHz serial output clock.
622.08MHz Transmit PLL Output Clock/16.
622.08MHz Transmit PLL Output Clock/16.
A4
A2
LLB
TxSYNC_RST
LVTTL input
LVTTL input
Line Loopback Enable. Active High.
Reset input to synchronize the external parallel transmit data to the internal
clock in the transmitter. Active High.
A3
B5
TxVCO_RST
TxVCO_MCTRL LVTTL input
LVTTL input
Reset pulse to start automatic range select for transmitter VCO. Active High.
Control for manual range select of transmitter VCO.
–13–
REV. PrA
PRELIMINARY TECHNICAL DATA
ADN2901
Receiver I/O Pins
Pin #
Mnemonic
Type
Description
T10
R10
P10
N10
T11
R11
P11
N11
T12
R12
P12
N12
T13
R13
N13
P13
R14
T14
N14
P14
R15
T15
N15
P15
R16
T16
N16
P16
M16
M15
L16
L15
RxOUT0_P
RxOUT0_N
RxOUT1_P
RxOUT1_N
RxOUT2_P
RxOUT2_N
RxOUT3_P
RxOUT3_N
RxOUT4_P
RxOUT4_N
RxOUT5_P
RxOUT5_N
RxOUT6_P
RxOUT6_N
RxOUT7_P
RxOUT7_N
RxOUT8_P
RxOUT8_N
RxOUT9_P
RxOUT9_N
RxOUT10_P
RxOUT10_N
RxOUT11_P
RxOUT11_N
RxOUT12_P
RxOUT12_N
RxOUT13_P
RxOUT13_N
RxOUT14_P
RxOUT14_N
RxOUT15_P
RxOUT15_N
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
Parallel data output at 622.08Mb/s. RxOUT0 is the LSB.
Parallel data output at 622.08Mb/s. RxOUT0 is the LSB.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s.
Parallel data output at 622.08Mb/s. RxOUT15 is the MSB.
Parallel data output at 622.08Mb/s. RxOUT15 is the MSB.
T9
R9
RxCLK_P
RxCLK_N
LVDS output
LVDS output
Parallel receivedata output clock at 622.08MHz. Recovered clock/16.
Parallel receive data output clock at 622.08MHz. Recovered clock/16.
D16
E16
RxIN_P1
CML Input
CML input
Serial input data stream at 9.953Gb/s.
Serial input data stream at 9.953Gb/s.
RxIN_N1
A13
B11
B16
A12
C11
Rx_LOCKDET
RxDATVLD
DLB
RxRST
BYPASS_AA
Open Collector Active Low after the PLL is locked to the REFCLK signal.
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
Indicates Active High when valid serial data from the optics module.
Diagnostic Loopback Mode. Active High.
Resets the receiver outputs to a logic low. Active High.
Disables Acquisition Aid block. Active High.
A16
Rx_IPDCTRL
Controls Receiver Phase Detector Bias Current.
C15, C16 VTERM
D15, E14
Analog Input
Input data termination voltage. See Figures 10 and 11.
F14, F16
G14, G15
G16
Common I/O Pins
A7
REFCLK
Analog Input
622.08MHz reference input clock to the transmitter and receiver PLLs.
Internally AC coupled.
B12
I_CTRL
Control for Bandgap current, controls chip bias current.
Notes:
1. The serial data inputs can be used differentially or single-ended with the following configurations:
a) Single-ended Input Signal: RxIN_P AC coupled per Figure 11, RxIN_N AC coupled to GND. Set VTERM to VDD-0.6.
b) Differential Input Signal:
RxIN_P/N AC coupled per Figure 10. Tie VTERM to VDD.
–14–
REV. PrA
PRELIMINARY TECHNICAL DATA
ADN2901
Ground and Power Pins
Pin #
Mnemonic
Type
Description
D12
F13
J13
D13
H13
N8
C3
D5
E4
A5
VSUB_1
VSUB_2
VSUB_3
VSUB_4
VSUB_5
VSUB_6
VSUB_7
VSUB_8
VSUB_9
VSUB_10
VSUB_11
VSUB_12
VSUB_13
VSUB for Rx VCO
VSUB for Rx Phase Detector
VSUB for Rx Digital: DeMUX and Acquisition Aid
VSUB for ESD I/O ring
VSUB for ESD I/O ring
VSUB for ESD I/O ring
VSUB for ESD I/O ring
VSUB for Tx VCO
VSUB for Tx CLK (Tx VCO Buffer)
VSUB for Tx output buffer and driver
VSUB for frequency synthesizer
VSUB for Tx Phase Align and MUX
VSUB for Bandgap reference
VSUB for die backplate
D6
D8
B6
A8, A11, B2, H16 VSUB_14
G1, G2, H3
K1, K2
G4
C4
D7
VDD_TX_OPBF
Power
Power for Tx serial data output
VDD_TX_OPDR Power
VDD_TX_PCKBD Power
VDD_TX_SYNTH Power
Power for 10G MUX and TxOUT buffer driver
Power for TxCLK_SRC output buffer
Power for Tx Frequency Synthesizer
D9
VDD_TX_DIG
Power
Power for Tx VCO Digital core tuning, MUX (w/o 10G MUX),
Phase Align, Tx input buffers.
C6
VDD_TX_VCO
VDD_TX_VCBF
Power
Power
Power for Tx VCO
Power for Tx VCO clock output buffer
C1, C2, D3, E3
F1, F2, F3
L14
H14, J14
C10, D14
C12
VDD_RX_DAA
VDD_RX_LVDBF Power
VDD_RX_PD
VDD_RX_VCO
VDD_BG
Power
Power for Rx 1:16 DEMUX and Acquisition Aid
Power for Rx LVDS output buffers
Power for Rx phase detector
Power for Rx VCO
Power for bandgap reference
Power
Power
Power
B7
H4
G3
D4
C7
C8
VSS_TX_OPBF
VSS_TX_OPDR
VSS_TX_PCKBD GND
VSS_TX_SYNTH GND
GND
GND
GND for Tx serial data output
GND for 10G MUX and TxOUT buffer driver
GND for TxCLK_SRC output buffer
GND for Tx Frequency Synthesizer
GND for Tx VCO Digital core tuning, MUX (w/o 10G MUX),
Phase Align, Tx input buffers.
VSS_TX_DIG
GND
C5
F4
K14
H15, J15
D10, E13
C13
VSS_TX_VCO
VSS_TX_VCBF
VSS_RX_DAA
GND
GND
GND
GND for Tx VCO
GND for Tx VCO clock output buffer
GND for Rx 1:16 DEMUX and Acquisition Aid
GND for Rx LVDS output buffers
GND for Rx phase detector
GND for Rx VCO
GND for bandgap reference
VSS_RX_LVDBF GND
VSS_RX_PD
VSS_RX_VCO
VSS_BG
GND
GND
GND
B8
–15–
REV. PrA
PRELIMINARY TECHNICAL DATA
ADN2901
Figure 15. 186 Flip-Chip BGA Package Dimensions
–16–
REV. PrA
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