ADP2387ACPZN-R7 [ADI]
20 V, 6 A, Synchronous, Step-Down DC-to-DC Regulator;
| 型号： | ADP2387ACPZN-R7 |
| 厂家： | 
ADI |
| 描述： | 20 V, 6 A, Synchronous, Step-Down DC-to-DC Regulator 开关 |
| 文件： | 总26页 (文件大小：607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
20 V, 6 A, Synchronous, Step-Down
DC-to-DC Regulator
Data Sheet
ADP2387
FEATURES
TYPICAL APPLICATIONS CIRCUIT
Input voltage range: 4.5 V to 20 V
Integrated MOSFET: 44 mΩ typical/11 mΩ typical
Reference voltage: 0.6 V 1%
ADP2387
BST
V
PVIN
EN
IN
C
BST
L
C
IN
SW
V
OUT
Continuous output current: 6 A
C
OUT
PGOOD
ILIM
RT
R
TOP
Programmable current-limit threshold
Programmable switching frequency: 200 kHz to 1400 kHz
Precision enable and power good
External compensation
Internal soft start with external adjustable option
Startup into a precharged output
FB
COMP
SS
R
ILIM
R
T
R
C
R
VREG
BOT
C
C
VREG
GND PGND
C
C
SS
Supported by ADIsimPower design tool
Figure 1.
APPLICATIONS
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point of load applications
GENERAL DESCRIPTION
The ADP2387 is a synchronous step-down, dc-to-dc regulator with
an integrated 44 mΩ, high-side power, metal oxide semiconductor
field effect transistor (MOSFET) and an 11 mΩ, synchronous
rectifier MOSFET to provide a high efficiency solution in a
compact 4 mm × 4 mm LFCSP. This device uses a peak current
mode, constant frequency pulse-width modulation (PWM)
control scheme for excellent stability and transient response.
The switching frequency of the ADP2387 can be programmed
between 200 kHz to 1400 kHz.
Other key features include undervoltage lockout (UVLO),
overvoltage protection (OVP), overcurrent protection (OCP),
short-circuit protection (SCP), and thermal shutdown (TSD).
The ADP2387 operates over the −40°C to +125°C junction
temperature range and is available in a 24-lead, 4 mm × 4 mm
LFCSP.
100
95
90
85
80
75
70
65
60
The ADP2387 requires minimal external components and operates
from an input voltage of 4.5 V to 20 V. The output voltage can
be adjusted from 0.6 V to 90% of the input voltage and delivers
up to 6 A of continuous current. Each IC draws less than 110 µA
current from the input source when it is disabled.
This regulator targets high performance applications that require
high efficiency and design flexibility. External compensation
and an adjustable soft start function provide design flexibility.
The power-good output and precision enable input provide
simple and reliable power sequencing. The programmable
current-limit function allows the inductor to be optimized by
output current.
V
V
V
= 5.0V
= 3.3V
= 1.2V
OUT
OUT
OUT
55
50
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current, VIN = 12 V, fSW = 300 kHz
Rev. C
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ADP2387* PRODUCT PAGE QUICK LINKS
Last Content Update: 04/25/2017
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DESIGN RESOURCES
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EVALUATION KITS
• ADP2387 Evaluation Board
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Data Sheet
DISCUSSIONS
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• ADP2387: 20 V, 6 A, Synchronous, Step-Down DC-to-DC
Regulator Data Sheet
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User Guides
• UG-786: Evaluation Board for the ADP2387 20 V, 6 A
Synchronous, Step-Down, DC-to-DC Regulator
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ADP2387
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 15
Input Capacitor Selection.......................................................... 15
Output Voltage Setting .............................................................. 15
Voltage Conversion Limitations............................................... 15
Inductor Selection...................................................................... 16
Output Capacitor Selection....................................................... 16
Programming Input Voltage UVLO ........................................ 17
Compensation Design ............................................................... 17
ADIsimPower Design Tool ....................................................... 18
Design Example.............................................................................. 19
Output Voltage Setting .............................................................. 19
Frequency Setting....................................................................... 19
Current-Limit Threshold Setting............................................. 19
Inductor Selection...................................................................... 19
Output Capacitor Selection....................................................... 20
Compensation Components..................................................... 20
Soft Start Time Program ........................................................... 20
Input Capacitor Selection.......................................................... 20
Recommended External Components .................................... 21
Circuit Board Layout Recommendations ................................... 22
Typical Applications Circuits........................................................ 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 12
Control Scheme .......................................................................... 12
Precision Enable/Shutdown ...................................................... 12
Internal Regulator (VREG)....................................................... 12
Bootstrap Circuitry .................................................................... 12
Oscillator ..................................................................................... 12
Soft Start ...................................................................................... 12
Power Good................................................................................. 13
Peak Current-Limit and Short-Circuit Protection................. 13
Overvoltage Protection (OVP)................................................. 13
Undervoltage Lockout (UVLO) ............................................... 14
Thermal Shutdown..................................................................... 14
REVISION HISTORY
4/2017—Rev. B to Rev. C
Added Maximum Junction Temperature Parameter, Table 2 ....... 6
1/2016—Revision B: Initial Version
Rev. C | Page 2 of 25
Data Sheet
ADP2387
FUNCTIONAL BLOCK DIAGRAM
VREG
CLK
BIAS AND DRIVER
REGULATOR
PVIN
OSC
RT
SLOPE RAMP
UVLO
EN
EN_BUF
BOOST
REGULATOR
1.17V
1µA
4µA
A
CS
OCP
THRESHOLD
SETTING
V
I_MAX
–
ILIM
HICCUP
MODE
OCP
+
BST
SW
SLOPE RAMP
NFET
NFET
Σ
DRIVER
COMP
0.6V
+
+
–
+
CMP
–
I
SS
CONTROL
LOGIC
SS
FB
AMP
AND MOSFET
DRIVER WITH
ANTICROSS
VREG
PROTECTION
DRIVER
OVP
0.7V
PGND
–
CLK
NEG CURRENT
CMP
+
–
+
–
V
I_NEG
0.54V
+
PGOOD
GND
DEGLITCH
ADP2387
Figure 3. Functional Block Diagram
Rev. C | Page 3 of 25
ADP2387
Data Sheet
SPECIFICATIONS
VPVIN = 12 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
PVIN
PVIN Voltage Range
Quiescent Current
Shutdown Current
PVIN Undervoltage Lockout Threshold
VPVIN
IQ
ISHDN
UVLO
4.5
2.4
50
20
V
No switching
EN = GND
PVIN rising
PVIN falling
2.9
80
4.3
3.8
3.6
110
4.4
mA
µA
V
3.6
V
FB
FB Regulation Voltage
VFB
0°C < TJ < 85°C
−10°C < TJ < +115°C
−40°C < TJ < +125°C
596.4
595.2
594
600
600
600
0.01
603.6
604.8
606
mV
mV
mV
µA
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
EA Sink Current
IFB
0.1
gm
ISOURCE
ISINK
380
40
40
480
60
60
580
80
80
µS
µA
µA
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
VVREG
VPVIN = 12 V, IVREG = 50 mA
VPVIN = 12 V, IVREG = 50 mA
7.6
62
8
350
100
8.4
V
mV
mA
Current-Limit Regulator
138
SW
High-Side On Resistance1
Low-Side On Resistance1
SW Minimum On Time
SW Minimum Off Time
BST
RDSON_HS
RDSON_LS
tMIN_ON
VBST − VSW = 5 V
VVREG = 8 V
44
11
130
200
70
18
165
260
mΩ
mΩ
ns
tMIN_OFF
ns
Bootstrap Voltage
OSCILLATOR (RT PIN)
Switching Frequency
Switching Frequency Range
CURRENT LIMIT
VBOOT
fSW
4.6
5
5.4
V
RT = 100 kΩ
540
200
600
660
1400
kHz
kHz
High-Side Peak
RILIM = 44.2 kΩ
RILIM = 66.5 kΩ
RILIM = 133 kΩ
7.7
5.1
2.3
9.2
6.1
2.9
2.5
0.6
10.7
7.1
3.5
A
A
A
A
V
µA
Low-Side Negative2
ILIM Voltage2
ILIM Current Range2
VILIM
IILIM
4
15
SS
Internal Soft Start
SS Pin Pull-Up Current
PGOOD
1600
3.1
Clock cycles
µA
ISS_UP
2.2
3.8
Power-Good Range
FB Rising Threshold
FB Rising Hysteresis
FB Falling Threshold
FB Falling Hysteresis
Power-Good Deglitch Time
PGOOD from low to high
PGOOD from high to low
PGOOD from low to high
PGOOD from high to low
PGOOD from low to high
PGOOD from high to low
VPGOOD = 5 V
95
5
%
%
%
%
105
11.7
1024
16
0.01
125
Clock cycles
Clock cycles
µA
Power-Good Leakage Current
Power-Good Output Low Voltage
0.1
190
IPGOOD = 1 mA
mV
Rev. C | Page 4 of 25
Data Sheet
ADP2387
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
EN
EN Rising Threshold
EN Falling Threshold
EN Source Current
1.17
1.07
5
1.25
V
V
µA
µA
0.97
EN voltage below falling threshold
EN voltage above rising threshold
1
THERMAL SHUTDOWN (TSD)
Threshold
Hysteresis
150
25
°C
°C
1 Pin-to-pin measurement.
2 Guaranteed by design.
Rev. C | Page 5 of 25
ADP2387
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Rating
JA is specified for the worst case conditions, that is, a device
soldered in the circuit board (4-layer, JEDEC standard board)
for surface mount packages.
PVIN, SW, EN, PGOOD
SW 10 ns Transient
SW 100 ns Transient
BST
FB, SS, COMP, ILIM, RT
VREG
−0.3 V to +22 V
−2.5 V to +22 V
−1 V to +22 V
VSW + 6 V
−0.3 V to +6 V
−0.3 V to +12 V
−0.3 V to +0.3 V
Table 3. Thermal Resistance
Package Type
JA
42.6
JC
Unit
°C/W
°C/W
24-Lead LFCSP
6.8 (EP, SW)
2.3 (EP, GND)
PGND to GND
Operating Junction Temperature Range −40°C to +125°C
ESD CAUTION
Maximum Junction Temperature
Storage Temperature Range
Soldering Conditions
150°C
−65°C to +150°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 6 of 25
Data Sheet
ADP2387
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMP 1
FB 2
18 PVIN
17 PVIN
16 PVIN
15 BST
14 SW
25
GND
VREG 3
GND 4
SW 5
26
SW
SW 6
13 PGND
ADP2387
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED GND PAD MUST BE SOLDERED
TO A LARGE, EXTERNAL, COPPER GND PLANE
TO REDUCE THERMAL RESISTANCE.
2. THE EXPOSED SW PAD MUST BE CONNECTED
TO THE SW PINS OF THE ADP2387 BY USING
SHORT, WIDE TRACES, OR ELSE SOLDERED
TO A LARGE, EXTERNAL, COPPER SW PLANE
TO REDUCE THERMAL RESISTANCE.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
COMP
FB
Description
Error Amplifier Output. Connect an RC network from COMP to GND.
Feedback Voltage Sense Input. Connect this pin to a resistor divider from the output voltage, VOUT
Output of the Internal 8 V Regulator. The control circuits are powered from this voltage. Place a 1 µF, X7R or
X5R ceramic capacitor between this pin and GND.
1
2
3
.
VREG
4
GND
SW
PGND
BST
Analog Ground. This pin is the return of the internal control circuit.
Switch Node Outputs. Connect these pins to the output inductor.
Power Ground. This pin is the return of the low-side power MOSFET.
Supply Rail for the High-Side Gate Drive. Place a 0.1 µF, X7R or X5R capacitor between SW and BST.
5 to 7, 14
8 to 13
15
16 to 19
PVIN
Power Inputs. Connect these pins to the input power source and connect a bypass capacitor between these
pins and PGND.
20
EN
Precision Enable Pin. An external resistor divider can set the turn on threshold. To enable the device
automatically, connect the EN pin to the PVIN pin.
21
22
PGOOD
RT
Power-Good Output (Open Drain). Connecting a pull-up resistor of 10 kΩ to 100 kΩ to this pin is recommended.
Frequency Setting. Connect a resistor between RT and GND to program the switching frequency between
200 kHz to 1400 kHz.
23
24
ILIM
SS
Current-Limit Threshold Setting. Connect a resistor between ILIM and GND to program the current-limit
threshold.
Soft Start Control. Connect a capacitor from SS to GND to program the soft start time. If this pin is open, the
regulator uses the internal soft start time.
25
26
E P, G N D
E P, S W
The exposed GND pad must be soldered to a large, external, copper GND plane to reduce thermal resistance.
The exposed SW pad must be connected to the SW pins of the ADP2387 by using short, wide traces, or else
soldered to a large, external copper SW plane to reduce thermal resistance.
Rev. C | Page 7 of 25
ADP2387
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25oC, VIN = 12 V, VOUT = 3.3 V, L = 2.2 µH, COUT = 100 µF + 47 µF, fSW = 600 kHz, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
INDUCTOR:
INDUCTOR:
FDVE1040-4R7
FDVE1040-
2R2
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5.0V
V
V
V
V
V
= 1.2V
OUT
OUT
OUT
OUT
OUT
OUT
V
= 1.8V
= 2.5V
= 3.3V
= 5.0V
OUT
V
V
V
OUT
OUT
OUT
0
0
4
1
2
3
4
5
6
0
0
4
1
2
3
4
5
6
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 5. Efficiency at VIN = 12 V, fSW = 600 kHz
Figure 8. Efficiency at VIN = 12 V, fSW = 300 kHz
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
INDUCTOR:
744 333 0100
INDUCTOR:
V
V
V
V
V
= 1.0V
FDVE1040-
2R2
OUT
OUT
OUT
OUT
OUT
V
= 1.8V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
OUT
V
V
V
= 2.5V
= 3.3V
= 5.0V
OUT
OUT
OUT
1
2
3
4
5
6
1
2
3
4
5
6
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 6. Efficiency at VIN = 18 V, fSW = 600 kHz
Figure 9. Efficiency at VIN = 5 V, fSW = 600 kHz
100
90
80
70
60
50
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
J
J
J
J
J
J
6
8
10
12
14
16
18
20
6
8
10
12
14
16
18
20
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 7. Shutdown Current vs. Input Voltage
Figure 10. Quiescent Current vs. Input Voltage
Rev. C | Page 8 of 25
Data Sheet
ADP2387
4.5
1.25
1.20
1.15
1.10
1.05
1.00
0.95
RISING
FALLING
RISING
FALLING
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
–40
–20
0
20
40
60
80
100
120
120
120
–40
–20
0
20
40
60
80
100
120
120
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. PVIN UVLO Threshold vs. Temperature
Figure 14. EN Threshold vs. Temperature
3.20
3.15
3.10
3.05
3.00
2.95
2.90
606
604
602
600
598
596
594
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. SS Pin Pull-Up Current vs. Temperature
Figure 15. Feedback Voltage vs. Temperature
630
620
610
600
590
580
570
8.4
8.3
8.2
8.1
8.0
7.9
7.8
7.7
R
= 100kΩ
T
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Frequency vs. Temperature
Figure 16. VREG Voltage vs. Temperature
Rev. C | Page 9 of 25
ADP2387
Data Sheet
65
55
45
35
25
15
5
10
9
HIGH-SIDE R
LOW-SIDE R
DSON
DSON
8
I
I
I
= 9A
= 6A
= 3A
OCP
OCP
OCP
7
6
5
4
3
2
–40
–40
–20
0
20
40
60
80
100
120
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. MOSFET Resistor vs. Temperature
Figure 20. Peak Current-Limit Threshold vs. Temperature
EN
V
(AC)
OUT
I
L
V
OUT
PGOOD
SW
I
OUT
Figure 18. Working Mode Waveform
Figure 21. Soft Start with Full Load
EN
EN
V
OUT
V
OUT
PGOOD
PGOOD
I
OUT
I
L
Figure 19. Precharged Output
Figure 22. Shutdown with Full Load
Rev. C | Page 10 of 25
Data Sheet
ADP2387
V
(AC)
V
(AC)
OUT
OUT
V
IN
SW
I
OUT
Figure 23. Load Transient Response, 1 A to 5 A
Figure 26. Line Transient Response, VIN from 8 V to 14 V, IOUT = 6 A
V
OUT
V
OUT
SW
SW
I
L
I
L
Figure 24. Output Short Entry
Figure 27. Output Short Recovery
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
V
V
V
V
V
V
= 1.0V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5.0V
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5.0V
OUT
OUT
OUT
OUT
OUT
70
75
80
85
90
95
100
70
75
80
85
90
95
100
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 25. Output Current vs. Ambient Temperature at VIN = 12 V,
SW = 600 kHz, Measured on the ADP2387 Evaluation Board
Figure 28. Output Current vs. Ambient Temperature at VIN = 12 V,
SW = 300 kHz, Measured on the ADP2387 Evaluation Board
f
f
Rev. C | Page 11 of 25
ADP2387
Data Sheet
THEORY OF OPERATION
The ADP2387 is a synchronous step-down, dc-to-dc regulator
that uses a current mode architecture with an integrated high-
side power switch and a low-side synchronous rectifier. The
regulator targets high performance applications that require
high efficiency and design flexibility.
OSCILLATOR
The RT pin controls the ADP2387 switching frequency. A
resistor (RT) from RT to GND can program the switching
frequency according to the following equation:
69,120
( )
RT kΩ +15
fSW (kHz) =
The ADP2387 operates with an input voltage from 4.5 V to 20 V
and regulates the output voltage from 0.6 V to 90% of the input
voltage. Additional features that maximize design flexibility
include programmable current-limit threshold, programmable
switching frequency, programmable soft start, external
A 100 kΩ resistor sets the frequency to 600 kHz, and a 42.2 kΩ
resistor sets the frequency to 1.2 MHz. Figure 29 shows the typical
relationship between the switching frequency (fSW) and RT.
1400
compensation, precision enable, and a power-good output.
CONTROL SCHEME
1200
1000
800
600
400
200
0
The ADP2387 uses a fixed frequency, peak current mode PWM
control architecture. At the start of each oscillator cycle, the
high-side MOSFET turns on, generating a positive voltage
across the inductor. When the inductor current crosses the peak
inductor current threshold, the high-side MOSFET turns off,
and the low-side MOSFET turns on. Turning on the low-side
MOSFET generates a negative voltage across the inductor,
which causes the inductor current to decrease. The low-side
MOSFET stays on for the rest of cycle (see Figure 18).
PRECISION ENABLE/SHUTDOWN
20
60
100
140
180
(kΩ)
220
260
300
R
T
The EN input pin has a precision analog threshold of 1.17 V
(typical) with 100 mV of hysteresis. When the enable voltage
exceeds 1.17 V, the regulator turns on. When the enable voltage
falls below 1.07 V (typical), the regulator turns off. To force the
regulator to start automatically when input power is applied,
connect EN to PVIN.
Figure 29. Switching Frequency vs. RT
SOFT START
The ADP2387 has integrated soft start circuitry to limit the output
voltage rising time and reduce inrush current at startup. Calculate
the internal soft start time (tSS_INT) by using the following equation:
The precision EN pin has an internal pull-down current source
(5 µA) that provides a default turn off when the EN pin is open.
1600
fSW (kHz)
tSS_INT
=
(ms)
When the EN pin voltage exceeds 1.17 V (typical), the ADP2387
is enabled and the internal pull-down current source at the EN
pin decreases to 1 µA, which allows users to program the PVIN
UVLO and hysteresis.
To program a slower soft start time, use the SS pin. When a
capacitor is connected between the SS pin and GND, an internal
current charges the capacitor to establish the soft start ramp.
Calculate the external soft start time (tSS_EXT) by using the
following equation:
INTERNAL REGULATOR (VREG)
The on-board regulator provides a stable supply for the internal
circuits. Place a 1 µF, X7R or X5R ceramic capacitor between
the VREG pin and the GND pin. The internal regulator includes
a current-limit circuit to protect the output if the maximum
external load current is exceeded.
0.6 V ×CSS
tSS_EXT
=
ISS_UP
where:
SS is the soft start capacitance.
SS_UP is the soft start pull-up current (3.1 µA).
C
I
BOOTSTRAP CIRCUITRY
The internal error amplifier includes three positive inputs: the
internal reference voltage, the internal digital soft start voltage,
and the SS pin voltage. The error amplifier regulates the FB
voltage to the lowest of the three voltages.
The ADP2387 includes a regulator to provide the gate drive
voltage for the high-side MOSFET. It uses differential sensing to
generate a 5 V bootstrap voltage between the BST and SW pins.
Place a 0.1 µF, X7R or X5R ceramic capacitor between the BST
and the SW pins.
When the output voltage is charged prior to turn on, the
ADP2387 prevents the reverse inductor current from discharging
the output capacitor. This function remains active until the soft
start voltage exceeds the voltage on the FB pin.
Rev. C | Page 12 of 25
Data Sheet
ADP2387
10
9
POWER GOOD
The power-good pin (PGOOD) is an active high, open-drain
output that requires an external resistor to pull it up to a
voltage. A logic high on the PGOOD pin indicates that the
voltage on the FB pin (and, therefore, the output voltage) is
within regulation.
8
7
6
The power-good circuitry monitors the output voltage on the
FB pin and compares it to the rising and falling thresholds that
are specified in Table 1. If the rising output voltage exceeds the
target value, the PGOOD pin is held low. The PGOOD pin
continues to be held low until the falling output voltage returns
to the target value.
5
4
3
2
40
60
80
100
120
(kΩ)
140
160
180
200
R
ILIM
If the output voltage falls below the target output voltage, the
PGOOD pin is held low. The PGOOD pin continues to be held
low until the rising output voltage returns to the target value.
Figure 31. Peak Current-Limit Threshold vs. RILIM
Table 5. FB Pin Voltage and Switching Frequency
The power-good rising and falling thresholds are shown in
Figure 30. There is a 1024 clock cycle waiting period before
the PGOOD pin is pulled from low to high, and there is a
16 clock cycle waiting period before the PGOOD pin is pulled
from high to low.
FB Pin Voltage
Switching Frequency
VFB ≥ 0.4 V
0.4 V > VFB ≥ 0.2 V
VFB < 0.2 V
fSW
fSW/2
fSW/4
For protection against heavy loads, the ADP2387 uses a hiccup
mode for overcurrent protection. When the inductor peak current
reaches the current-limit value, the high-side MOSFET turns
off and the low-side MOSFET turns on until the next cycle.
The overcurrent counter increments during this process. If the
overcurrent counter reaches 10 or if the FB pin voltage falls to
0.4 V after the soft start, the regulator enters hiccup mode. The
high-side and low-side MOSFETs both turn off. The regulator
remains in hiccup mode for 4096 clock cycles and then attempts
to restart. If the current-limit fault clears, the regulator resumes
normal operation. Otherwise, it reenters hiccup mode.
V
RISING
V
FALLING
OUT
OUT
116.7%
105%
100%
95
%
90%
PGOOD
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
Figure 30. PGOOD Rising and Falling Thresholds
The ADP2387 also provides a sink current-limit to prevent the
low-side MOSFET from sinking excessive current from the load.
When the voltage across the low-side MOSFET exceeds the sink
current-limit threshold, which is typically 2.5 A, the low-side
MOSFET turns off immediately for the rest of the cycle. Both high-
side and low-side MOSFETs turn off until the next clock cycle.
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2387 has a peak current-limit protection circuit to
prevent current runaway. A resistor between ILIM and GND
programs the peak current-limit threshold according to the
following equation:
In some cases, the input voltage (VPVIN) ramp rate is too slow or
the output capacitor is too large for the output to reach regulation
during the soft start process, which causes the regulator to enter
hiccup mode. To avoid such occurrences, use a resistor divider
at the EN pin to program the input voltage UVLO, or use a
longer soft start time.
405
I
OCP (A) =
RILIM kΩ + 0.5
( )
where:
OCP is the peak current-limit threshold.
ILIM is the resistor between ILIM and GND.
Figure 31 shows the typical relationship between the peak
current-limit threshold and RILIM
I
R
OVERVOLTAGE PROTECTION (OVP)
The ADP2387 includes an overvoltage protection feature to
protect the regulator against an output short to a higher voltage
supply or when a strong load disconnect transient occurs. If the
feedback voltage increases to 0.7 V, the internal high-side and
low-side MOSFETs turn off until the voltage at the FB pin
decreases to 0.63 V. At that time, the ADP2387 resumes normal
operation.
.
During the initial soft start, the ADP2387 uses frequency
foldback to prevent output current runaway. The switching
frequency reduces according to the voltage on the FB pin,
which allows more time for the inductor to discharge. Table 5
shows the correlation between the switching frequency and
FB pin voltage.
Rev. C | Page 13 of 25
ADP2387
Data Sheet
UNDERVOLTAGE LOCKOUT (UVLO)
THERMAL SHUTDOWN
Undervoltage lockout circuitry is integrated in the ADP2387 to
prevent the occurrence of power-on glitches. If the VPVIN voltage
drops below 3.8 V typical, the device shuts down and both the
power switch and synchronous rectifier turn off. When the VPVIN
voltage rises again above 4.3 V typical, the soft start period is
initiated and the device is enabled.
If the ADP2387 junction temperatures rises above 150°C, the
internal thermal shutdown circuit turns off the regulator for self
protection. Extreme junction temperatures can be the result of
high current operation, poor circuit board thermal design,
and/or high ambient temperature. If an overtemperature event
occurs, the ADP2387 does not return to normal operation until
the on-chip temperature falls below 125°C because a 25°C
hysteresis is included in the thermal shutdown circuit. Upon
recovery, a soft start initiates before normal operation begins.
Rev. C | Page 14 of 25
Data Sheet
ADP2387
APPLICATIONS INFORMATION
INPUT CAPACITOR SELECTION
VOLTAGE CONVERSION LIMITATIONS
The input capacitor reduces the input voltage ripple caused by
the switch current on PVIN. Place the input capacitor as close
as possible to the PVIN pin. A ceramic capacitor in the 10 µF to
47 µF range is recommended. Keep the loop that is composed of
this input capacitor, the high-side MOSFET, and the low-side
MOSFET as small as possible.
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2387 is typically 130 ns.
Calculate the minimum output voltage for a given input voltage
and switching frequency by using the following equation:
V
OUT_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) ×
OUT_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT_MIN
where:
OUT_MIN is the minimum output voltage.
MIN_ON is the minimum on time.
SW is the switching frequency.
The voltage rating of the input capacitor must be greater than the
maximum input voltage. The rms current rating of the input
capacitor must be larger than the value calculated by the
following equation:
I
(1)
V
t
f
IC
= IOUT × D × (1 − D)
IN−RMS
R
R
DSON_HS is the high-side MOSFET on resistance.
DSON_LS is the low-side MOSFET on resistance.
OUTPUT VOLTAGE SETTING
An external resistive divider sets the output voltage of the
ADP2387. Use the following equation to calculate the resistor
values:
IOUT_MIN is the minimum output current.
RL is the series resistance of the output inductor.
The maximum output voltage for a given input voltage and
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is typically
200 ns, and the maximum duty cycle of the ADP2387 is
typically 90%.
RTOP
RBOT
VOUT = 0.6 × 1 +
where:
R
TOP is the top feedback resistor between VOUT and FB.
Calculate the maximum output voltage, limited by the minimum
off time for a given input voltage and switching frequency, by
using the following equation:
RBOT is the bottom feedback resistor between FB and GND.
To limit output voltage accuracy degradation due to the FB bias
current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT < 30 kΩ.
V
OUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) ×
OUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT_MAX (2)
where:
OUT_MAX is the maximum output voltage.
MIN_OFF is the minimum off time.
I
Table 6 lists the recommended resistor divider values for various
output voltages.
V
t
I
Table 6. Resistor Divider Values for Various Output Voltages
VOUT (V)
OUT_MAX is the maximum output current.
RTOP 1% (kΩ)
RBOT 1% (kΩ)
Calculate the maximum output voltage, limited by the maximum
duty cycle for a given input voltage, using the following equation:
1.0
1.2
1.5
1.8
2.5
3.3
5.0
10
10
15
20
47.5
10
22
15
10
10
10
15
2.21
3
VOUT_MAX = DMAX × VIN
(3)
where DMAX is the maximum duty cycle.
As shown in Equation 1 to Equation 3, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.
Rev. C | Page 15 of 25
ADP2387
Data Sheet
INDUCTOR SELECTION
OUTPUT CAPACITOR SELECTION
The operating frequency, input voltage, output voltage, and
inductor ripple current determine the inductor value. Using a
small inductor leads to a faster transient response, but it degrades
efficiency due to a larger inductor ripple current; whereas using
a large inductor value leads to smaller ripple current and better
efficiency but results in a slower transient response.
The output capacitor selection affects the output ripple voltage
load step transient and the loop stability of the regulator.
For example, during a load step transient where the load is
suddenly increased, the output capacitor supplies the load until
the control loop can ramp up the inductor current. The delay
caused by the control loop causes output undershoot. Calculate
the output capacitance that is required to satisfy the voltage
droop requirement by using the following equation:
As a guideline, the inductor ripple current, ΔIL, is typically set to
one-third of the maximum load current. Calculate the inductor
value by using the following equation:
KUV × ∆ISTEP2 × L
2 ×(VIN −VOUT )× ∆VOUT _UV
COUT_UV
=
(VIN −VOUT )× D
L =
∆IL × fSW
where:
KUV is a factor, with a typical setting of KUV = 2.
where:
V
V
IN is the input voltage.
OUT is the output voltage.
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
D is the duty cycle (D = VOUT/VIN).
ΔIL is the inductor current ripple.
Another example occurs when a load is suddenly removed from
the output, and the energy stored in the inductor rushes into
the output capacitor, causing the output to overshoot.
fSW is the switching frequency.
The ADP2387 uses adaptive slope compensation in the current
loop to prevent subharmonic oscillations when the duty cycle is
larger than 50%. The internal slope compensation limits the
minimum inductor value.
Calculate the output capacitance required to meet the overshoot
requirement by using the following equation:
KOV × ∆ISTEP2 × L
(VOUT + ∆VOUT _OV ) −VOUT
COUT_OV
=
2
2
For a duty cycle that is larger than 50%, determine the
minimum inductor value by using the following equation:
where:
OV is a factor, with a typical setting of KOV = 2.
K
VOUT
×
(
1− D
)
L (Minimum) =
ΔVOUT_OV is the allowable overshoot on the output voltage.
4× fSW
The equivalent series resistance (ESR) and capacitance value
determine the output ripple. Use the following equations to
select a capacitor to meet the output ripple requirements:
Calculate the peak inductor current as follows:
ΔIL
2
IPEAK = IOUT +
∆IL
COUT_RIPPLE
=
8 × fSW × ∆VOUT _ RIPPLE
The saturation current of the inductor must be larger than the peak
inductor current. For ferrite core inductors with a quick saturation
characteristic, the saturation current rating of the inductor must
be higher than the current-limit threshold of the switch. This
higher rating prevents the inductor from reaching saturation.
∆VOUT _ RIPPLE
RESR
=
∆IL
where:
ΔVOUT_RIPPLE is the allowable output ripple voltage.
ESR is the ESR of the output capacitor in ohms (Ω).
Calculate the rms current of the inductor as follows:
R
2
∆IL
12
2
IRMS
=
Select the largest output capacitance given by COUT_UV, COUT_OV
and COUT_RIPPLE to meet both load transient and output ripple
performance.
,
IOUT
+
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 7 lists some recommended inductors.
The selected output capacitor voltage rating must be greater
than the output voltage. The rms current rating of the output
capacitor must be larger than the value calculated by
∆IL
12
ICOUT_RMS
=
Rev. C | Page 16 of 25
Data Sheet
ADP2387
Table 7. Recommended Inductors
Vendor
Part No.
Value (µH)
0.47
0.75
1.0
1.5
2.2
ISAT (A)
15.6
10.9
9.5
13.7
11.4
9.8
IRMS (A)
14.1
10.7
9.5
14.6
11.6
9.0
DCR (mΩ)
3.7
6.2
8.5
4.6
Toko
FDVE0630-R47M
FDVE0630-R75M
FDVE0630-1R0M
FDVE1040-1R5M
FDVE1040-2R2M
FDVE1040-3R3M
FDVE1040-4R7M
IHLP3232DZ-R47M-11
IHLP3232DZ-R68M-11
IHLP3232DZ-1R0M-11
IHLP4040DZ-1R5M-01
IHLP4040DZ-2R2M-01
IHLP4040DZ-3R3M-01
IHLP4040DZ-4R7M-01
744 325 120
6.8
3.3
4.7
10.1
13.8
2.38
3.22
4.63
5.8
8.2
8.0
Vishay
0.47
0.68
1.0
1.5
2.2
14
14.5
12
27.5
25.6
18.6
17
25
22.2
18.2
15
12
10
9
3.3
4.7
14.4
16.5
1.8
9.5
Wurth Elektronik
1.2
25
20
744 325 180
1.8
18
16
3.5
744 325 240
744 325 330
2.4
3.3
17
15
14
12
4.75
5.9
744 325 420
4.2
14
11
7.1
PROGRAMMING INPUT VOLTAGE UVLO
COMPENSATION DESIGN
The ADP2387 has a precision enable input that can program
the UVLO threshold of the input voltage (see Figure 32).
For peak current-mode control, simplify the power stage as a
voltage controlled current source supplying current to the output
capacitor and load resistor. It is composed of one domain pole
and a zero that is contributed by the output capacitor ESR. The
control-to-output transfer function is based on the following:
PVIN
ADP2387
R
TOP_EN
s
1+
1+
EN CMP
2× π× fZ
EN
V
OUT (s)
GVD (s) =
= AVI × R ×
VCOMP (s)
s
1.17V
4µA
R
BOT_EN
2× π× fP
1µA
1
fz =
2 × π × RESR ×COUT
Figure 32. Programming the Input Voltage UVLO
Use the following equations to calculate RTOP_EN and RBOT_EN
1.07 V ×VIN _ RISING −1.17 V ×VIN _ FALLING
1
fp =
:
2 × π×(R + RESR )×COUT
RTOP_EN
=
where:
VI = 8.7 A/V.
R is the load resistance.
ESR is the equivalent series resistance of the output capacitor.
OUT is the output capacitance.
1.07 V ×5 μA −1.17 V ×1 μA
A
1.17 V× RTOP _ EN
RBOT_EN
where:
=
R
C
VIN _ RISING − RTOP _ EN ×5 μA −1.17 V
A transconductance amplifier is used on the ADP2387 as an
error amplifier and to compensate the system. Figure 33 shows
the simplified, peak current mode control, small signal circuit.
V
V
IN_RISING is the VIN rising threshold.
IN_FALLING is the VIN falling threshold.
Rev. C | Page 17 of 25
ADP2387
Data Sheet
V
V
R
OUT
OUT
Calculate RC by using the following equation:
2 × π ×VOUT COUT fC
m × AVI
R
×
×
TOP
RC =
V
C
R
0.6V ×
g
COMP
OUT
–
gm
+
–
A
VI
+
Place the compensation zero at the domain pole (fP), then
determine CC by using the following equation:
R
BOT
R
C
C
CP
ESR
C
C
(R + RESR )×COUT
CC =
RC
CCP is optional. It can be used to cancel the zero caused by the
ESR of the output capacitor.
Figure 33. Simplified, Peak Current Mode Control, Small Signal Circuit
The compensation components, RC and CC, contribute a zero, and
the optional components, CCP and RC, contribute an optional pole.
R
ESR ×COUT
CCP
=
RC
The closed-loop transfer equation is as follows:
ADIsimPower DESIGN TOOL
RBOT
−gm
TV (s) =
×
×
RBOT + RTOP CC + CCP
The ADP2387 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic and bill of materials
and to calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and parts count,
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For
more information about the ADIsimPower design tools, go to
www.analog.com/ADIsimPower. The tool set is available from
the Analog Devices, Inc., website, and users can request an
unpopulated board.
1+ RC ×CC ×s
×GVD (s)
RC ×CC ×CCP
CC ×CCP
s× 1+
×s
The following design guideline shows how to select the RC, CC,
and CCP compensation components for ceramic output capacitor
applications.
Determine the cross frequency (fC). Generally, fC is between
fSW/12 and fSW/6.
Rev. C | Page 18 of 25
Data Sheet
ADP2387
DESIGN EXAMPLE
ADP2387
V
= 12V
IN
PVIN
EN
BST
SW
C
IN
C
0.1µF
BST
L1
10µF
25V
2.2µH
V
= 3.3V
PGOOD
OUT
C
100µF
C
OUT2
47µF
6.3V
ILIM
OUT1
R
10kΩ
R
TOP
ILIM
R
T
44.2kΩ
6.3V
100kΩ
1%
RT
FB
VREG
R
BOT
2.21kΩ
1%
C
COMP
VREG
1µF
R
C
SS
44.2kΩ
C
22nF
C
4.7pF
SS
C
CP
GND PGND
C
1.2nF
Figure 34. Schematic for Design Example
This section describes the procedures for selecting the external
components, based on the example specifications that are listed
in Table 8. See Figure 34 for the schematic of this design example.
INDUCTOR SELECTION
The peak-to-peak inductor ripple current, ∆IL, is set to 30% of
the maximum output current. To estimate the inductor value,
use the following equation:
Table 8. Step-Down DC-to-DC Regulator Requirements
Parameter
Specification
12.0 V 10%
3.3 V
6 A
33 mV
(VIN −VOUT )× D
L =
Input Voltage (VIN)
Output Voltage (VOUT
Output Current (IOUT
Output Voltage Ripple (∆VOUT_RIPPLE
Load Transient
Switching Frequency (fSW)
∆IL × fSW
)
where:
)
V
V
IN = 12 V.
OUT = 3.3 V.
D = 0.275.
∆IL = 1.8 A.
)
5%, 1 A to 5 A, 2 A/µs
600 kHz
fSW = 600 kHz.
OUTPUT VOLTAGE SETTING
This calculation results in L = 2.215 µH. Choose the standard
inductor value of 2.2 µH.
Choose a 10 kΩ resistor as the top feedback resistor (RTOP),
and calculate the bottom feedback resistor (RBOT) by
Calculate the peak-to-peak inductor ripple current by using the
following equation:
0.6
RBOT = RTOP ×
VOUT − 0.6
(VIN −VOUT )× D
ΔIL =
To set the output voltage to 3.3 V, the resistors values are as
follows: RTOP = 10 kΩ, and RBOT = 2.21 kΩ.
L × fSW
This calculation results in ∆IL = 1.81 A.
FREQUENCY SETTING
To calculate the peak inductor current, use the following equation:
To set the switching frequency to 600 kHz, connect a 100 kΩ
resistor from the RT pin to GND.
∆IL
2
IPEAK = IOUT +
CURRENT-LIMIT THRESHOLD SETTING
This calculation results in IPEAK = 6.905 A.
Connect a 44.2 kΩ resistor between ILIM pin and GND to set
the current-limit threshold at 9 A.
To calculate the rms current flowing through the inductor, use
the following equation:
2
∆IL
12
2
IRMS
=
IOUT
+
This calculation results in IRMS = 6.023 A.
Based on the calculated current value, select an inductor with
a minimum rms current rating of 6.03 A and a minimum
saturation current rating of 6.91 A.
However, to protect the inductor from reaching its saturation
point under the current-limit condition, rate the inductor for at
least a 9.2 A saturation current for reliable operation.
Rev. C | Page 19 of 25
ADP2387
Data Sheet
Based on the requirements previously described, select a 2.2 µH
inductor, such as the FDVE1040-2R2M from Toko, which has
a 6.1 mΩ DCR and an 11.4 A saturation current.
2× π ×3.3 V ×94 μF×60 kHz
0.6 V × 480μS ×8.7 A/V
RC =
CC =
= 46.7 kΩ
(0.55 Ω +0.002 Ω )× 94 μF
= 1111 pF
OUTPUT CAPACITOR SELECTION
46.7 kΩ
The output capacitor is required to meet both the output voltage
ripple and load transient response requirements.
0.002 Ω× 94 μF
46.7 kΩ
CCP
=
= 4.0 pF
To meet the output voltage ripple requirement, use the following
equation to calculate the ESR and capacitance value of the
output capacitor:
Choose standard components, as follows: RC = 44.2 kΩ,
CC = 1200 pF, and CCP = 4.7 pF.
Figure 35 shows the bode plot at 6 A. The cross frequency is
58 kHz, and the phase margin is 62°.
∆IL
COUT_RIPPLE
=
8 × fSW × ∆VOUT _ RIPPLE
60
180
144
108
72
∆VOUT _ RIPPLE
48
RESR
=
∆IL
36
This calculation results in COUT_RIPPLE = 11.4 µF, and RESR = 18 mΩ.
24
12
36
To meet the 5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
0
0
–12
–24
–36
–48
–60
–36
–72
–108
–144
–180
KOV × ∆ISTEP2 × L
COUT_OV
=
=
2
2
(VOUT + ∆VOUT _OV ) −VOUT
KUV × ∆ISTEP2 × L
2 ×(VIN −VOUT )× ∆VOUT _UV
COUT_UV
1k
10k
100k
1M
FREQUENCY (Hz)
where:
OV = KUV = 2 are the coefficients for estimation purposes.
Figure 35. Bode Plot at 6 A
K
∆ISTEP = 4 A is the load transient step.
∆VOUT_OV = 5% VOUT is the overshoot voltage.
∆VOUT_UV = 5% VOUT is the undershoot voltage.
SOFT START TIME PROGRAM
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
This calculation results in COUT_OV = 63.1 µF, and COUT_UV = 24.5 µF.
According to the calculation, the output capacitance must be
greater than 63 µF, and the ESR of the output capacitor must be
smaller than 18 mΩ. It is recommended that one 100 µF/X5R/
6.3 V ceramic capacitor and one 47 µF/X5R/6.3 V ceramic
capacitor be used, such as the GRM32ER60J107ME20 and
GRM32ER60J476ME20 from Murata, with an ESR of 2 mΩ.
tSS _ EXT × ISS _UP 4 ms × 3.1 μA
CSS
=
= 20.7 nF
=
0.6
0.6V
Choose a standard component value, as follows: CSS = 22 nF.
INPUT CAPACITOR SELECTION
COMPENSATION COMPONENTS
Place a minimum 10 µF ceramic capacitor near the PVIN pin.
In this application, it is recommended that one 10 µF, X5R, 25 V
ceramic capacitor be used.
For better load transient and stability performance, set the cross
frequency (fC) to fSW/10. In this case, fSW is running at 600 kHz;
therefore, fC is set to 60 kHz.
The 100 µF and 47 µF ceramic output capacitors have a derated
value of 62 µF and 32 µF, respectively.
Rev. C | Page 20 of 25
Data Sheet
ADP2387
RECOMMENDED EXTERNAL COMPONENTS
Table 9. Recommended External Components for Typical Applications with 6 A Output Current
fSW (kHz)
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
VOUT (V)
L (µH)
1.5
2.2
2.2
3.3
3.3
4.7
4.7
1.5
1.5
2.2
2.2
2.2
2.2
1
1.5
2.2
2.2
3.3
1
1
1
1
1
COUT (µF)1
680 + 2 × 100
680 + 2 × 100
680
680
470
3 × 100
100 + 47
680 + 2 × 100
680
680
470
3 × 100
3 × 100
3 × 100
3 × 100
2 × 100
100 + 47
100
RTOP (kΩ)
RBOT (kΩ)
RC (kΩ)
57.6
68.1
73.2
88.7
84.5
44.2
33
57.6
57.6
73.2
61.9
33
44.2
39
47
44.2
44.2
44.2
97.6
82
CC (pF)
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
680
CCP (pF)
150
120
100
82
300
1
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
15
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
10
15
2.21
3
15
10
10
10
15
2.21
15
2.21
3
15
10
1.2
1.5
1.8
2.5
3.3
5
47
8.2
4.7
150
120
100
82
10
8.2
10
8.2
4.7
4.7
2.2
68
1
1.2
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
5
5
600
12
12
12
12
12
5
5
5
5
5
15
20
47.5
10
22
10
10
15
20
1
680
470
1.2
1.5
1.8
2.5
3.3
2.5
3.3
5
47
10
3 × 100
2 × 100
100
100 + 47
100
39
33
22
8.2
4.7
4.7
3.3
2.2
2.2
8.2
6.8
4.7
4.7
3.3
2.2
47.5
10
5
1
44.2
37.4
47
73.2
44.2
34.8
33
39
37.4
47
1000
12
12
12
5
5
5
5
5
5
1
47.5
10
22
10
10
15
20
47.5
10
1.5
1.5
0.47
0.47
0.68
0.68
0.68
0.68
100
100
680
680
680
680
680
680
680
680
1
3 × 100
2 × 100
100 + 47
100 + 47
100
1.2
1.5
1.8
2.5
3.3
10
10
15
2.21
100
1 680 µF: 4 V, KEMET T520Y687M004ATE010; 470 µF: 6.3 V, KEMET T520X477M006ATE010; 100 µF: 6.3 V, X5R, Murata GRM32ER60J107ME20; and 47 µF: 6.3 V, X5R,
Murata GRM32ER60J476ME20.
Rev. C | Page 21 of 25
ADP2387
Data Sheet
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good printed circuit board (PCB) layout is essential for obtaining
the best performance from the ADP2387. Poor PCB layout
can degrade the output regulation, as well as the EMI and
electromagnetic compatibility (EMC) performance. Figure 37
shows an example of a good PCB layout for the ADP2387. For
optimum layout, refer to the following guidelines:
•
•
Connect the exposed GND pad of the ADP2387 to a large,
external copper ground plane to maximize its power
dissipation capability and to minimize junction temperature.
In addition, connect the exposed SW pad to the SW pins
of the ADP2387, using short, wide traces; or connect the
exposed SW pad to a large external copper plane of the
switching node for high current flow.
Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Minimize
the length of the trace that connects the top of the feedback
resistor divider to the output while keeping the trace away
from the high current traces and the switching node to
avoid noise pickup. To further reduce noise pickup, place
an analog ground plane on either side of the FB trace and
ensure that the trace is as short as possible to reduce the
parasitic capacitance pickup.
•
Use separate analog ground planes and power ground
planes. Connect the ground reference of sensitive analog
circuitry, such as output voltage divider components, to
analog ground. In addition, connect the ground reference
of power components, such as input and output capacitors,
to power ground. Connect both ground planes to the
exposed GND pad of the ADP2387.
•
Place the input capacitor, inductor, and output capacitor as
close as possible to the IC, and use short traces. Ensure that
the high current loop traces are as short and as wide as
possible. Make the high current path from the input
capacitor through the inductor, the output capacitor, and
the power ground plane back to the input capacitor as
short as possible by ensuring that the input and output
capacitors share a common power ground plane.
In addition, ensure that the high current path from the
power ground plane through the inductor and output
capacitor back to the power ground plane is as short as
possible by tying the PGND pins of the ADP2387 to the
PGND plane as close as possible to the input and output
capacitors.
ADP2387
V
PVIN
BST
SW
IN
C
C
IN
BST
EN
V
L
OUT
PGOOD
C
OUT
R
R
TOP
ILIM
FB
RT
COMP
SS
BOT
R
VREG
C
R
R
T
ILIM
C
GND PGND
VREG
C
C
C
SS
Figure 36. High Current Path in the PCB Circuit
Rev. C | Page 22 of 25
Data Sheet
ADP2387
ANALOG GROUND PLANE
R
BOT
PVIN
COMP
PVIN
PVIN
R
TOP
FB
INPUT
INPUT
GND
SW
BYPASS BULK
CAP
CAP
VREG
PVIN
BST
C
VREG
GND
SW
+
C
BST
SW
SW
PGND
SW
INDUCTOR
POWER GROUND PLANE
OUTPUT
CAPACITOR
VOUT
VIA
BOTTOM LAYER TRACE
COPPER PLANE
Figure 37. Recommended PCB Layout
Rev. C | Page 23 of 25
ADP2387
Data Sheet
TYPICAL APPLICATIONS CIRCUITS
ADP2387
V
= 12V
IN
PVIN
EN
BST
SW
C
IN
C
BST
0.1µF
L1
1.0µH
10µF
25V
PGOOD
V
= 1.2V
OUT
C
470µF
C
OUT2
100µF
6.3V
ILIM
OUT1
R
10kΩ
R
TOP
ILIM
44.2kΩ
R
T
6.3V
124kΩ
1%
RT
FB
VREG
R
10kΩ
BOT
C
COMP
VREG
1µF
R
1%
C
SS
66.5kΩ
C
22nF
C
SS
C
CP
68pF
GND PGND
C
1.5nF
Figure 38. Typical Applications Circuit, VIN = 12 V, VOUT = 1.2 V, IOUT = 6 A, fSW = 500 kHz
ADP2387
V
= 12V
IN
PVIN
BST
SW
C
R
IN
TOP_EN
16.9kΩ
C
0.1µF
BST
L1
10µF
3.3µH
V
= 5.0V
OUT
25V
EN
R
BOT_EN
2kΩ
C
OUT
100µF
6.3V
PGOOD
ILIM
R
TOP
22kΩ
1%
R
R
ILIM
T
FB
44.2kΩ
100kΩ
RT
R
BOT
COMP
3kΩ
1%
VREG
R
C
C
VREG
44.2kΩ
1µF
C
C
SS
CP
2.2pF
GND PGND
C
C
SS
1.2nF
22nF
Figure 39. Programming Input Voltage UVLO Rising Threshold at 11 V, Falling Threshold at 10 V, VIN = 12 V, VOUT = 5 V, IOUT = 6 A, fSW = 600 kHz
ADP2387
V
= 12V
IN
PVIN
EN
BST
SW
C
IN
C
BST
0.1µF
L1
4.7µH
10µF
25V
PGOOD
V
= 3.3V
OUT
C
100µF
C
OUT2
47µF
6.3V
ILIM
OUT1
R
10kΩ
R
TOP
ILIM
80.6kΩ
R
T
6.3V
100kΩ
1%
RT
FB
VREG
R
BOT
C
COMP
2.21kΩ
VREG
1µF
R
1%
C
SS
44.2kΩ
C
22nF
C
SS
C
CP
4.7pF
GND PGND
C
2.2nF
Figure 40. Programming Peak Current-Limit Threshold at 5 A, VIN = 12 V, VOUT = 3.3 V, IOUT = 3 A, fSW = 600 kHz
Rev. C | Page 24 of 25
Data Sheet
ADP2387
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
2.80
2.70
2.60
0.20
MIN
0.20 MIN
PIN 1
PIN 1
INDICATOR
INDICATOR
1.50
0.20
MIN
19
24
18
1.40
1
1.30
0.45
EXPOSED
PAD
0.35
0.25
0.50
BSC
EXPOSED
PAD
1.05
0.95
0.85
6
13
7
12
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
0.20
MIN
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD .
Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option
ADP2387ACPZN-R7 −40°C to +125°C
ADP2387-EVALZ
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7”Tape and Reel
Evaluation Board
CP-24-12
1 Z = RoHS Compliant Part.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12643-0-4/17(C)
Rev. C | Page 25 of 25
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