ADP2389 [ADI]
18 V, 12 A Step-Down Regulator with Programmable Current Limit;
| 型号： | ADP2389 |
| 厂家： | 
ADI |
| 描述： | 18 V, 12 A Step-Down Regulator with Programmable Current Limit |
| 文件： | 总23页 (文件大小：776K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
18 V, 12 A Step-Down Regulator with
Programmable Current Limit
Data Sheet
ADP2389/ADP2390
FEATURES
TYPICAL APPLICATIONS CIRCUIT
Input voltage: 4.5 V to 18 V
Continuous output current: 12 A
Integrated MOSFETs: 17 mΩ high-side/4.5 mΩ low-side
0.6 V 0.5% reference voltage
Programmable switching frequency range: 200 kHz to 2200 kHz
Enhanced transient response
VIN
PVIN
EN
BST
V
C
IN
BST
C
IN
V
SW
OUT
L
PGOOD
C
OUT
ADP2389/
ADP2390
R
R
TOP
BOT
FTW
FB
COMP
SS
ILIM
RT
Programmable current limit with 10% accuracy
Precision enable and power good
VREG
R
C
R
R
R
T
FTW
ILIM
GND PGND
External compensation and soft start
PFM mode (ADP2390 only)
C
C
C
C
VREG
SS
Start up into a precharged output
Supported by the ADIsimPower design tool
Figure 1.
APPLICATIONS
Communication infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversions
DC-to-DC point of load applications
GENERAL DESCRIPTION
The ADP2389/ADP2390 are current mode control, synchronous
step-down, dc-to-dc regulators. They integrate a 17 mΩ high-side
power MOSFET and a 4.5 mΩ synchronous rectifier MOSFET to
provide a high efficiency solution. The ADP2390 operates in pulse
frequency modulation (PFM) mode to improve the system
efficiency at light load. The ADP2389/ADP2390 run from an
input voltage of 4.5 V to 18 V and can deliver up to 12 A of output
current. The output voltage can be adjusted to 0.6 V and the
switching frequency can be programmed between 200 kHz to
2200 kHz.
The ADP2389/ADP2390 operates over a −40°C to +125°C
junction temperature range and is available in 32-lead, 5 mm ×
5 mm LFCSP package.
100
95
90
85
80
75
70
The ADP2389/ADP2390 target high performance applications
that require high efficiency and design flexibility. External
compensation and soft start provide design flexibility. The power-
good output and precision enable input provide simple and reliable
power sequencing. An enhanced transient response feature
improves the load transient performance, which reduces the
output capacitance. Programmable current limit allows the user
to optimized the inductor design and provide a compact solution.
V
V
V
V
= 1.2V
= 1.8V
= 3.3V
= 5.0V
OUT
OUT
OUT
OUT
65
60
0
1
2
3
4
5
6
7
8
9
10 11 12
OUTPUT CURRENT (A)
Figure 2. ADP2389 Efficiency vs. Output Current, VIN = 12 V, fSW = 300 kHz
Other key features include undervoltage lockout (UVLO),
overvoltage protection (OVP), overcurrent protection (OCP),
and thermal shutdown (TSD).
Rev. 0
Document Feedback
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Technical Support
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www.analog.com
ADP2389/ADP2390
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Undervoltage Lockout (UVLO) ............................................... 13
Thermal Shutdown .................................................................... 13
Applications Information.............................................................. 14
Input Capacitor Selection.......................................................... 14
Output Voltage Setting .............................................................. 14
Inductor Selection...................................................................... 14
Output Capacitor Selection....................................................... 15
Programming Input Voltage UVLO ........................................ 15
Compensation Design ............................................................... 15
Design Example.............................................................................. 17
Output Voltage Setting .............................................................. 17
Frequency Setting....................................................................... 17
Inductor Selection...................................................................... 17
Output Capacitor Selection....................................................... 17
Compensation Components..................................................... 18
Soft Start Time Program ........................................................... 18
Input Capacitor Selection.......................................................... 18
Schematic for Design Example................................................. 18
External Components Recommendation.................................... 19
Circuit Board Layout Recommendations ................................... 20
Typical Application Circuits ......................................................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Detailed Functional Block Diagram .............................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Information................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 12
Control Scheme .......................................................................... 12
PFM Mode (ADP2390 Only).................................................... 12
Precision Enable/Shutdown...................................................... 12
Internal Regulator (VREG)....................................................... 12
Bootstrap Circuitry .................................................................... 12
Oscillator ..................................................................................... 12
Soft Start ...................................................................................... 13
Fast Transient Response ............................................................ 13
Power Good................................................................................. 13
Peak Current-Limit and Short-Circuit Protection................. 13
Overvoltage Protection (OVP)................................................. 13
REVISION HISTORY
8/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 23
Data Sheet
ADP2389/ADP2390
DETAILED FUNCTIONAL BLOCK DIAGRAM
VREG
5V
CLK
VIN
REGULATOR
RT
EN
OSC
SLOPE RAMP
1.2V
UVLO
EN_BUF
SHUTDOWN
LOGIC
THERMAL
SHUTDOWN
1.3µA
4.8µA
PVIN
BOOST
REGULATOR
OCP
THRESHOLD
SETTING
I
MAX
ILIM
+
HICCUP
MODE
OCP
–
+
A
CS
–
SLOPE RAMP
Σ
COMP
0.6V
+
+
–
+
I
SS
CMP
–
g
SS
FB
m
BST
SW
SKIP
CMP
NFET
NFET
–
+
DRIVER
PFM
THRESHOLD
CONTROL
LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
ADP2390
ONLY
FTW
FAST
TRANSIENT
WINDOW
VREG
DRIVER
0.7V
OVP
–
+
–
+
–
+
PGND
+
–
I
NEG
CLK
NEGATIVE
0.66V
CURRENT
COMPARATOR
0.54V
PGOOD
GND
DEGLITCH
ADP2389/ADP2390
Figure 3. ADP2389/ADP2390 Detailed Functional Block Diagram
Rev. 0 | Page 3 of 23
ADP2389/ADP2390
SPECIFICATIONS
Data Sheet
VPVIN = VVIN = 12 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless
otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Units
SUPPLY VOLTAGE (PVIN AND VIN)
PVIN Voltage Range
VIN Voltage Range
Quiescent Current
Shutdown Current
VPVIN
VVIN
IQ
ISHDN
UVLO
4.5
4.5
18
18
1.5
20
4.4
V
V
mA
µA
V
No switching
EN = GND
VIN rising
1.16
7.5
4.2
VIN Undervoltage Lockout Threshold
VIN falling
3.5
3.7
V
FEEDBACK (FB)
FB Regulation Voltage
VFB
IFB
0°C < TJ < 85°C
−40°C < TJ < +125°C
0.597
0.594
0.6
0.6
0.01
0.603
0.606
0.1
V
V
µA
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
gm
ISOURCE
ISINK
450
40
40
500
50
50
550
60
60
µS
µA
µA
EA Sink Current
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
Regulator Current Limit
SWITCH NODE (SW)
On Resistance1
VVREG
IVREG = 10 mA
IVREG = 50 mA
4.8
5
355
100
5.2
V
mV
mA
High-Side
Low-Side
SW Minimum On Time2
SW Minimum Off Time2
CURRENT LIMIT
RDSON_H
RDSON_L
tMIN_ON
tMIN_OFF
VBOOT = 5 V
VVREG = 5 V
17
30
9
mΩ
mΩ
ns
4.5
100
150
ns
ILIM Voltage
VILIM
IILIM
IOCP
0.592
V
µA
A
ILIM Current Range
High-Side Peak Current Limit
Low-Side Negative Current Limit2
BST
1.8
15
12
18.6
RILIM = 59 kΩ
16.8
4
A
Bootstrap Voltage
VBOOT
fSW
4.6
5
5.4
V
OSCILLATOR (RT )
Switching Frequency
Switching Frequency Range
FAST TRANSIENT WINDOW (FTW)
Fast Transient Response Window
Minimum Fast Transient Response Window2
SS
RT = 100 kΩ
540
200
600
660
2200
kHz
kHz
RFTW = 100 kΩ
2
1
%
%
SS Pin Pull-Up Current
ISS
2.7
3.4
4.1
µA
Rev. 0 | Page 4 of 23
Data Sheet
ADP2389/ADP2390
Parameter
PGOOD
Symbol
Test Conditions/Comments
Min
Typ
Max
Units
FB Threshold
Rising
Falling
106
86
110
90
114
94
%
%
FB Hysteresis
Rising
5
%
Falling
5
%
Power-Good Deglitch Time
PGOOD from low to high
PGOOD from high to low
VPGOOD = 5 V
16
16
0.01
150
Cycles
Cycles
µA
PGOOD Leakage Current
PGOOD Output Low Voltage
EN
0.1
260
IPGOOD = 1 mA
mV
EN Rising Threshold
EN Falling Threshold
EN Source Current
1.2
1.1
6.1
1.3
1.28
V
V
µA
µA
1.02
EN voltage < 1.1 V
EN voltage > 1.2 V
THERMAL
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
150
25
°C
°C
1 Pin-to-pin measurement.
2 Guaranteed by design.
Rev. 0 | Page 5 of 23
ADP2389/ADP2390
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL INFORMATION
Table 2.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board (4-layer, JEDEC standard board) for
surface-mount packages.
Parameter
Rating
PVIN, VIN, EN, PGOOD
SW
BST
FB, SS, COMP, RT, ILIM, FTW, VREG
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
−0.3 V to +22 V
−1 V to +22 V
VSW + 6 V
−0.3 V to +6 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Table 3. Thermal Resistance
Package Type
θJA
θJC
Unit
32-Lead LFCSP
41
2.2
°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Unless otherwise specified, all other voltages are referenced to
GND.
Rev. 0 | Page 6 of 23
Data Sheet
ADP2389/ADP2390
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP2389/ADP2390
TOP VIEW
(Not to Scale)
SS 1
COMP 2
FB 3
24 PVIN
23 PVIN
22 PVIN
21 BST
20 SW
33
GND
VREG 4
GND 5
SW 6
19 SW
34
SW
SW 7
18 PGND
17 PGND
SW 8
NOTES
1. THE EXPOSED GND PAD MUST BE SOLDERED TO A LARGE, EXTERNAL,
COPPER GND PLANE TO REDUCE THERMAL RESISTANCE.
2. THE EXPOSED SW PAD MUST BE CONNECTED TO THE SW PINS BY
USING SHORT, WIDE TRACES, OR SOLDERED TO A LARGE, EXTERNAL,
COPPER SW PLANE TO REDUCE THERMAL RESISTANCE.
Figure 4. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
SS
COMP
FB
Soft Start Control. Connect a capacitor from the SS pin to GND to program the soft start time.
Error Amplifier Output. Connect an RC network from the COMP pin to GND.
Feedback Voltage Sense Input. Connect this pin to a resistor divider from the output voltage, VOUT
Output of the Internal 5 V Regulator. The control circuits are powered from this voltage. Place a 1 μF, X7R or
X5R ceramic capacitor between this pin and GND.
.
VREG
5
GND
Analog Ground.
6 to 11, 19, 20 SW
Switch Node. Connect this pin to an inductor.
12 to 18
21
PGND
BST
Power Ground. Return of the low-side MOSFET.
Supply Rail for the High-Side Gate Drive. Place a 0.1 μF, X7R or X5R capacitor between SW and BST.
22 to 26
PVIN
Power Input. Connect PVIN to the input power source and connect a bypass capacitor between this pin and
PGND.
27
28
29
30
31
32
33
34
VIN
Power Input for Control Circuitry. Bypass VIN to GND with a low equivalent series resistance (ESR) capacitor
as close to the device as possible. Connect VIN to PVIN directly.
Precision Enable. Use an external resistor divider to set the turn on threshold. To enable the device
automatically, connect the EN pin to PVIN.
Fast Transient Response Window Setting. Connect a resistor between the FTW pin and GND to set the fast
transient response window.
Power-Good Output (Open-Drain). Connecting a 10 kΩ to 100 kΩ pull-up resistor from PGOOD to a pull-up
voltage is recommended.
Current-Limit Threshold Setting. Connect a resistor from the ILIM pin to GND to program the current-limit
threshold.
Frequency Setting. Connect a resistor between the RT pin and GND to program the switching frequency
between 200 kHz to 2.2 MHz.
Exposed GND Pad. The exposed GND pad must be soldered to a large, external, copper GND plane to reduce
thermal resistance.
Exposed SW Pad. The exposed SW pad must be connected to the SW pins by using short, wide traces, or
soldered to a large, external, copper SW plane to reduce thermal resistance.
EN
FTW
PGOOD
ILIM
RT
EP, GND
EP, SW
Rev. 0 | Page 7 of 23
ADP2389/ADP2390
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VPVIN = VVIN = 12 V, V OUT = 1.8 V, L = 1 µH, COUT = 5 × 100 µF, fSW = 500 kHz, unless otherwise noted.
100
100
95
90
85
80
75
70
65
60
95
90
85
80
INDUCTOR:
744 333 0100
INDUCTOR:
744 333 0220
75
70
65
60
V
V
V
V
V
V
V
= 1.0V
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
= 5.0V
V
V
V
V
V
V
V
= 1.0V
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
= 5.0V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 5. ADP2389 Efficiency at VPVIN = 12 V, fSW = 600 kHz
Figure 8. ADP2389 Efficiency at VPVIN = 12 V, fSW = 300 kHz
100
100
95
90
95
90
85
80
75
70
65
60
85
80
INDUCTOR:
744 333 0220
75
70
65
60
INDUCTOR:
744 333 0100
V
V
V
V
V
V
V
= 1.0V
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
= 5.0V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
V
V
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
= 5.0V
OUT
OUT
OUT
OUT
OUT
OUT
0.1
1
10
0.1
1
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 6. ADP2390 Efficiency at VPVIN = 12 V, fSW = 600 kHz
Figure 9. ADP2390 Efficiency at VPVIN = 12 V, fSW = 300 kHz
16
1.25
14
12
1.20
1.15
1.10
1.05
10
8
6
4
2
0
T
T
T
= –40°C
= +25°C
= +125°C
T
T
T
= –40°C
= +25°C
= +125°C
J
J
J
J
J
J
1.00
4
6
8
10
12
14
16 18
4
6
8
10
12
14
16 18
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 7. Shutdown Current (ISHDN) vs. Input Voltage
Figure 10. Quiescent Current (IQ) vs. Input Voltage
Rev. 0 | Page 8 of 23
Data Sheet
ADP2389/ADP2390
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
1.25
1.20
RISING
RISING
1.15
1.10
FALLING
1.05
1.00
FALLING
40
0.95
–40
–40
–20
0
20
60
80
100
120
–20
0
20
40
60
80
100
120
120
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. VIN UVLO Threshold vs. Temperature
Figure 14. EN Threshold vs. Temperature
3.55
606
604
602
600
598
596
594
3.50
3.45
3.40
3.35
3.30
3.25
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. SS Pin Pull-Up Current vs. Temperature
Figure 15. Feedback Voltage vs. Temperature
620
610
5.3
5.2
5.1
5.0
4.9
4.8
4.7
R
= 100kΩ
T
600
590
580
570
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. VREG Voltage vs. Temperature
Figure 13. Frequency vs. Temperature
Rev. 0 | Page 9 of 23
ADP2389/ADP2390
Data Sheet
18.0
17.5
17.0
16.5
16.0
15.5
15.0
30
R
= 59kΩ
ILIM
25
HIGH-SIDE R
DSON
20
15
10
5
LOW-SIDE R
DSON
0
–40
–40
–20
0
20
40
60
80
100
120
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. Peak Current-Limit Threshold vs. Temperature
Figure 17. MOSFET RDSON vs. Temperature
520
510
500
490
480
470
T
V
(AC)
OUT
1
I
L
SW
4
2
B
CH1 10.0mV
CH2 10.0V
M
T
2.00µsA CH2
50.20%
5.40V
–40
–20
0
20
40
60
80
100
120
W
CH4 5.00A Ω
TEMPERATURE (°C)
Figure 18. EA Transconductance vs. Temperature
Figure 21. Continuous Conduction Mode (CCM) Waveform
T
T
V
(AC)
OUT
EN
1
2
V
OUT
1
3
I
L
PGOOD
4
2
SW
I
OUT
4
B
B
B
B
B
CH1 50.0mV
CH2 10.0V
CH4 2.00A Ω
M
T
100µs A CH1
50.20%
–2.00mV
CH1 1.00V
CH3 5.00V
CH2 10.0V
CH4 10.0A Ω
M1.00ms A CH1
50.00%
1.08V
W
W
W
W
W
B
T
W
Figure 19. PFM Mode Waveform (ADP2390)
Figure 22. Soft Start with Full Load
Rev. 0 | Page 10 of 23
Data Sheet
ADP2389/ADP2390
T
T
EN
V
(AC)
OUT
1
2
V
OUT
1
3
4
I
PGOOD
OUT
I
L
4
B
B
B
B
B
CH1 1.00V
CH3 5.00V
CH2 10.0V
CH4 5.00A
M1.00ms A CH3
50.40%
2.90V
CH1 50.0mV
M 200µs
20.00%
A
CH4
4.90A
W
W
W
W
W
B
Ω
T
CH4 5.00A Ω
T
W
Figure 23. Precharged Output
Figure 26. Load Transient Response, IOUT = 2.4 A to 9.6 A
T
T
V
(AC)
OUT
V
(AC)
OUT
1
1
PVIN
SW
I
OUT
3
2
4
B
B
B
B
CH2 10.0V
CH1 50.0mV
M 200µs
20.00%
A
CH4
6.00A
CH1 10.0mV
CH3 5.00V
M1.00ms A CH3
T 20.40%
11.0V
W
W
W
B
CH4 5.00A Ω
T
W
W
Figure 24. Load Transient Response with Fast Transient Enable,
Figure 27. Line Transient Response, VPVIN from 8 V to 14 V, IOUT = 12 A
I
OUT = 2.4 A to 9.6 A
T
T
SW
SW
2
2
V
V
OUT
OUT
1
4
1
I
I
L
L
4
B
B
B
B
B
CH1 1.00V
CH2 10.0V
CH4 10.0A
M1.00ms A CH1
20.20%
1.08V
CH1 1.00V
CH2 10.0V
CH4 10.0A Ω
M10.0ms A CH1
80.20%
1.06V
W
W
B
W
W
W
Ω
T
T
W
Figure 25. Output Short Entry
Figure 28. Output Short Recovery
Rev. 0 | Page 11 of 23
ADP2389/ADP2390
Data Sheet
THEORY OF OPERATION
The ADP2389/ADP2390 are synchronous step-down, dc-to-dc
regulators. These devices use a current-mode control architecture
with an integrated high-side power switch and a low-side synchro-
nous rectifier. The regulators target high performance applications
that require high efficiency and design flexibility.
When the EN pin voltage exceeds 1.2 V (typical), the
ADP2389/ADP2390 are enabled and the internal pull-down
current source at the EN pin decreases to 1 µA, which allows
users to program the PVIN UVLO and hysteresis.
INTERNAL REGULATOR (VREG)
The ADP2389/ADP2390 can operate with an input voltage from
4.5 V to 18 V and can regulate the output voltage to 0.6 V. Addi-
tional features added for design flexibility include programmable
switching frequency, programmable soft start, programmable
current limit, external compensation, precision enable, and a
power-good output.
The on-board regulator provides a stable supply for the internal
circuits. Place a 1 µF, X7R or X5R ceramic capacitor between
the VREG pin and GND. The internal regulator includes a
current-limit circuit to protect the output if the maximum
external load current is exceeded.
BOOTSTRAP CIRCUITRY
CONTROL SCHEME
The ADP2389/ADP2390 include a boot strap regulator to
provide the gate drive voltage for the high-side MOSFET. The
boot strap regulator uses differential sensing to generate a 5 V
bootstrap voltage between the BST pin and the SW pin.
The ADP2389/ADP2390 use a fixed frequency, peak current
mode pulse-width modulation (PWM) control architecture. At
the start of each oscillator cycle, the high-side MOSFET turns
on, adding a positive voltage across the inductor. The current in
the inductor (IL) increases until the current sense signal crosses
the peak inductor current threshold that turns off the high-side
MOSFET and turns on the low-side MOSFET. This action adds a
negative voltage across the inductor, causing the inductor current to
decrease. The low-side MOSFET remains on for the rest of cycle.
Place a 0.1 µF, X7R or X5R ceramic capacitor between the
BST pin and the SW pin.
OSCILLATOR
The switching frequency of the ADP2389/ADP2390 (fSW) is
controlled by the RT pin. A resistor (RT) from the RT pin to
GND can program the switching frequency according to the
following equation:
PFM MODE (ADP2390 ONLY)
The ADP2390 can work in PFM mode during a light load.
When the COMP pin voltage is below the PFM threshold
voltage, the device enters PFM mode. In PFM mode, the device
monitors the FB voltage to regulate the output voltage. Because
the high-side and low-side MOSFETs are turned off, the load
current discharges the output capacitor, causing the output
voltage to drop. When the FB voltage drops below 0.605 V, the
device begins switching and the output voltage increases as the
output capacitor is charged by the inductor current. When the
FB voltage exceeds 0.62 V, the device turns off both the high-side
and low-side MOSFETs until the FB voltage drops to 0.605 V. In
the PFM mode, the output voltage ripple is greater than the
ripple in the PWM mode.
67,000
RT (kΩ) +12
f
SW (kHz) =
A 100 kΩ resistor sets the switching frequency to 600 kHz, and
a 44.2 kΩ resistor sets the switching frequency to 1.2 MHz.
Figure 29 shows the typical relationship between fSW and RT.
2200
2000
1800
1600
1400
1200
1000
800
PRECISION ENABLE/SHUTDOWN
The EN input pin has a precision analog threshold of 1.2 V (typical)
with 100 mV of hysteresis. When the enable pin (EN) voltage
exceeds 1.2 V, the regulator turns on; when it falls below 1.1 V
(typical), the regulator turns off. To force the regulator to start
automatically when input power is applied, connect the EN pin
to PVIN.
600
400
200
0
10
40
70 100 130 160 190 220 250 280 310 340
(kΩ)
R
T
Figure 29. Switching Frequency (fSW) vs. RT
The precision EN pin has an internal pull-down current source
(5 µA) that provides a default turn off when the EN pin is open.
Rev. 0 | Page 12 of 23
Data Sheet
ADP2389/ADP2390
For protection against heavy loads, the ADP2389/ADP2390 use
a hiccup mode for overcurrent protection. When the inductor T
turns off and the low-side MOSFET turns on until the next
cycle. The overcurrent counter increments during this process.
If the overcurrent counter reaches four or the FB pin voltage falls
to 0.2 V after the soft start, the device enters hiccup mode. During
hiccup mode, the high-side MOSFET and the low-side both turn
off. The device remains in this mode for seven soft start times and
then attempts to restart from soft start. If the current-limit fault is
cleared, the device resumes normal operation; otherwise, it
reenters hiccup mode.
SOFT START
The SS pin programs the soft start time. Place a capacitor
between the SS pin and GND; an internal current charges this
capacitor to establish the soft start ramp. Calculate the soft start
time using the following equation:
0.6 V ×CSS
tSS
=
ISS
where:
SS is the soft start capacitance.
SS is the soft start pull-up current (3.4 µA).
C
I
In some cases, the input voltage (PVIN) ramp rate is too slow,
or the output capacitor is too large for the output to reach
regulation during the soft start process, which causes the
regulator to enter hiccup mode. To avoid such cases, use a
resistor divider at the EN pin to program the input voltage
UVLO, or use a longer soft start time.
If the output voltage is precharged before power-up, the ADP2389/
ADP2390 prevent the low-side MOSFET from turning on until
the soft start voltage exceeds the voltage on the FB pin.
FAST TRANSIENT RESPONSE
The ADP2389/ADP2390 use the FTW pin to set the fast transient
response window. Place a resistor (RFTW) between the FTW pin
and GND to program the window. Calculate the window
threshold using the following equation:
OVERVOLTAGE PROTECTION (OVP)
The ADP2389/ADP2390 include an OVP feature that protects
the regulator against an output short to a higher voltage supply
or against a strong load disconnect transient. If the feedback
voltage increases to 0.7 V, the internal high-side MOSFET and
low-side MOSFET turn off until the voltage at FB decreases to
0.63 V. At that time, the ADP2389/ADP2390 resumes normal
operation.
200
( )
RFTW kΩ +1
Window Threshold =
%
If the output voltage is greater than the setting window, the fast
transient response is enabled. The fast transient response
function is disabled if the FTW pin is open and the minimum
window is 1%.
UNDERVOLTAGE LOCKOUT (UVLO)
To avoid false trigger of the fast transient, the window threshold
must be 2× greater than the output ripple.
The undervoltage lockout (UVLO) threshold is 4.2 V with a 0.5 V
hysteresis, which prevents power-on glitches from occurring.
When the VIN voltage rises above 4.2 V, the device enables and
the soft start period initiates. When the VIN voltage drops
below 3.7 V, the device turns off.
POWER GOOD
The power-good (PGOOD) pin is an active high, open-drain
output that requires an external resistor to pull it up to a voltage. A
logic high on the PGOOD pin indicates that the voltage at the
FB pin (and thus the output voltage) is within 10% of the desired
value, and there is a 16 cycle waiting period before PGOOD is
pulled high. A logic low indicates that the voltage at the FB pin
is out of 10% of the desired value, and there is a 16-cycle
waiting period before PGOOD is pulled low.
THERMAL SHUTDOWN
In the event that the ADP2389/ADP2390 junction temperatures
rises above 150°C, the internal thermal shutdown circuit turns
off the regulator for self protection. Extreme junction temperatures
can be the result of high current operation, poor circuit board
thermal design, and/or high ambient temperature. A 25°C
hysteresis is included in the thermal shutdown circuit so that if an
overtemperature event occurs, the ADP2389/ADP2390 does
not return to normal operation until the on-chip temperature
drops below 125°C. Upon recovery, a soft start initiates before
normal operation.
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2389/ADP2390 have a cycle-by-cycle peak current-
limit protection circuit to prevent current runaway. A resistor
(RILIM) from the ILIM pin to GND programs the peak current-
limit threshold according to the following equation:
1000
IOCP (A) =
R
ILIM (kΩ) + 0.5
Rev. 0 | Page 13 of 23
ADP2389/ADP2390
Data Sheet
APPLICATIONS INFORMATION
As a guideline, the inductor ripple current, ΔIL, is typically set
to one third of the maximum load current. Calculate the inductor
value using the following equation:
INPUT CAPACITOR SELECTION
The input decoupling capacitor attenuates high frequency noise
on the input. This capacitor must be a ceramic type in the range
of 10 µF to 47 µF. Place the capacitor close to the PVIN pin. Keep
the loop composed by this input capacitor, high-side MOSFET
and low-side MOSFET as small as possible.
(VIN –VOUT )× D
L =
∆IL × fSW
where:
The voltage rating of the input capacitor must be greater than
the maximum input voltage. The rms current rating of the input
capacitor must be larger than the value calculated from the
following equation:
V
V
IN is the input voltage.
OUT is the output voltage.
D is the duty cycle.
ΔIL is the inductor ripple current.
f
SW is the switching frequency.
ICIN _ RMS = IOUT × D×
where:
1– D
( )
VOUT
D =
VIN
IOUT is the output current.
D is the duty cycle.
The peak inductor current (IPEAK) is calculated using
OUTPUT VOLTAGE SETTING
∆IL
2
IPEAK = IOUT
+
An external resistor divider sets the output voltages of the
ADP2389/ADP2390. Calculate the resistor values using the
following equation:
The saturation current of the inductor must be greater than the
peak inductor current. For the ferrite core inductors with a quick
saturation characteristic, the saturation current rating (ISAT) of the
inductor must be greater than the current-limit threshold of the
switch to prevent the inductor from being saturated.
RTOP
RBOT
VOUT = 0.6× 1+
where :
Calculate the rms current of the inductor (IRMS) from the
following equation:
RTOP is the top feedback resistor.
RBOT is the bottom feedback resistor.
2
∆IL
12
2
IRMS
=
IOUT
+
To limit output voltage accuracy degradation due to FB bias
current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT is less than 30 kΩ.
Shielded ferrite core materials are recommended for low core
loss and low electromagnetic interference (EMI). Table 6 lists
recommended inductors.
Table 5 gives the recommended resistor divider for various
output voltages.
Table 6. Recommended Inductors
Table 5. Resistor Divider for Difference Output Voltage
Value ISAT
IRMS DCR
(A) (mΩ)
VOUT (V)
RTOP
,
1% (kΩ)
RBOT
, 1% (kΩ)
Vendor
Device No.
(µH)
(A)
1.0
1.2
1.5
1.8
2.5
3.3
5.0
10
10
15
20
47.5
10
22
15
10
10
10
15
2.21
3
CoilCraft
XAL7030-102ME
XAL7030-152ME
XAL7030-222ME
1
1.5
2.2
21.8 16.1 4.55
11.9 23.5 7.6
10
32
27
21
18
18
32
24
20
16
13.7
0.64
1.02
1.7
Toko
FDUE1040D-H-R22M 0.22
FDUE1040D-H-R45M 0.45
FDU1040D-H-R68M
0.68
FDUE1040D-H-1R0M 1.0
2.35
FDA1254-H-1R2M
744 333 0022
744 333 0047
744 333 0068
744 333 0082
744 332 0100
744 325 120
1.2
20.2 18.4 2.6
INDUCTOR SELECTION
Würth
Elektronik
0.22
0.47
0.68
0.82
1.0
1.2
1.5
2.2
60
47
38
36
21.5 0.6
The inductor value is determined by the operating frequency,
the input voltage, output voltage, and inductor ripple current.
Using a small inductor leads to a faster transient response; however,
it degrades efficiency due to its larger inductor ripple current.
Using a large inductor value leads to smaller ripple current and
better efficiency but results in a slower transient response.
20
20
20
0.8
1.35
1.35
1.35
1.8
27.5 20
25
27
22
20
18
16
744 333 0150
744 333 0220
2.5
3.7
Rev. 0 | Page 14 of 23
Data Sheet
ADP2389/ADP2390
OUTPUT CAPACITOR SELECTION
PROGRAMMING INPUT VOLTAGE UVLO
The output capacitor selection affects both the output ripple
voltage and the loop dynamics of the regulator.
The ADP2389/ADP2390 have a precision enable input that
programs the UVLO threshold of the input voltage, as shown in
Figure 30.
During a step load transient, for instance, when the load is
suddenly increased, the output capacitor supplies the load until
the control loop ramps up the inductor current. The delay caused
by the control loop causes the output to undershoot. Use the
following equation to calculate the output capacitance required
to satisfy the voltage droop requirement:
PVIN
ADP2389/
ADP2390
R
TOP_EN
EN CMP
EN
K
UV × ∆ISTEP2 × L
VIN −VOUT × ∆VOUT _UV
1.2V
4.8µA
COUT _UV
=
R
BOT_EN
2×
(
)
1.3µA
where:
UV is a factor; the typical setting is KUV = 2.
K
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
Figure 30. Programming the Input Voltage UVLO
Use the following equations to calculate RTOP_EN and RBOT_EN
1.1 V ×VIN _ RISING – 1.2 V ×VIN _ FALLING
:
When a load is suddenly removed from the output and the
energy stored in the inductor rushes into the output capacitor,
the output overshoots. Calculate the output capacitance required to
meet the overshoot requirement using the following equation:
RTOP _ EN
=
1.1 V × 6.1μΑ – 1.2 V ×1μA
where:
KOV × ∆ISTEP2 × L
V
V
IN_RISING is the VIN rising threshold.
IN_FALLING is the VIN falling threshold.
COUT _OV
=
2× VOUT − ∆VOUT _OV −VOUT
1.2 V × RTOP _ EN
RBOT _ EN
=
where:
OV is a factor; the typical setting is KOV = 2.
VIN _ RISING – RTOP _ EN × 6.1μΑ – 1.2 V
K
ΔISTEP is the load step.
ΔVOUT_OV is the allowable overshoot on the output voltage.
COMPENSATION DESIGN
For peak current mode control, the power stage can be simplified
as a voltage controlled current source supplying current to the
output capacitor and load resistor. It is composed of one
domain pole and a zero contributed by the output capacitor
ESR. The control to output transfer function is shown with the
following equations:
The output ripple is determined by the ESR and the value of the
capacitance. Use the following equations to select a capacitor
that can meet the output ripple requirements:
∆IL
COUT _ RIPPLE
=
8× fSW × ∆VOUT _ RIPPLE
s
where ΔVOUT_RIPPLE is the allowable output ripple voltage.
∆VOUT _ RIPPLE
1+
1+
2×π × fZ
VOUT (s)
GVD (s) =
= AVI × R×
VCOMP (s)
RESR
=
s
∆IL
2×π × fP
where RESR is the equivalent series resistance of the output
capacitor in ohms.
where:
G
A
VD is the control to output transfer function.
Select the largest output capacitance given by COUT_UV, COUT_OV
and COUT_RIPPLE to meet both load transient and output ripple
performance.
,
VI = 20 A /V.
R is the load resistance.
fZ is the zero of GVD
.
fP is the domain pole of GVD
.
The selected output capacitor voltage rating must be greater
than the output voltage. The rms current rating of the output
capacitor must be greater than the value calculated using the
following equation:
1
fZ =
2×π × RESR ×COUT
where:
ESR is the equivalent series resistance of the output capacitor.
∆IL
R
C
ICOUT _ RMS
=
12
OUT is the output capacitance.
1
fP =
2×π ×
(
R + RESR × COUT
)
Rev. 0 | Page 15 of 23
ADP2389/ADP2390
Data Sheet
The ADP2389/ADP2390 use a transconductance amplifier for the
error amplifier and to compensate the system. Figure 31 shows
the simplified, peak current mode control, small signal circuit.
The following design guideline shows how to select the
compensation components RC, CC, and CCP for ceramic output
capacitor applications.
V
V
OUT
OUT
1. Determine the cross frequency, fC. Generally, fC is between
fSW/12 and fSW/6.
R
TOP
2. Calculate RC using the following equation:
V
C
R
–
COMP
C
OUT
+
–
A
VI
g
m
2 × π ×VOUT × COUT × fC
RC =
+
R
R
BOT
R
0.6 V × gm × A
C
VI
CP
ESR
C
C
3. Place the compensation zero at the domain pole, fP, and
determine CC by
Figure 31. Simplified Peak Current Mode Control, Small Signal Circuit
(R + RESR )×COUT
CC =
RC
The compensation components, RC and CC, contribute a zero
and the optional CCP and RC contribute an optional pole.
4.
CCP is optional. Use CCP to cancel the zero caused by the
ESR of the output capacitor.
The closed-loop transfer equation is as follows:
RESR ×COUT
RBOT
– gm
CCP
=
TV (s) =
×
×
RC
RBOT + RTOP CC + CCP
1+ RC ×CC × s
RC ×CC ×CCP
×GVD (s)
s × 1+
× s
CC + CP
Rev. 0 | Page 16 of 23
Data Sheet
ADP2389/ADP2390
DESIGN EXAMPLE
This section provides the procedures of selecting the external
components based on the example specifications listed in Table 7.
The schematic of this design example is shown in Figure 32.
Calculate the peak inductor current with the following equation:
∆IL
IPEAK = IOUT
+
2
This results in IPEAK = 13.588 A.
Table 7. Step-Down DC-to-DC Regulator Requirements
Parameter
Specification
12.0 V 10%
1.2 V
12 A
12 mV
Calculate the rms current flowing through the inductor by the
following equation:
Input Voltage
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
2
∆IL
12
2
IRMS
=
IOUT
+
5%, 3 A to 9 A, 2 A/µs
500 kHz
This results in IRMS = 12.035 A.
Switching Frequency
According to the calculated current value, select an inductor
with a minimum rms current rating of 12.035 A and a minimum
saturation current rating of 13.588 A.
OUTPUT VOLTAGE SETTING
Select a 10 kΩ resistor as the top feedback resistor (RTOP) and
calculate the bottom feedback resistor (RBOT) using the
following equation:
However, to protect the inductor from reaching its saturation
point under a current-limit condition, the inductor must be
rated for at least a 20 A saturation current for reliable operation.
0.6
Based on these requirements, select a 0.68 µH inductor, such as
the 7443330068 from Würth Elektronik, which has 1.35 mΩ dc
resistance (DCR) and a 38 A saturation current.
RBOT = RTOP
×
VOUT − 0.6
To set the output voltage to 1.2 V, the resistors values are RTOP
10 kΩ and RBOT = 10 kΩ.
=
OUTPUT CAPACITOR SELECTION
The output capacitor must meet both the output voltage ripple
requirement and load transient response.
FREQUENCY SETTING
Use the following equation to calculate the value of RT:
To meet the output voltage ripple requirement, use the following
equation to calculate the ESR and capacitance value of the
output capacitor:
67,000
RT (kΩ) =
– 12
fSW (kHz)
Thus, when fSW = 500 kHz, the value of RT = 122 kΩ.
Select the standard resistor value of 121 kΩ for RT.
INDUCTOR SELECTION
∆IL
COUT _ RIPPLE
=
8× fSW × ∆VOUT _ RIPPLE
∆VOUT _ RIPPLE
The peak-to-peak inductor ripple current, ∆IL, is set to 33% of
the maximum output current. Use the following equation to
estimate the inductor value:
RESR =
∆IL
This results in COUT_RIPPLE = 66 μF and RESR = 3.78 mΩ.
(
VIN – VOUT
)
× D
To meet the 5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
L =
∆IL × fSW
where:
KOV × ∆ISTEP2 × L
V
V
IN = 12.0 V
OUT = 1.2 V
COUT _OV
=
=
2× VOUT − ∆VOUT _OV −VOUT
D = 10%
∆IL = 4 A
KUV × ∆ISTEP2 × L
COUT _UV
f
SW = 500 kHz
2×
(
VIN −VOUT × ∆VOUT _UV
)
This results in L = 0.54 µH. Select the standard inductor value
of 0.68 µH.
where:
OV = KUV = 2, and are the coefficients for estimation purpose.
K
∆ISTEP = 6 A, and is the load transient step.
∆VOUT_OV = 5% × VOUT and, is the overshoot voltage.
∆VOUT_UV = 5% × VOUT, and is the undershoot voltage.
Calculate the peak-to-peak inductor ripple current using the
following equation:
(
VIN –VOUT × D
)
∆IL =
This results in COUT_OV = 332 µF and COUT_UV = 38 µF.
L× fSW
This results in ∆IL = 3.176 A.
Rev. 0 | Page 17 of 23
ADP2389/ADP2390
Data Sheet
According to the calculations for COUT_RIPPLE, COUT_OV, and
SOFT START TIME PROGRAM
C
OUT_UV, the output capacitance must be greater than 332 µF and
The soft start feature ramps up the output voltage in a controlled
manner, eliminating output voltage overshoot during soft start,
and limiting the inrush current. Set the soft start time to 4 ms.
the ESR of the output capacitor must be less than 3.78 mΩ. It is
recommended that five 100 µF, X5R, 6.3 V ceramic capacitors
be used, such as the GRM32ER60J107ME20 from Murata, with
an ESR of 2 mΩ.
tSS × ISS 4 ms × 3.4 μA
CSS
=
=
= 22.67 nF
0.6 V
0.6 V
COMPENSATION COMPONENTS
Choose a standard component value of CSS = 22 nF.
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this case, fSW is running at 500 kHz;
therefore, set fC to 50 kHz.
INPUT CAPACITOR SELECTION
Place a minimum 10 µF ceramic capacitor near the PVIN pin.
In this application, one 10 µF, X5R, 25 V ceramic capacitor is
recommended.
The 100 µF ceramic output capacitors have a derated value of
62 µF.
2×π ×1.2 V × 5× 62 μF × 50 kHz
RC =
CC =
=19.47 kΩ
0.6 V × 500 μS × 20 A/V
(
0.1 Ω + 0.002 Ω × 5 × 62 μF
)
=1623 pF
19.47 kΩ
0.002 Ω × 5 × 62 μF
19.47 kΩ
CCP
=
= 31.8 pF
Choose the following standard components: RC = 20 kΩ, CC =
1500 pF, and CCP = 33 pF.
SCHEMATIC FOR DESIGN EXAMPLE
C
0.1µF
BST
V
= 12V
VIN
PVIN
EN
BST
SW
IN
V
= 1.2V
OUT
C
C
IN
10µF
25V
L
C
C
C
C
OUT4
PGOOD
OUT1
OUT2
OUT3
OUT5
0.68µH
100µF
6.3V
100µF
6.3V
100µF
6.3V
100µF
6.3V
100µF
6.3V
ADP2389/
ADP2390
R
10kΩ
FTW
TOP
ILIM
RT
FB
R
BOT
COMP
10kΩ
R
VREG
R
20kΩ
T
C
SS
121kΩ
GND PGND
C
C
C
CP
SS
C
22nF 1500pF
33pF
C
VREG
1µF
Figure 32. Schematic for Design Example
Rev. 0 | Page 18 of 23
Data Sheet
ADP2389/ADP2390
EXTERNAL COMPONENTS RECOMMENDATION
Table 8. Recommended External Components for Typical Applications with 10 A Output Current
fSW (kHz)
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
VOUT (V)
L (µH)
0.82
1
1
1.2
1.5
2.2
2.2
0.68
0.82
0.82
1
1
1
COUT (µF)1
680
RTOP (kΩ)
RBOT (kΩ)
RC (kΩ)
21
18
15
18
15
20
10
15
18
12
15
10
12
18
18
21
20
12
20
20
18
18
14
10
12
20
12
18
15
18
22.1
14
9.1
12
CC (pF)
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
680
CCP (pF)
330
270
39
33
22
18
10
330
270
39
300
1
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
15
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
10
10
15
2.21
3
15
10
10
10
15
2.21
15
2.21
3
15
1.2
1.5
1.8
2.5
3.3
5
470
5 × 100
5 × 100
3 × 100
3 × 100
100
1
470
470
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5
5 × 100
4 × 100
2 × 100
2 × 100
4 × 100
3 × 100
3 × 100
2 × 100
100
33
22
18
5
600
12
12
12
12
12
12
5
5
5
5
5
0.47
0.47
0.68
0.82
1
10
15
20
47.5
10
22
10
10
15
27
22
18
12
10
6.8
33
27
22
1.2
100
1
0.47
0.47
0.47
0.47
0.47
0.47
0.47
0.47
0.68
0.13
0.24
0.24
0.24
0.24
0.24
5 × 100
4 × 100
3 × 100
2 × 100
100
1.2
1.5
1.8
2.5
3.3
2.5
3.3
5
20
47.5
10
18
12
10
5
100
1200
12
12
12
5
5
5
5
5
5
100
47
47
2 × 100
2 × 100
2 × 100
100
47
47
47.5
10
22
10
10
15
20
47.5
10
6.8
4.7
3.3
12
12
10
8.2
6.8
4.7
680
680
680
680
680
680
680
680
1
1.2
1.5
1.8
2.5
3.3
10
10
10
15
2.21
1 680 µF: 6.3 V, KEMET T530X687M006ATE010; 470 µF: 6.3 V, KEMET T520X477M006ATE010; 100 µF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 µF: 6.3 V, X5R, Murata
GRM32ER60J476ME20.
Rev. 0 | Page 19 of 23
ADP2389/ADP2390
Data Sheet
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good printed circuit board (PCB) layout is essential for obtaining
the best performance from the ADP2389/ADP2390. Poor PCB
layout can degrade the output regulation, as well as the EMI and
electromagnetic compatibility (EMC) performance. Figure 34
shows an example of a good PCB layout for the ADP2389/
ADP2390. For optimum layout, refer to the following guidelines:
Connect the exposed GND pad of the ADP2389/ADP2390
to a large, external copper ground plane to maximize its power
dissipation capability and minimize junction temperature. In
addition, connect the exposed SW pad to the SW pins of the
ADP2389/ADP2390, using short, wide traces, or connect
the exposed SW pad to a large copper plane of the switching
node for high current flow to reduce thermal resistance.
Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Minimize
the length of the trace that connects the top of the feedback
resistor divider to the output while keeping the trace away
from the high current traces and the switching node to
avoid noise pickup. To reduce noise pickup further, place
an analog ground plane on either side of the FB trace and
ensure that the trace is as short as possible to reduce the
parasitic capacitance pickup.
Use separate analog ground planes and power ground
planes. Connect the ground reference of sensitive analog
circuitry, such as output voltage divider components, to the
analog ground. In addition, connect the ground reference
of power components, such as input and output capacitors,
to power ground. Connect both ground planes to the
exposed GND pad of the ADP2389/ADP2390.
Place the input capacitor, the inductor, and the output
capacitor as close as possible to the IC, and use short traces.
Ensure that the high current loop traces are as short and as
wide as possible. Make the high current path from the input
capacitor through the inductor, the output capacitor, and the
power ground plane back to the input capacitor as short as
possible. To accomplish this, ensure that the input and output
capacitors share a common power ground plane.
VIN
PVIN
EN
BST
SW
V
C
IN
BST
C
IN
V
OUT
L
PGOOD
C
OUT
ADP2389/
ADP2390
R
R
TOP
FTW
In addition, ensure that the high current path from the power
ground plane through the inductor and output capacitor
back to the power ground plane is as short as possible by
tying the PGND pins of the ADP2389/ADP2390 to the
PGND plane as close as possible to the input and output
capacitors.
FB
COMP
SS
ILIM
RT
BOT
VREG
R
C
R
R
R
T
FTW
ILIM
GND PGND
C
CP
C
C
C
C
VREG
SS
NOTES
1. ITEMS IN GRAY INDICATES HIGH CURRENT.
Figure 33. High Current Path in the PCB Circuit
Rev. 0 | Page 20 of 23
Data Sheet
ADP2389/ADP2390
VIA
ANALOG GROUND PLANE
BOTTOM LAYER TRACE
COPPER PLANE
PVIN
R
BOT
SS
COMP
FB
PVIN
GND
INPUT
INPUT
BULK
PVIN
BYPASS
R
TOP
CAPACITOR CAPACITOR
PVIN
BST
VREG
C
C
BST
VREG
GND
SW
SW
SW
SW
PGND
PGND
SW
SW
SW
INDUCTOR
OUTPUT
CAPACITOR
POWER GROUND PLANE
VOUT
Figure 34. Recommended PCB Layout
Rev. 0 | Page 21 of 23
ADP2389/ADP2390
Data Sheet
TYPICAL APPLICATION CIRCUITS
Figure 35 through Figure 37 show some typical application circuits of the ADP2389/ADP2390 for user information.
V
12V
IN
VIN
PVIN
EN
BST
SW
C
0.1µF
BST
V
OUT
3.3V, 12A
C
IN
10µF
25V
L
PGOOD
C
100µF
6.3V
C
100µF
6.3V
C
OUT3
100µF
6.3V
OUT1
OUT2
1.2µH
ADP2390
R
TOP
10kΩ
FTW
FB
COMP
SS
ILIM
RT
R
BOT
2.21kΩ
R
C
R
VREG
T
38.3kΩ
100kΩ
GND PGND
C
10pF
C
22nF
C
C
1500pF
CP
SS
C
VREG
1µF
Figure 35. VIN = 12 V, VOUT = 3.3 V, IOUT = 12 A, fSW = 600 kHz with PFM Mode
V
12V
IN
VIN
PVIN
EN
BST
SW
C
0.1µF
BST
V
OUT
1.2V, 8A
C
IN
10µF
25V
L
1µH
PGOOD
C
330µF
16V
C
OUT2
OUT1
10µF
6.3V
ADP2389
R
TOP
10kΩ
FTW
FB
COMP
SS
ILIM
RT
R
BOT
10kΩ
R
21kΩ
C
VREG
R
R
ILIM
T
82.5kΩ 121kΩ
GND PGND
C
C
C
C
CP
SS
100pF
22nF
2200pF
C
VREG
1µF
Figure 36. VIN = 12 V, VOUT = 1.2 V, IOUT = 8 A, fSW = 500 kHz with Programmable Current Limit
V
12V
IN
VIN
PVIN
EN
BST
SW
C
0.1µF
BST
V
OUT
1.8V, 12A
C
IN
10µF
25V
L
PGOOD
C
100µF
6.3V
C
100µF
6.3V
C
100µF
6.3V
C
OUT4
100µF
6.3V
OUT1
OUT2
OUT3
0.68µH
ADP2389
R
TOP
20kΩ
FTW
FB
COMP
SS
ILIM
RT
R
BOT
10kΩ
R
27kΩ
C
VREG
R
R
FTW
T
78.7kΩ 100kΩ
GND PGND
C
C
C
C
CP
SS
22pF
22nF
1200pF
C
VREG
1µF
Figure 37. VIN = 12 V, VOUT = 1.8 V, IOUT = 12 A, fSW = 600 kHz with Fast Transient
Rev. 0 | Page 22 of 23
Data Sheet
ADP2389/ADP2390
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
3.80
3.70
3.55
0.65
0.65
PIN 1
INDICATOR
PIN 1
INDICATOR
1.777
1.677
1.527
25
24
32
1
0.50
BSC
EXPOSED
PAD
0.425
EXPOSED
PAD
0.45
0.35
0.25
1.725
1.625
1.475
17
8
16
9
BOTTOM VIEW
3.441
3.341
TOP VIEW
0.625
0.984
1.00
0.90
0.80
3.191
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
COPLANARITY
0.08
0.30
0.25
0.20
0.152 REF
SEATING
PLANE
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-19)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Output Voltage Package Description
Package Option
CP-32-19
CP-32-19
ADP2389ACPZ-R7 −40°C to +125°C
ADP2390ACPZ-R7 −40°C to +125°C
ADP2389-EVALZ
Adjustable
Adjustable
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
ADP2390-EVALZ
Evaluation Board
1 Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12192-0-8/15(0)
Rev. 0 | Page 23 of 23
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