ADP3186JRQZ-REEL [ADI]
5-Bit Programmable 2-/3-/4-Phase Synchronous Buck Controller; 5位可编程的双/三/四相位同步降压控制器
| 型号： | ADP3186JRQZ-REEL |
| 厂家： | 
ADI |
| 描述： | 5-Bit Programmable 2-/3-/4-Phase Synchronous Buck Controller |
| 文件： | 总24页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5-Bit Programmable 2-/3-/4-Phase
Synchronous Buck Controller
ADP3186
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VCC
28
RAMPADJ RT
14 13
Selectable 2-, 3-, or 4-phase operation at up to 1 MHz
per phase
ADP3186
1ꢀ worst-case differential sensing error over temperature
Logic-level PWM outputs for interface to external high
power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
UVLO
SHUTDOWN
AND BIAS
11
EN
OSCILLATOR
SET
EN
27
26
CMP
RESET
PWM1
PWM2
19
6
GND
CMP
RESET
CROWBAR
CURRENT
BALANCING
CIRCUIT
2-/3-/4-PHASE
DRIVER LOGIC
CSREF
2.1V
25
24
CMP
RESET
PWM3
PWM4
5-bit digitally programmable 0.8 V to 1.55 V output
Programmable short-circuit protection with programmable
latch-off delay
CMP
RESET
DAC + 300mV
CSREF
CROWBAR
CURRENT
LIMIT
DAC – 300mV
APPLICATIONS
23
22
21
20
SW1
SW2
SW3
SW4
Desktop PC power supplies for
AMD Opteron™ processors
VRM modules
10
DELAY
PWRGD
ILIMIT
15
EN
17
16
18
CSSUM
CSREF
CURRENT
LIMIT
CIRCUIT
GENERAL DESCRIPTION
The ADP3186 is a highly efficient multiphase synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance AMD processors. It uses an internal 5-bit DAC to
read a voltage identification (VID) code directly from the pro-
cessor, which is used to set the output voltage between 0.8 V
and 1.55 V. It uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relation-
ship of the output signals can be programmed to provide 2-, 3-,
or 4-phase operation, allowing the construction of up to four
complementary buck switching stages.
12
DELAY
COMP
CSCOMP
SOFT
START
8
FB
9
PRECISION
REFERENCE
VID
DAC
7
1
2
3
4
5
FBRTN
VID4
VID3
VID2
VID1
VID0
Figure 1.
The ADP3186 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current, so that it is always optimally positioned for a system
transient. The ADP3186 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a power
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
The ADP3186 is specified over the commercial temperature
range of 0°C to 85°C and is available in 28-lead TSSOP and
QSOP packages.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADP3186
TABLE OF CONTENTS
Features .............................................................................................. 1
Setting the Clock Frequency..................................................... 14
Soft Start and Current Limit Latch-Off Delay Times............ 14
Inductor Selection...................................................................... 14
Designing an Inductor............................................................... 15
Selecting a Standard Inductor .............................................. 15
Output Droop Resistance.......................................................... 15
Inductor DCR Temperature Correction ................................. 16
Output Offset.............................................................................. 16
COUT Selection ............................................................................. 17
Power MOSFETs......................................................................... 17
Ramp Resistor Selection............................................................ 18
COMP Pin Ramp ....................................................................... 19
Current Limit Setpoint .............................................................. 19
Feedback Loop Compensation Design.................................... 19
CIN Selection and Input Current di/dt Reduction.................. 20
Tuning Procedure....................................................................... 21
DC Loadline Setting .............................................................. 21
AC Loadline Setting............................................................... 21
Initial Transient Setting......................................................... 22
Layout and Component Placement ......................................... 22
General Recommendations .................................................. 22
Power Circuitry Recommendations .................................... 23
Signal Circuitry Recommendations .................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Specifications..................................................................................... 3
Test Circuits....................................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ........................................................................ 9
Start-Up Sequence........................................................................ 9
Master Clock Frequency.............................................................. 9
Output Voltage Differential Sensing.......................................... 9
Output Current Sensing .............................................................. 9
Active Impedance Control Mode............................................. 10
Current Control Mode and Thermal Balance ........................ 10
Voltage Control Mode................................................................ 10
Soft Start ...................................................................................... 10
Current Limit, Short-Circuit, and Latch-Off Protection ...... 11
Dynamic VID.............................................................................. 11
Power Good Monitoring ........................................................... 12
Output Crowbar ......................................................................... 12
Output Enable and UVLO ........................................................ 12
Application Information................................................................ 14
REVISION HISTORY
3/06—Rev. 0 to Rev. A
Updated ADP3110 to ADP3110A................................. Universal
Changes to Table 1.......................................................................... 3
Added QSOP Package..................................................................24
Updated Ordering Guide.............................................................24
8/04—Revision Sp0: Initial Version
Rev. A | Page 2 of 24
ADP3186
SPECIFICATIONS
VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise specified.1
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIER
Output Voltage Range2
Accuracy
VCOMP
VFB
0.5
3.5
V
0.8 V Output
Referenced to FBRTN,
CSSUM = CSCOMP, Figure 2
TSSOP
QSOP
0.7920
0.7880
0.8080
0.8120
V
V
1.175 V Output
1.55 V Output
Referenced to FBRTN,
CSSUM = CSCOMP, Figure 2
TSSOP
QSOP
Referenced to FBRTN,
1.1633
1.1574
1.1868
1.1926
V
V
CSSUM = CSCOMP, Figure 2
TSSOP
QSOP
1.5345
1.5268
1.5655
1.5733
V
V
Line Regulation
Input Bias Current
FBRTN Current
VCC = 10 V to 14 V
0.05
−15.5
100
500
20
%
ΔVFB
IFB
−13
−17
200
μA
IFBRTN
IO(ERR)
GBW(ERR)
μA
μA
MHz
Output Current
Gain Bandwidth Product
Slew Rate
FB Forced to VOUT – 3%
COMP = FB
CCOMP = 10 pF
25
V/μs
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current, Input Voltage Low
Pull-Up Resistance
Internal Pull-Up Voltage
VID Transition Delay Time2
VIL(VID)
VIH(VID)
IIL(VID)
RVID
0.8
26
V
V
1.5
VID(X) = 0 V
20
μA
kΩ
V
ns
ns
100
2.0
400
400
120
2.4
2.65
VID code change to FB change
VID code change to 11111 to PWM
going low
No CPU Detection Turn-Off Delay
Time2
OSCILLATOR
Frequency Range2
Frequency Variation
fOSC
fPHASE
0.25
155
4
245
MHz
kHz
kHz
kHz
V
kΩ
mV
μA
TA = 25°C, RT = 250 kΩ, 4-phase
TA = 25°C, RT = 115 kΩ, 4-phase
TA = 25°C, RT = 75 kΩ, 4-phase
RT = 100 kΩ to GND
200
400
600
2.0
Output Voltage
VRT
1.9
2.1
500
+50
50
Timing Resistor Value
RAMPADJ Output Voltage
RAMPADJ Input Current Range
VRAMPADJ
IRAMPADJ
RAMPADJ – FB
−50
0
CURRENT SENSE AMPLIFIER
Offset Voltage
VOS(CSA)
CSSUM – CSREF, Figure 3
TSSOP
QSOP
−3
−3.5
−50
+3
+3.5
+50
mV
mV
nA
Input Bias Current
Gain Bandwidth Product
Slew Rate
IBIAS(CSSUM)
GBW(CSA)
10
10
MHz
V/μs
V
CCSCOMP = 10 pF
Input Common-Mode Range
CSSUM and CSREF
0
2.7
Rev. A | Page 3 of 24
ADP3186
Parameter
Symbol
Conditions
Min
−77
0.05
Typ
Max
−83
2.7
Unit
mV
V
Positioning Accuracy
Output Voltage Range
Output Current
Figure 4
−80
ΔVFB
ICSCOMP
500
μA
CURRENT BALANCE CIRCUIT
Common-Mode Range
Input Resistance
VSW(X)CM
RSW(X)
ISW(X)
−600
20
4
+200
40
10
mV
kΩ
μA
%
SW(X) = 0 V
SW(X) = 0 V
SW(X) = 0 V
30
7
Input Current
Input Current Matching
−5
+5
ΔISW(X)
CURRENT LIMIT COMPARATOR
Output Voltage
Normal Mode
Shutdown Mode
VILIMIT(NM)
VILIMIT(SD)
IILIMIT(NM)
EN > 2.0 V, RILIMIT = 250 kΩ
EN < 0.8 V, IILIMIT = −100 μA
EN > 2.0 V, RILIMIT = 250 kΩ
2.9
3
3.1
400
V
mV
Output Current, Normal Mode
Maximum Output Current2
Current Limit Threshold Voltage
Current Limit Setting Ratio
DELAY Normal Mode Voltage
DELAY Overcurrent Threshold
Latch-Off Delay Time
12
μA
μA
mV
mV/μA
V
60
VCL
VCSREF – VCSCOMP, RILIMIT = 250 kΩ
VCL/IILIMIT
105
125
10.4
3
1.8
1.5
145
VDELAY(NM)
VDELAY(OC)
tDELAY
RDELAY = 250 kΩ
RDELAY = 250 kΩ
RDELAY = 250 kΩ, CDELAY = 12 nF
2.9
1.7
3.1
1.9
V
ms
SOFT START
Output Current, Soft Start Mode
Soft Start Delay Time
IDELAY(SS)
tDELAY(SS)
During startup, DELAY < 2.8 V
15
20
1
25
μA
ms
RDELAY = 250 kΩ, CDELAY = 12 nF,
VID code = 011111
ENABLE INPUT
Input Low Voltage
Input High Voltage
Input Current, Input Voltage Low
VIL(EN)
VIH(EN)
IIL(EN)
0.8
+1
V
V
2.0
−1
EN = 0 V
μA
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
OFF_State Leakage Current
Power Good Delay Time
VID Code Changing
VID Code Static
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
Relative to nominal DAC output
Relative to nominal DAC output
IPWRGD(SINK) = 4 mA
−200
200
−300
300
150
−400
400
400
50
mV
mV
mV
μA
VCSREF = VDAC
100
250
200
2.1
μs
ns
V
Crowbar Trip Point
VCROWBAR
tCROWBAR
2.0
300
2.2
500
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
400
mV
Overvoltage to PWM going low
100
250
400
μs
ns
PWM OUTPUTS
Output Low Voltage
Output High Voltage
VOL(PWM)
VOH(PWM)
160
5
500
mV
V
IPWM(SINK) = −400 μA
IPWM(SOURCE) = +400 μA
4.0
SUPPLY
DC Supply Current
UVLO Threshold Voltage
UVLO Hysteresis
5
6.9
0.9
10
7.3
1.1
mA
V
V
VUVLO
VCC rising
6.5
0.7
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 Guaranteed by design or bench characterization, not production tested.
Rev. A | Page 4 of 24
ADP3186
TEST CIRCUITS
ADP3186
1
2
3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VCC
PWM1
PWM2
PWM3
PWM4
SW1
12V
+
1
μ
F
100nF
VID3
VID2
5-BIT CODE
4
VID1
ADP3186
5
6
7
8
VID0
VCC
28
8
12V
CROWBAR
FBRTN
FB
FB
SW2
10kΩ
COMP
CSCOMP
SW3
9
9
COMP
PWRGD
EN
SW4
200kΩ
1kΩ
18
10
GND
200kΩ
CSSUM
CSREF
GND
11
12
13
14
1.25V
CSCOMP
CSSUM
CSREF
ILIMIT
20kΩ
100nF
17
16
19
DELAY
RT
80mV
1.0V
4.7nF
250kΩ
RAMPADJ
250kΩ
Figure 2. Closed-Loop Output Voltage Accuracy
Figure 4. Positioning Voltage
ADP3186
VCC
28
12V
CSCOMP
18
39kΩ
100nF
CSSUM
17
1kΩ
CSREF
16
1.0V
CSCOMP – 1V
GND
V
=
OS
40
19
Figure 3. Current Sense Amplifier, VOS
Rev. A | Page 5 of 24
ADP3186
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified all other
voltages re referenced to GND.
Parameter
Rating
VCC
FBRTN
−0.3 V to +15 V
−0.3 V to +0.3 V
−0.3 V to +5.5 V
VID0 – VID4, EN, DELAY, ILIMIT, CSCOMP,
RT, PWM1–PWM4, COMP, CROWBAR
SW1–SW4
All Other Inputs and Outputs
Storage Temperature
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA)
Lead Temperature
−5 V to +25 V
−0.3 V to VCC + 0.3 V
−65°C to +150°C
0°C to 85°C
125°C
100°C/W
Soldering (10 sec)
Infrared (15 sec)
300°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 24
ADP3186
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VCC
2
VID3
PWM1
PWM2
PWM3
PWM4
SW1
3
VID2
4
VID1
ADP3186
TOP VIEW
(Not to Scale)
5
VID0
6
CROWBAR
FBRTN
FB
7
SW2
8
SW3
9
COMP
PWRGD
EN
SW4
10
11
12
13
14
GND
CSCOMP
CSSUM
CSREF
ILIMIT
DELAY
RT
RAMPADJ
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 5
VID4 to VID0 Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a Logic 1, if
left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8 V to
1.55 V (see Table 4). Leaving all the VID pins open results in the ADP3186 going into No CPU mode, shutting off
its PWM outputs and pulling the PWRGD output low.
6
CROWBAR
Crowbar Output. This logic-level output can be used to control an external device to short the 12 V supply to
ground to protect the CPU from overvoltage, if CSREF exceeds 2.1 V.
7
8
FBRTN
FB
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this
pin and the output voltage sets the no-load offset point.
9
COMP
Error Amplifier Output and Compensation Point.
10
PWRGD
Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating
range.
11
12
EN
DELAY
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
Soft Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time.
13
14
15
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit threshold
of the converter. This pin is actively pulled low when the ADP3186 EN input is low, or when VCC is below its UVLO
threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low.
RAMPADJ
ILIMIT
16
CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the power good and crowbar functions. This pin should be connected to the common point of the
output inductors.
17
18
CSSUM
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope of the
load line and the positioning loop response time.
CSCOMP
19
GND
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23
SW4 to SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
24 to 27
28
PWM4 to
PMW1
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3110A. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the
ADP3186 to operate as a 2-, 3-, or 4-phase controller.
VCC
Supply Voltage for the Device.
Rev. A | Page 7 of 24
ADP3186
TYPICAL PERFORMANCE CHARACTERISTICS
4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
T
= 25°C
A
4-PHASE OPERATION
3
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
50
100
150
200
250
300
OSCILLATOR FREQUENCY (MHz)
R
VALUE (kΩ)
T
Figure 6. Master Clock Frequency vs. RT
Figure 7. Supply Current vs. Oscillator Frequency
Rev. A | Page 8 of 24
ADP3186
THEORY OF OPERATION
The ADP3186 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal VID DAC is designed to interface with AMD
Opteron CPUs. Multiphase operation is important for
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3110A. Because each
phase is monitored independently, operation approaching 100%
duty cycle is possible. Also, more than one output can be on at
the same time for overlapping phases.
producing the high currents and low voltages demanded by
today’s microprocessors. Handling the high currents in a single-
phase converter places high thermal demands on the
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3186 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, then divide the master clock by 3 for the
frequency of the remaining phases. If PWM3 and PWM4 are
grounded, then divide by 2. If all phases are in use, divide by 4.
components in the system such as the inductors and MOSFETs.
The multimode control of the ADP3186 ensures a stable, high
performance topology for
•
•
Balancing currents and thermals between phases
High speed response at the lowest possible switching
frequency and output decoupling
OUTPUT VOLTAGE DIFFERENTIAL SENSING
•
Minimizing thermal switching losses due to lower
frequency operation
The ADP3186 combines differential sensing with a high accuracy
VID DAC and reference and a low offset error amplifier. This
maintains a worst-case specification of 1% differential sensing
error over its full operating output voltage and temperature
range. The output voltage is sensed between the FB and FBRTN
pins. FB should be connected through a resistor to the regula-
tion point, usually the remote sense pin of the microprocessor.
FBRTN should be connected directly to the remote sense
ground point. The internal VID DAC and precision reference
are referenced to FBRTN, which has a minimal current of
100 μA to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.
•
•
•
•
•
Tight loadline regulation and accuracy
High current output for up to 4-phase operation
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
•
Flexibility in operation for tailoring design to low cost or
high performance
START-UP SEQUENCE
OUTPUT CURRENT SENSING
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3186 operates
as a 4-phase PWM controller. Grounding the PWM4 pin
programs 3-phase operation and grounding the PWM3 and
PWM4 pins programs 2-phase operation.
The ADP3186 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
This amplifier can be configured several ways depending on the
objectives of the system:
When the ADP3186 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 675 mV. An internal
comparator checks each pin’s voltage versus a threshold of
300 mV. If the pin is grounded, it is below the threshold and the
phase is disabled. The output resistance of the PWM pin is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pin should not be
less than 25 kΩ to ensure proper operation. PWM1 and PWM2
are disabled during the phase detection interval, which occurs
during the first two clock cycles of the internal oscillator. After
this time, if the PWM output is not grounded, the 5 kΩ resis-
tance is removed and it switches between 0 V and 5 V. If the
PWM output was grounded, it remains off.
•
•
•
Output inductor DCR sensing without a thermistor for
lowest cost
Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor temperature
Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM.
Rev. A | Page 9 of 24
ADP3186
The feedback resistor between CSCOMP and CSSUM sets the
gain of the amplifier and a filter capacitor is placed in parallel
with this resistor. The gain of the amplifier is programmable by
adjusting the feedback resistor to set the load line required by
the microprocessor. The current information is then given as
the difference of CSREF minus CSCOMP. This difference signal
is used internally to offset the VID DAC for voltage positioning
and as a differential input for the current limit comparator.
To increase the current in any given phase, make RSW for that
phase larger (make RSW = 0 for the hottest phase and do not
change during balancing). Increasing RSW to only 500 Ω
substantially increases the phase current. Increase each RSW
value by small amounts to achieve balance, starting with the
coolest phase first.
VOLTAGE CONTROL MODE
A high gain-bandwidth voltage-mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID logic, according to the voltages
listed in Table 4. This voltage is also offset by the droop voltage
for active positioning of the output voltage as a function of
current, commonly known as active voltage positioning. The
output of the amplifier is the COMP pin, which sets the termi-
nation voltage for the internal PWM ramps.
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. Also, the sensing
gain is determined by external resistors so that it can be made
extremely accurate.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output current
at the CSCOMP pin can be scaled to equal the droop impedance
of the regulator times the output current. This droop voltage is
then used to set the input control voltage to the system. The
droop voltage is subtracted from the DAC reference input vol-
tage directly to tell the error amplifier where the output voltage
should be. This differs from previous implementations and allows
enhanced feed-forward response.
The negative input (FB) is tied to the output sense location with
a resistor (RB) and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage is positive with respect to
the VID DAC. The main loop compensation is incorporated
into the feedback network between FB and COMP.
CURRENT CONTROL MODE AND THERMAL
BALANCE
SOFT START
The power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit
latch-off time, as explained in the Current Limit, Short-Circuit,
and Latch-Off Protection section. In UVLO or when EN is a
logic low, the DELAY pin is held at ground. After the UVLO
thresh-hold is reached and EN is a logic high, the DELAY
capacitor is charged with an internal 20 μA current source. The
output voltage follows the ramping voltage on the DELAY pin,
limiting the inrush current. The soft start time depends on the
The ADP3186 has individual inputs for each phase, which are
used for monitoring the current in each phase. This information
is combined with an internal ramp to create a current balancing
feedback system, which has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for positioning
described previously.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply
voltage for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the RAMPADJ
pin determines the slope of the internal PWM ramp. Detailed
information about programming the ramp is given in the
Application Information section.
value of VID DAC and CDLY, with a secondary effect from RDLY
See the Application Information section for details on setting
.
CDLY
.
If EN is taken low or VCC drops below UVLO, the DELAY
capacitor is reset to ground to be ready for another soft start
cycle. Figure 8 shows a typical soft start sequence for
the ADP3186.
External resistors can be placed in series with individual phases
to create, if desired, an intentional current imbalance such as
when one phase may have better cooling and can support higher
currents. Resistors RSW1 through RSW4 (see the typical appli-
cation circuit in Figure 10) can be used for adjusting thermal
balance. It is best to have the ability to add these resistors during
the initial design, so make sure that placeholders are provided in
the layout.
Rev. A | Page 10 of 24
ADP3186
CH1 = CSREF
CH2 = DELAY
CH3 = COMP
CH4 = PGD
The resistor has an impact on the soft start time, because the
current through it adds to the internal 20 μA current source.
During startup when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary, because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage to
the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry.
An inherent per phase current limit protects individual phases,
if one or more phases stops functioning because of a faulty
component. This limit is based on the maximum normal mode
COMP voltage.
Figure 8. Typical Start-Up Waveforms—Channel 1: PWRGD,
Channel 2: CSREF, Channel 3: DELAY, Channel 4: COMP
CURRENT LIMIT, SHORT-CIRCUIT, AND LATCH-
OFF PROTECTION
The ADP3186 compares a programmable current-limit setpoint
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to give a current limit threshold of 10.4 mV/μA. If the
difference in voltage between CSREF and CSCOMP rises above
the current limit threshold, the internal current limit amplifier
controls the internal COMP voltage to maintain the average
output current at the limit.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops below
1.8 V. The current limit latch-off delay time is, therefore, set by the
RC time constant discharging from 3 V to 1.8 V. The Application
Figure 9. Overcurrent Latch-Off Waveforms—Channel 1: CSREF,
Channel 2: DELAY, Channel 3: COMP, Channel 4: Phase 1 Switch Node
DYNAMIC VID
The ADP3186 has the ability to dynamically change the VID
input while the controller is running. This allows the output
voltage to change while the supply is running and supplying
current to the load. This is commonly referred to as VID
on-the-fly (OTF). A VID OTF can occur under either light or
heavy load conditions. The processor signals the controller by
changing the VID inputs in multiple steps from the start code to
the finish code. This change can be positive or negative.
Information section discusses the selection of CDLY and RDLY
.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if short circuit has caused
the output voltage to drop below the PWRGD threshold, a soft
start cycle is initiated.
When a VID input changes state, the ADP3186 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time prevents a false code due to logic skew while the five
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and CROWBAR blanking functions for a
minimum of 100 μs to prevent a false PWRGD or CROWBAR
event. Each VID change resets the internal timer.
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3186, or by pulling the EN pin low
for a short time. To disable the short circuit latch-off function,
the external resistor to ground should be left open, and a high-
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached.
Rev. A | Page 11 of 24
ADP3186
Table 4. VID Codes for the ADP3186
OUTPUT CROWBAR
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Output
No CPU
0.800 V
0.825 V
0.850 V
0.875 V
0.900 V
0.925 V
0.950 V
0.975 V
1.000 V
1.025 V
1.050 V
1.075 V
1.100 V
1.125 V
1.150 V
1.175 V
1.200 V
1.225 V
1.250 V
1.275 V
1.300 V
1.325 V
1.350 V
1.375 V
1.400 V
1.425 V
1.450 V
1.475 V
1.500 V
1.525 V
1.550 V
As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) and the CROWBAR logic output goes high
when the output voltage exceeds the upper crowbar threshold.
This crowbar action stops once the output voltage falls below the
release threshold of approximately 400 mV.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over-
voltage is due to a short in the high-side MOSFET, this action
current-limits the input supply or blows its fuse, protecting the
microprocessor from destruction.
The CROWBAR output can be used to signal an external input
crowbar or other protection circuit.
OUTPUT ENABLE AND UVLO
For the ADP3186 to begin switching, the input supply (VCC) to
the controller must be higher than the UVLO threshold, and
the EN pin must be higher than its logic threshold. If UVLO is
less than the threshold or the EN pin is a logic low, the ADP3186
is disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be connected
OD
to the
pins of the ADP3110A. The ILIMIT being grounded
disables the drivers such that both DRVH and DRVL are
grounded. This feature is important in preventing the discharge
of the output capacitors when the controller is shut off. If the
driver outputs were not disabled, a negative voltage could be
generated during output due to the high current discharge of
the output capacitors through the inductors.
POWER GOOD MONITORING
The power good comparator monitors the output voltage via the
CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified in the
specifications in Table 4 based on the VID voltage setting.
PWRGD goes low if the output voltage is outside this specified
range, if all the VID DAC inputs are high, or whenever the EN
pin is pulled low. PWRGD is blanked during a VID OTF event
for a period of 100 μs to prevent false signals during the time
the output is changing.
Rev. A | Page 12 of 24
ADP3186
L1
1.6μH
2200μF/16V
⋅ 3
NICHICON PW SERIES
V
IN
12V
C6
4.7μF
+
+
+
V
RTN
D1
IN
C5
100nF
1N4148WS
U2
ADP3110A
C1
C2
C3
Q1
NTD60N02
1
2
3
4
BST
DRVH
8
7
6
5
820μF/4V ⋅ 8
L2
OS-CON SP SERIES
600nH/1.6mΩ
IN
SW
PGND
DRVL
12mΩ ESR (EACH)
V
CC(CORE)
0.8V – 1.55V
OD
VCC
+
+
C7
4.7nF
R1
2.2Ω
C4
1μF
V
CC(CORE) RTN
C30
C23
Q2
NTD110N02
C10
D2
10μF ⋅
MLCC
IN
8
C9
4.7μF
1N4148WS
U3
ADP3110A
100nF
SOCKET
Q4
NTD60N02
1
2
3
4
BST DRVH
8
7
6
5
L3
600nH/1.6mΩ
IN
SW
PGND
DRVL
OD
VCC
C11
4.7nF
C8
1μF
R2
2.2Ω
Q5
NTD110N02
C14
4.7μF
D3
C13
100nF
1N4148WS
U4
ADP3110A
Q7
NTD60N02
1
2
3
4
BST DRVH
8
7
6
5
L4
600nH/1.6mΩ
IN
SW
PGND
DRVL
OD
VCC
C15
4.7nF
C12
1μF
R3
2.2Ω
RTH1
100kΩ, 1%
Q8
NTD110N02
D4
1N4148WS
C16
1μF
R4
10Ω
R5
332kΩ
U1
ADP3186
1
2
VCC 28
VID4
27
26
25
24
23
22
21
20
19
18
17
16
15
PWM1
PWM2
PWM3
PWM4
SW1
VID3
3
VID2
4
VID1
5
VID0
CROWBAR
6
CROWBAR
FBRTN
FB
7
SW2
C17
680nF
8
SW3
C19
27pF
R12
9
SW4
COMP
PWRGD
EN
147kΩ
R6
C18
R7
680pF
POWER
GOOD
2.00kΩ
8.45kΩ
R13
147kΩ
10
11
12
13
14
GND
R10
R11
35.7kΩ 73.2kΩ
R14
147kΩ
ENABLE
CSCOMP
CSSUM
CSREF
ILIMIT
DELAY
RT
C21
1.5nF
C22
2.2nF
C20
39nF
R8
390kΩ
R9
RAMPADJ
187kΩ
R15
280kΩ
Figure 10. Typical VR 10.1 Application Circuit
Rev. A | Page 13 of 24
ADP3186
APPLICATION INFORMATION
The design parameters for a typical AMD Opteron CPU
application are as follows:
Alternatively, the value for RT can be calculated using
1
(1)
RT
=
−27 kΩ
•
•
•
•
•
•
Input voltage (VIN) = 12 V
n × fSW × 4.7 pF
VID setting voltage (VVID) = 1.500 V
Duty cycle (D) = 0.125
where 4.7 pF and 27 kΩ are internal IC component values. For
good initial accuracy and frequency stability, a 1% resistor is
recommended.
Maximum static output voltage error (±VSRER) = ±50 mV
Maximum dynamic output voltage error (±VDRER) = ±70 mV
SOFT START AND CURRENT LIMIT LATCH-OFF
DELAY TIMES
Error voltage allowed for controller and ripple (±VRERR) =
±20 mV
Because the soft start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set CDLY for the soft start ramp. This
ramp is generated with a 20 μA internal current source. The
value of RDLY has a second-order impact on the soft start time,
because it sinks part of the current source to ground. However,
as long as RDLY is kept greater than 200 kΩ, this effect is minor.
The value for CDLY can be approximated using
•
•
•
Maximum output current (IO) = 56 A
Maximum output current step (ΔIO) = 24 A
Static output drop resistance (RO) based on
1. No load output voltage set at upper output voltage
limit.
V
ONL = VVID + VSERR – VRERR = 1.530 V
2. Full load output voltage set at lower output voltage
limit.
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VVID
2 × RDLY
tSS
VVID
⎜
CDLY = 20 μA −
×
(2)
V
OFL = VVID – VSERR + VRERR = 1.470 V
3. RO = (VONL – VOFL)/IO = (1.53 V – 1.47 V)/56 A =
where tSS is the desired soft start time. Assuming an RDLY of
1.1 mΩ
390 kΩ and a desired soft start time of 3 ms, CDLY is 36 nF. The
closest standard value for CDLY is 39 nF. Once CDLY is chosen,
•
Dynamic output drop resistance (ROD) based on
RDLY can be calculated for the current limit latch-off time using
1. Output current step to no load with output voltage set
at upper output dynamic voltage limit.
1.96 × tDELAY
RDLY
=
(3)
V
ONLD = VVID + VDERR – VRERR = 1.550 V
2. Output voltage prior to load change (at IOUT = ΔIO).
OL = VONL – (ΔIO × RO) = 1.504 V
OD = (VONLD – VOL)/ΔIO = (1.55 V – 1.504 V)/24 A =
1.9 mΩ
CDLY
If the result for RDLY is less than 200 kΩ, a smaller soft start time
should be considered by recalculating the equation for CDLY, or a
longer latch-off time should be used. RDLY should never be less
than 200 kΩ. In this example, a delay time of 8 ms results in
RDLY equal to 402 kΩ. The closest standard 5% value is 390 kΩ.
V
3.
R
•
•
Number of phases (n) = 3
INDUCTOR SELECTION
Switching frequency per phase (fSW) = 330 kHz
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduction
losses in the MOSFETs, but allows using smaller inductors and,
for a specified peak-to-peak transient deviation, less total output
capacitance. Conversely, a higher inductance means lower
ripple current and reduced conduction losses, but requires
larger inductors and more output capacitance for the same
peak-to-peak transient deviation. In any multiphase converter, a
practical value for the peak-to-peak inductor ripple current is
less than 50% of the maximum dc current in the same inductor.
Equation 4 shows the relationships among the inductance,
oscillator frequency, and peak-to-peak ripple current in the
inductor.
SETTING THE CLOCK FREQUENCY
The ADP3186 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses,
and the sizes of the inductors, and the sizes of the input and
output capacitors. With n = 3 for three phases, a clock
frequency of 990 kHz sets the switching frequency (fSW) of each
phase to 330 kHz, which represents a practical trade-off
between the switching losses and the sizes of the output filter
components. Figure 6 shows that, to achieve an 990 kHz
oscillator frequency, the correct value for RT is 187 kΩ.
Rev. A | Page 14 of 24
ADP3186
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
Many useful magnetics design references are available for
quickly designing a power inductor, such as
•
Magnetic Designer Software
Intusoft (www.intusoft.com)
VVID
×
(
1− D
)
IR
=
(4)
(5)
fSW × L
•
Designing Magnetic Components for High-Frequency DC-
DC Converters, by William T. McLyman, Kg Magnetics,
Inc., ISBN 1883107008
VVID × ROD
×
1−
n × D
L ≥
fSW × VRIPPLE
Selecting a Standard Inductor
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
1.5 V ×1.9 mꢀ × 1−0.375
The following power inductor manufacturers can provide design
consultation and deliver power inductors optimized for high
power applications upon request:
(
)
L ≥
= 540 nH
330 kHz ×10 mV
If the resulting ripple voltage is less than that designed for, the
inductor can be made smaller until the ripple value is met. This
allows optimal transient response and minimum output
decoupling.
•
•
•
•
Coilcraft
(847) 639-6400
www.coilcraft.com
Coiltronics
(561) 752-5000
www.coiltronics.com
The smallest possible inductor should be used to minimize the
number of output capacitors. For this example, choosing a
600 nH inductor is a good starting point and gives a calculated
ripple current of 6.6 A. The inductor should not saturate at the
peak current of 22 A and should be able to handle the sum of
the power dissipation caused by the average current of 18.7 A in
the winding and core loss.
Sumida Corporation
(510) 668-0660
www.sumida.com
Vishay
(402) 563-6866
www.vishay.com
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
can cause excessive power losses, while too small a value can
lead to increased measurement error. A good rule is to have the
DCR be about 1 to 1½ times the droop resistance (RO). The
example uses an inductor with a DCR of 1.6 mΩ.
OUTPUT DROOP RESISTANCE
The design requires that the regulator output voltage measured
at the CPU pins drop when the output current increases. The
specified voltage drop corresponds to the static output droop
resistance (RO).
DESIGNING AN INDUCTOR
Once the inductance and DCR are known, the next step is to
either design an inductor or to find a standard inductor that
comes as close as possible to meeting the overall design goals. It
is also important to have the inductance and DCR tolerance
specified to control the accuracy of the system. 20% inductance
and 8% DCR (at room temperature) are reasonable tolerances
that most manufacturers can meet.
The output current is measured by summing the voltage across
each inductor and passing the signal through a low-pass filter.
This summer filter is the CS amplifier configured with resistors
RPH(X) (summers), and RCS and CCS (filter). The output resistance
of the regulator is set by the following equations, where RL is the
DCR of the output inductors:
RCS
The first decision in designing the inductor is to choose the
core material. Several possibilities for providing low core loss at
high frequencies include the powder cores (for example,
Kool-Mμ® from Magnetics, Inc. or from Micrometals) and the
gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips).
Low frequency powdered iron cores should be avoided due to
their high core loss, especially when the inductor value is
relatively low and the ripple current is high.
RO
=
× RL
(6)
(7)
RPH x
(
)
L
CCS
=
RL × RCS
One has the flexibility of choosing either RCS or RPH(X). It is best
to select RCS equal to 100 kΩ, and then solve for RPH(X) by
rearranging Equation 6:
The best choice for a core geometry is a closed-loop type such
as a potentiometer core, PQ, U, E core, or toroid. A good
compromise between price and performance is a core with a
toroidal shape.
Rev. A | Page 15 of 24
ADP3186
RL
RO
2. Based on the type of NTC, find its relative resistance value
at two temperatures. The temperatures that work well are
50°C and 90°C. These resistance values are called A
(RTH(50°C)/RTH(25°C)) and B (RTH(90°C)/RTH(25°C)). Note that the
NTC’s relative value is always 1 at 25°C.
RPH
=
× RCS
(
x
)
1.6 mꢀ
1.1 mꢀ
RPH
=
×100 kꢀ = 145.5 kꢀ
(
x
)
3. Find the relative value of RCS required for each of these
temperatures. This is based on the percentage change
needed, which in this example is initially 0.39%/°C. These
are called r1 (1/(1 + TC × (T1 − 25))) and r2 (1/(1 + TC ×
(T2 − 25))), where TC = 0.0039 for copper. T1 = 50°C and
T2 = 90°C are chosen. From this, one can calculate that
r1 = 0.9112 and r2 = 0.7978.
Next, use Equation 6 to solve for CCS.
600 nH
CCS
=
= 3.75 nF
1.6 mꢀ ×100 kꢀ
It is best to have a dual location for CCS in the layout, so that
standard values can be used in parallel to get as close as possible
to the value desired. For best accuracy, CCS should be a 5% or
10% NPO capacitor. This example uses a 5% combination for
CCS of 1.5 nF and 2.2 nF in parallel. Recalculating RPH(X) using
this capacitor combination yields a 1% value of 147 kΩ.
4. Compute the relative values for RCS1, RCS2, and RTH using
(
A − B
)
× r × r2 − A ×
(
1− B
(
)
× r2 + B ×
× r2 −
(
1− A
)
× r
1
)
1
rCS2
=
=
A ×
(1− B
)
× r1 − B × 1− A
)
(
A − B
INDUCTOR DCR TEMPERATURE CORRECTION
(
1− A
)
When the inductor’s DCR is used as the sense element and
copper wire is the source of the DCR, one needs to compensate
for temperature changes of the inductor’s winding. Fortunately,
copper has a well-known temperature coefficient (TC) of
0.39%/°C.
rCS1
1
A
−
1−rCS2 r1 −rCS2
1
rTH
=
(8)
1
1
−
If RCS is designed to have an opposite and equal percentage
change in resistance to that of the wire, it cancels the tempera-
ture variation of the inductor’s DCR. Due to the nonlinear
nature of NTC thermistors, resistors RCS1 and RCS2 are needed.
See Figure 11 to linearize the NTC and produce the desired
temperature tracking.
1− rCS2 rCS1
5. Calculate RTH = rTH × RCS, then select the closest value of
thermistor available. Also compute a scaling factor k based
on the ratio of the actual thermistor value used relative to
the computed one:
RTH
(
ACTUAL
RTH
(
CALCULATED
)
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
k =
(9)
TO
SWITCH
NODES
TO
OR LOW-SIDE MOSFET
)
V
OUT
SENSE
R
TH
6. Calculate values for RCS1 and RCS2 using Equation 10:
RCS1 = RCS × k × rCS1
R
R
R
PH3
PH1
PH2
ADP3186
R
R
CS2
CSCOMP
CS1
RCS2 = RCS
×
1− k
)
+
k × rCS2
(10)
18
17
16
C
C
CS2
CS1
KEEP THIS PATH
CSSUM
CSREF
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES
For this example, RCS has been calculated to be 100 kΩ, so
start with a thermistor value of 100 kΩ. Looking through
available 0603 size thermistors, one finds a Vishay
NTHS0603N01N1003JR NTC thermistor with A = 0.3602
and B = 0.09174. From these, one can compute rCS1
=
Figure 11. Temperature Compensation Circuit Values
0.3796, rCS2 = 0.7195, and rTH = 1.0751. Solving for RTH
yields 107.51 kΩ, so 100 kΩ is chosen, making k = 0.9302.
Finally, one finds that RCS1 and RCS2 are 35.3 kΩ and
73.9 kΩ. Choosing the closest 1% resistor values yields a
choice of 35.7 kΩ and 73.2 kΩ.
The following procedure and expressions yield values to use for
RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given RCS
value:
1. Select an NTC based on type and value. Because the value
has not yet been found, start with a thermistor with a value
close to RCS. The NTC should also have an initial tolerance
of better than 5%.
OUTPUT OFFSET
The AMD specification requires that at no load the nominal
output voltage of the regulator be offset to a value higher than
the nominal voltage corresponding to the VID code.
Rev. A | Page 16 of 24
ADP3186
The offset is set by a constant current source flowing into of the
FB pin (IFB) and flowing through RB. The value of RB can be
found using Equation 11:
This example uses a combination of MLC capacitors (CZ =
80 μF). The VID on-the-fly step change is from 1.5 V to 0.8 V
(making VV = 700 mV) in 100 μs with a setting error of 3%.
Solving for the bulk capacitance yields
VONL −VVID
RB
RB
=
=
IFB
⎛
⎜
⎜
⎝
⎞
⎟
⎠
600 nH ×24 A
⎟
Cx
≤
MIN
)
−80 ꢁF =1.6 mF
(
3 ×1.9 mꢀ×1.5 V
1.53 V−1.5 V
= 2.00 kꢀ
(11)
600 nH × 700 mV
3 × 3.52 ×1.1mΩ ×1.5 V
15 ꢁA
Cx
≤
MAX )
×
(
The closest standard 1% resistor value is 2 kΩ.
2
⎛
⎜
⎞
COUT SELECTION
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
100 ꢁs ×1.5 V × 3 × 3.5 ×1.1 mꢀ
700 mV × 600 nH
⎟
1+
−1 −80 μF = 20.4 mF
⎜
⎟
The required output decoupling for the regulator is typically
⎜
⎟
⎝
⎠
recommended by AMD for various processors and platforms.
One can also use some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.
where k = 3.5.
Using eight 820 μF OS-CON capacitors with a typical ESR of
12 mΩ each yields CX = 6.56 mF with an RX = 1.5 mΩ.
First select the total amount of ceramic capacitance. This is
based on the number and type of capacitor to be used. The best
location for ceramics is inside the socket. Others can be placed
along the outer edge of the socket as well.
One last check should be made to ensure that the ESL of the
bulk capacitors (LX) is low enough to limit the high frequency
ringing during a load change. This is tested using
Combined ceramic values of 30 μF to 100 μF are recommended,
usually made up of multiple 10 μF or 22 μF capacitors. Select the
number of ceramics and find the total ceramic capacitance (CZ).
Lx ≤ Q2 ×Cz × ROD
2
(14)
2
Lx ≤ 2× 80 ꢁF ×
(
1.9 mꢀ
)
= 580 pH
Next, there is an upper limit imposed on the total amount of
bulk capacitance (CX) when one considers the VID on-the-fly
voltage stepping of the output (voltage step VV in time tV with
error of VERR). A lower limit is based on meeting the capacitance
for load release for a given maximum load step ∆IO and a maxi-
mum allowable overshoot. The total amount of load release
voltage is given as ΔVO = ΔIO × ROD.
where Q is limited to the square root of 2 to ensure a critically
damped system. In this example, LX is approximately 500 pH for
the eight OS-CON capacitors, which satisfies this limitation. If
the LX of the chosen bulk capacitor bank is too large, the number
of ceramic capacitors might need to be increased, if there is
excessive ringing.
One should note that for this multimode control technique,
all ceramic designs can be used as long as the conditions of
Equations 11, 12, and 13 are satisfied.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
L × ꢂIO
Cx
Cx
≥
≤
−Cz
(12)
(
MIN
)
n × ROD ×VVID
POWER MOSFETS
(
MAX
)
2
For this example, the N channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive
voltage (the supply voltage to the ADP3110A) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH)
< 2.5 V) are recommended.
⎛
⎞
⎛
⎜
⎝
⎞
⎟
⎟
⎠
⎜
⎟
L
VV
VVID
VVID nKRO
(13)
⎜
×
×
1+ tv ×
×
−1 − C
⎜
⎜
⎝
⎟
Z
nK 2RO2
VV
L
⎟
⎠
⎛
⎞
⎟
⎟
⎠
VERR
VV
⎜
⎜
⎝
where K = l n
To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (RX) should be less
than or equal to the dynamic droop resistance (ROD). If the
The maximum output current (IO) determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. With
the ADP3186, currents are balanced between phases, therefore
the current in each low-side MOSFET is the output current
divided by the total number of MOSFETs (nSF).
C
X(MIN) is larger than CX(MAX), the system cannot meet the VID
on-the-fly specification and might require the use of a smaller
inductor or more phases (and might have to increase the
switching frequency to keep the output ripple the same).
Rev. A | Page 17 of 24
ADP3186
With conduction losses being dominant, the following
expression shows the total power being dissipated in each
synchronous MOSFET in terms of the ripple current per phase
(IR) and average total output current (IO):
It is interesting to note that adding more main MOSFETs (nMF)
does not help the switching loss per MOSFET, because the
additional gate capacitance slows switching. The best way to
reduce switching loss is to use lower gate capacitance devices.
2
2
The conduction loss of the main MOSFET is given by the
following equation, where RDS(MF) is the on resistance of the
MOSFET:
⎡
⎤
n I
⎞
R
⎛
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
IO
nSF
1
12
⎢⎜
⎟ ⎥
×RDS
PSF
=
(1− D
)
×
+
×
(15)
)
(
SF
⎜
⎟
nSF
⎠
⎢
⎥
⎝
⎣
⎦
2
2
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, one can find the
required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to
an ambient temperature of 50°C, a safe limit for PSF is 1 W to
1.5 W at 120°C junction temperature. Thus, for this example
(56 A maximum), RDS(SF) < 4.8 mΩ. This RDS(SF) is also at a
junction temperature of about 120°C, so one needs to make sure
to account for this when making this selection. This example
uses one low-side MOSFET at 4.8 mΩ at 120°C.
⎡
⎤
n × I
⎞
R
⎛
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
IO
nMF
1
12
⎢⎜
⎟ ⎥
×RDS
PC
= D ×
+
×
(17)
MF
)
(
MF
)
(
⎜
⎟
nMF
⎠
⎢
⎥
⎝
⎣
⎦
Typically, for main MOSFETs, the highest speed (low CISS)
device is preferred, but these usually have higher on resistance.
Select a device that meets the total power dissipation (about
1.5 W for a single D-PAK) when combining the switching and
conduction losses.
For this example, an NTD60N02 was selected as the main
MOSFET (three total; nMF = 3), with a CISS = 948 pF (max), and
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input needs to be small (less than 10% is recom-
mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.
R
DS(MF) = 11.2 mΩ (max at TJ = 120°C), and an NTD110N02 was
selected as the synchronous MOSFET (three total; nSF = 3), with
ISS = 2710 pF (max), and RDS(SF) = 4.8 mΩ (max at TJ = 120°C).
C
The synchronous MOSFET CISS is less than 6000 pF, satisfying
that requirement. Solving for the power dissipation per MOSFET
at IO = 56 A and IR = 6.6 A yields 913 mW for each synchronous
MOSFET and 1.48 W for each main MOSFET.
Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3110A). The output impedance of the
driver is approximately 2 Ω, and the typical MOSFET input gate
resistances are about 1 Ω to 2 Ω, so a total gate capacitance of
less than 6000 pF should be adhered to. Because there is one
MOSFET, the input capacitance for the synchronous MOSFET
should be limited to 6000 pF.
One last issue to consider is the power dissipation in the driver
for each phase. This is best described in terms of the QG for the
MOSFETs and is given by the following equation, where QGMF is
the total gate charge for each main MOSFET and QGSF is the
total gate charge for each synchronous MOSFET:
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it
takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the switching
speed on the rise and fall time of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET,
where nMF is the total number of main MOSFETs:
⎡
⎢
⎤
fSW
2 × n
PDRV
=
×
(
nMF × QGMF +nSF × QGSF
)
+ ICC ×V
⎥
CC
⎢
⎣
⎥
⎦
(18)
Also shown is the standby dissipation factor (ICC × VCC) for the
driver. For the ADP3110A, the maximum dissipation should be
less than 400 mW. In this example, with ICC = 7 mA, QGMF
16 nC, and QGSF = 48 nC, one finds 211 mW in each driver,
which is below the 400 mW dissipation limit. See the
ADP3110A data sheet for more details.
=
VCC × IO
nMF
n
PS
= 2 × fSW
MF )
×
× RG
×
× CISS
(16)
(
nMF
RAMP RESISTOR SELECTION
where:
The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used for determining the
optimum value:
RG is the total gate resistance (2 Ω for the ADP3110A and about
1 Ω for typical high speed switching MOSFETs, making
RG = 3 Ω).
CISS is the input capacitance of the main MOSFET.
Rev. A | Page 18 of 24
ADP3186
AR × L
In this example, choosing a peak current limit of 100 A for ILIM
results in RLIM = 284 kΩ, for which 280 kΩ is chosen as the
nearest 1% value.
RR
RR
=
=
3 × AD × RDS × CR
(19)
0.2 × 600 nH
The per-phase current limit described in the Current Limit,
Short-Circuit, and Latch-Off Protection section is determined
by
= 333 kꢀ
3 × 5 × 4.8 mꢀ × 5 pF
where:
VCOMP
) −VRT −VBIAS
MAX
IR
2
(
IPHLIM
≅
−
(23)
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
AD × RDS
(
MAX)
R
DS is the total low-side MOSFET on resistance.
For the ADP3186, the maximum COMP voltage (VCOMP(MAX)) is
3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the
current balancing amplifier gain (AD) is 5. Using VR of 560 mV
and RDS(MAX) of 4.8 mΩ (low-side on resistance at 150°C), one
finds a per-phase peak current limit of 61 A. Although this
number may seem high, this current level can be reached only
with an absolute short at the output, and the current limit latch-
off function shuts down the regulator before overheating can
occur.
CR is the internal ramp capacitor value.
The closest standard 1% resistor value is 332 kΩ.
The internal ramp voltage magnitude can be calculated by using
AR
×
(
1− D
)
×VVID
VR
VR
=
=
RR × CR × fSW
(20)
0.2 ×
1−0.125 ×1.5V
( )
= 480 mV
This limit can be adjusted by changing the ramp voltage (VR),
but make sure not to set the per-phase limit lower than the
average per-phase current (ILIM/n).
332 kꢀ × 5 pF × 330 kHz
The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response improve, but
thermal balance degrades. Likewise, if the ramp is made
smaller, thermal balance improves at the sacrifice of transient
response and stability. The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.
The per-phase initial duty cycle limit is determined by
VCOMP
) −VBIAS
(
MAX
(24)
DMAX = D ×
VRT
In this example, the maximum duty cycle is 0.47.
FEEDBACK LOOP COMPENSATION DESIGN
COMP PIN RAMP
Optimized compensation of the ADP3186 allows the best
A ramp signal on the COMP pin is due to the droop voltage and
output voltage ramps. This ramp amplitude adds to the internal
ramp to produce the following overall ramp signal at the PWM
input:
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resis-
tances (RO and ROD). With the resistive output impedance, the
output voltage droops in proportion to the load current at any
load current slew rate. This ensures optimal positioning and
helps to minimize the output decoupling.
VR
VRT
=
(21)
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
(
RO + ROD
)
×
(
1−n × D
)
1−
n × fSW × CX × RO ×ROD
In this example, the overall ramp signal is 560 mV.
With the multimode feedback structure of the ADP3186, the
feedback compensation must be set so that the converter’s
output impedance works in parallel with the output decoupling
to meet this goal. Several poles and zeros created by the output
inductor and decoupling capacitors (output filter) need to be
compensated for.
CURRENT LIMIT SETPOINT
To select the current limit setpoint, first find the resistor value
for RLIM. The current limit threshold for the ADP3186 is set
with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/μA
(ALIM). RLIM can be found using
ALIM × VLIM
ILIM × RO
A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. Equations 25 to 29
are intended to yield an optimal starting point for the design;
some adjustments might be necessary to account for PCB and
component parasitic effects.
RLIM
=
(22)
For values of RLIM greater than 500 kΩ, the current limit might
be lower than expected, so some adjustment of RLIM might be
needed. Here, ILIM is the average current limit for the output of the
supply.
Rev. A | Page 19 of 24
ADP3186
The first step is to compute the time constants for all the poles and zeros in the system:
RL ×VRT (RO + ROD )×L×(1−n×D)×VRT
Re = n×ROD + AD ×RDS
+
+
VVID
n×CX ×RO ×ROD ×VVID
1.6 mꢀ × 0.56 V
1.1mꢀ+1.9 mꢀ
× 600 nH ×
1 − 0.375 × 0.56 V
(25)
Re = 3 ×1.9 mꢀ + 5 × 4.8 mꢀ +
+
= 40.5 mꢀ
1.5 V
3 × 6.56 mF ×1.1mꢀ × 1.9 mꢀ × 1.5 V
500 pH 1.9 mꢀ − 0.6 mꢀ
ROD − R'
LX
ROD
(
ROD − R'
)
+
×
= 6.56 mF ×
(
1.9 mꢀ − 0.6 mꢀ
)
+
×
= 8.76 ꢁs
(26)
(27)
Ta = CX
×
RX
1.9 mꢀ
1.5mꢀ
Tb =
RX + R'− ROD
× CX
=
1.5 mꢀ +0.6 mꢀ −1.9 mꢀ
× 6.56 mF =1.31μs
⎛
⎞
⎟
⎟
⎠
⎛
⎞
⎟
⎟
⎠
AD × RDS
2 × fSW
5 × 4.8 mꢀ
2 × 330 kHz
⎜
⎜
VRT × L −
0.56 V × 600 nH−
⎜
⎜
⎝
⎝
Tc =
Td =
=
= 5.2 ꢁs
(28)
(29)
VVID × Re
1.5 V × 40.5 mꢀ
2
CX × CZ × RO2 D
6.56 mF × 80 ꢁF ×
1.9 mꢀ
)
=
= 218 ns
CX
×
(
ROD − R' +CZ × ROD 6.56 mF ×
)
(
1.9 mꢀ − 0.6 mꢀ
)
+80 ꢁF ×1.9 mꢀ
where, for the ADP3186, R' is the PCB resistance from the bulk
capacitors to the ceramics and where RDS is the total low-side
MOSFET on resistance per phase. In this example, AD is 5, VRT
equals 0.56 V, R' is approximately 0.6 mΩ (assuming a 4-layer,
1 oz motherboard), and LX is 500 pH for the eight OS-CON
capacitors.
CIN SELECTION AND INPUT CURRENT di/dt
REDUCTION
In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude of 1 nth the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor, sized for the maximum rms current,
must be used. The maximum rms capacitor current is given by
The compensation values can then be solved using
n × ROD ×Ta
CA
=
1
Re × RB
ICrms = D × IO
×
−1
N × D
(30)
(34)
1
3×1.9 mꢀ × 8.76 ꢁs
40.5mꢀ × 2 kꢀ
ICrms = 0.125 × 56 A ×
−1 = 9.05 A
CA
RA
CB
=
=
=
= 616 pF
3 × 0.125
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2,000 hours of life. This makes it advisable
to further derate the capacitor or to choose a capacitor rated at a
higher temperature than required. Several capacitors can be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 2,200 μF, 16 V aluminum electrolytic capacitors with a
ripple rating of 3.5 A each.
5.2 ꢁs
Tc
=
= 8.44 kꢀ
(31)
(32)
(33)
CA 616 pF
1.31μs
Tb
RB
=
655 pF
2 kꢀ
Td
218 ns
CFB
=
=
= 25.8 pF
RA 8.44 kꢀ
To reduce the input current di/dt to a level below the recom-
mended maximum of 0.1 A/μs, an additional small inductor
(L > 1 μH @ 15 A) should be inserted between the converter
and the supply bus. That inductor also acts as a filter between
the converter and the primary power source.
These are the starting values prior to tuning the design to
account for layout and other parasitic effects (see the Tuning
Procedure section). The final values selected after tuning are
CA = 680 pF
RA = 8.45 kΩ
DB = 860 pF
CFB = 27 pF
Rev. A | Page 20 of 24
ADP3186
TUNING PROCEDURE
AC Loadline Setting
To tune the AD3186, follow these steps:
11. Remove the dc load from the circuit and hook up the
dynamic load.
1. Build a circuit based on the compensation values
computed from the design spreadsheet.
12. Hook up the scope to the output voltage and set it to
dc coupling with the time scale at 100 μs/div.
2. Hook up the dc load to circuit, turn it on, and verify its
operation. Also check for jitter at no-load and full-load.
13. Set the dynamic load for a transient step of about 24 A
at 1 kHz with 50% duty cycle.
DC Loadline Setting
14. Measure the output waveform (you might have to use
dc offset on scope to see the waveform). Try to use a
vertical scale of 100 mV/div or finer. This waveform
should look similar to Figure 12.
3. Measure the output voltage at no-load (VNL). Verify that it
is within tolerance.
4. Measure the output voltage at full-load cold (VFLCOLD). Let
the board sit for ~10 minutes at full-load, and then measure
the output (VFLHOT). If there is a change of more than a few
mV, adjust RCS1 and RCS2 using Equations 35 and 37.
15. Use the horizontal cursors to measure VACDRP and
VDCDRP as shown. Do not measure the undershoot or
overshoot that happens immediately after the step.
V
V
NL −VFLCOLD
NL −VFLHOT
(35)
RCS2
= RCS2
×
OLD
)
(
NEW
)
(
16. If VACDRP and VDCDRP are different by more than a few
mV, use Equation 38 to adjust CCS. You might need to
parallel different values to get the right one, because
the standard capacitor values available are limited. It is
a good idea to have locations for two capacitors in the
layout for this.
5. Repeat Step 4 until the cold and hot voltage measurements
remain the same.
6. Measure the output voltage from no-load to full-load using
5 A steps. Compute the loadline slope for each change, and
then average them to determine the overall loadline slope
(ROMEAS).
VACDRP
VDCDRP
(38)
CCS
= CCS
×
OLD
)
(
NEW
)
(
7. If ROMEAS is off from RO by more than 0.05 mΩ, use the
following to adjust the RPH values:
17. Repeat Steps 11 to 13 and repeat the adjustments, if
necessary. Once complete, do not change CCS for the
remainder of the procedure.
ROMEAS
RO
(36)
RPH
= RPH
×
OLD
)
(
NEW
)
(
18. Set the dynamic load step to the maximum step size
(do not use a step size larger than needed) and verify
that the output waveform is square, which means that
VACDRP and VDCDRP are equal.
8. Repeat Steps 6 and 7 to check the loadline, and repeat
adjustments, if necessary.
9. Once dc loadline adjustment is complete, do not change
RPH, RCS1, RCS2, or RTH for the remainder of the procedure.
10. Measure the output ripple at no-load and full-load with a
scope, and make sure that it is within specifications.
V
ACDRP
V
DCDRP
Figure 12. AC Loadline Waveform
1
RCS1
=
NEW
)
(37)
(
RCS1
) + RTH
1
(
OLD
(25°C
)
−
RCS1
) × RTH
+
(
RCS1
) − RCS2
)
×
(
RCS1
) − RTH
)
RTH
(OLD
(
25°C
)
(
OLD
(
NEW
)
(OLD
(
25°C
)
(25°C
)
Rev. A | Page 21 of 24
ADP3186
Because the ADP3186 turns off all the phases (switches inductors
to ground), there is no ripple voltage present during load release.
Therefore, you do not have to add headroom for ripple,
allowing your load release VTRANREL to be larger than VTRAN1 by the
amount of ripple, and still meet specifications.
Initial Transient Setting
19. With the dynamic load still set at the maximum step size,
expand the scope time scale to see 2 μs/div to 5 μs/div. The
waveform may have two overshoots and one minor under-
shoot (see Figure 13). Here, VDROOP is the final desired value.
If VTRAN1 and VTRANREL are less than the desired final droop, this
implies that capacitors can be removed. When removing capaci-
tors, check the output ripple voltage as well to make sure that it
is still within specifications.
V
DROOP
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
V
TRAN1
For good results, a PCB with at least four layers is recommended.
This provides the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input, and output power, and wide interconnection
traces in the remainder of the power delivery current paths.
Keep in mind that each square unit of 1 oz copper trace
has a resistance of ~0.53 mΩ at room temperature.
V
TRAN2
Figure 13. Transient Setting Waveform
20. If both overshoots are larger than desired, try making
the following adjustments. Note that, if these adjust-
ments do not change the response, you are limited by
the output decoupling. Check the output response
each time you make a change as well as the switching
nodes to make sure that the response is still stable.
Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths, so that the resistance and inductance introduced by
these current paths is minimized and the via current rating is
not exceeded.
21. Make the ramp resistor larger by 25% (RRAMP).
22. For VTRAN1, increase CB or increase the switching
frequency.
If critical signal lines (including the output voltage sense lines of
the ADP3186) must cross through power circuitry, it is best if a
signal ground plane can be interposed between those signal lines
and the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of
making signal ground a bit noisier.
23. For VTRAN2, increase RA and decrease CA by 25%.
24. For load release (see Figure 14), if VTRANREL is larger
than VTRAN1 (see Figure 13), there is not enough output
capacitance. You need more capacitance or you have
to make the inductor values smaller. (If you change
inductors, you need to start the design again using the
spreadsheet and this tuning procedure.)
An analog ground plane should be used around and under the
ADP3186 as a reference for the components associated with the
controller. This plane should be tied to the nearest output
decoupling capacitor ground and should not be tied to any other
power circuitry to prevent power currents from flowing in it.
The components around the ADP3186 should be located close
to the controller with short traces. The most important traces to
keep short and away from other traces are the FB and CSSUM
pins. The output capacitors should be connected as close as
possible to the load (or connector), for example, a micropro-
cessor core, that receives the power. If the load is distributed,
the capacitors should also be distributed and generally be in
proportion to where the load tends to be more dynamic.
V
TRANREL
V
DROOP
Avoid crossing any signal lines over the switching power path
loop, described in the Power Circuitry Recommendations
section.
Figure 14. Transient Setting Waveform
Rev. A | Page 22 of 24
ADP3186
Power Circuitry Recommendations
Make a mirror image of any pad being used to heat sink the
MOSFETs on the opposite side of the PCB to achieve the best
thermal dissipation to the air around the board. To further
improve thermal performance, use the largest possible pad area.
The switching power path should be routed on the PCB to
encompass the shortest possible length to minimize radiated
switching noise energy (EMI) and conduction losses in the
board. Failure to take proper precautions often results in EMI
problems for the entire PC system as well as noise-related
operational problems in the power converter control circuitry.
The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.
The switching power path is the loop formed by the current
path through the input capacitors and the power MOSFETs
including all interconnecting PCB traces and planes. Using
short and wide interconnection traces is especially critical in
this path for two reasons: it minimizes the inductance in the
switching loop, which can cause high energy ringing, and it
accommodates the high current demand with minimal
voltage loss.
For best EMI containment, a solid power ground plane should
be used as one of the inner layers extending fully under all the
power components.
Signal Circuitry Recommendations
The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connect to the signal ground at the
load. To avoid differential mode noise pickup in the sensed
signal, the loop area should be small. Therefore, the FB and
FBRTN traces should be routed adjacent to each other on top of
the power ground plane back to the controller.
Whenever a power dissipating component, for example, a
power MOSFET, is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately surround-
ing it, is recommended. Two important reasons for this are
improved current rating through the vias and improved thermal
performance from vias extended to the opposite side of the
PCB, where a plane can more readily transfer the heat to the air.
The feedback traces from the switch nodes should be connected
as close as possible to the inductor. The CSREF signal should be
connected to the output voltage at the nearest inductor to the
controller.
Rev. A | Page 23 of 24
ADP3186
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 15. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
0.390
BSC
28
1
15
14
0.154
BSC
0.236
BSC
PIN 1
0.069
0.053
0.065
0.049
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137-AF
Figure 16. 28-Lead Shrink Small Outline Package [QSOP]
(RQ-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP3186JRUZ-REEL1
ADP3186JRQZ-REEL1
Temperature Range
Package Description
28-Lead TSSOP
Package Option
RU-28
Quantity per Reel
0°C to 85°C
0°C to 85°C
2500
2500
28-Lead QSOP
RQ-28
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04914-0-3/06(A)
Rev. A | Page 24 of 24
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