ADP3206JCPZ-REEL [ADI]
IC SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PQCC40, LEAD FREE, MO-220-VJJD2, LFCSP-40, Switching Regulator or Controller;
| 型号： | ADP3206JCPZ-REEL |
| 厂家： | 
ADI |
| 描述： | IC SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PQCC40, LEAD FREE, MO-220-VJJD2, LFCSP-40, Switching Regulator or Controller 开关 |
| 文件： | 总32页 (文件大小：571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2-/3-/4-Phase Synchronous Buck
Controller for IMVP-5 CPUs
ADP3206
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
FUNCTIONAL BLOCK DIAGRAM
VCC
RAMPADJ RT
35
16 15
UVLO
SHUTDOWN
AND BIAS
6-bit digitally programmable 0.8375 V to 1.6 V output
10 mV DAC accuracy over temperature
13
SD
OSCILLATOR
SET
RESET
EN
34
CMP
CMP
PWM1
GND 21
Logic-level PWM outputs for interface to
external high power drivers
Active current/thermal balancing between phases
Built-in power good/crowbar blanking supports
on-the-fly VID code changes
ADP3206
RESET
33 PWM2
32 PWM3
31 PWM4
CURRENT-
BALANCING
CIRCUIT
TTMASK 22
2-/3-/4-PHASE
DRIVER LOGIC
RESET
THERMAL
THROTTLING
CONTROL
23
24
TTSENSE
VRTT
CMP
CMP
RESET
Programmable deep sleep offset and deeper sleep
reference voltage
Programmable soft transient control to minimize
inrush currents during output voltage changes
CSREF
CROWBAR
CURRENT LIMIT
28 SW1
27
SW2
Programmable short circuit protection with
programmable latch-off delay
26 SW3
PWRGD 12
DELAY
25
SW4
14
DELAY
APPLICATIONS
Desk-note and notebook PC power supplies for IMVP-5
compliant Intel® processors
19
18
20
CURRENT-
LIMITING
CIRCUIT
CSSUM
CSREF
ILIMIT 17
CSCOMP
SOFT
START
3
GENERAL DESCRIPTION
FB
4
COMP
11
10
9
DPSLP
DPSET
DPRSLP
The ADP3206 is a highly efficient multiphase synchronous
buck-switching regulator controller optimized for converting
the notebook main supply into the core supply voltage required
by IMVP-5 Intel processors. It uses an internal 6-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between
0.8375 V and 1.6 V, and uses a multimode PWM architecture
to drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency. The
phase relationship of the output signals can be programmed to
provide 2-, 3-, or 4-phase operation.
DEEP/
DEEPER
SLEEP
8
DPRSET
PGMASK
CONTROL
5
29 OD2
30
OD1
6
STSET
PRECISION
REFERENCE
VID
DAC
2
7
40
39
38
37
36
1
VID0
FBRTN REF
VID1 VID2 VID3 VID4 VID5
Figure 1.
The ADP3206 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current so that it is always optimally positioned for a system
transient. The ADP3206 also provides accurate and reliable
short circuit protection, adjustable current limiting, deep sleep
and deeper sleep programming inputs, and a delayed power
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
ADP3206 is specified over the commercial temperature range of
0°C to 100°C and is available in a 40-lead LFCSP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADP3206
TABLE OF CONTENTS
Specifications..................................................................................... 3
Inductor Selection...................................................................... 18
Selecting a Standard Inductor................................................... 19
Output Droop Resistance.......................................................... 19
Inductor DCR Temperature Correction ................................. 20
Output Offset.............................................................................. 20
COUT Selection ............................................................................. 21
Power MOSFETS........................................................................ 21
Ramp Resistor Selection............................................................ 22
COMP Pin Ramp ....................................................................... 22
Current Limit SetPoint .............................................................. 22
Feedback Loop Compensation Design.................................... 23
CIN Selection and Input Current di/dt Reduction.................. 23
Deepersleep Voltage and Transient Setting............................. 24
Deepsleep Offset Voltage Setting ............................................. 25
PWRGD Mask Timer Setting................................................... 25
Selecting Thermal Monitor Components............................... 25
Tuning Procedure for ADP3206............................................... 26
Layout and Component Placement ............................................. 28
General Recommendations....................................................... 28
Power Circuitry .......................................................................... 28
Signal Circuitry........................................................................... 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 30
Test Circuits....................................................................................... 6
Absolute Maximum Ratings............................................................ 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 11
Number of Phases ...................................................................... 11
Master Clock Frequency............................................................ 11
Output Voltage Differential Sensing ........................................ 11
Output Current Sensing ............................................................ 11
Active Impedance Control Mode............................................. 12
Current Control Mode and Thermal Balance ........................ 12
Voltage Control Mode................................................................ 12
Deep Sleep and Deeper Sleep Settings..................................... 13
Soft-Start...................................................................................... 14
Current Limit, Short Circuit, and Latch-Off Protection ....... 14
Dynamic VID.............................................................................. 15
Power Good Monitoring ........................................................... 15
Output Crowbar ......................................................................... 15
Output Enable and UVLO ........................................................ 15
Thermal Throttling Control...................................................... 15
Application Information................................................................ 18
Setting the Clock Frequency..................................................... 18
Soft-Start, Power Good, and Current Limit Latch-Off
Delay Times................................................................................. 18
REVISION HISTORY
4/04—Revision 0: Initial Version
Rev. 0| Page 2 of 32
ADP3206
SPECIFICATIONS
Table 1. VCC = 5 V, FBRTN = DPRSLP = GND,
= 1.2 V, DPSLP = 3.3 V, TA = 0oC to 100oC, unless otherwise noted.1
SD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
REFERENCE and VID DAC
Reference Output Voltage
VREF
2.95
2.93
0
3.0
3.0
3.05
3.07
4
V
IREF = 100 µA
IREF = 4 mA
V
mA
mV
Output Current Range
Normal Mode Output Accuracy
IREF
VFB
Relative to nominal DAC output,
referenced to FBRTN, DPRSLP = 0 V
+10
−10
Deeper Sleep Output Accuracy
VSTSET
Relative to DPRSET input, referenced
to FBRTN, DPRSLP = 3.3 V
+5
mV
−5
Input Low Voltage
Input High Voltage
Input Current, Input Voltage Low
Input Current, Input Voltage High
Pull-up resistance
VIL(VID)
VIH(VID)
IIL(VID)
IIH(VID)
RVID
0.4
V
V
0.8
VID(X) = 0 V
−20
5
−30
15
µA
µA
kΩ
V
ns
ns
VID(X) = 1.25 V
35
60
1.1
Internal Pull-up Voltage
VID Transition Delay Time1
No CPU Detection Turn-off Delay
Time2
0.9
400
400
1.25
VID change to DACREF change
VID change to 1111 to PWM going
low
DEEPSLEEP/DEEPERSLEEP CONTROL
DPSLP, DPRSLP
Input Low Voltage
Input High Voltage
Input Current
VIL
VIH
0.8
1
V
V
2.0
−1
µA
OD1, OD2
Output Voltage Low
Output Voltage High
DPSET
VOL
VOH
80
500
mV
V
I ODX(SINK) = 400 µA
I ODX(SOURCE) = 400 µA
4.0
5.0
Output Voltage
Output Current Range
DPRSET
VDPSET
IDPSET
DPSET – Nominal VID output
+70
100
mV
−70
0
µA
Input Voltage Range
Input Current
VDPRSET
IDPRSET
0.5
1.0
1
V
−1
µA
STSET
Minimum Capacitance
Transient Time
CSTET
100
0.5
pF
DPSET = 0.75 V
100
µs
Nominal VID output = 1.55 V,
CSTSET = 1.5 nF
Output Voltage Range
Output Current
3
V
ISTSET
DPSET = 0.75 V, DPRSLP – 3.3 V
VSTSET = 2 V
−19
13
−16
16
−13
19
µA
µA
VSTSET = 0.5 V
THERMAL THROTTLING CONTROL
TTSENSE Voltage Range
0
2
V
TTSENSE Threshold Voltage
TTSENSE Bias Current
1.46
1.5
1.5
1.54
1
V
−1
1.45
µA
V
mV
mV
V
TTMASK Threshold Voltage
TTMASK Output Low Voltage
VRTT Output Voltage Low
VRTT Output Voltage High
1.55
200
500
TTSENSE static, ITTMASK(SINK) = 1 mA
IVRTT(SINK) = 200 µA
VOL
VOH
100
5.0
4.0
IVRTT(SOURCE) = 200 µA
Rev. 0| Page 3 of 32
ADP3206
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIER
Output Voltage Range
Line Regulation
VCOMP
0.8
3.3
V
%
VCC = 4.5 V to 5.5 V
0.05
∆VFB
IFB
FB Input Bias Current
DPSLP = 3.3 V
14
70
16
75
85
500
20
50
18
µA
80
DPSLP = DRSLP = 0 V, I DPSET = 60 µA
µA
µA
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
IFBRTN
120
IO(ERR)
FB Forced to VOUT = 3%
COMP = FB
CCOMP = 10 pF
µA
MHz
GBW(ERR)
V/µs
OSCILLATOR
Frequency Range2
Frequency Variation
fOSC
fPHASE
0.25
155
4
245
MHz
kHz
200
400
600
2.0
TA = +25°C, RT = 250 kΩ, 4-Phase
TA = +25°C, RT = 115 kΩ, 4-Phase
TA = +25°C, RT = 75 kΩ, 4-Phase
kHz
kHz
Output Voltage
VRT
1.9
2.1
V
RT = 100 kΩ to GND
RAMPADJ Output Voltage
RAMPADJ Input Current Range
VRAMPADJ
IRAMPADJ
RAMPADJ = FB
+50
100
mV
µA
−50
CURRENT SENSE AMPLIFIER
Offset Voltage
VOS(CSA)
CSSUM – CSREF, see Figure 1
+1.5
mV
MHz
V/µs
V
−1.5
Gain Bandwidth Product
Slew Rate
GBW(CSA)
10
25
CCSCOMP = 10 pF
Input Common Mode Range
Positioning Accuracy
CSSUM and CSREF
FB – VVID, see Figure 2
0
3
mV
−75
−80
−85
∆VFB
ICSSUM
ICSREF
CSSUM Bias Current
CSREF Bias Current
Output Current2
20
0.5
100
5
nA
µA
ICSCOMP
CSAMP unity gain
Sourcing
500
µA
µA
Sinking
−300
CURRENT BALANCE CIRCUIT
Common Mode Range
Input Resistant
VSW(X)CM
RSW(X)
ISW(X)
+200
42
mV
−600
22
SW(X) = 0 V
SW(X) = 0 V
SW(X) = 0 V
32
7
kΩ
µA
%
Input Current
4
10
Input Current Matching
+5
−5
∆ISW(X)
CURRENT LIMIT COMPARATOR
Output Voltage
VILIMIT
IILIMIT
VCL
0.95
1
5
1.05
V
RILIMIT = 200 kΩ
Output Current
RILIMIT = 200 kΩ
VCSREF – VCSCOMP, RILIMIT = 200 kΩ
4 Phase
µA
Current Limit Threshold Voltage
DPRSLP = 0 V
DPRSLP = 3.3 V
In current limit
105
15
1.7
120
30
1.8
1.2
145
45
1.9
mV
mV
V
Latch-Off Delay Threshold
Latch-Off Delay Time
VDELAY
tDELAY
ms
RDELAY = 250 kΩ CDELAY = 4.7 nF
SOFT START
Output Current, Soft-Start Mode
Output Voltage
IDELAY(SS)
VDELAY
During start-up, delay < 2.8 V
15
20
3
25
µA
V
Soft-Start Delay Time
tDELAY(SS)
600
R
DELAY = 250 kΩ, CDELAY = 4.7 nF,
µs
VID code = 011111
Rev. 0| Page 4 of 32
ADP3206
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SHUTDOWN INPUT
Input Low Voltage
0.4
V
VIL(
)
SD
Input High Voltage
0.8
V
VIH(
)
SD
Input Current, Input Voltage Low
Input Current, Input Voltage High
SD = 0 V
1
IIL(
)
−1
µA
µA
SD
SD = 1.25 V
10
25
IIH(
)
SD
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Power Good Delay Time
VID Code Changing
VID Code Static
Crowbar Trip Point
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
Relative to nominal output
Relative to nominal output
IPWRGD(SINK) = 4 mA
mV
mV
mV
−200
100
−250
150
150
−300
200
400
CPGMASK = 150 pF
90
µs
ns
mV
mV
200
150
450
VCROWBAR
tCROWBAR
Relative to nominal output
100
350
200
550
Overvoltage to PWM going low
CPGMASK = 150 pF
90
µs
ns
400
POWER GOOD MASKING
Threshold Voltage
Output Current
2.85
3.5
3
5
3.15
6.5
V
DPRSLP or VID changing,
VPGMASK = 0 V
µA
DPRSLP or VID static,
VPGMASK = 0.5 V
500
µA
PWM OUTPUTS
Output Voltage Low
Output Voltage High
VOL(PWM)
VOH(PWM)
100
5.0
500
mV
V
IPWM(SINK) = 400 µA
4.0
4.5
IPWM(SOURCE) = 400 µA
SUPPLY
Supply Voltage Range
Supply Current
VCC
ICC
5.5
6
V
mA
V
3.5
3.8
100
UVLO Threshold Voltage
UVLO Hysteresis
VUVLO
VCC Rising
3.6
50
4.1
150
mV
∆VUVLO
1 All limits at temperature extremes are guaranteed via correlation using Standard Statistical Quality Control (SQC).
2 Guaranteed by design or bench characterization, not production tested.
Rev. 0| Page 5 of 32
ADP3206
TEST CIRCUITS
5V
+
1
µ
F
100nF
ADP3206
6-BIT CODE
VCC
35
3
5V
FB
1
2
3
4
5
6
7
8
9
10
30
PIN 1
INDICATOR
29
28
27
26
25
24
23
22
21
10kΩ
COMP
CSCOMP
CSSUM
CSREF
GND
4
ADP3206
1kΩ
TOP VIEW
4.7nF
250kΩ
200k
Ω
20
19
18
100nF
200k
Ω
–
+
∆V
1.25V
250k
Ω
100nF
20kΩ
1.0V
21
Figure 2. Closed-Loop Output Voltage Accuracy
∆V = FB
FB
– FB
∆V = 0mV
∆V = 80mV
Figure 4. Positioning Voltage
ADP3206
VCC
35
5V
CSCOMP
20
39k
Ω
100nF
CSSUM
–
19
+
1kΩ
CSREF
18
1.0V
CSCOMP – 1V
GND
V
=
OS
40
21
Figure 3. Current Sense Amplifier VOS
Rev. 0| Page 6 of 32
ADP3206
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified all other
voltages are referenced to GND.
Parameter
Rating
VCC
FBRTN
–0.3 V to + 6 V
–0.3 V to + 0.3 V
–5 V to + 25 V
–0.3 V to + 6 V
0°C to +100°C
SW1 – SW4
All other Inputs & Outputs
Operating Ambient Temperature
Range
Operating Junction Temperature
Storage Temperature Range
θJA
125°C
–65°C to +150°C
100°C/W
300°C
Lead Temperature Range
(Soldering 10 sec)
Infrared (15 sec)
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0| Page 7 of 32
ADP3206
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
30 OD1
VID5 1
FBRTN 2
FB 3
COMP 4
PGMASK 5
STSET 6
REF 7
PIN
INDICATOR
29 OD2
28 SW1
27 SW2
26 SW3
25 SW4
ADP3206
24 VRTT
23 TTSENSE
22 TTMASK
21 GND
DPRSET 8
DPRSLP 9
DPSET 10
TOP VIEW
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 36 to 40 VID5, VID4 to
VID0
Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1 if
left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375
V to 1.6 V. Leaving all VID4 through VID0 open results in the ADP3206 going into a “No CPU” mode, shutting
off its PWM outputs.
2
3
FBRTN
FB
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no-load offset point.
4
5
COMP
PGMASK
Error Amplifier Output and Compensation Point.
Power Good Masking. A capacitor connected between this pin and GND sets the Power Good Comparator
masking time during DPRSLP and VID pin transitions.
6
STSET
Soft Transient Setting Input. A capacitor connected between this pin and GND controls the slew rate of the
output voltage during transitions between various operating modes.
7
REF
Internal 3 V Reference Output.
8
9
10
DPRSET
DPRSLP
DPSET
Deeper Sleep Voltage Setting Input used as the DAC reference voltage when DPRSLP is asserted.
Deeper Sleep Control Input.
Deep Sleep Offset Voltage Setting Input. The offset programmed by a resistor connected between this pin
and GND is activated when DPSLP is asserted.
11
12
DPSLP
Deep Sleep Control Input.
PWRGD
Power Good Output. Open drain output that signals when the output voltage is outside of the proper
operating range.
13
14
SD
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.
DELAY
Soft-start Delay and Current Limit Latch-off Delay Setting Input. An external resistor/capacitor connected
between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off delay time.
15
16
17
18
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
Current Limit Set Point. An external resistor from this pin to GND sets the current limit threshold of the
converter.
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the power good and crowbar functions. This pin should be connected to the common point of
the output inductors.
RAMPADJ
ILIMIT
CSREF
19
CSSUM
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
Rev. 0| Page 8 of 32
ADP3206
Pin No.
Mnemonic
Description
20
CSCOMP
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the slope of
the load line and the positioning loop response time.
21
22
GND
TTMASK
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
Thermal Throttling Masking Time Setting Input. An external resistor from this pin to VCC and an external
capacitor to GND set the delay time during which the VRTT output is masked. This delay is triggered by the
assertion or de-assertion of VRTT.
23
TTSENSE
VR Hot Thermal Throttling Sense Input. This pin monitors the common tap point of an external resistor-
thermistor voltage divider network and causes VRTT output signal to go high if the remotely sensed hot spot
temperature exceeds the programmed temperature threshold.
24
VRTT
Voltage Regulator Thermal Throttling Output. This logic output alerts the CPU that the temperature at one of
the designated monitoring points has exceeded the programmed temperature threshold.
25-28
29
SW4 – SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
OD2
OD1
This pin is actively pulled low under the same conditions as those of OD1. In addition, this pin is actively
pulled low when DPRSLP is asserted. This pin is normally connected to the SD input of the drivers for phases
2 through 4.
30
This pin is actively pulled low when the ADP3206 SD input is low, or when VCC is below its UVLO threshold
to signal to the driver IC that the driver high-side and low-side outputs should go low. This pin is normally
connected to the SD input of the phase 1 driver.
31-34
35
PWM4 –
PWM1
Logic-level PWM Outputs. Each output connects to the input of an external MOSFET driver. Connecting the
PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the ADP3206 to operate as a
2-, 3-, or 4-phase controller.
VCC
Supply Voltage for the device.
Rev. 0| Page 9 of 32
ADP3206
TYPICAL PERFORMANCE CHARACTERISTICS
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
TA = 25°C
4-PHASE OPERATION
3
2
1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
50
100
150
200
250
300
MASTER CLOCK FREQUENCY (MHz)
R
VALUE (kΩ)
T
Figure 6. Master Clock Frequency vs. RT
Figure 7. Supply Current vs. Oscillator Frequency
Rev. 0| Page 10 of 32
ADP3206
THEORY OF OPERATION
The ADP3206 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal 6-bit VID DAC conforms to Intel's IMVP-5
specifications. Multiphase operation is important for producing
the high currents and low voltages demanded by today's
microprocessors. Handling the high currents in a single-phase
converter would place high thermal demands on the
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3419. Because each phase
is monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3206 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is to be divided by the number of phases in use.
If PWM4 is grounded, then divide the master clock by 3 for the
frequency of the remaining phases. If PWM3 and 4 are
components in the system such as the inductors and MOSFETs.
The multimode control of the ADP3206 ensures a stable, high
performance topology for
•
•
Balancing currents and thermals between phases
grounded, then divide by 2. If all phases are in use, divide by 4.
High speed response at the lowest possible switching
frequency and output decoupling
OUTPUT VOLTAGE DIFFERENTIAL SENSING
•
Minimizing thermal switching losses due to lower
frequency operation
The ADP3206 combines differential sensing with a high
accuracy VID DAC, precision REF output, and a low offset error
amplifier to meet Intel's IMVP-5 specification. During normal
mode, the VID DAC and error amplifier maintain a worst-case
specification of 10 mV over the full operating output voltage
and temperature range. For Deeper Sleep operation, an external
resistor divider from the REF pin to FBRTN creates the
DPRSET voltage. This voltage is buffered by a low offset, slew
rate limited amplifier that is used to drive the noninverting
input of the error amplifier.
•
•
•
•
•
Tight load line regulation and accuracy
High current output from having up to 4 phase operation
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
•
Flexibility in operation for tailoring design to low cost or
high performance
The core output voltage is sensed between the FB and FBRTN
pins. FB should be connected through a resistor to the
regulation point, usually the remote sense pin of the
microprocessor. FBRTN should be connected directly to the
remote sense ground point. The internal VID DAC, DPRSET
voltage, and precision REF output are referenced to FBRTN,
which has a minimal current of 100 µA to allow accurate
remote sensing.
NUMBER OF PHASES
The number of operational phases and their phase relationship
is determined by internal circuitry that monitors the PWM
outputs. Normally, the ADP3206 operates as a 4-phase PWM
controller. Grounding the PWM4 pin programs 3-phase
operation, and grounding the PWM3 and PWM4 pins
programs 2-phase operation.
OUTPUT CURRENT SENSING
The ADP3206 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method then peak current detection or sampling the
current across a sense element such as the low side MOSFET.
This amplifier can be configured several ways depending on the
objectives of the system:
When the ADP3206 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 550 mV. An
internal comparator checks each pin's voltage versus a threshold
of 300 mV. If the pin is grounded, then it is below the threshold
and the phase is disabled. The output impedance of the PWM
pin is approximately 5 kΩ during the phase detect. Any external
pull-down resistance connected to the PWM pin should not be
less than 25 kΩ to ensure proper phase detection. The phase
detection is made during the first two clock cycles of the
internal oscillator. After this time, if the PWM output was not
grounded, then it switches between 0 V and 5 V. If the PWM
output was grounded, then switching to the pin remains off.
•
•
•
Output inductor ESR sensing without thermistor for
lowest cost
Output inductor ESR sensing with thermistor to
improve accuracy for tracking inductor temperature
Sense resistors for highest accuracy measurements
Rev. 0| Page 11 of 32
ADP3206
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output in-
ductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor.
The gain of the amplifier is programmable by adjusting the
feedback resistor to set the load line required by the micro-
processor. The current information is then given as the
difference of CSREF − CSCOMP. This difference signal is used
internally to offset the error amplifier for voltage positioning
and as a differential input for the current limit comparator.
External resistors can be placed in series with individual phases
to create an intentional current imbalance if desired, such as
when one phase may have better cooling and can support
higher currents. Resistors RSW1 through RSW4 (see the typical
application circuit in Figure 1) can be used for adjusting
thermal balance. It is best to have the ability to add these
resistors during the initial design, so make sure placeholders are
provided in the layout.
To increase the current in any given phase, make RSW for that
phase larger (make RSW = 0 for the hottest phase and do not
change during balancing). Increasing RSW to only 500 Ω makes
a substantial increase in phase current. Increase each RSW value
by small amounts to achieve balance, starting with the coolest
phase first.
To provide the best accuracy for current sensing, the CSA has
been designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors so that it can be
made extremely accurate.
VOLTAGE CONTROL MODE
A high gain-bandwidth error amplifier is used for the voltage-
mode control loop. During normal mode, the noninverting
input voltage is set via the 6-bit VID logic code listed in Table 4,
while during Deeper Sleep operation, it is set to track the
buffered DPRSET voltage. The noninverting input voltage is
also offset by the droop voltage for offsetting the output voltage
as a function of current, commonly known as active voltage
positioning. The output of the amplifier is the COMP pin,
which sets the termination voltage for the internal PWM ramps.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output
current at the CSCOMP pin can be scaled to be equal to the
droop impedance of the regulator times the output current. This
droop voltage is then used to set the input control voltage to the
system. The droop voltage is subtracted from the error amplifier
offset voltage to tell the error amplifier where the output voltage
should be. This differs from previous implementations and
allows enhanced feed-forward response
The negative input (FB) is tied to the output sense location with
a resistor RB and is used for sensing and controlling the output
voltage at this point. During normal mode, a current source
from the FB pin flowing through RB is used for setting the no-
load offset voltage from the VID voltage. The no-load voltage is
negative with respect to the VID DAC. The main loop
compensation is incorporated in the feedback network between
FB and COMP.
CURRENT CONTROL MODE AND THERMAL
BALANCE
The ADP3206 has individual inputs for each phase which are
used for monitoring the current in each phase. This information
is combined with an internal ramp to create a current balancing
feedback system that has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for positioning
described previously.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It is also monitors the supply
voltage for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the
RAMPADJ pin determines the slope of the internal PWM ramp.
Detailed information about programming the ramp is given in
the applications section.
Rev. 0| Page 12 of 32
ADP3206
Table 4. Output Voltage vs. VID Code (X = Don’t Care)
VID4 VID3 VID2 VID1 VID0 VID5
VOUT(NOM)
0.8375 V
0.850 V
0.8625 V
0.875 V
0.8875 V
0.900 V
0.9125 V
0.925 V
0.9375 V
0.950 V
0.9625 V
0.975 V
0.9875 V
1.000 V
1.0125 V
1.025 V
1.0375 V
1.050 V
1.0625 V
1.075 V
1.0875 V
1.100 V
1.1125 V
1.125 V
1.1375 V
1.150 V
1.1625 V
1.175 V
1.1875 V
1.200 V
1.2125 V
1.225 V
VID4 VID3 VID2 VID1 VID0 VID5
VOUT(NOM)
1.2375 V
1.250 V
1.2625 V
1.275 V
1.2875 V
1.300 V
1.3125 V
1.325 V
1.3375 V
1.350 V
1.3625 V
1.375 V
1.3875 V
1.400 V
1.4125 V
1.425 V
1.4375 V
1.450 V
1.4625 V
1.475 V
1.4875 V
1.500 V
1.5125 V
1.525 V
1.5375 V
1.550 V
1.5625 V
1.575 V
1.5875 V
1.600 V
No CPU
0
0
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1
X
DEEP SLEEP AND DEEPER SLEEP SETTINGS
external capacitor on the STSET pin and the 15 µA output
current of the low offset buffer. During normal and Deep Sleep
modes, the output of the VID DAC is connected to the buffer,
thereby forcing the STSET voltage to the nominal DAC voltage.
When the DPRSLP signal is forced high, the ADP3206 enters
into Deeper Sleep mode. First, the Deep Sleep offset current is
shut off. Next, the VID DAC output is disconnected from the
noninverting input of the Error Amplifier, while the STSET pin
is connected. The DPRSET pin is then connected to the input of
the buffer, which causes the STSET voltage to slew from the
nominal DAC voltage to the DPRSET voltage. Because the core
voltage follows the noninverting input of the error amplifier, the
output voltage transitions to the Deeper Sleep voltage. To exit
Deeper Sleep, the DPRSLP pin must be forced low. The
The ADP3206 includes circuitry to perform both Deep Sleep
and Deeper Sleep functions. During Deep Sleep, the IMVP-5
specification requires that the core output voltage be decreased
by a fixed percentage. This decrease is user programmable. The
ADP3206 accomplishes this function by forcing the
programmed DAC voltage on the DPSET pin. An external
resistor between this pin and ground generates a current that is
proportional to the DAC voltage. This Deep Sleep offset current
is then mirrored and forced out of the FB pin along with the no-
load offset current. This causes the core output voltage to be
negative with respect to the VID DAC. To enter Deep Sleep
operation, DPSLP and DPRSLP must be low.
The ADP3206 also provides a soft transient function to reduce
inrush current during transitions into and out of Deeper Sleep.
Reducing the inrush current helps decrease the acoustic noise
generated by the MLCC input capacitors and inductors due to
added stress. The slew rate for the soft transient is set by the
DPRSET pin is then disconnected from the buffer and the VID
DAC signal is connected. This causes the STSET voltage to slew
from the DPRSET voltage to the programmed DAC voltage.
The core voltage follows this transition. After the STSET voltage
Rev. 0| Page 13 of 32
ADP3206
reaches the programmed DAC voltage, the STSET pin is dis-
connected from noninverting input of the error amplifier, while
the VID DAC output is connected.
During transitions into/out of Deeper Sleep, the Power Good
circuit is masked to prevent false triggering of the PWRGD
signal. The masking time is set by an external capacitor, which is
placed between the PGMASK pin and ground. This capacitor is
discharged to ground during normal operation. During a
transition of the DPRSLP pin, the masking time begins and the
capacitor is charged up by a current source. Once the voltage on
the PGMASK pin reaches 3V, the masking time has ended and
the PGMASK capacitor is reset to ground. If a DPRSLP
transition occurs during a masking event, the capacitor on
PGMASK is reset to ground to restart the masking time.
Figure 8. Typical Start-Up Waveforms
Channel 1: PWRGD, Channel 2: VCORE
Channel 3: Phase 2 Switch Node, Channel 4:
,
To minimize power dissipation during Deeper Sleep, the
ADP3206 switches over to single-phase operation. This is
SD
accomplished by taking the
and PWM2, 3, and 4 outputs
OD2
CURRENT LIMIT, SHORT CIRCUIT, AND LATCH-OFF
PROTECTION
low upon the completion of the Power Good masking time.
This allows for all phases to aid in discharging the core output
during the soft transient into Deeper Sleep. When DPRSLP goes
The ADP3206 compares a programmable current limit set point
to the voltage from the output of the current sense amplifier.
The nominal voltage on the ILIMIT pin is 1 V. The level of
current limit is set with a resistor from the ILIMIT pin to
ground. For four-phase operation during normal mode, the
current through the external resistor is internally scaled to give
a current limit threshold of 24 mV/µA. During Deeper Sleep
mode, the current limit threshold is scaled down to a fraction of
the normal mode threshold where the scaling factor is the
number of operational phases. For example, a four-phase design
scales the current limit threshold to 6 mV/µA. During any
mode of operation, if the difference in voltage between CSREF
and CSCOMP rises above the current limit threshold, the
internal current limit amplifier controls the internal COMP
voltage to maintain the average output current at the limit.
low, the
signal immediately goes high, followed by the
OD2
normal operation of the PWM2 through PWM4 signals. This
allows all phases to aid in the charging of the core output back
to the Deep Sleep voltage.
SOFT-START
The power-on ramp up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current limit
latch-off time as explained in the following section. In UVLO or
when
is a logic low, the DELAY pin is held at ground. After
SD
the UVLO threshold is reached and
is asserted, the DELAY
SD
cap is charged up with an internal 20 µA current source. The
output voltage follows the ramping voltage on the DELAY pin,
limiting the inrush current. The soft-start time depends on the
value of VID DAC and CDLY, with a secondary effect from RDLY
Refer to the applications section for detailed information on
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the
DELAY voltage and shuts off the controller when the voltage
drops below 1.8 V. The current limit latch-off delay time is
therefore set by the RC time constant discharging from 3 V to
1.8 V.
.
setting CDLY
.
When the PWRGD threshold is reached, the soft-start cycle is
stopped and the DELAY pin is pulled up to 3 V. This ensures
that the output voltage is at the VID voltage when the PWRGD
Because the controller continues to cycle the phases during the
latch-off delay time, if the current limit is removed before the
1.8 V threshold is reached, the controller returns to normal
operation. The recovery characteristic depends on the state of
PWRGD. If the output voltage is within the PWRGD window,
the controller resumes normal operation. However, if current
limit has caused the output voltage to drop below the PWRGD
threshold, then a soft-start cycle is initiated.
signals to the system that the output voltage is good. If either
is taken low or VCC drops below UVLO, the DELAY cap is reset
to ground to be ready for another soft-start cycle.
SD
Rev. 0| Page 14 of 32
ADP3206
The latch-off function can be reset by both removing and
reapplying VCC to the ADP3206, or by pulling the pin low
for a short time. To disable the current limit latch-off function,
the external resistor on the DELAY pin to ground should be left
open. This prevents the DELAY capacitor from discharging so
the 1.8 V threshold is never reached.
POWER GOOD MONITORING
SD
The power good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open drain output whose
high level (i.e., when it is connected to a pull-up resistor)
indicates that the output voltage is within the nominal limits
based on the VID voltage setting. PWRGD goes low if the
output voltage is outside of this specified range. PWRGD is
masked during a VID-OTF event for a period determined by
the PGMASK capacitor.
During start-up when the output voltage is below 200 mV, a
secondary current limit is active because the voltage swing of
CSCOMP cannot go below ground. This secondary current
limit controls the internal COMP voltage to the PWM
comparators to 2 V. This limits the voltage drop across the low
side MOSFETs through the current balance circuitry.
OUTPUT CROWBAR
As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
power good threshold. This crowbar action stops once the
output voltage has fallen below the release threshold of
approximately 450 mV.
There is also an inherent per phase current limit that protects
individual phases in the case where one or more phases may
stop functioning because of a faulty component. This limit is
based on the maximum normal-mode COMP voltage.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output
overvoltage is due to a short of the high side MOSFET, this
action current limits the input supply or blows its fuse,
protecting the microprocessor from destruction.
OUTPUT ENABLE AND UVLO
The input supply (VCC) to the controller must be higher than
the UVLO threshold and the
pin must be higher than its
SD
logic threshold for the ADP3206 to begin switching. If UVLO is
less than the threshold or the SD pin is a logic low, the ADP3206
is disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the
and
pins
OD1
OD2
at ground.
Figure 9. Overcurrent Latch-Off Waveforms
Proper power supply sequencing must be adhered to during
start-up and shutdown of the ADP3206. All input pins must be
at ground prior to applying VCC. During the power down
sequence, all input pins must be forced to ground prior to VCC
ramping down to ground. All output pins should be left in a
high impedance state when VCC is off.
Channel 1: PWRGD, Channel 2: VCORE
,
Channel 3: Delay, Channel 4: Phase 2 Switch Node
DYNAMIC VID
The ADP3206 incorporates the ability to dynamically change
the VID input while the controller is running. This allows the
output voltage to change while the supply is running and
supplying current to the load. This is commonly referred to as
VID-on-the-fly (OTF). A VID-OTF can occur under either light
load or heavy load conditions. The processor signals the
controller by changing the VID inputs in multiple steps from
the start code to the finish code. This change can be either
positive or negative.
THERMAL THROTTLING CONTROL
The ADP3206 includes a thermal monitoring and masking
circuit to detect when a point on the VR has exceeded a user-
defined temperature. The thermal monitoring circuit requires
an external resistor divider connected between the REF pin and
GND. This divider uses a NTC thermistor and a resistor. The
midpoint of the divider is connected to the TTSENSE pin in
order to generate a voltage that is proportional to temperature.
When a VID input changes state, the ADP3206 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time is to prevent a false code due to logic skew while the6
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and CROWBAR masking functions to
prevent a false PWRGD or CROWBAR event. Each VID change
resets the voltage on the PGMASK capacitor.
An internal circuit compares this voltage to a 1.5 V threshold
and outputs a logic level signal at the VRTT output. The VRTT
output is designed to drive an external transistor. This transistor
should be connected to the processors thermal control circuit.
Rev. 0| Page 15 of 32
ADP3206
In order to provide temperature hysteresis, a timer is provided
to mask the VRTT output. The time is programmed with an
external series RC circuit connected between REF and GND.
The midpoint of the RC circuit is connected to the TTMASK
pin. During shutdown, the TTMASK voltage is forced to ground
while the VRTT output is forced low.
transition, the masking timer starts. The TTMASK voltage now
increases based upon the RC time constant. During this
charging time, the VRTT signal is latched and remains high
regardless of changes in the TTSENSE voltage. Once the
TTMASK voltage reaches the 1.5 V threshold, the TTMASK pin
is forced to ground to reset the timer and complete the masking
time. In the event that the TTSENSE voltage goes below the
threshold, the above masking time and latching of the new
VRTT signal occurs again.
Once
goes high, the voltage on TTSENSE is compared to an
SD
internal threshold of 1.5 V. If the voltage on TTSENSE rises
above the threshold, the VRTT output goes high. During this
Rev. 0| Page 16 of 32
ADP3206
0 1 0 0 -
0 4 6 5 1 -
P W M 4
P W M 3
P W M 2
P W M 1
C S C O M P
2 0
3 1
3 2
3 3
3 4
3 5
C S S U M
1 9
C S R E F
1 8
I L I M I T
1 7
1 Ω %
1 Ω %
1 Ω %
R L I M 1 5 4 k
R R 2 8 0 k
V C C
R A M P A D J
1 6
V I D 4
V I D 3
V I D 2
V I D 1
V I D 0
R T
V R _ V I D 4
3 6
1 5
R T 1 6 9 k
D E L A Y
1 4
V R _ V I D 3
3 7
S D
V R _ V I D 2
3 8
1 3
P W R G D
1 2
V R _ V I D 1
3 9
D P S L P
V R _ V I D 0
4 0
1 1
Figure 10. Typical IMVP-5 Application Circuit
Rev. 0| Page 17 of 32
ADP3206
APPLICATION INFORMATION
The design parameters for a typical Intel IMVP5-compliant
CPU Core VR application are as follows:
SOFT-START, POWER GOOD, AND CURRENT LIMIT
LATCH-OFF DELAY TIMES
•
•
•
•
•
•
•
•
•
•
Maximum input voltage (VINMAX) = 19 V
The soft-start and current limit latch-off delay functions share
the DELAY pin, consequently, these two parameters must be
considered together. The first step is to set CDLY for the soft-start
ramp. This ramp is generated with a 20 µA internal current
source. The value of RDLY has a second-order impact on the soft-
start time by sinking a portion of the current to ground.
However, as long as RDLY is kept greater than 200 kΩ, this effect
is negligible. The value for CDLY can be approximated using:
Minimum input voltage (VINMIN) = 8 V
Output voltage by VID setting (VVID) = 1.350 V
Nominal output voltage at No Load (VONL) = 1.325 V
Offset voltage (VOFFSET) = 1.350 V-1.325 V = 0.025 V
Nominal output voltage at 80 A Load (VOFL) = 1.221 V
Duty cycle at maximum input voltage (DMIN) = 0.070
Duty cycle at minimum input voltage (DMAX) = 0.166
Load line slope (RO) = 1.3 mΩ
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VVID
2× RDLY
t
SS
CDLY
=
20 mA −
×
(2)
VVID
Where tSS is the desired soft-start time. Assuming an RDLY of
390 kΩ and a desired a soft-start time of 2.2 ms, CDLY is 56 nF.
Static output voltage drop from no load to full load
(V∆) = VONL - VOFL = 1.325 V - 1.221 V = 104 mV
Once CDLY has been chosen, RDLY can be recalculated for the
current limit latch off time using:
•
•
•
•
•
•
Maximum output current (IO) = 80 A
Maximum output current step (∆IO) = 56 A
Number of phases (n) = 4
1.96×tDELAY
RDLY
=
(3)
CDLY
If the result for RDLY is less than 200 kΩ, then a smaller soft-start
time or longer latch-off time should be considered when CDLY is
recalculated. In no case should RDLY be less than 200 kΩ. In this
example, a delay time of 10 ms gives RDLY = 371 kΩ. The closest
standard 5% value is 390 kΩ.
Switching frequency per phase (fSW) = 280 kHz
Deepersleep voltage at no load (VDPRSLP) = 0.8V
Deepsleep offset percentage (kOS%) = -1.7%
The PWRGD delay, defined as the time period between the
SETTING THE CLOCK FREQUENCY
VCORE voltage reaching VID voltage and the assertion of
The ADP3206 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
In case of a four-phase design, a clock frequency of 1.12 MHz
sets the switching frequency to 280 kHz per phase. This
selection represents trade-off between the switching losses and
the minimum sizes of the output filter components. Figure 6
shows that to achieve a 1.12 MHz oscillator frequency, RT has to
be 169 kΩ. Alternatively, the value for RT can be calculated
using:
PWRGD signal, is also controlled by the DELAY pin. The
ADP3206 does not assert the PWRGD signal until DELAY pin
voltage reaches about 2.2 V. Given the previously calculated
values for RDELAY and CDELAY, the PWRGD delay is in the range
of 2.4 ms to 4 ms. This satisfies the specification range of 1 ms
to 10 ms.
INDUCTOR SELECTION
The choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and also the conduction
losses in the MOSFETs. However, this allows the use of smaller-
size inductors, and for a specified peak-to-peak transient
deviation, it allows less total output capacitance. Conversely, a
higher inductance means lower ripple current and reduced
conduction losses, but requires larger-size inductors and more
output capacitance for the same peak-to-peak transient
deviation. In multiphase converter, the practical value for peak-
to-peak inductor ripple current is less than 50% of the
1
RT =
1
(
n × fSW × 5.83 pF −
)
1.5 MΩ
(1)
where 5.83 pF and 1.5 MΩ are internal IC component values.
For good initial accuracy and frequency stability, it is
recommended to use a 1% resistor.
maximum DC current in the same inductor. Equation 4 shows
the relationship between the inductance, oscillator frequency,
Rev. 0| Page 18 of 32
ADP3206
and peak-to-peak ripple current. Equation 5 can be used to
determine the minimum inductance based on a given output
ripple voltage:
POWER INDUCTOR MANUFACTURERS
The following companies provide surface mount power
inductors optimized for high power applications upon request.
V
VID ×(1− DMIN )
• Vishay Dale Electronics, Inc.
(605) 665-9301
http://www.vishay.com
IR =
L ≥
(4)
fSW × L
VVID × RO × (1 − (n × DMIN )) × (1 − DMIN
fSW × VRIPPLE
)
(5)
• Panasonic
(714) 373-7334
http://www.panasonic.com
Solving Equation 5 for a 10 mV peak-to-peak output ripple
voltage yields
• Sumida Electric Company
(847) 545-6700
http://www.sumida.com
1.350 V ×1.3 mΩ × (1 − (4 × 0.07)) × (1 − 0.07)
L ≥
= 417 nH
280 kHz ×10 mV
• NEC Tokin Corporation
(510) 324-4110
http://www.nec-tokin.com/
If the ripple voltage ends up being less than the initially selected
value was, then the inductor can be changed to a smaller value
until the ripple value is met. This iteration allows optimal
transient response and minimum output decoupling.
OUTPUT DROOP RESISTANCE
The design requires that the regulator output voltage measured
at the CPU pins drops when the output current increases. The
specified voltage drop corresponds to a DC output resistance
(RO).
The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 560 nH inductor is a
good choice for a starting point, and it gives a calculated ripple
current of 8.0 A. The inductor should not saturate at the peak
current of 24 A, and should be able to handle the sum of the
power dissipation caused by the average current of 20 A in the
winding and also the AC core loss.
The output current is measured by summing the currents of the
resistors monitoring the voltage across each inductor and by
passing the signal through a low-pass filter. This summer-filter
is implemented by the CS amplifier that is configured with
resistors RPH(X) (summers), and RCS and CCS (filter). The output
resistance of the regulator is set by the following equations,
where RL is the DCR of the output inductors:
Another important factor in regarding the inductor design is
the DCR, which is used for measuring the phase currents. A
large DCR causes excessive power losses, while too small of a
value leads to increased measurement error. A good rule of
thumb is to have the DCR to be about 1 to 1½ times of the
droop resistance (RO). For our example, we are using an
inductor with a DCR of 1.7 mΩ.
RCS
RPH(X)
RO =
× RL (6)
L
RL × RCS
CCS
=
(7)
SELECTING A STANDARD INDUCTOR
Once the inductance and DCR are known, the next step is to
select a standard inductor that comes as close as possible to
meeting the overall design goals. It is also important to have the
inductance and DCR tolerance specified to keep the accuracy of
the system controlled. Using 20% tolerance for the inductance
and 8% for the DCR (at room temperature) are reasonable
assumptions that most manufacturers can meet.
One has the flexibility of choosing either RCS or RPH(X). Due to
the current drive ability of CSCOMP pin, the RCS resistance
should be larger than 100 kΩ. For example, select RCS to be
equal to 100 kΩ, then solve for RPH(X) by rearranging Equation 6.
1.7 mΩ
RPH
=
(X )
×150 kΩ = 196 kΩ
1.3 mΩ
Next, use Equation 7 to solve for CCS:
560 nH
1.7 mΩ ×150 kΩ
CCS
=
= 2.2 nF
Rev. 0| Page 19 of 32
ADP3206
For this example, CCS calculates to 3.3 nF, which is a standard
capacitance. In case that the calculated CCS is not a standard
value, adjust RCS until standard CCS capacitor value is achieved.
For best accuracy, CCS should be a 5% NPO capacitor. The
standard 1% value for RPH(X) is 130 kΩ.
3. Next, find the relative value of RCS required for each
of these temperatures. This is based on the percentage
change needed, which we initially make 0.39%/°C.
We call these r1 (r1 is 1/(1+ TC × (T1 - 25))) and
r2 (r2 is 1/(1 + TC × (T2 - 25))), where TC=0.0039,
T1 = 50°C and T2 = 90°C.
INDUCTOR DCR TEMPERATURE CORRECTION
With the inductor's DCR being used as sense element, and
copper wire being the source of the DCR, one needs to
compensate for temperature changes of the inductor's winding.
Fortunately, copper has a well-known temperature coefficient
(TC) of 0.39%/°C.
4. Compute the relative values for RCS1, RCS2, and RTH using:
(A − B)× r × r2 − A × (1− B)× r2 + B ×(1− A)× r
1
1
rCS2
=
=
A ×(1− B) × r − B × (1− A)× r2 − (A − B)
1
(1 − A)
rCS1
If RCS is designed to have an opposite sign but equal percentage
change in resistance, it cancels the temperature variation of the
inductor's DCR. Due to the nonlinear nature of NTC
thermistors, series resistors, RCS1 and RCS2 (see Figure 11) are
needed to linearize the NTC and produce the desired
temperature coefficient tracking.
1
A
−
1− rCS2 r − r
1
CS2
1
r
=
(8)
TH
1
1
−
1− rCS2 rCS1
PLACE AS CLOSE AS POSSIBLE
TO
5. Calculate RTH = rTH × RCS, then select the closest value of
thermistor available. Also compute a scaling factor k based
on the ratio of the actual thermistor value used relative to
the computed one:
TO NEAREST INDUCTOR
TO SWITCH
NODES
V
OUT
SENSE
OR LOW-SIDE MOSFET
R
TH
ADP3206
R
R
R
PH3
PH1
PH2
RTH
(
ACTUAL
)
CSCOMP
CSSUM
R
R
CS2
CS1
k =
(9)
18
17
RTH
(CALCULATED
)
KEEP THIS PATH
AS SHORT AS
POSSIBLE AND
WELL AWAY FROM
SWITCH NODE LINES
C
CS
6. Finally, calculate values for RCS1 and RCS2 using:
CS1 = RCS × k × rCS1
R
CSREF
16
RCS2 = RCS ×((1− k) + (k × rCS2 )) (10)
For this example, we start with a thermistor value of 100 kΩ.
Looking through available 0603 size thermistors, we can find
a Vishay NTHS0603N01N1003JR NTC thermistor with
A = 0.3602 and B = 0.09174. From these data we compute
Figure 11. Temperature Compensation Circuit Values
The following procedure and expressions yield values for
CS1, RCS2, and RTH (the thermistor value at 25°C) for a given
R
RCS value.
r
CS1 = 0.3796, rCS2 = 0.7195 and rTH = 1.0751. Solving for RTH
yields 107.5 kΩ, so we choose 100 kΩ, making k = 0.9302.
Finally, we find RCS1 and RCS2 to be 35.3 kΩ and 73.9 kΩ.
Choosing the closest 1% resistor values yields a choice of
35.7 kΩ and 73.2 kΩ.
1. Select an NTC to be used based on type and value. Because
we do not have a value yet, start with a thermistor with a
value close to RCS. The NTC should also have an initial
tolerance of better than 5%.
OUTPUT OFFSET
2. Based on the type of NTC, find its relative resistance value
at two temperatures. The temperatures to use that work
well are 50°C and 90°C. We call these resistance values A
(A is RTH(50°C)/RTH(25°C)) and B (B is
Intel's specification requires that at no load the nominal output
voltage of the regulator to be offset to a lower value than the
nominal voltage corresponding to the VID code. The offset is
set by a constant current source flowing out of the FB pin (IFB)
and flowing through RB. The value of RB can be found using the
following equation. The closest standard 1% resistor value is
1.58 kΩ.
RTH(90°C)/RTH(25°C)). Note that the NTC's relative value
is always 1 at 25°C.
0.025 V
15 μA
VOFFSET
IFB
RB =
(11) RB =
= 1.67 kΩ
Rev. 0| Page 20 of 32
ADP3206
Using six 330 µF Panasonic SP capacitors with a typical ESR of
7 mΩ each yields CX = 1.98 mF with an RX = 1.2 mΩ.
COUT SELECTION
The required output decoupling for processors and platforms is
typically recommended by Intel. The following guidelines can
also be used if there are both bulk and ceramic capacitors in
the system.
One last check should be made to ensure that the ESL of the
bulk capacitors (LX) is low enough to limit the initial high-
frequency transient spike. This is tested using:
2
The first thing is to select the total amount of ceramic
capacitance. This is based on the number and type of capacitor
to be used. The best location for ceramics is inside the socket;
12 to 18 pieces of size 1206 being the physical limit. Others can
be placed along the outer edge of the socket as well.
LX ≤ CZ × RO
(14)
LX ≤ 300 μF × (1.3 mΩ)2 = 507 pH
In this example, LX is about 150 pH for the six SP cap capacitors,
which satisfies this limitation. If the LX of the chosen bulk
capacitor bank is too large, the number of capacitors must be
increased. One should note, for this multimode control
technique, an all-ceramic capacitor design can be used as long
as the conditions of Equations 12, 13 and 14 are satisfied.
Combined ceramic values of 200 to 300 µF are recommended,
and are usually made up of multiple 10 µF or 22 µF capacitors.
Select the number of ceramics and find the total ceramic
capacitance (CZ).
POWER MOSFETS
Next, there is an upper limit imposed on the total amount of
bulk capacitance (CX) when one considers the VID on-the-fly
output voltage stepping (voltage step VV in time tV with error of
VERR), and also a lower limit based on meeting the critical
capacitance for load release at a given maximum load step ∆IO.
The IMVP-5 specification allows a maximum Vcore overshoot
(VOSMAX) of 50 mV over VID voltage for a step-off load current.
For normal 20 A per phase application, the N-channel power
MOSFETs are selected for two high-side switches and two or
three low-side switches per phase. The main selection param-
eters for the power MOSFETs are VGS(TH), QG, CISS, CRSS and
RDS(ON). Because the gate drive voltage (the supply voltage to the
ADP3419) is 5 V, logic-level threshold MOSFETs must be used.
The maximum output current IO determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. In the
ADP3206, currents are balanced between phases; the current in
each low-side MOSFET is the output current divided by the
total number of MOSFETs (nSF). With conduction losses being
dominant, the following expression shows the total power being
dissipated in each synchronous MOSFET in terms of the ripple
current per phase (IR) and average total output current (IO):
L × ∆IO
CX(MIN)
≥
−CZ (12)
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOSMAX + VOFFSET
⎜
n ×VVID × RO +
∆IO
CX
≤
MAX)
(
2
⎛
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎟
⎠
L
VV
⎜
VVID nkRO
VV
⎜
×
×
1+ tV
×
−1 −CZ
⎜
⎜
⎝
⎟
nK 2RO2 VVID
L
⎟
⎠
2
2
⎡
⎢
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
n IR
nSF
IO
nSF
1
12
PSF
=
(1 − D
)
×
+
×
× RDS
(15)
SF )
⎛
⎞
⎟
⎟
⎠
VVERR
VV
(
⎜
⎜
⎝
⎢
⎣
⎥
⎦
where K =1n
Knowing the maximum output current and the maximum
allowed power dissipation, one can find the required RDS(ON) for
the MOSFET. For SO-8 or SO-8 compatible packaged
To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (RX) should be less
than two times the droop resistance, RO. If the CX(MIN) is larger
than CX(MAX), the system does not meet the VID on-the-fly
and/or Deepersleep exit specification and may require a smaller
inductor or more phases (the switching frequency may also
have to be increased to keep the output ripple the same).
MOSFETs, the junction to ambient (PCB) thermal impedance is
50°C/W. In worst case, the PCB temperature is 70°C to 80°C
during heavy load operation of the notebook, a safe limit for PSF
is 0.8 W~1.0 W at 120°C junction temperature. Thus, for our
example (80 A maximum), we find RDS(SF) (per MOSFET) <
8.5mΩ for two pieces of low-side MOSFET. This RDS(SF) is also at
a junction temperature of about 120°C, therefore, the RDS(SF)
(per MOSFET) should be lower than 6 mΩ at room
For our example, we use thirty pieces of 10 µF 0805 MLC
capacitors (CZ = 300 µF). The largest VID voltage change is the
exit of Deepersleep, VCORE change is 525 mV in 100 µs with a
setting error of 20 mV. Where K = 3.3, solving for the bulk
capacitance yields:
temperature, which gives 8.5 mΩ at high temperature.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input needs to be small (less than 10% is
recommended) to prevent accidental turn-on of the
synchronous MOSFETs when the switch node goes high.
560 nH × 56 A
CX(MIN)
≥
− 300 µF = 1.9 mF
⎛
⎜
⎝
⎞
⎟
⎟
⎠
50 mV + 25 mV
⎜
4 ×1.350 × 1.3 mΩ +
56 A
Rev. 0| Page 21 of 32
ADP3206
The high-side (main) MOSFET has to be able to handle two
main power dissipation components; conduction and switching
losses. The switching loss is related to the amount of time it
takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, the following
expression provides an approximate value for the switching loss
per main MOSFET, where nMF is the total number of main
MOSFETs:
and the maximum temperature increase is 50°C. For our
example, with ICC = 2 mA, QGMF = 22.8 nC and QGSF = 84 nC, we
find 160 mW dissipation in each driver, which is below the 300
mW dissipation limit. See the ADP3419 data sheet for details.
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. Use this expression to determine a starting value:
V
CC × IO
nMF
AR × L
RR =
nMF
n
P ( ) = 2 × fSW
×
× RG ×
×CISS (16)
S
MF
3 × AD × RDS × CR
(19)
Here, RG is the total gate resistance (1.5 Ω for the ADP3419
and about 0.5 Ω for two pieces of typical high speed switching
MOSFETs, making RG = 2 Ω) and CISS is the input capacitance
of the main MOSFET. The best thing to reduce switching loss is
to use lower gate capacitance devices.
0.2 × 600 nH
3 × 5 × 4.2 mΩ × 5 pF
RR =
= 381kΩ
where AR is the internal ramp amplifier gain, AD is the current
balancing amplifier gain, RDS is the total low-side MOSFET
ON-resistance, and CR is the internal ramp capacitor value.
Another consideration in the selection of RR is the size of the
internal ramp voltage (see Equation 20). For stability and noise
immunity, keep this ramp size larger than 0.5 V. Taking this into
consideration, the value of RR is selected as 280 kΩ.
The conduction loss of the main MOSFET is given by the
following, where RDS(MF) is the ON-resistance of the MOSFET:
2
⎡
⎢
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛ n× IR ⎞2
IO
nMF
1
12
⎜
⎜
⎝
⎟
⎟
⎠
PC ) = D ×
+
×
× RDS
(17)
MF )
(
MF
(
nMF
⎢
⎣
⎥
⎦
The internal ramp voltage magnitude can be calculated using:
Typically, for main MOSFETs, one wants the highest speed (low
CISS) device, but these usually have higher ON-resistance. One
must select a device that meets the total power dissipation
(0.8~1.0 W for a single SO-8 package) when combining the
switching and conduction losses.
AR ×
RR × CR × fSW
(
1− D
) × VVID
VR =
(20)
0.2 ×
1− 0.125 ×1.5V
( )
VR =
= 0.51mV
For our example, we have selected a Vishay SI7860 device as the
383 kΩ × 5 pF × 267 kHz
main MOSFET (eight in total; i.e., nMF = 8), with about CISS
=
The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response improves, but
thermal balance degrades. Likewise, if the ramp is made smaller,
thermal balance improves at the sacrifice of transient response
and stability. The factor of three in the denominator of equation
19 sets a minimum ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.
1560 pF (max) and RDS(MF) = 15 mΩ (max at Tj = 120°C) and a
Vishay SI7889 device as the synchronous MOSFET (eight in
total; i.e., nSF = 8), RDS(SF) = 7.9 mΩ (max at Tj = 120°C). Solving
for the power dissipation per MOSFET at IO = 80 A and IR =
8.0 A yields 700 mW for each synchronous MOSFET and
730 mW for each main MOSFET. A 3rd synchronous MOSFET
is an option to further increase the conversion efficiency and
reduce thermal stress.
COMP PIN RAMP
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds to
the internal ramp to produce the following overall ramp signal
at the PWM input.
One last thing to look at is the power dissipation in the driver
for each phase. This is best described in terms of the QG for the
MOSFETs and is given by the following, where QGMF is the total
gate charge for each main MOSFET and QGSF is the total gate
charge for each synchronous MOSFET:
VR
VRT
=
(21)
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
2 ×
(1−n × D
)
f
⎡
⎤
SW
1−
PDRV
=
× n ×QGMF+nSF ×QGSF +I
×VCC (18)
(
)
MF
CC
⎢
⎣
⎥
⎦
n × fSW ×CX × RO
2× n
For this example, the overall ramp signal is found to be 1.1V.
Also shown is the standby dissipation (ICC times the VCC) of the
driver. For the ADP3419, the maximum dissipation should be
less than 300 mW, considering its thermal impedance 220°C/W
Rev. 0| Page 22 of 32
ADP3206
There are several poles and zeros created by the output inductor
and decoupling capacitors (output filter) that need to be
compensated for.
CURRENT LIMIT SETPOINT
To select the current limit set point, we need to find the resistor
value for RLIM. The current limit threshold for the ADP3206 is
set with a 1 V source (VLIM) across RLIM with a gain of 6 mV/µA
per phase. RLIM can be found using the following:
A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. The expressions
given below are intended to yield an optimal starting point for
the design; some adjustments may be necessary to account for
PCB and component parasitic effects.(See Tuning Guide)
A
LIM ×VLIM ×n
RLIM
=
(22)
I
LIM × RO
The first step is to compute the time constants for all of the
poles and zeros in the system:
For values of RLIM greater than 500 kΩ, the current limit may be
lower than expected, so some adjustment of RLIM may be
needed. Here, ILIM is the average current limit for the output of
the supply. For our example, choosing 120 A for ILIM, we find
RL ×VRT 2 × L ×
VVID
1−n × D
n × CX × RO ×VVID
(25)
×VRT
RE = n × RO + AD × RDS
+
+
R
LIM to be 154 kΩ, which is a standard 1% resistance.
The per phase current limit described earlier has its limit
determined by the following:
LX RO − R'
TA = CX ×
(
RO − R'
)
+
×
(26)
RO
×CX (27)
RX
VCOMP
) −VR −VBIAS
MAX
IR
2
(
IPHLIM
≅
−
(23)
TB =
RX + R'−RO
AD × RDS
(
MAX )
⎛
⎞
⎟
⎟
⎠
AD × RDS
2× fSW
For the ADP3206, the maximum COMP voltage (VCOMP(MAX)) is
3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the
current balancing amplifier gain (AD) is 5. Using VR of 1.1 V,
and RDS(MAX) of 4.2 mΩ (low-side ON-resistance at 150°C), we
find a per-phase limit of 66 A.
⎜
V
RT × L −
⎜
⎝
TC =
TD =
(28)
V
VID × RE
CX × C × R2
Z
O
(29)
CX ×
(
RO − R' + CZ × RO
)
This limit can be adjusted by changing the ramp voltage VR. But
make sure not to set the per-phase limit lower than the average
per-phase current (ILIM/n).
where, for the ADP3206, R' is the PCB resistance from the bulk
capacitors to the ceramics and where RDS is the total low-side
MOSFET ON-resistance per phase. For this example, AD is 5,
VRT equals 1.1V, R' is approximately 0.4 mΩ (assuming an
8-layer motherboard) and LX is 150 pH for the six Panasonic SP
capacitors.
The per phase initial duty cycle limit at maximum input voltage
is:
VCOMP
) −VBIAS
MAX
(
DLIM = DMIN = D ×
(24)
VRT
The compensation values can be solved using the following:
For this example, the duty cycle limit at maximum input voltage
is found to be 0.23 when D is 0.07.
n × RO ×TA
CA =
RE × RB
(30)
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3206 allows the best
possible response of the regulator's output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resistance
(RO). With the resistive output impedance, the output voltage
droops in proportion with the load current at any load current
slew rate; this ensures the optimal positioning and allows the
minimization of the output decoupling.
TC
CA
RA =
CB =
(31)
(32)
(33)
TB
RB
TD
RA
CFB
=
The standard values for these components are subject to the
tuning procedure, as introduced in the next section.
With the multimode feedback structure of the ADP3206, one
needs to set the feedback compensation to make the converter's
output impedance work in parallel with the output decoupling.
Rev. 0| Page 23 of 32
ADP3206
The suggested current for the DPRSET pin resistor divider is
CIN SELECTION AND INPUT CURRENT DI/DT
REDUCTION
IDPRSET=50 µA. Therefore, the divider resistors are:
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude of one-nth of the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current happens at
the lowest input voltage, and is given by
VREF − VDPRSET
RDPRSET1
=
=
= 43.5 kΩ (36)
IDPRSLP
VDPRSET
IDPRSLP
RDPRSET2
= 16.5 kΩ (37)
The closest 1% resistors are 43.2 kΩ and 16.5 kΩ.
1
During the transient of entering and exiting Deepersleep, the
slew-rate of VCORE reference voltage change is controlled by the
STSET pin capacitance, which can be calculated as below.
ICRMS = DMAX × IO ×
ICRMS = 01.66 × 80 A ×
−1
N × DMAX
(34)
1
−1 = 9.4 A
4 × 0.166
0.8 ×TDPRSLP × ISTSET
VVIDHFM − VOFFSET − VDPRSLP
CSTSET
=
(38)
In a typical notebook system, the battery rail decouplings are
MLCC capacitors or a mixture of MLCC capacitors and bulk
capacitors. In this example, the input capacitor bank is formed
by 12 pieces of 10 µF, 25 V MLCC capacitors with a ripple
current rating of about 1A each.
TDPRSLP is the longest duration of Deepersleep exit, specified as
100 µs in IMVP-5. ISTSET is the charge and discharge current of
the STSET pin, and has a value of 15 µA. VVIDHFM is the highest
possible VID voltage the system returns when it exits from
Deepersleep. It is specified as 1.350 V in IMVP-5. Therefore,
CSTSET is calculated as 2.4 nF, with the closest standard
capacitance 2.2 nF.
90
VDC = 8V
Figure 4 shows the transition from active mode to Deepersleep
mode. As soon as DPRSLP is asserted, the VCORE voltage is
gradually discharged to Deepersleep voltage (0.8 V). Once the
transition is completed, the PWM outputs of phase 2, 3, and 4
are disabled, switching the converter to single-phase operation.
85
VDC = 12V
VDC = 19V
80
75
10
20
30
40
50
60
70
80
90
LOAD CURRENT (A)
Figure 12. Efficiency of Power Conversion vs. Output Current and Input
Voltage
DEEPERSLEEP VOLTAGE AND TRANSIENT SETTING
The Deepersleep voltage is set on the DPRSET pin via a resistor
divider from VREF voltage, which is 3.0 V. The voltage set on the
DPRSET pin is used as the reference voltage for the error
amplifier when DPRSLP is asserted. Considering there is a zero
load offset voltage, the voltage on the DPRSET pin should be
VDPRSET = VOFFSET +VDPRSLP (35)
Figure 13. Transient to Deepersleep Mode
Channel 1–DPRSLP, Channel 2–VCORE (with 1 V Offset),
Channel 3–Switch Node of Phase 2, Channel 4–SW node of Phase 1.
With VDPRSLP = 0.8 V and VOFFSET = 25 mV, VDPRSET = 0.825 V.
Figure 5 shows the power conversion efficiency improvement of
single-phase operation during Deepersleep.
Rev. 0| Page 24 of 32
ADP3206
90
70
50
SELECTING THERMAL MONITOR COMPONENTS
1-PHASE OPERATION
For single-point hot spot thermal monitoring, simply set RTTSET1
equal to the NTC thermistor's resistance at the alarm tempera-
ture. For example, if VRTT alarm temperature is 100°C and we
use a Vishay thermistor (NTHS-0603N011003J), whose resis-
tance is 100 kΩ at 25°C, and 6.8 kΩ at 100°C, then we simply
can set RTTSET1 = RTH1(100°C) to 6.8 kΩ.
4-PHASE OPERATION
REFERENCE VOLTAGE (3.0V)
REF
R
R
ADP3206
R
R
T
TH1
TSENSE
30
0
1
2
3
4
5
6
C
TTSET1
LOAD CURRENT (A)
TT
Figure 14. Efficiency Improvement in Deepersleep Mode
DEEPSLEEP OFFSET VOLTAGE SETTING
Figure 15. Single-Point Thermal Monitoring
The Deepsleep offset voltage is programmed by a resistor on the
DPSET pin. The voltage on the DPSET pin is equal to the VID
voltage. When DPSLP is asserted, the current programmed on
the DPSET pin is sourced on the FB pin, resulting in an
additional negative offset voltage. The DPSET pin resistor
should be:
Multiple-point hot spots thermal monitoring can be
implemented as shown in Figure 16. If any of the monitored hot
spots reaches alarm temperature, VRTT signal is asserted. The
following calculation sets the alarm temperature:
1
+ VFD
2
VOFFSET
VOS%IFB
VREF
−VFD
RDPSET
=
(39)
RTTSET1
=
RTH1 AlarmTemperature (41)
1
2
VREF
where VOS% is the Deepsleep offset percentage, specified as 1.7%
in IMVP-5. The VOFFSET over IFB term is actually the RB
resistance (see Output Offset section). Thus, RDPSET is calculated
as 98 kΩ, with the closest standard resistance 97.6 kΩ.
where VFD is the forward drop voltage of the parallel diode.
Because the forward current is very small, the forward drop
voltage is very low, i.e., 100 mV. Assuming the same 100°C
alarm temperature used in the single-spot thermal monitoring
example, and the same Vishay thermistor, then the above
formula leads to RTTSET = 7.8 kΩ, whose closest standard resistor
is 7.87 kΩ (1%).
PWRGD MASK TIMER SETTING
The PWRGD (Power Good) mask is programmed by the
capacitance on the PGMASK pin. During the period of
PWRGD masking, there is a source current (IPGMASK = 5 µA) out
of the PGMASK pin, to charge a capacitor, CPGMASK. PWRGD
masking is terminated when the voltage on the PGMASK pin
reaches VPGMASK = 3.0 V.
REFERENCE
VOLTAGE (3.0V)
REF
ADP3206
V
R
R
TH2
FD
R
R
TH1
R
R
THn
T
Thus, the capacitance on the PGMASK pin can be calculated as:
TSENSE
VRTT
TPGMASK × IPGMASK
C
R
R
TTSET2
TT
TTSET1
TTSETn
CPGMASK
=
(40)
VPGMASK
In IMVP-5, the PWRGD mask time is defined as
TPGMASK = 100 µs
Figure 16. Multiple-Point Thermal Monitoring
The number of hot spots monitored is not limited as long as the
current limit of REF pin (4 mA) is not exceeded. The alarm
temperature of each hot spot can be set differently by playing
different RTTSET1, RTTSET2, …RTTSETn.
resulting in CPGMASK = 167 pF. Because the specified TPGMASK is
the maximum length of masking time, please select the next
lower standard capacitance: 150 pF.
Rev. 0| Page 25 of 32
ADP3206
12. Hook up scope to output voltage and set to dc coupling
with time scale at 100 µs/div.
According to IMVP-5, the shortest duration of assertion and
de-assertion of VRTT single is 1 ms (TVRTT = 1 ms). This VRTT
duration is programmed by the RC timer (RTTMASK, CTTMASK) on
the TTMASK pin. If the RC timer is charged by the VCC
voltage (5.0 V), then the RC timer can be set according to the
following formula:
13. Set dynamic load for a transient step of about 40 A at
1 kHz with 50% duty cycle.
14. Measure output waveform (may have to use dc offset on
scope to see waveform). Try to use vertical scale of
100 mV/div or finer.
R
TTMASK × CTTMASK = 2.8 ×TVRTT (42)
Select a standard capacitance CTTMASK = 47 nF, and then the
above formula leads to RTTMASK = 59.6 kΩ, whose next larger
standard resistor is 62 kΩ (5%).
15. You see a waveform that looks something like Figure 17.
Use the horizontal cursors to measure VACDRP and VDCDRP
as shown. Do not measure the undershoot or overshoot
that happens immediately after the step.
TUNING PROCEDURE FOR ADP3206
1. Build circuit based on compensation values computed
from design spreadsheet.
2. Hook-up dc load to circuit, turn on and verify operation.
Check for jitter at no-load and full-load.
V
DC Loadline Setting
ACDRP
3. Measure output voltage at no-load (VNL). Verify it is within
tolerance.
V
DCDRP
4. Measure output voltage at full-load and at cold (VFLCOLD).
Let board set for ~10 minutes at full-load and measure
output (VFLHOT). If there is a change of more than a few
millivolts, adjust RCS1 and RCS2 using Equations 43 and 44.
Figure 17. AC Loadline Waveform
(VNL −VFLCOLD
)
16. If the VACDRP and VDCDRP are different by more than a
couple of millivolts, use the following to adjust CCS. You
may need to parallel different values to get the right one
because there are limited standard capacitor values
available (it is a good idea to have locations for two
capacitors in the layout for this).
RCS2
) = RCS2 ×
(OLD)
(43)
(
NEW
(VNL −VFLHOT
)
5. Repeat Step 4 until cold and hot voltage measurements
remain the same.
6. Measure output voltage from no-load to full-load using 5 A
steps. Compute the load line slope for each change and
then average to get overall load line slope (ROMEAS).
VACDRP
CCS
= CCS ×
OLD
( )
(46)
(
NEW
)
VDCDRP
7. If ROMEAS is off from RO by more than 0.05 mΩ, use the
17. Repeat steps 15-16 and repeat adjustments if necessary.
Once complete, do not change CCS for the rest of the
procedure.
following to adjust the RPH values;
ROMEAS
RO
RPH
) = RPH ×
(OLD)
(45)
(
NEW
18. Set dynamic load step to maximum step size (do not use a
step size larger than you need) and verify output waveform
is square (which means VACDRP and VDCDRP are equal).
8. Repeat steps 6-7 to check load line and repeat adjustments
if necessary.
Note: Makes sure load step slew rate and turn-on are set for a
slew rate of ~150-250 A/µs (for example, a load step of 50 A
should take 200-300 ns) with no overshoot. Some dynamic
loads have an excessive turn-on overshoot if a minimum
current is not set properly (this is an issue if you are using a
VTT tool).
9. Once complete with dc load line adjustment, do not change
RPH, RCS1, RCS2, or RTH for rest of procedure.
10. Measure output ripple at no-load and full-load with scope
and make sure it is within spec.
AC Loadline Setting
11. Remove dc load from circuit and hook up dynamic load.
Rev. 0| Page 26 of 32
ADP3206
Initial Transient Setting
Figure 20 shows the typical transient response using these
compensation values.
19. With dynamic load still set at maximum step size, expand
scope time scale to see 2-5 µs/div. You see a waveform that
may have two overshoots and one minor undershoot (see
Figure 18). Here, VDROOP is the final desired value.
V
DROOP
V
TRAN1
V
TRAN2
(a)
Figure 18. Transient Setting Waveform, Load Step
20. If both overshoots are larger than desired, try making the
following adjustments in this order (NOTE—if these
adjustments do not change the response, you are limited by
the output decoupling). Check the output response each
time you make a change as well as the switching nodes (to
make sure it is still stable).
a. Make ramp resistor larger by 25% (RRAMP).
b. For VTRAN1, increase CB or increase switching
frequency.
c. For VTRAN2, increase RA and decrease CA both by 25%.
21. For load release (see Figure 19), if VTRANREL is larger than
the IMVP-5 specification, you do not have enough output
capacitance. You either need more capacitance or to make
the inductor values smaller (if you change inductors, you
need to start the design over using the spreadsheet and this
tuning guide).
(b)
Figure 20. Typical Transient Response for Design Example
(a) Load Step, (b) Load Release
V
TRANREL
V
DROOP
Figure 19. Transient Setting Waveform, Load Release
Rev. 0| Page 27 of 32
ADP3206
LAYOUT AND COMPONENT PLACEMENT
results in EMI problems for the entire PC system as well as
noise-related operational problems in the power converter
control circuitry. The switching power path is the loop formed
by the current path through the input capacitors and the power
MOSFETs including all interconnecting PCB traces and planes.
The use of short and wide interconnection traces is especially
critical in this path for two reasons: it minimizes the inductance
in the switching loop, which can cause high-energy ringing, and
it accommodates the high current demand with minimal
voltage loss.
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
GENERAL RECOMMENDATIONS
For good results, at least a four-layer PCB is recommended. This
should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input, and output power, and wide interconnection
traces in the rest of the power delivery current paths. Keep in
mind that each square unit of 1 ounce copper trace has a
resistance of ~0.53 mΩ at room temperature.
Whenever a power dissipating component (for example, a
power MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons for this
are: improved current rating through the vias, and improved
thermal performance from vias extended to the opposite side of
the PCB where a plane can more readily transfer the heat to the
air. Make a mirror image of any pad being used to heat sink the
MOSFETs on the opposite side of the PCB to achieve the best
thermal dissipation to the air around the board. To further
improve thermal performance, the largest possible pad area
should be used.
Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by these
current paths is minimized and the via current rating is not
exceeded.
If critical signal lines (including the output voltage sense lines of
the ADP3206) must cross through power circuitry, it is best if a
signal ground plane can be interposed between those signal
lines and the traces of the power circuitry. This serves as a
shield to minimize noise injection into the signals at the
expense of making signal ground a bit noisier.
The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.
An analog ground plane should be used around and under the
ADP3206 for referencing the components associated with the
controller. This plane should be tied to the nearest output de-
coupling capacitor ground and should not be tied to any other
power circuitry to prevent power currents from flowing in it.
For best EMI containment, a solid power ground plane should
be used as one of the inner layers extending fully under all the
power components.
The components around the ADP3206 should be located close
to the controller with short traces. The most important traces to
keep short and away from other traces are the FB and CSSUM
pins. See Figure 2 for details on layout for the CSSUM node.
SIGNAL CIRCUITRY
The output voltage is sensed and regulated between the FB pin
and the FBRTN pin (which connects to the signal ground at the
load). In order to avoid differential mode noise pickup in the
sensed signal, the loop area should be small. Thus the FB and
FBRTN traces should be routed adjacent to each other atop the
power ground plane back to the controller.
The output capacitors should be connected as closely as possible
to the load (or connector) that receives the power (e.g., a
microprocessor core). If the load is distributed, the capacitors
should also be distributed, and generally in proportion to where
the load tends to be more dynamic.
The feedback traces from the switch nodes should be connected
as close as possible to the inductor. The CSREF signal should be
Kelvin connected to the center point of the copper bar which is
the VCORE common node for the inductors of all the phases.
Avoid crossing any signal lines over the switching power path
loop, described below.
POWER CIRCUITRY
The ADP3206 has a metal pad in the back side of the package.
This metal pad is not a ground node. Do not ground this metal
pad. In addition, vias under the ADP3206 are not
The switching power path should be routed on the PCB to
encompass the shortest possible length in order to minimize
radiated switching noise energy (i.e., EMI) and conduction
losses in the board. Failure to take proper precautions often
recommended, because the metal pad may short between vias.
Rev. 0| Page 28 of 32
ADP3206
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
40
1
30
PIN 1
INDICATOR
0.50
BSC
4.25
4.10 SQ
3.95
TOP
VIEW
5.75
BSC SQ
BOTTOM
VIEW
0.50
0.40
0.30
21
10
11
20
0.25 MIN
4.50
REF
12° MAX
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 21. 40-Lead Frame Chip Scale Package [LFCSP]
(CP-40)
Dimensions shown in millimeters
Rev. 0| Page 29 of 32
ADP3206
ORDERING GUIDE
Model
Temperature Package
Package Description
Package Option
ADP3206JCPZ-REEL1
0°C to +100°C
Lead Frame Chip Scale Package
CP-40
1 Z = Pb-free part.
Rev. 0| Page 30 of 32
ADP3206
NOTES
Rev. 0| Page 31 of 32
ADP3206
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04651-0-4/04(0)
Rev. 0| Page 32 of 32
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