ADP3207JCPZ-RL_技术文档

7-Bit Programmable Multiphase Mobile

CPU Synchronous Buck Controller

ADP3207

FUNCTIONAL BLOCK DIAGRAM

FEATURES

VCC

VRPM RRPM RT RAMPADJ

1-, 2-, or 3-phase operation at up to 750 kHz per phase

31

12 13 14 15

8 mꢀ worst-case differential sensing error over

temperature

Interleaved PWM outputs for driving external high power

MOSFET drivers

Automatic power-saving modes maximize efficiency during

light load and deeper sleep operation

ADP3207

1

EN

UVLO

SHUTDOWN

AND BIAS

OSCILLATOR

SET EN

RESET

+

GND

20

30

26 PWM1

25 PWM2

CMP

–

1/2/3 – PHASE

TTSENSE

DRIVER

CURRENT

BALANCING

CIRCUIT

THERMAL

THROTTLING

CONTROL

LOGIC

+

RESET

CMP

–

29

VRTT

+

Soft transient control reduces inrush current and audio noise

Active current balancing between output phases

Independent current limit and load line setting inputs for

additional design flexibility

Built-in power-good masking supports ꢀID on-the-fly

7-bit digitally programmable 0.3 ꢀ to 1.5 ꢀ output

Overload and short-circuit protection with programmable

latch-off delay

24

RESET

CMP

–

PWM3

–

+

1.7V

CSREF

CROWBAR

–

+

DAC + 200mV

CSREF

CURRENT LIMIT

23 SW1

22 SW2

21 SW3

+

–

DAC – 300mV

DELAY

3

2

PGDELAY

PWRGD

19 CSCOMP

–

11

18

Built-in clock enable output delays CPU clock until CPU

supply voltage stabilizes

ILIMIT

CSSUM

CURRENT

+

LIMIT

CIRCUIT

17

6

CSREF

FB

4

7

CLKEN

COMP

SOFT

START

–

+

APPLICATIONS

Notebook power supplies for next generation Intel®

processors

16 LLSET

+

–

33

32

10

9

DPRSTP

PSI

SOFT START/

BOOT/

DEEPER

SLEEP

CONTROL

DPRSLP

STSET

DCM

GENERAL DESCRIPTION

28

27

8

1

The ADP3207 is a high efficiency, multiphase, synchronous,

PRECISION

REFERENCE

OD

buck-switching regulator controller optimized for converting

notebook battery voltage into the core supply voltage required

by high performance Intel processors. The part uses an internal

7-bit DAC to read voltage identification (VID) code directly

from the processor that sets the output voltage. The phase

relationship of the output signals can be programmed to

provide 1-, 2-, or 3-phase operation, allowing for the

SS

VID

DAC

5

34 35 36 37 38 39 40

Figure 1.

The chip also provides accurate and reliable short-circuit

construction of up to three interleaved buck-switching stages.

protection, adjustable current limiting, and a delayed power-

good output that accommodates on-the-fly output voltage

changes requested by the CPU.

The ADP3207 uses a multimode architecture to drive the logic-

level PWM outputs at a programmable switching frequency that

can be optimized depending on the output current requirement.

The part switches between multiphase and single-phase operation

to maximize its effectiveness under all load conditions. In addition,

the ADP3207 includes a programmable slope function to adjust

the output voltage as a function of the load current. As a result,

it is always best positioned for a system transient.

The ADP3207 is specified over the extended commercial

temperature range of 0°C to 100°C and is available in a 40-lead

LFCSP package.

¹Patent 6,683,441.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADP3207

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Test Circuits ....................................................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 11

Number of Phases....................................................................... 11

Operation Modes........................................................................ 11

Switch Frequency Setting .......................................................... 12

Output Voltage Differential Sensing........................................ 12

Output Current Sensing ............................................................ 12

Active Impedance Control Mode............................................. 13

Current Control Mode and Thermal Balance ........................ 13

Voltage Control Mode................................................................ 13

Power-Good Monitoring........................................................... 13

Power-Up Sequence and Soft Start .......................................... 14

Soft Transient .............................................................................. 14

Current-Limit, Short-Circuit, and Latch-Off Protection...... 15

Changing VID on-the-Fly......................................................... 15

Output Crowbar ......................................................................... 16

Reverse Voltage Protection ....................................................... 16

Output Enable and UVLO ........................................................ 16

Thermal Throttling Control ..................................................... 16

Application Information................................................................ 20

Setting the Clock Frequency for PWM Mode........................ 20

Soft-Start and Current-Limit Latch-Off Delay Times........... 20

PWRGD Delay Timer................................................................ 20

Inductor Selection...................................................................... 20

C_OUTSelection ............................................................................. 22

Power MOSFETs......................................................................... 23

Ramp Resistor Selection............................................................ 24

Setting the Switching Frequency for RPM Mode Operation of

Phase 1 ......................................................................................... 25

Current-Limit Setpoint.............................................................. 25

Feedback Loop Compensation Design.................................... 25

C_INSelection and Input Current D_I/D_TReduction................ 26

Soft Transient Setting................................................................. 26

Selecting Thermal Monitor Components............................... 26

Tuning Procedure for ADP3207............................................... 27

Layout and Component Placement ......................................... 28

Outline Dimensions....................................................................... 30

Ordering Guide .......................................................................... 30

REꢀISION HISTORY

1/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

ADP3207

SPECIFICATIONS

VCC = 5 V, FBRTN = GND, EN = VCC, V_VID= 0.50 V to 1.5000 V,

T_A= 0°C to 100°C, unless otherwise noted.¹

PSI

DPRSTP

= 1.05 V, LLSET = CSREF,

= 1.05 V, DPRSLP = GND,

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Units

VOLTAGE ERROR AMPLIFIER

Output Voltage Range²

VID DAC DC Accuracy

V_COMP

V_FB− V_VID

V_FB(BOOT)

0.85

−8

4.0

+8

V

mV

V

Measured at FB, relative to V_VID, see Figure 2

Measured at end of start-up

1.192 1.200 1.208

Load Line Positioning DC Accuracy V_FB− V_VID

Differential Nonlinearity²

Measured at FB, relative to V_VID, LLSET – CSREF = −80 mV

−78

−1

−80

−82

+1

mV

LSB

%

Line Regulation

VCC = 4.75 V to 5.25 V

0.05

∆V_FB

I_FB

Input Bias Current

Output Current

Gain Bandwidth Product

Slew Rate

−1

+1

µA

mA

MHz

I_COMP

GBW_(ERR)

FB forced to V_OUT– 3%

COMP = FB

C_COMP= 10 pF

3

20

25

V/µs

LLSET Input Voltage Range²

LLSET Input Bias Current

FBRTN Current

V_LLSET

I_LLSET

I_FBRTN

Relative to CSREF

−200

−100

+200 mV

+100 nA

400

70

µA

VID DAC INPUTS

Input Low Voltage

Input High Voltage

Input Current

V_IL

V_IH

I_IN(VID)

VID_X

0.5

−1

0.3

V

0.7

µA

ns

VID Transition Delay Time²

VID change to FB change

400

OSCILLATOR

Frequency Range²

f_OSC

PSI = DPRSTP = 1.05 V, DPRSLP = GND

0.3

3

MHz

kHz

V

Frequency Setting

f_PHASE

155

200

300

600

1.1

245

T_A= +25°C, V_VID= 1.2000 V, R_T= 215 kΩ

T_A= +25°C, PWM3 = VCC, V_VID= 1.2000 V, R_T= 215 kΩ

T_A= +25°C, PWM2 = VCC, V_VID= 1.2000 V, R_T= 215 kΩ

I_RAMPADJ= 60 µA

RAMPADJ Voltage

RAMPADJ Input Current Range²

V_RAMPADJ

I_RAMPADJ

0.9

1

1.2

120

+1

In normal mode

60

µA

In shutdown, or in UVLO, RAMPADJ = 19 V

−1

RPM

RT Voltage

V_RT

1.08

.95

1.0

1.2

1

1.03

−5.5

1

1.32

1.05

1.10

V

R_T= 215 kΩ to GND, V_VID= 1.4000 V

I_VRPM= 0

I_VRPM= 120 µA

VRPM Reference Voltage

V_VRPM

V

RRPM Output Current

RPM Comparator Offset

I_RRPM

V_VID= 1.2 V, R_T= 215 kΩ

V_OS(RPM)= V_COMP− V_RRPM, PSI = GND

µA

mV

V_OS(RPM)

CURRENT-SENSE AMPLIFIER

Offset Voltage

Input Bias Current

Gain Bandwidth Product

Slew Rate

Input Common-Mode Range²

Output Voltage Range²

Output Current

V_OS(CSA)

I_BIAS(CSSUM)

GBW_(CSA)

CSSUM – CSREF

−1.0

−50

+1.0

+50

mV

nA

MHz

V/µs

V

10

C_CSCOMP= 10 pF

CSSUM and CSREF

0

0.05

3.5

2.0

V

I_CSCOMP

Sinking Current

470

µA

Rev. 0 | Page 3 of 32

ADP3207

Parameter

Symbol

Conditions

Min

Typ

Max

Units

CURRENT BALANCE AMPLIFIER

Common Mode Range²

Input Resistance

V_SW(X)CM

R_SW(X)

I_SW(X)

−600

30

3

+200 mV

SW_X= 0 V

40

4.5

60

6

kΩ

µA

%

Input Current

Input Current Matching

SW_X= 0 V

−5

+5

∆I_SW(X)

Zero Current Switching

Threshold Voltage

V_DCM(SW1)

In DCM mode, DPRSLP = 3.3 V

−6

mV

Masked Off-Time

t_OFFMSKD

Measured from PWM turn-off

350

ns

CURRENT-LIMIT COMPARATOR

ILIMIT Voltage

ILIMIT Current

Maximum ILIMIT Current²

Current-Limit Threshold Voltage

V_ILIMIT

I_ILIMIT

R_ILIMIT= 113 kΩ

1.65

1.7

−15

1.75

V

µA

mV

−60

180

V_CL

V_CSREF– V_CSCOMP, R_ILIMIT= 113 kΩ, PSI = 1.05 V

192

210

V_CSREF– V_CSCOMP, R_ILIMIT= 113 kΩ, 1-phase, (PWM2 =

VCC), PSI = GND

V_CSREF– V_CSCOMP, R_ILIMIT= 113 kΩ, 2-phase, (PWM3 =

VCC), PSI = GND

86

55

96

64

107

72

mV

V_CSREF– V_CSCOMP, R_ILIMIT= 113 kΩ, 3-phase,

(neither PWM2 = VCC nor PWM3 = VCC), PSI = GND

SOFT START TIMER

SS Current

I_SS

During start-up, V_SS< 1.7 V

In normal mode, V_SS= 2.0 V

In current limit, V_SS= 2.0 V

During start-up, SS is rising

In normal mode

−10

−8

−48

2

1.7

2.9

1.7

−6

µA

V

1.5

1.6

2.5

1.8

SS Termination Threshold Voltage V_TH(SS)

SS Clamp Voltage

Current-Limit Latch-Off Voltage

SOFT TRANSIENT CONTROL

STSET Current

V

V_ILO(SS)

In current limit, SS is falling

1.6

1.8

V

I_{SOURCE(STSET)}Fast exit from deeper sleep,

DPRSLP = 0 V, STSET = V_DAC– 0.3 V

−8

µA

Slow exit from deeper sleep,

DPRSLP = 3.3 V, STSET = V_DAC– 0.3 V

Slow entry to deeper sleep,

−2.5

+2.5

DPRSLP = 3.3 V, STSET = V_DAC+ 0.3 V

Minimum STSET Capacitance²

C_STSET

100

pF

Long Transient Threshold Accuracy V_OS(SSMASK)

V_OS(SSMASK)= V_STSET– V_DAC

170

mV

SYSTEM INTERFACE CONTROL

INPUTS

PSI and DPRSTP

Input Low Voltage

Input High Voltage

DPRSLP and EN

Input Low Voltage

Input High Voltage

V_IL

V_IH

0.5

0.3

1.0

V

0.7

2.3

V_IL

V_IH

1.3

1.9

V

THERMAL THROTTLING CONTROL

TTSENSE Voltage Range²

TTSENSE VRTT Threshold Voltage

TTSENSE VRTT Hysteresis

TTSENSE Bias Current

0

5

2.55

V

mV

µA

mV

V

VCC = 5 V, TTSENSE is falling

2.45

50

−2

2.5

95

TTSENSE = 2.6 V

I_VRTT(SINK)= 400 µA

I_VRTT(SOURCE)= 400 µA

2

500

VRTT Output Low Voltage

VRTT Output High Voltage

V_OL(VRTT)

V_OH(VRTT)

10

5

4

Rev. 0 | Page 4 of 32

ADP3207

Parameter

Symbol

Conditions

Min

Typ

Max

Units

POWER-GOOD COMPARATOR

Undervoltage Threshold

Overvoltage Threshold

Output Low Voltage

Output Leakage Current

Power-Good Delay Timer

PGDELAY Threshold

PGDELAY Charge Current

PGDELAY Discharge Resistance R_PGDELAY

Power-Good Masking Time

V_CSREF(UV)

V_CSREF(OV)

V_PWRGD(L)

I_PWRGD

Relative to nominal DAC voltage

I_PWRGD(SINK)= 4 mA

−240 −300 −360 mV

150

200

85

250

3

mV

μA

V_PWRDG= 5 V

V_PGDELAY(TH)

I_PGDELAY

2.9

1.9

550

130

1.7

V

µA

V_PGDELAY= 2.0 V

V_PGDELAY= 0.2 V

Ω

μs

V

Crowbar Threshold Voltage

Reverse Voltage Detection

Threshold

V_CSREF(CB)

V_CSREF(RV)

Relative to FBRTN

1.65

1.75

CSREF is falling

CSREF is rising

−300 −350 mV

−75

−10

mV

CLKEN OUTPUT

Output Low Voltage

I _CLKEN(SINK)= 4 mA

30

400

3

mV

µA

Output Leakage Current

V_CLKEN= 5 V, V_SS= GND

OD/DCM OUTPUTS

Output Low Voltage

Output High Voltage

PWM OUTPUTS

Output Low Voltage

Output High Voltage

SUPPLY

V_OL

V_OH

I_SINK= 400 µA

I_SOURCE= 400 µA

10

5

500

mV

V

4

V_OL(PWM)

V_OH(PWM)

I_PWM(SINK)= 400 µA

I_PWM(SOURCE)= 400 µA

10

5

mV

V

4.0

4.5

Supply Voltage Range

Supply Current

V_CC

5.5

10

300

4.5

V

Normal mode

EN = 0 V

VCC is rising

VCC is falling

4.2

190

4.4

4.15

260

mA

µA

V

mV

VCCOK Threshold Voltage

VCC UVLO Threshold Voltage

VCC Hysteresis²

V_CCOK

V_CCUVLO

4.0

¹All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).

²Guaranteed by design or bench characterization, not production tested.

Rev. 0 | Page 5 of 32

ADP3207

TEST CIRCUITS

7-BIT CODE

5V

ADP3207

+

1µF

100nF

VCC

31

5V

40

COMP

FB

7

6

1

TTSENSE

VRTT

DCM

3.3V

EN

PWRGD

PGDELAY

CLKEN

FBRTN

FB

COMP

SS

10kΩ

OD

ADP3207

PWM1

PWM2

PWM3

SW1

SW2

SW3

1kΩ

STSET

DPRSLP

10nF

LLSET

CSREF

GND

16

∆V

17

VID DAC

V

DAC

1.0V

113kΩ

20kΩ

V

DAC

20

∆V = FB = 80mV – FB

FB ∆V

100nF

∆V = 0mV

Figure 2. Closed-Loop Output Voltage Accuracy

Figure 4. Positioning Accuracy

ADP3207

VCC

31

5V

CSCOMP

19

100nF

39kΩ

CSSUM

18

1kΩ

CSREF

17

1.0V

GND

CSCOMP – 1V

=

OS

20

V

40

Figure 3. Current-Sense Amplifier V_OS

Rev. 0 | Page 6 of 32

ADP3207

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

VCC

FBRTN

SW1 to SW3

–0.3 V to +6 V

–0.3 V to +0.3 V

−10 V to +25 V

–0.3 V to +25 V

–0.3 V to VCC + 0.3 V

–65°C to +150°C

0°C to 100°C

125°C

RAMPADJ (In Shutdown)

All Other Inputs and Outputs

Storage Temperature

Operating Ambient Temperature Range

Operating Junction Temperature

Thermal Impedance (θ_JA)

Lead Temperature

Soldering (10 sec)

Absolute maximum ratings apply individually only, not in

combination. Unless otherwise specified, all other voltages are

referenced to GND.

98°C/W

300°C

260°C

Infrared (15 sec)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page 7 of 32

ADP3207

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

35 34

36

33 32 31

40 39 38 37

30

29

1

2

TTSENSE

VRTT

EN

PIN 1

INDICATOR

PWRGD

28 DCM

27

3

PGDELAY

OD

4

5

6

7

8

ADP3207

CLKEN

FBRTN

TOP VIEW

(Not to Scale)

26 PWM1

25

PWM2

FB

24

PWM3

COMP

SS

23

SW1

22

SW2

9

STSET

21

SW3

10

DPRSLP

16 17 18 19 20

15

11 12 13 14

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

EN

PWRGD

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.

Power-Good Output. Open drain output that signals when the output voltage is outside of the proper operating

range. The pull-high voltage on this pin cannot be higher than VCC.

3

4

5

6

7

8

PGDELAY

CLKEN

FBRTN

FB

COMP

SS

Power-Good Delay Setting Input. A capacitor between this pin and GND sets the power-good delay time.

Clock Enable Output. The pull-high voltage on this pin cannot be higher than VCC.

Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

Feedback Input. Error amplifier input for remote sensing of the output voltage.

Error Amplifier Output and Compensation Point.

Soft-Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft-start

ramp-up time and the current-limit latch-off delay time.

9

STSET

Soft Transient Slew Rate Timing Input. A capacitor from this pin to GND sets the slew rate of the output voltage

when transitioning between the boot voltage and the programmed VID voltage, and when transitioning

between active mode and deeper sleep mode.

10

11

12

13

14

DPRSLP

ILIMIT

VRPM

RRPM

RT

Deeper Sleep Control Input.

Current-Limit Setpoint. An external resistor from this pin to GND sets the current-limit threshold of the converter.

RPM Mode Reference Voltage Output.

RPM Mode Timing Control Input. A resistor between this pin and VRPM sets the RPM mode turn-on threshold voltage.

Multiphase Frequency Setting Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device when operating in multiphase PWM mode.

15

16

17

RAMPADJ

LLSET

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM

ramp.

Output Load Line Programming Input. The center point of a resistor divider between CSREF and CSCOMP is

connected to this pin to set the load line slope.

Current-Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-sense

amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the

output inductors.

CSREF

18

19

CSSUM

CSCOMP

GND

Current-Sense Summing Node. External resistors from each switch node to this pin sum the inductor currents

together to measure the total output current.

Current-Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of the

current-sense amplifier and the positioning loop response time.

20

Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

21 to 23

SW3 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases

should be left open.

Rev. 0 | Page 8 of 32

ADP3207

Pin No.

Mnemonic

Description

24 to 26

PWM3 to

PWM1

Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3419. Connecting the PWM2 and/or PWM3 outputs to VCC causes that phase to turn off, allowing the

ADP3207 to operate as a 1-, 2-, or 3-phase controller.

27

28

29

30

OD

Multiphase Output Disable Logic Output. This pin is actively pulled low when the ADP3207 enters single-phase mode

or during shutdown. Connect this pin to the SD inputs of the Phase-2 and Phase-3 MOSFET drivers.

Discontinuous Current Mode Enable Output. This pin is actively pulled low when the single-phase inductor

current crosses zero.

Voltage Regulator Thermal Throttling Logic Output. This pin goes high if the temperature at the monitoring point

connected to TTSENSE exceeds the programmed VRTT temperature threshold.

Thermal Throttling Sense Input and OVP Disable. The center point of a resistor divider (where the lower resistor is

an NTC thermistor) between VCC and GND is connected to this pin to remotely sense the temperature at the

desired thermal monitoring point. Grounding TTSENSE disables OVP function.

DCM

VRTT

TTSENSE

31

VCC

Supply Voltage for the Device.

32

PSI

Power State Indicator Input. Pulling this pin to GND forces the ADP3207 to operate in single-phase mode.

Deeper Stop Control Input.

33

DPRSTP

34 to 40

VID6 to

VID0

Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB regulation

voltage from 0.3 V to 1.5 V (see Table 6).

Rev. 0 | Page 9 of 32

ADP3207

TYPICAL PERFORMANCE CHARACTERISTICS

2500

250

200

150

100

2000

VID = 1.2875V

3-PHASE PSI = HIGH

1500

VID = 1.1500V

1000

VID = 0.8375V

2-PHASE PSI = LOW

3-PHASE PSI = LOW

500

0

50

0

100

200

300

(kΩ)

400

500

600

100

200

300

400

500

600

700

800

900 1000

R

(kΩ)

T

LIMIT

Figure 8. Current-Limit Threshold Voltage vs. R_LIMIT

Figure 6. Master Clock Frequency vs. R_T

400

350

300

250

200

150

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

VID (V)

Figure 7. Master Clock vs. VID

Rev. 0 | Page 10 of 32

ADP3207

THEORY OF OPERATION

The ADP3207 combines a multimode PWM/RPM (ramp pulse

modulated) control with multiphase logic outputs for use in 1-,

2-, and 3-phase synchronous buck CPU core supply power

converters. The internal 7-bit VID DAC conforms to Intel

IMVP-6 specifications. Multiphase operation is important for

producing the high currents and low voltages demanded by

today’s microprocessors. Handling high currents in a single-

phase converter puts high thermal stress on the system

components such as the inductors and MOSFETs.

The PWM outputs are 5 V logic-level signals intended for

driving external gate drivers such as the ADP3419. Because

each phase is monitored independently, operation approaching

100% duty cycle is possible. In addition, more than one output

can operate at a time to allow overlapping phases.

OPERATION MODES

For ADP3207, the number of phases can be selected by the user

as described in the Number of Phases section, or they can

dynamically change based on system signals to optimize the

power conversion efficiency at heavy and light CPU loads.

The multimode control of the ADP3207 ensures a stable high

performance topology for:

During a VID transient or at a heavy load condition, indicated

•

Balancing currents and thermals between phases

PSI

by DPRSLP going low and

going high, the ADP3207 runs

in full-phase mode. All user selected phases operate in inter-

leaved PWM mode that results in minimal V_COREripple

and best transient performance. While in light load mode,

High speed response at the lowest possible switching

frequency and minimal output decoupling

•

Minimizing thermal switching losses due to lower

frequency operation

PSI

indicated by either

going low or DPRSLP going high,

only Phase 1 of ADP3207 is in operation to maximize

power conversion efficiency.

•

Tight load line regulation and accuracy

In addition to the change of phase number, the ADP3207

dynamically changes operation modes. In multiphase operation,

the ADP3207 runs in PWM mode, with switching frequency

controlled by the master clock. In single-phase mode based on

High current output by supporting up to 3-phase operation

Reduced output ripple due to multiphase ripple cancellation

High power conversion efficiency both at heavy load and

light load

PSI

signal, the ADP3207 switches to RPM mode, where the

switching frequency is no longer controlled by the master clock,

but by the ripple voltage appearing on the COMP pin. The

PWM1 pin is set to high each time the COMP pin voltage rises

to a limit determined by the VID voltage and programmed

by the external resistor connected between Pin VRPM and

Pin RRPM. In single-phase mode based on the DPRSLP signal,

the ADP3207 runs in RPM mode, with the synchronous

rectifier (low-side) MOSFETs of Phase 1 being controlled by the

•

PC board layout noise immunity

Ease of use and design due to independent component

selection

•

Flexibility in operation by allowing optimization of design

for low cost or high performance

DCM

pin to prevent any reverse inductor current. Thus, the

NUMBER OF PHASES

switch frequency varies with the load current, resulting in

maximum power conversion efficiency in deeper sleep mode of

CPU operation. In addition, during any VID transient, system

transient (entry/exit of deeper sleep), or current limit, the

ADP3207 goes into full phase mode, regardless of DPRSLP and

The number of operational phases and their phase relationship

is determined by internal circuitry that monitors the PWM

outputs. Normally, the ADP3207 operates as a 3-phase

controller. For 2-phase operation, the PWM3 pin is connected

to VCC 5 V programs, and for 1-phase operation, the PWM3

and PWM2 pins are connected to VCC 5 V programs.

PSI

signals, eliminating current stress to Phase 1.

Table 4 summarizes how the ADP3207 dynamically changes

phase number and operation modes based on system signals

and operating conditions.

When the ADP3207 is initially enabled, the controller sinks 50 µA

on the PWM2 and PWM3 pins. An internal comparator checks

the voltage of each pin against a high threshold of 3 V. If the pin

voltage is high due to pull up to the VCC 5 V rail, then the

phase is disabled. The phase detection is made during the first

three clock cycles of the internal oscillator. After phase detection,

the 50 µA current sink is removed. The pins that are not connected

to the VCC 5 V rail function as normal PWM outputs. The pins

that are connected to VCC enter into high impedance state.

Rev. 0 | Page 11 of 32

ADP3207

Table 4. Phase Number and Operation Modes

ꢀID Transient

Hit Current

No. of Phases

Selected by User

No. of Phases

in Operation

Period¹

Limit

DNC²

No

Yes

No

Operation Mode

PWM, CCM³only

RPM, CCM³only

PWM, CCM³only

RPM, automatic CCM³/DCM⁴

PWM, CCM³only

PSI

DNC²DNC²

DPRSLP

Yes

No

N 3, 2, or 1

DNC²

N

1

0

1

0

Phase 1 only

N

Phase 1 only

N

DNC²

Yes

DNC²

¹VID transient period is the time period following any VID change, including entrance and exit of deeper sleep mode. The duration of VID transient period is the same

as that of PWRGD masking time.

²DNC means do not care.

³CCM means continuous conduction mode

⁴DCM means discontinuous conduction mode.

SWITCH FREQUENCY SETTING

OUTPUT ꢀOLTAGE DIFFERENTIAL SENSING

Master Clock Frequency for PWM Mode

The ADP3207 combines differential sensing with a high accuracy,

VID DAC, precision REF output and a low offset error amplifier to

meet the rigorous accuracy requirement of the Intel IMVP-6

specification. In steady-state, the VID DAC and error amplifier

meet the worst-case error specification of 10 mV over the full

operating output voltage and temperature range.

The clock frequency of the ADP3207 is set by an external

resistor connected from the RT pin to ground. The frequency

varies with the VID voltage: the lower the VID voltage, the

lower the clock frequency. The variation of clock frequency

with VID voltage makes V_COREripple remain constant and

improves power conversion efficiency at a lower VID voltage.

Figure 6 shows the relationship between clock frequency and

VID voltage, parameterized by RT resistance.

The CPU core output voltage is sensed between the FB and

FBRTN pins. Connect FB through a resistor to the positive

regulation point, usually the VCC remote sense pin of the

microprocessor. Connect FBRTN directly to the negative

remote sense point, the VSS sense point of the CPU. The

internal VID DAC and precision voltage reference are

referenced to FBRTN, and have a maximum current of 200 µA

to guarantee accurate remote sensing.

To determine the switching frequency per phase, the clock is

divided by the number of phases in use. If PWM3 is pulled up

to VCC, then the master clock is divided by 2 for the frequency

of the remaining phases. If PWM2 and PWM3 are pulled up to

VCC, then the switching frequency of a Phase 1 equals the

master clock frequency. If all phases are in use, divide by 3.

OUTPUT CURRENT SENSING

Switching Frequency for RPM Mode–Phase 1

The ADP3207 provides a dedicated current-sense amplifier

(CSA) to monitor the total output current of the converter for

proper voltage positioning vs. load current, and for current-

limit detection. Sensing the load current being delivered to the

load is inherently more accurate than detecting peak current or

sampling the current across a sense element, such as the low-

side MOSFET. The current-sense amplifier can be configured

several ways depending on system requirements.

When ADP3207 operates in single-phase RPM mode, its

switching frequency is not controlled by the master clock, but

by the ripple voltage on the COMP pin. The PWM1 pin is set

high each time the COMP pin voltage rises to a voltage limit

determined by the VID voltage and the external resistance

connected between Pin VRPM and Pin RRPM. Whenever

PWM1 pin is high, an internal ramp signal rises at a slew rate

programmed by the current flowing into the RAMPADJ pin.

Once this internal ramp signal hits the COMP pin voltage, the

PWM1 pin is reset to low.

•

Output inductor ESR sensing without use of a thermistor

for lowest cost

Output inductor ESR sensing with use of a thermistor that

tracks inductor temperature to improve accuracy

In continuous current mode, the switching frequency of RPM

operation is maintained almost constantly. While in

discontinuous current mode, the switching frequency reduces

with the load current.

Discrete resistor sensing for highest accuracy

Rev. 0 | Page 12 of 32

ADP3207

The positive input of the CSA is connected to the CSREF pin,

which is connected to the output voltage. At the negative input

CSSUM pin of the CSA, signals from the sensing element

(that is, in case of inductor RDC sensing, signals from the

switch node side of the output inductors) are summed together

by using series summing resistors. The feedback resistor

between CSCOMP and CSSUM sets the gain of the current-

sense amplifier, and a filter capacitor is placed in parallel

with this resistor. The current information is then given as

the voltage difference between CSREF and CSCOMP. This

signal is used internally as a differential input for the current-

limit comparator.

The magnitude of the internal ramp can be set so the transient

response of the system becomes optimal. The ADP3207 also

monitors the supply voltage to achieve feed-forward control

whenever the supply voltage changes. A resistor connected from

the power input voltage rail to the RAMPADJ pin determines

the slope of the internal PWM ramp. Detailed information

about programming the ramp is given in the Ramp Resistor

Selection section.

External resistors can be placed in series with the SW2 and SW3

pins to create an intentional current imbalance, if desired. Such

a condition can exist when one phase has better cooling and

supports higher currents than the other phase. Resistor RSW2

and Resistor RSW3 (see the typical application circuit in Figure 10)

can be used to adjust thermal balance. It is recommended to

add these resistors during the initial design to make sure

placeholders are provided in the layout.

An additional resistor divider connected between CSREF and

CSCOMP with the midpoint connected to LLSET can be used

to set the load line required by the microprocessor specification.

The current information for load line setting is then given as

the voltage difference of CSREF − LLSET. The configuration in

the previous paragraph makes it possible for the load line slope

to be set independently of the current-limit threshold. In the

event that the current-limit threshold and load line do not have

to be independent, the resistor divider between CSREF and

CSCOMP can be omitted and the CSCOMP pin can be

To increase the current in any given phase, users should make

RSW for that phase larger (that is, make RSW = 0 for the hottest

phase and do not change it during balance optimization).

Increasing RSW to 500 Ω makes a substantial increase in phase

current. Increase each RSW value by small amounts to achieve

thermal balance starting with the coolest phase.

connected directly to LLSET. To disable voltage positioning

entirely (that is, to set no load line), tie LLSET to CSREF.

When current limit is reached, the ADP3207 switches to full-

PSI

phase PWM mode, regardless of System Signal DRPSLP and

to avoid inrush current stress to the Phase 1 power stage.

,

To provide the best accuracy for current sensing, the CSA is

designed to have a low offset input voltage. In addition, the

sensing gain is set by an external resistor ratio.

ꢀOLTAGE CONTROL MODE

ACTIꢀE IMPEDANCE CONTROL MODE

A high gain bandwidth error amplifier is used for the voltage-

mode control loop. The noninverting input voltage is set via the

7-bit VID DAC. The VID codes are listed in Table 6. The

noninverting input voltage is offset by the droop voltage as a

function of current, commonly known as active voltage

positioning. The output of the error amplifier is the COMP pin,

which sets the termination voltage for the internal PWM ramps.

To control the dynamic output voltage droop as a function of

the output current, the signal proportional to the total output

current is converted to a voltage that appears between CSREF

and LLSET. This voltage can be scaled to equal the droop voltage,

which is calculated by multiplying the droop impedance of the

regulator with the output current. The droop voltage is then

used as the control voltage of the PWM regulator. The droop

voltage is subtracted from the DAC reference output voltage

and determines the voltage positioning setpoint. The setup

results in an enhanced feed-forward response.

The negative input, FB, is tied to the output sense location

through a resistor, RB, for sensing and controlling the output

voltage at the remote sense point. The main loop compensation

is incorporated in the feedback network connected between FB

and COMP.

CURRENT CONTROL MODE AND THERMAL

BALANCE

POWER-GOOD MONITORING

The ADP3207 has individual inputs for monitoring the current in

each phase. The phase current information is combined with an

internal ramp to create a current balancing feedback system that

is optimized for initial current accuracy and dynamic thermal

balance. The current balance information is independent of the

total inductor current information used for voltage positioning

described in the Active Impedance Control Mode section.

The power-good comparator monitors the output voltage via

the CSREF pin. The PWRGD pin is an open drain output that

can be pulled up through an external resistor to a voltage rail

that is not necessarily the same VCC voltage rail of the

controller. Logic high level indicates that the output voltage is

within the voltage limits defined by a window around the VID

voltage setting. PWRGD goes low when the output voltage is

outside of that window.

Rev. 0 | Page 13 of 32

ADP3207

Following the IMVP-6 specification, PWRGD window is

defined as −300 mV below and +200 mV above the actual VID

DAC output voltage. For any DAC voltage below 300 mV, only

the upper limit of the PWRGD window is monitored. To

prevent false alarm, the power-good circuit is masked during

various system transitions, including any VID change and

entrance/exit out of deeper sleep. The duration of the PWRGD

mask is set by an internal timer to be about 100 µs. In

VCC

EN

2.9V

1.7V

conditions where a larger than 200 mV voltage drop occurs

during deeper sleep entry or slow deeper sleep exit, the duration

of PWRGD masking is extended by an internal logic circuit.

SS

1.2V

V

BOOT

POWER-UP SEQUENCE AND SOFT START

The power-on ramp-up time of the output voltage is set with a

capacitor tied from the SS pin to GND. The capacitance on the

SS pin also determines the current-limit latch-off time as

explained in the Soft Transient section. The whole power-up

sequence, including soft start, is illustrated in Figure 9.

V

CORE

V

VID

CLKEN

In VCC UVLO or in shutdown, the SS pin is held at zero

potential. When VCC ramps above the upper UVLO threshold

and EN is asserted high, the ADP3207 enables internal bias and

starts a reset cycle that lasts about 50 μs to 60 µs. Next, when

initial reset is over, the chip detects the number of phases set by

the user, and gives a go signal to ramp up the SS voltage. During

soft start, the external SS capacitor is charged by an internal

8 µA current source. The V_COREvoltage follows the ramping SS

voltage up to the V_BOOTvoltage level, which is determined by a

burnt-in VID code (the 1.2 V code by IMVP-6 specification).

While V_COREis being regulated at V_BOOTvoltage, the SS capacitor

continues to rise. When the SS pin voltage reaches 1.7 V, the

t_{CPU_PWRGD}

PWRGD

Figure 9. Power-Up Sequence

SOFT TRANSIENT

The ADP3207 provides a soft transient function to reduce inrush

current during various transitions, including the entrance/exit of

deeper sleep and the transition from V_BOOTto VID voltage.

Reducing the inrush current helps decrease the acoustic noise

generated by the MLCC input capacitors and inductors.

The soft transient feature is implemented with an STSET buffer

amplifier that outputs constant sink or source current on the

STSET pin where an external capacitor is connected. The

capacitor is used to program the slew rate of V_COREvoltage

during any VID voltage transient. During steady-state

operation, both the reference input of the voltage error

amplifier and the STSET amplifier are connected to the VID

DAC output. Consequently, the STSET voltage is a buffered

version of VID DAC output. When system signals trigger a soft

transition, the reference input of the voltage error amplifier

switches from the DAC output to the STSET output, while the

input of the STSET amplifier remains connected to the DAC.

The STSET buffer input sees the almost instantaneous VID

voltage change and tries to track it. Tracking is not

instantaneous because the buffer slew rate is limited by the

source/sink current capability of the STSET output. Therefore,

V_COREvoltage follows the VID DAC output voltage change with

a controlled slew rate. When the transient period is complete,

the reference input of the voltage amplifier switches back to the

VID DAC output to ensure higher accuracy.

CLKEN

ADP3207 asserts the

signal low, given that the V_CORE

voltage is within the power-good window of V_BOOT. The

ADP3207 reads the VID codes provided by the CPU on VID0

to VID6 input pins. The V_COREvoltage changes from V_BOOTto

the VID voltage by a well controlled soft transition, as

introduced in the Soft Transient section. Meanwhile, the SS pin

voltage is quickly charged up to a clamp voltage of 2.9 V.

The PWRGD signal is not asserted until there is a t_{CPU_PWRGD}

delay of about 3 ms to 10 ms as specified by the IMVP-6. The

power-good delay can be programmed by the capacitor

CLKEN

connected from PGDELAY to GND. Before the

is asserted low, PGDELAY is reset to zero. After the assertion of

CLKEN

signal

the

signal, an internal source current of 2 µA starts

charging up the external capacitor on the PGDELAY pin.

Assuming the V_COREvoltage is settled within the power-good

window defined by the VID DAC voltage, the PWRGD signal is

asserted high when the PGDELAY voltage reaches the 2.9 V

power-good delay termination threshold.

If either EN is taken low or VCC drops below the lower VCC

UVLO threshold, then both the SS capacitor and PGDELAY

capacitor are reset to ground to be ready for another soft-start cycle.

Rev. 0 | Page 14 of 32

ADP3207

Table 5 lists the source/sink current on the STSET pin for

various transitions. By charging/discharging the external

capacitor on the STSET pin, users actually program the voltage

slew rate on the STSET pin, and consequently, on the V_CORE

output. For example, a 750 pF STSET capacitor leads to a

10 mV/s V_COREslew rate appropriate for a fast exit from deeper

sleep, and to a ±3.3 mV/µs V_COREslew rate for a slow entry to, or

exit from, deeper sleep.

An inherent per phase current limit protects individual phases

in case one or more phases stop functioning because of a faulty

component. This limit is based on the maximum normal-mode

COMP voltage.

After a current limit is hit, or following a PWRGD failure, the

SS pin is discharged by an internal sink current of 2 µA. A

comparator monitors the SS pin voltage and shuts off the

controller when the voltage drops below about 1.65 V. Because

voltage ramp (2.9 V − 1.65 V = 1.25 V) and discharge current

(2 µA) are internally fixed, current-limit latch-off delay time

can be set by selecting the external SS pin capacitor.

Table 5. Source/Sink Current of STSET

System Signals

STSET

DPRSLP DPRSTP

ꢀID Transient

Current

Entrance to Deeper Sleep

Fast Exit from Deeper Sleep

Slow Exit from Deeper Sleep

Transient from V_BOOTto VID

HIGH

LOW

HIGH

DNC¹

HIGH

DNC¹

−2.5 µA

+7.5 µA

+2.5 µA

±2.5 µA

The controller keeps cycling the phases during latch-off delay

time. If current overload is removed and PWRGD is recovered

before the 1.65 V threshold is reached, then the controller

resumes normal operation, and the SS pin voltage recovers to

2.9 V clamp level.

¹Do not care.

CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-

OFF PROTECTION

The latch-off can be reset by removing and reapplying VCC, or

by recycling the EN pin low and high for a short time. To

disable the current-limit latch-off function, an external pull-up

resistor can be tied from the SS pin to the VCC rail. The pull-up

current has to override the 2 µA sink current of the SS pin to

prevent the SS capacitor from discharging down to the 1.65 V

latch-off threshold.

The ADP3207 compares the differential output of a current-

sense amplifier to a programmable current-limit setpoint to

provide current-limiting function. The nominal voltage on the

ILIMIT pin is 1.7 V. The current-limit threshold is set with a

resistor connected from the ILIMIT pin to GND. In multiphase

normal operating mode, the ILIMIT is internally scaled by

using a trimmed 12 kΩ resistor to give a current-limit threshold

of 10 mV for each µA of ILIMIT current. For single-phase

operation, the current-limit threshold is scaled down even

further. The scaling factor is the user selected number of phases.

For example, a 3-phase design scales the current-limit threshold

to 3.3 mV/µA referred to single-phase operation; a 2-phase

design scales the current-limit threshold to 5 mV/µA also

referred to single-phase operation. During any mode of

operation, if the voltage difference between CSREF and

CSCOMP rises above the current-limit threshold, the internal

current-limit amplifier takes control over the internal COMP

voltage to maintain an average output current equal to the set

limit level.

CHANGING ꢀID ON-THE-FLY

The ADP3207 is designed to track dynamically changing VID

code. As a result, the converter output voltage, that is, the CPU

VCC voltage, can change without the need to reset either the

controller or the CPU. This concept is commonly referred to as

VID on-the-fly (VID OTF) transient. A VID-OTF can occur

either under light load or heavy load conditions. The processor

signals the controller by changing the VID inputs in LSB

incremental steps from the start code to the finish code. The

change can be either upwards or downwards steps.

When a VID input changes state, the ADP3207 detects the

change but ignores the new code for a minimum of time of

400 ns. This keep out is required to prevent reaction to false

code that can occur by a skew in the VID code while the 7-bit

VID input code is in transition. Additionally, the VID change

triggers a PWRGD masking timer to prevent a PWRGD failure.

Each VID change resets and retriggers the internal PWRGD

masking timer. As listed in Table 5, during any VID transient,

the ADP3207 forces a multiphase PWM mode regardless of

system input signals.

During start-up when the output voltage is below 200 mV, a

secondary current limit is activated. This is necessary because

the voltage swing on CSCOMP cannot extend below ground.

The secondary current-limit circuit clamps the internal COMP

voltage and sets the internal compensation ramp termination

voltage at 1.5 V level. The clamp actually limits voltage drop

across the low side MOSFETs through the current balance

circuitry.

Rev. 0 | Page 15 of 32

ADP3207

DCM

OD

low.

MOSFETs are turned off by setting both

and

OUTPUT CROWBAR

DCM OD

recovers above −100 mV.

and

pins are set high again when CSREF voltage

To protect the CPU load and output components of the

DCM

OD

converter, the PWM outputs are driven low,

and

are

driven high (that is, commanded to turn on the low-side

MOSFETs of all phases) when the output voltage exceeds an

OVP threshold of 1.7 V as specified by IMVP-6.

OUTPUT ENABLE AND UꢀLO

The VCC supply voltage to the controller must be higher than

the UVLO upper threshold, and the EN pin must be higher

than its logic threshold so the ADP3207 can begin switching. If

the VCC voltage is less than the UVLO threshold, or the EN pin

is logic low, then the ADP3207 is in shutdown. In shutdown, the

controller holds the PWM outputs at ground, shorts the SS pin

Turning on the low-side MOSFETs discharges the output

capacitor as soon as reverse current builds up in the inductors.

If the output overvoltage is due to a short of the high-side

MOSFET, then this crowbar action current limits the input

supply or causes the input rail fuse to blow, protecting the

microprocessor from destruction.

DCM

and PGDELAY pin capacitors to ground, and drives

OD

and

pins low.

Once overvoltage protection (OVP) is triggered, the ADP3207 is

latched off. The latch-off function can be reset by removing and

reapplying VCC, or by recycling EN low and high for a short

time. OVP can be disabled by grounding the TTSENSE pin. The

OVP comparator monitors the output voltage via the CSREF pin.

Proper power supply sequencing during start-up and shutdown

of the ADP3207 must be adhered to. All input pins must be at

ground prior to applying or removing VCC. All output pins

should be left in high impedance state while VCC is off.

THERMAL THROTTLING CONTROL

REꢀERSE ꢀOLTAGE PROTECTION

The ADP3207 includes a thermal monitoring circuit to detect if

the temperature of the variable resistor (VR) has exceeded a

user-defined thermal throttling threshold. The thermal

monitoring circuit requires an external resistor divider

connected between the VCC pin and GND. The divider consists

of an NTC thermistor and a resistor. To generate a voltage that

is proportional to temperature, the midpoint of the divider is

connected to the TTSENSE pin. Whenever the temperature

trips the set alarm threshold, an internal comparator circuit

compares the TTSENSE voltage to a half VCC threshold and

outputs a logic level signal at the VRTT output. The VRTT

output is designed to drive an external transistor that, in turn,

Very large reverse currents in inductors can cause negative

V_COREvoltage, which is harmful to the CPU and other output

components. ADP3207 provides reverse voltage protection

(RVP) function without additional system cost. The V_CORE

voltage is monitored through the CSREF pin. Any time the

CSREF pin voltage is below −300 mV, the ADP3207 triggers its

RVP function by disabling all PWM outputs and setting both

DCM

OD

and

pins low. Thus, all the MOSFETs are turned off.

The reverse inductor current can be quickly reset to zero by

dumping the energy built up in the inductor into the input dc

voltage source via the forward-biased body diode of the high-

side MOSFETs. The RVP function is terminated when the

CSREF pin voltage returns above −100 mV.

VRTT

provides the high current, open drain

signal that is

required by the IMVP-6 specification. When the temperature is

around the set alarm point, the internal VRTT comparator has

a hysteresis of about 100 mV to prevent high frequency

oscillation of VRTT. The TTSENSE pin also serves the function

of disabling OVP. In extreme heat, users should make sure that

the TTSENSE pin voltage remains above 1 V if OVP is desired.

Occasionally, overvoltage crowbar protection results in negative

V_COREvoltage, because turn-on of all low-side MOSFETs leads

to very large reverse inductor current. To prevent damage of the

CPU by negative voltage, ADP3207 keeps its RVP monitoring

function alive even after OVP latch-off. During OVP latch-off,

if the CSREF pin voltage drops below −300mV, then all low-side

Rev. 0 | Page 16 of 32

ADP3207

Table 6. VID Code Table

ꢀID6 ꢀID5 ꢀID4 ꢀID3 ꢀID2 ꢀID1 ꢀID0 OUTPUT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.5000 V

1.4875 V

1.4750 V

1.4625 V

1.4500 V

1.4375 V

1.4250 V

1.4125 V

1.4000 V

1.3875 V

1.3750 V

1.3625 V

1.3500 V

1.3375 V

1.3250 V

1.3125 V

1.3000 V

1.2875 V

1.2750 V

1.2625 V

1.2500 V

1.2375 V

1.2250 V

1.2125 V

1.2000 V

1.1875 V

1.1750 V

1.1625 V

1.1500 V

1.1375 V

1.1250 V

1.1125 V

1.1000 V

1.0875 V

1.0750 V

1.0625 V

1.0500 V

1.0375 V

1.0250 V

1.0125 V

1.0000 V

0.9875 V

0.9750 V

0.9625 V

0.9500 V

0.9375 V

0.9250 V

0.9125 V

0.9000 V

0.8875 V

0.8750 V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.8625 V

0.8500 V

0.8375 V

0.8250 V

0.8125 V

0.8000 V

0.7875 V

0.7750 V

0.7625 V

0.7500 V

0.7375 V

0.7250 V

0.7125 V

0.7000 V

0.6875 V

0.6750 V

0.6625 V

0.6500 V

0.6375 V

0.6250 V

0.6125 V

0.6000 V

0.5875 V

0.5750 V

0.5625 V

0.5500 V

0.5375 V

0.5250 V

0.5125 V

0.5000 V

0.4875 V

0.4750 V

0.4625 V

0.4500 V

0.4375 V

0.4250 V

0.4125 V

0.4000 V

0.3875 V

0.3750 V

0.3625 V

0.3500 V

0.3375 V

0.3250 V

0.3125 V

0.3000 V

0.2875 V

0.2750 V

0.2625 V

0.2500 V

0.2375 V

Rev. 0 | Page 17 of 32

ADP3207

ꢀID6 ꢀID5 ꢀID4 ꢀID3 ꢀID2 ꢀID1 ꢀID0 OUTPUT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.2250 V

0.2125 V

0.2000 V

0.1875 V

0.1750 V

0.1625 V

0.1500 V

0.1375 V

0.1250 V

0.1125 V

0.1000 V

0.0875 V

0.0750 V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.0625 V

0.0500 V

0.0375 V

0.0250 V

0.0125 V

0.0000 V

Rev. 0 | Page 18 of 32

ADP3207

VID0

VID1

VID2

VID3

VID4

VID5

VID6

DPRSTP

ILIMIT

VRPM

RRPM

RT

RAMPADJ

LLSET

CSREF

CSSUM

PSI

VCC

CSCOMP

GND

05782-010

Figure 10. Typical 2-Phase Application Circuit

Rev. 0 | Page 19 of 32

ADP3207

APPLICATION INFORMATION

8 μA×t_SS

The design parameters for a typical Intel IMVP6-compliant

CPU Core VR application are as follows:

(2)

C_SS

=

V_BOOT

where:

_BOOTis the boot voltage for the CPU, defined in the IMVP-6

specification as 1.2 V.

_SSis the desired soft-start time, recommended to be below 3 ms

in the IMVP-6 specification.

Assuming a desired soft-start time of 2 ms, C_SSis 13.3 nF, with

•

Maximum input voltage (V_INMAX) = 19 V

Minimum input voltage (V_INMIN) = 7 V

Output voltage by VID setting (V_VID) = 1.150 V

Maximum output current (I_O) = 44 A

V

t

the closest standard capacitance at 12 nF.

Load line slope (R_O) = 2.1 mΩ

Once C_SShas been chosen, the current-limit latch-off time is

equal to 7.2 ms according to the following calculation:

Maximum output current step (ΔI_O) = 34.5 A

Maximum output thermal current (I_OTDC) = 32 A

Number of phases (n) = 2

1.2 V ×C_SS

(3)

(4)

t_DELAY

=

2 μA

PWRGD DELAY TIMER

Switching frequency per phase (f_SW) = 280 kHz

Duty cycle at maximum input voltage (D_MIN) = 0.061

Duty cycle at minimum input voltage (D_MAX) = 0.164

The PWRGD delay, t_{CPU_PWRGD}, is defined in the IMVP-6

specification as the time period between the

and the PWRGD assertion. It is programmed by a cap on the

PGDELAY pin.

CLKEN

assertion

1.9μA×t_{CPU _ PWRGD}

C_PGDLY

=

SETTING THE CLOCK FREQUENCY FOR PWM

MODE

2.9 V

The IMVP-6 specifies that the PWRGD delay is between 3 ms

to 20 ms. Assuming 7 ms PWRGD delay is preferred, then

C_PGDLYis 4.7 nF.

In PWM mode operation, The ADP3207 uses a fixed-frequency

control architecture. The frequency is set by an external timing

resistor (R_T). The clock frequency and the number of phases

determine the switching frequency per phase, which directly

relates to switching losses, and the sizes of the inductors and

input and output capacitors. In a 2-phase design, a clock

frequency of 560 kHz sets the switching frequency to 280 kHz

per phase. This selection represents a trade-off between the

switching losses and the minimum sizes of the output filter

components. To achieve a 560 kHz oscillator frequency at VID

voltage 1.150 V, R_Thas to be 237 kΩ. Alternatively, the value for

R_Tcan be calculated using

INDUCTOR SELECTION

The choice of inductance determines the ripple current in the

inductor. Less inductance leads to more ripple current, which

increases the output ripple voltage and conduction losses in the

MOSFETs. However, this allows the use of smaller-size inductors,

and for a specified peak-to-peak transient deviation, it allows

less total output capacitance. Conversely, a higher inductance

means lower ripple current and reduced conduction losses, but

requires larger size inductors and more output capacitance for

the same peak-to-peak transient deviation. In a multiphase

converter, the practical peak-to-peak inductor ripple current is

less than 50% of the maximum dc current in the same inductor.

Equation 5 shows the relationship between the inductance,

oscillator frequency, and peak-to-peak ripple current. Equation

6 can be used to determine the minimum inductance based on

a given output ripple voltage.

V_VID+1.0 V

(1)

R_T

=

−5 kΩ

n × f_SW×16 pF

where 16 pF and 25 kΩ are internal IC component values. For

good initial accuracy and frequency stability, it is recommended

to use a 1% resistor.

SOFT-START AND CURRENT-LIMIT LATCH-OFF

DELAY TIMES

V_VID

×

(

1− D _MIN

)

(5)

I_R

=

f_SW× L

The soft-start and current-limit latch-off delay functions share

the SS pin. Consequently, these two parameters must be

considered together. The first step is to set C_SSfor the soft-start

ramp. This ramp is generated with a 8 µA internal current

source. The value for C_SScan be set as

V_VID×R_O× 1−

(

n×D _MIN))

×

(

1− D _MIN

)

(6)

L ≥

f_SW×V_RIPPLE

Rev. 0 | Page 20 of 32

ADP3207

Solving Equation 6 for a 20 mV peak-to-peak output ripple

voltage yields

Output Droop Resistance

The inductor design requires that the regulator output voltage

measured at the CPU pins drops when the output current

increases. The specified voltage drop corresponds to a dc output

resistance (R_O).

1.150 V ×2.1mΩ×

(

1−

2×0.061 × 1−0.061

( )) ( )

L ≥

= 356 nH

280 kHz ×20 mV

If the ripple voltage ends up being less than the initially selected

value, then the inductor can be changed to a smaller value until

the ripple value is met. This iteration allows optimal transient

response and minimum output decoupling.

The output current is measured by summing the currents of the

resistors monitoring the voltage across each inductor and by

passing the signal through a low-pass filter. This summer-filter

is implemented by the CS amplifier that is configured with

resistors R_PH(X)(summer), and R_CSand C_CS(filter). The output

resistance of the regulator is set by the following equations,

where R_Lis the DCR of the output inductors:

The smallest possible inductor should be used to minimize the

number of output capacitors. For this example, choosing a

360 nH inductor is a good starting point, and gives a calculated

ripple current of 10.7 A. The inductor should not saturate at the

peak current of 27.4 A, and should be able to handle the sum of

the power dissipation caused by the average current of 16 A in

the winding and core loss.

R_CS

(7)

R_O

=

×R_L

R_PH(X)

L

R_L×R_CS

(8)

C_CS

=

Another important factor in the inductor design is the DCR,

which is used to measure phase currents. A large DCR causes

excessive power losses, though too small a value leads to

increased measurement error. This example uses an inductor

with a DCR of 0.89 mΩ.

Users have the flexibility of choosing either R_CSor R_PH(X). Due to

the current drive ability of the CSCOMP pin, the R_CSresistance

should be larger than 100 kΩ. For example, users should

initially select R_CSto be equal to 220 kΩ, then use Equation 8 to

solve for C_CS

Selecting a Standard Inductor

360nH

0.89mΩ×220kΩ

Once the inductance and DCR are known, the next step is to

either design an inductor or select a standard inductor that

comes as close as possible to meeting the overall design goals. It

is also important to have the inductance and DCR tolerance

specified to keep the accuracy of the system controlled; 20%

inductance and 15% DCR (at room temperature) are reasonable

assumptions that most manufacturers can meet.

C_CS

=

= 1.84nF

Because C_CSis not the standard capacitance, it is implemented

with two standard capacitors in parallel: 1.8 nF and 47 pF. For

the best accuracy, C_CSshould be a 5% NPO capacitor.

Next, solve R_PH(X)by rearranging Equation 7.

0.89mΩ

Power Inductor Manufacturers

R_PH(X)

≥

× 220 kΩ = 93.2kΩ

2.1mΩ

The following companies provide surface mount power

inductors optimized for high power applications upon request:

The standard 1% resistor for R_PH(X)is 93.1 kΩ.

•

Vishay Dale Electronics, Inc.

http://www.vishay.com

Inductor DCR Temperature Correction

With the inductor DCR used as a sense element, and copper

wire being the source of the DCR, users need to compensate for

temperature changes in the inductor’s winding. Fortunately,

copper has a well-known temperature coefficient (TC) of

0.39%/°C.

Panasonic

http://www.panasonic.com

Sumida Corporation

http://www.sumida.com

NEC Tokin Corporation

http://www.nec-tokin.com

If R_CSis designed to have an opposite sign but equal percentage

change in resistance, then it cancels the temperature variation of

the inductor DCR. Due to the nonlinear nature of NTC

thermistors, series resistors, R_CS1and R_CS2(see Figure 11) are

needed to linearize the NTC and produce the desired

temperature coefficient tracking.

Rev. 0 | Page 21 of 32

ADP3207

PLACE AS CLOSE AS POSSIBLE

TO NEAREST INDUCTOR

OR LOW–SIDE MOSFET

5. Calculate R_TH= R_TH× R_CS, then select the closest value of

thermistor that is available. Also, compute a scaling factor

k based on the ratio of the actual thermistor value relative

to the computed one

TO

OUT

SENSE

TO

V

SWITCH

NODES

R

TH

ADP3207

R

PH3

PH1

PH2

R_TH(ACTUAL)

(11)

k =

R_{TH(CALCULATED)}

CSCOMP

CSSUM

CSREF

R

CS1

CS2

18

17

KEEP THIS PATH

AS SHORT AS POSSIBLE

AND WELL AWAY FROM

SWITCH NODE LINES

C

CS

6. Finally, calculate values for R_CS1and R_CS2using

R_CS1= R_CS×k ×r_CS1

(12)

R_CS2= R_CS

× (1− k)+ k ×r_CS2))

( (

16

This example starts with a thermistor value of 100 kΩ and uses

a Vishay NTHS0603N04 NTC thermistor (a 0603 size thermistor)

with A = 0.3359 and B = 0.0771. From this data, r_CS1= 0.359,

Figure 11. Temperature Compensation Circuit Values

The following procedure and equations yield values for

_CS1, R_CS2, and R_TH(the thermistor value at 25°C) for a given

r

_CS2= 0.729 and r_TH= 1.094. Solving for R_THyields 240 kΩ, so

R

220 kΩ is chosen, making k = 0.914. Finally, R_CS1and R_CS2are

72.3 kΩ and 166 kΩ. Choosing the closest 1% resistor values

yields a choice of 71.5 kΩ and 165 kΩ.

R_CSvalue:

1. Select an NTC to be used based on type and value. Because

there is no value yet, start with a thermistor with a value

close to R_CS. The NTC should also have an initial tolerance

of better than 5%.

C_OUTSELECTION

The required output decoupling for processors and platforms is

typically recommended by Intel. The following guidelines can

also be used if both bulk and ceramic capacitors in the system:

2. Based on the type of NTC, find its relative resistance value

at two temperatures. Temperatures that work well are 50°C

and 90°C. These are called Resistance Value A (A is

R_TH(50°C)/R_TH(25°C)) and Resistance Value B (B is

R_TH(90°C)/R_TH(25°C)). Note that the relative value of NTC

is always 1 at 25°C.

•

Select the total amount of ceramic capacitance. This is based

on the number and type of capacitors to be used. The best

location for ceramics is inside the socket; 20 pieces of

Size 0805 being the physical limit. Additional capacitors

can be placed along the outer edge of the socket.

3. Next, find the relative value of R_CSthat is required for each

of these temperatures. This is based on the percentage of

change needed, which is initially 0.39%/°C. These are

called r₁and r_2.

•

Select the number of ceramics and find the total ceramic

capacitance (C_Z). Combined ceramic values of 200 µF to

300 µF are recommended and are usually made up of

multiple 10 µF or 22 µF capacitors.

1

r₁=

1+TC ×

(

T₁−25

1

)

(9)

Note that there is an upper limit imposed on the total

amount of bulk capacitance (C_X) when considering the

VID on-the-fly output voltage stepping (voltage step V_Vin

time t_Vwith error of V_ERR), and also a lower limit based on

meeting the critical capacitance for load release at a given

maximum load step ΔI_O. For a step-off load current, the

current version of the IMVP-6 specification allows a

maximum V_COREovershoot (V_OSMAX) of 10 mV, plus 1.5% of

the VID voltage. For example, if the VID is 1.150 V, then

the largest overshoot allowed is 27 mV.

r₂=

1+TC ×

(

T₂−25

)

where:

TC = 0.0039

T₁= 50°C

T₂= 90°C.

4. Compute the relative values for r_CS1, r_CS2, and r_THusing

(

A − B

A×

)

×r ×r₂− A×

(

1− B

(

)

×r₂+ B ×

×r₂−

(

1− A

A − B

)

×r

1

r_CS2

r_CS1

=

(

1− B

)

×r − B × 1− A

)

1

⎛

⎜

⎞

⎟

(10)

(

1− A

)

⎜

⎝

⎟

⎠

L × ∆I_O

1

A

(13)

(14)

C_x

≥

MIN )

−C_z

−

(

1− r_CS2r − r_CS2

⎛

⎜

⎝

⎞

⎟

⎠

V_OSMAX

1

⎜

n × R_O

+

×V_VID

1

∆I_O

r

=

TH

1

−

2

⎛

⎜

⎞

1− r_CS2r_CS1

⎛

⎜

⎝

⎞

⎟

⎠

L

V_V

V_VIDnKR_O

⎟

⎜

C_X(MAX)

≤

×

1+ t_v

×

−1 −C_z

⎜

⎝

⎟

nK ²R_O²V_VID

V_V

L

⎟

⎠

Rev. 0 | Page 22 of 32

ADP3207

where:

POWER MOSFETS

For normal 20 A per phase application, the N-channel power

MOSFETs are selected for two high-side switches and two low-

side switches per phase. The main selection parameters for the

power MOSFETs are V_GS(TH), Q_G, C_ISS, C_RSSand R_DS(ON). Because

the gate drive voltage (the supply voltage to the ADP3419) is

5 V, logic-level threshold MOSFETs must be used.

⎛

⎜

⎝

⎞

⎟

⎠

V_ERR

V _V

(15)

K = −1n

To meet the conditions of these equations and transient

response, the ESR of the bulk capacitor bank (R_X) should be less

than two times the droop resistance, R_O. If the C_X(MIN)is larger

than C_X(MAX), the system does not meet the VID on-the-fly

and/or deeper sleep exit specification and can require a smaller

inductor or more phases (the switching frequency can also have

to be increased to keep the output ripple the same).

The maximum output current I_Odetermines the R_DS(ON)

requirement for the low-side (synchronous) MOSFETs. In the

ADP3207, currents are balanced between phases; the current in

each low-side MOSFET is the output current divided by the

total number of MOSFETs (n_SF). With conduction losses being

dominant, the following equation shows the total power

dissipated in each synchronous MOSFET in terms of the ripple

current per phase (I_R) and average total output current (I_O):

For example, if using 32 pieces of 10 µF 0805 MLC capacitors

(C_Z= 320 µF), the fastest VID voltage change is the exit of

deeper sleep, and V_COREchange is 220 mV in 22 µs with a

setting error of 10 mV. Where K = 3.1, solving for the bulk

capacitance yields

2

⎡

⎤

⎥

⎛

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

I_O

n_SF

1

12

n× I_R

n_SF

(17)

⎜

⎢

P

=

(1− D

)

×

+

×

× R_DS(SF)

SF

⎜

⎛

⎜

⎞

⎟

⎢

⎥

⎦

⎝

⎣

⎜

⎟

360nH × 34.5A

⎟

C_x

≥

MIN )

− 320µF = 1.1mF

(

Knowing the maximum output thermal current and the

maximum allowed power dissipation, users can find the

required R_DS(ON)for the MOSFET. For 8-lead SOIC or 8-lead

⎛

⎞

⎟

⎠

27mV

34.5A

⎟

⎜

2 × 2.1mΩ +

× 1.150V

⎜

⎟

⎜

⎝

⎠

360 nH × 220 mV

SOIC compatible packaged MOSFETs, the junction to ambient

(PCB) thermal impedance is 50°C/W. In the worst case, the

PCB temperature is 90°C during heavy load operation of the

notebook; a safe limit for P_SFis 0.6 W at 120°C junction

temperature. Thus, for this example (32 A maximum thermal

current), R_DS(SF)(per MOSFET) is less than 9.6 mΩ for two

pieces of low-side MOSFET. This R_DS(SF)is also at a junction

temperature of about 120°C; therefore, the R_DS(SF)(per

MOSFET) should be lower than 6.8 mΩ at room temperature,

giving 9.6 mΩ at high temperature.

≤

MAX

)

(

2 × 3.1²×

(

2.1 mΩ

)

×1.150V

2

⎛

⎜

⎞

⎟

⎛

⎞

⎟

⎠

22 µs ×1.150 V × 2 × 3.1× 2.1 mΩ

220 mV × 360 nH

⎜

⎝

1+

−1 −320 µF = 2.3 mF

⎜

⎟

⎜

⎝

⎟

⎠

Using four 330 µF Panasonic SP capacitors with a typical ESR of

6 mΩ each yields C_X= 1.32 mF with an R_X= 1.5 mΩ.

Another important factor for the synchronous MOSFET is the

input capacitance and feedback capacitance. The ratio of

feedback to input needs to be small (less than 10% is

recommended) to prevent accidental turn-on of the

synchronous MOSFETs when the switch node goes high.

One last check should be made to ensure that the ESL of the

bulk capacitors (L_X) is low enough to limit the high frequency

ringing during a load change. This is tested using

L_x≤ C_z× R_O²×Q²

(16)

L_x≤ 320 µF ×

(

2.1 mΩ

)

²×2 = 2nH

The high-side (main) MOSFET has to be able to handle two

main power dissipation components, conduction and switching

losses. The switching loss is related to the amount of time it

takes for the main MOSFET to turn on and off, and to the

current and voltage that are being switched. Basing the

switching speed on the rise and fall time of the gate driver

impedance and MOSFET input capacitance, Equation 18

provides an approximate value for the switching loss per main

MOSFETs

where:

Q is limited to the square root of 2 to ensure a critically damped

system.

In this example, L_Xis about 250 pH for the four SP capacitors,

which satisfies this limitation. If the L_Xof the chosen bulk

capacitor bank is too large, the number of ceramic capacitors

may need to be increased if there is excessive ringing.

Note that for this multimode control technique, an all-ceramic

capacitor design can be used as long as the conditions of

Equation 13, Equation 14, and Equation 15 are satisfied.

V_CC× I_O

n_MF

n

(18)

P_S(MF)= 2× f_SW

×

× R_G×

×C_ISS

Rev. 0 | Page 23 of 32

ADP3207

where:

RAMP RESISTOR SELECTION

n_MFis the total number of main MOSFETs.

The ramp resistor (R_R) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the

best combination of thermal balance, stability, and transient

response. Use this equation to determine a starting value

R_Gis the total gate resistance (1.5 Ω for the ADP3419 and about

0.5 Ω for two pieces of typical high speed switching MOSFETs,

making R_G= 2 Ω).

C_ISSis the input capacitance of the main MOSFET. The best

A_R× L

R_R=

thing to reduce switching loss is to use lower gate capacitance

devices.

3× A_D× R_DS×C_R

(21)

The conduction loss of the main MOSFET is given by

0.2×360nH

3×5×3.4mΩ×5pF

R_R=

= 282kΩ

2

⎡

⎢

⎤

⎥

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

I_O

n_MF

n×I_R

n_MF

1

12

(19)

P_C(MF)= D×

+

×

×R_DS(MF)

⎢

⎣

⎥

⎦

where:

A_Ris the internal ramp amplifier gain.

A_Dis the current balancing amplifier gain.

where:

_DS(MF)is the on-resistance of the MOSFET.

R

_DSis the total low-side MOSFET ON-resistance,

C_Ris the internal ramp capacitor value.

Typically, for main MOSFETs, users want the highest speed (low

C_ISS) device, but these usually have higher on-resistance. Users

must select a device that meets the total power dissipation

(0.6 W for a single 8-lead SOIC package) when combining the

switching and conduction losses.

Another consideration in the selection of R_Ris the size of the

internal ramp voltage (see Equation 22). For stability and noise

immunity, keep this ramp size larger than 0.5 V. Taking this into

consideration, the value of R_Ris selected as 280 kΩ.

For example, using an IRF7821 device as the main MOSFET

(four in total; that is, n_MF= 4), with about C_ISS= 1010 pF (max)

and R_DS(MF)= 18 mΩ (max at T_J= 120°C) and an IR7832 device

as the synchronous MOSFET (four in total; that is, n_SF= 4),

R_DS(SF)= 6.7 mΩ (max at T_J= 120°C). Solving for the power

dissipation per MOSFET at I_O= 32 A and I_R= 10.7 A yields

420 mW for each synchronous MOSFET and 410 mW for each

main MOSFET.

The internal ramp voltage magnitude can be calculated using:

A_R×(1 − D)×V_VID

V_R=

R_R×C_R× f_SW

(22)

0.2 ×(1 − 0.061)×1.150 V

V_R=

= 0.55 V

280 kΩ × 5pF × 280 kHz

The size of the internal ramp can be made larger or smaller. If it

is made larger, then stability and transient response improves,

but thermal balance degrades. Likewise, if the ramp is made

smaller, then thermal balance improves at the sacrifice of

transient response and stability. The factor of three in the

denominator of Equation 21 sets a minimum ramp size that

gives an optimal balance for good stability, transient response,

and thermal balance.

One last consideration is the power dissipation in the driver for

each phase. This is best described in terms of the QG for the

MOSFETs and is given by the following equation:

f_SW

2×n

⎡

⎤

(20)

P_DRV

=

×

(

n_MF×Q_GMF+ n_SF×Q_GSF

)

+ I_CC×V_CC

⎢

⎣

⎥

⎦

where:

Q

_GMFis the total gate charge for each main MOSFET.

COMP Pin Ramp

Q_GSFis the total gate charge for each synchronous MOSFET.

There is a ramp signal on the COMP pin due to the droop

voltage and output voltage ramps. This ramp amplitude adds to

the internal ramp to produce the following overall ramp signal

at the PWM input:

Also shown is the standby dissipation (I_CC× V_CC) of the driver.

For the ADP3419, the maximum dissipation should be less than

300 mW, considering its thermal impedance is 220°C/W and

the maximum temperature increase is 50°C. For this example,

with I_CC= 2 mA, Q_GMF= 14 nC and Q_GSF= 51 nC, there is 120

mW dissipation in each driver, which is below the 300 mW

dissipation limit. See the ADP3419 data sheet for more details.

V_R

(23)

V_RT

=

⎛

⎜

⎝

⎞

⎟

⎠

2×

(1−n×D)

1−

n× f_SW×C_X×R_O

For this example, the overall ramp signal is found to be 1.5 V.

Rev. 0 | Page 24 of 32

ADP3207

For the ADP3207, the maximum COMP voltage (V_COMP(MAX)) is

3.3 V, the COMP pin bias voltage (V_BIAS) is 1.0 V, and the

current balancing amplifier gain (A_D) is 5. Using a V_Rof 0.55 V,

and a R_DS(MAX)of 3.8 mΩ (low-side on-resistance at 150°C)

results in a per-phase limit of 85 A. Although this number

seems high, this current level can only be reached with a

absolute short at the output and the current-limit latch-off

function shutting down the regulator before overheating occurs.

SETTING THE SWITCHING FREQUENCY FOR RPM

MODE OPERATION OF PHASE 1

During the RPM mode operation of Phase 1, the ADP3207 runs

in pseudo constant frequency, given that the load current is

high enough for continuous current mode. While in

discontinuous current mode, the switching frequency is

reduced with the load current in a linear manner. When

considering power conversion efficiency in light load, lower

switching frequency is usually preferred for RPM mode.

However, the V_COREripple specification in the IMVP-6 sets the

limitation for lowest switching frequency. Therefore, depending

on the inductor and output capacitors, the switching frequency

in RPM mode can be equal, larger, or smaller than its

counterpart in PWM mode.

This limit can be adjusted by changing the ramp voltage V_R.

However, users should not set the per-phase limit lower than

the average per-phase current (I_LIM/n).

There is also a per-phase initial duty-cycle limit at maximum

input voltage:

V_COMP(MAX)−V_BIAS

(27)

A resistor between VRPM and RRPM pins sets the pseudo

constant frequency as following:

D_LIM= D_MIN

×

V_R

2 × R_T

V_VID+1.0 V

A_R×(1 − D)×V_VID

R_R×C_R× f_SW

For this example, the duty-cycle limit at maximum input voltage

is found to be 0.25 when D is 0.061.

(24)

R_RPM

=

×

− 0.5kΩ

where:

FEEDBACK LOOP COMPENSATION DESIGN

A_Ris the internal ramp amplifier gain.

Optimized compensation of the ADP3207 allows the best

possible response of the regulator’s output to a load change. The

basis for determining the optimum compensation is to make

the regulator and output decoupling appear as an output

impedance that is entirely resistive over the widest possible

frequency range, including dc, and equal to the droop resistance

(R_O). With the resistive output impedance, the output voltage

droops in proportion with the load current at any load current

slew rate. This ensures the optimal positioning and minimizes

the output decoupling.

C_Ris the internal ramp capacitor value.

R_Ris an external resistor on the RAMPADJ pin to set the

internal ramp magnitude.

Because R_R= 280 kΩ, the following resistance sets up 300 kHz

switching frequency in RPM operation.

2 × 237 kΩ

1.150V +1.0V 280kΩ ×7pF ×300kHz

0.2×(1− 0.061)×1.150

R_RPM

=

×

− 500Ω = 80.6 kΩ

CURRENT-LIMIT SETPOINT

With the multimode feedback structure of the ADP3207, users

need to set the feedback compensation to make the converter

output impedance work in parallel with the output decoupling.

Several poles and zeros are created by the output inductor and

decoupling capacitors (output filter) that need to be

compensated for.

To select the current-limit setpoint, we need to find the resistor

value for R_LIM. The current-limit threshold for the ADP3207 is

set with a 1.7 V source (V_LIM) across R_LIMwith a gain of

13 mV/µA. R_LIMcan be found using the following equation:

A_LIM×V_LIM

(25)

R_LIM

=

I_LIM× R_O

A type-three compensator on the voltage feedback is adequate

for proper compensation of the output filter. Equation 28 to

Equation 36 is intended to yield an optimal starting point for

the design; some adjustments can be necessary to account for

PCB and component parasitic effects (see the Tuning Procedure

for ADP3207).

For values of R_LIMgreater than 500 kΩ, the current limit may be

lower than expected, so some adjustment of R_LIMmay be

needed. Here, I_LIMis the average current limit for the output of

the supply. In this example, if choosing 55 A for I_LIM, R_LIMis

190 kΩ, which is close to a standard 1% resistance of 191 kΩ.

The per-phase current limit described earlier has its limit

determined by the following:

V_COMP(MAX)−V_R−V_BIAS

A_D× R_DS(MAX)

I_R

2

(26)

I_PHLIM

≅

+

Rev. 0 | Page 25 of 32

ADP3207

The first step is to compute the time constants for all of the

poles and zeros in the system

In a typical notebook system, the battery rail decouplings are

MLCC capacitors or a mixture of MLCC capacitors and bulk

capacitors. In this example, the input capacitor bank is formed

by eight pieces of 10 µF, and 25 V MLCC capacitors with a

ripple current rating of about 1.5 A each.

R_L×V_RT2× L ×

(

1−n× D

)×V_RT

(28)

R_E= n× R_O+ A_D× R_DS

+

V_ID

n×C_X× R_O×V_VID

R_O− R'

R_X

L_X

R_O

(29)

(30)

T_A= C_X

×

(

R_O− R'

)

+

×

SOFT TRANSIENT SETTING

As described in the Soft Transient section, during the soft

transient, the slew rate of V_COREreference voltage change is

controlled by the STSET pin capacitance. Because the timing of

deeper sleep exit is critical, the STSET pin capacitance is set to

satisfy the fast deeper sleep exit slew rate as

T_B=

T_C=

(

R_X+ R'−R_O

)

×C_X

⎛

⎞

⎟

⎠

A_D× R_DS

2 × f_SW

⎜

V_RT× L −

⎜

⎝

(31)

(32)

V_VID× R_E

C_X×C_Z× R_O²

R_O− R' + C_Z× R_O

8µ A

(38)

C_STSET

=

T_D

=

2×SLEWRATE_C4E

C_X

×

(

)

where:

8 µA is the source/sink current of the STSET pin.

SLEWRATE_C4Eis the voltage slew rate during deeper sleep exit,

where:

R’ is the PCB resistance from the bulk capacitors to the ceramics.

_DSis the total low-side MOSFET on-resistance per phase.

R

defined as 10 mV/µs in the IMVP-6 specification.

For this example, A_Dis 5, V_RT= 1. 5 V, R’ is approximately

0.4 mΩ (assuming an 8-layer motherboard) and L_Xis 250 pH

for the four Panasonic SP capacitors.

C_STSETequals 400 pF, with the closest standard capacitance at 390 pF.

SELECTING THERMAL MONITOR COMPONENTS

For single-point hot spot thermal monitoring, simply set R_TTSET1

equal to the NTC thermistor’s resistance at the alarm

temperature (see Figure 12). For example, if the VRTT alarm

temperature is 100°C using a Vishey thermistor (NTHS-

0603N011003J) with a resistance of 100 kΩ at 25°C, and 6.8 kΩ

at 100°C, simply set R_TTSET1= R_TH1(100°C) to 6.8 kΩ.

The compensation values can be solved using the following:

n×R_O×T_A

R_E×R_B

(33)

(34)

C_A

=

T_C

C_A

R_A

5V

T_B

R_B

VCC

31

(35)

(36)

C_B

R_TTSET1

R

T_D

R_A

TTSENSE

C_FB

=

VRTT

30

-

+

R_TH1

C_TT

The standard values for these components are subject to the

R

ADP3207

tuning procedure, as introduced in the CIN Selection and Input

Current DI/DT Reduction section.

Figure 12. Single-Point Thermal Monitoring

C_INSELECTION AND INPUT CURRENT D_I/D_T

REDUCTION

Multiple-point hot spot thermal monitoring can be

implemented as shown in Figure 13. If any of the monitored hot

spots reaches alarm temperature, the VRTT signal is asserted.

The following calculation sets the alarm temperature:

In continuous inductor-current mode, the source current of the

high-side MOSFET is approximately a square wave with a duty

ratio equal to n × V_OUT/V_INand an amplitude of 1-nth the

maximum output current. To prevent large voltage transients, a

low ESR input capacitor sized for the maximum rms current

must be used. The maximum rms capacitor current happens at

the lowest input voltage, and is given by:

V_FD

½+

V_REF

(39)

R_TTSET1

=

R_{TH1ALARMTEMPERATURE}

V_FD

V_REF

½−

where V_FDis the forward drop voltage of the parallel diode.

1

(37)

I_CRMS= D × I_O

×

−1

n × D

Because the forward current is very small, the forward drop

voltage is very low (100 mV). Assuming the same 100°C alarm

temperature used in the single-spot thermal monitoring example,

and the same Vishay thermistor, then Equation 39 leads to

R_TTSET= 7.37 kΩ, whose closest standard resistor is 7.32 kΩ (1%).

1

I_CRMS= 0.164 × 44 A ×

−1 =10.3A

2 ×0.164

Rev. 0 | Page 26 of 32

ADP3207

5V

AC Loadline Setting

VCC

31

30

R

TTSETn

TTSET1

TTSET2

R

V

FD

…

VRTT

TTSENSE

R

THn

TH1

TH2

ADP3207

V

ACDRP

V

DCDRP

Figure 13. Multiple-Point Thermal Monitoring

The number of hot spots monitored is not limited. The alarm

temperature of each hot spot can be set differently by playing

different RTTSET₁, RTTSET₂, RTTSET_n.

Figure 14. AC Loadline Waveform

TUNING PROCEDURE FOR ADP3207

1. Build the circuit based on compensation values computed

from Equation 1 to Equation 39.

11. Remove the dc load from the circuit and hook up the dynamic

load.

2. Hook-up the dc load to the circuit. Turn the circuit on and

verify operation. Check for jitter at no load and full load.

12. Hook up the scope to the output voltage and set it to dc

coupling with the time scale at 100 µs/div.

DC Loadline Setting

13. Set the dynamic load for a transient step of about 40 A at

1 kHz with a 50% duty cycle.

3. Measure the output voltage at no load (V_NL). Verify that it

is within tolerance.

14. Measure the output waveform (using the dc offset on scope

to see the waveform, if necessary). Try to use the vertical

scale of 100 mV/div or finer.

4. Measure the output voltage at full load and at cold (V_FLCOLD).

Let the board set for a ~10 minutes at full load and measure

the output (V_FLHOT). If there is a change of more than a few

millivolts, then adjust R_CS1and R_CS2using Equation 40 and

Equation 41.

15. Users should see a waveform that similar to the one in

Figure 15. Use the horizontal cursors to measure V_ACDRP

and V_DCDRPas shown. Do not measure the undershoot or

overshoot that occurs immediately after the step.

V_NL−V_FLCOLD

V_NL−V_FLHOT

(40)

R_{CS2(NEW )}= R_CS2(OLD)

×

16. If the V_ACDRPand V_DCDRPare different by more than a couple

of mV, use the following to adjust C_CS(note that users may

need to parallel different values to get the right one due to

the limited standard capacitor values available. It is also wise

to have locations for two capacitors in the layout for this):

5. Repeat Step 4 until cold and hot voltage measurements

remain the same.

6. Measure output voltage from no load to full load using 5 A

steps. Compute the load line slope for each change and

then average it to get the overall load line slope (R_OMEAS).

V_ACDRP

(42)

C_CS(NEW)= C_CS(OLD)

×

V_DCDRP

7. If R_OMEASis off from R_Oby more than 0.05 mΩ, use the

17. Repeat Steps15 and Step 16. Repeat adjustments if

necessary. Once complete, do not change C_CSfor the

rest of the procedure.

following to adjust the R_PHvalues:

R_OMEAS

(41)

R_PH(NEW)= R_PH(OLD)

×

R_O

18. Set dynamic load step to maximum step size. Do not use a

step size larger than needed. Verify that the output waveform

is square, which means V_ACDRPand V_DCDRPare equal.

8. Repeat Step 6 and Step 7 to check load line and repeat

adjustments if necessary.

9. Once complete with dc load line adjustment, do not change

R_PH, R_CS1, R_CS2, or R_THfor the rest of procedure.

Note: Make sure that the load step slew rate and turn-on

are set for a slew rate of ~150 A/µs to 250 A/µs (for

example, a load step of 50 A should take 200 ns to 300 ns)

with no overshoot. Some dynamic loads have an excessive

turn-on overshoot if a minimum current is not set properly

(this is an issue if you are using a VTT tool).

10. Measure output ripple at no load and full load with a scope

to make sure it is within specification.

Rev. 0 | Page 27 of 32

ADP3207

Initial Transient Setting

LAYOUT AND COMPONENT PLACEMENT

19. With dynamic load still set at the maximum step size, expand

the scope time scale to see 2 µs/div to 5 µs/div. A waveform

that has two overshoots and one minor undershoot can result

(see Figure 15). Here, VDROOP is the final desired value.

The following guidelines are recommended for optimal

performance of a switching regulator in a PC system.

General Recommendations

For effective results, at least a four-layer PCB is recommended.

This allows the needed versatility for control circuitry

interconnections with optimal placement, power planes for

ground, input and output power, and wide interconnection

traces in the rest of the power delivery current paths. Note that

each square unit of 1 ounce copper trace has a resistance of

~0.53 mΩ at room temperature.

V

DROOP

When high currents need to be routed between PCB layers, vias

should be used liberally to create several parallel current paths so

that the resistance and inductance introduced by these current

paths are minimized, and the via current rating is not exceeded.

V

TRAN1

V

TRAN2

If critical signal lines (including the output voltage sense lines of

the ADP3207) must cross through power circuitry, then a signal

ground plane should be interposed between those signal lines

and the traces of the power circuitry. This serves as a shield to

minimize noise injection into the signals at the expense of

making signal ground a bit noisier.

Figure 15. Transient Setting Waveform, Load Step

20. If both overshoots are larger than desired, make the

following adjustments in the order they appear. Note that if

these adjustments do not change the response, then users

are limited by the output decoupling. In addition, check the

output response each time a change is made, as well as the

switching nodes to make sure they are still stable.

An analog ground plane should be used around and under the

ADP3207 for referencing the components associated with the

controller. Tie this plane to the nearest output decoupling

capacitor ground. It should not be tied to any other power

circuitry to prevent power currents from flowing in it.

a. Make ramp resistor larger by 25% (R_RAMP).

b. For V_TRAN1, increase C_Bor increase switching

frequency.

The best location for the ADP3207 is close to the CPU corner

c. For V_TRAN2, increase R_Aand decrease C_Aboth by 25%.

PSI

where all the related signal pins are located: VID0 to VID6,

V_CCSENSE, and V_SSSENSE.

,

21. For load release (see Figure 16), if V_TRANRELis larger than

the IMVP-6 specification, there is not enough output

capacitance. Either more capacitance is needed or the

inductor values needed to be smaller. If the inductors are

changed, then start the design over using Equation 1 to

Equation 39 and this tuning guide.

The components around the ADP3207 should be located close to

the controller with short traces. The most important traces to keep

short and away from other traces are the FB and CSSUM pins (refer

to Figure 10 for more details on layout for the CSSUM node.) The

MLCC for the VCC decoupling should be placed as close to the

VCC pin as possible. In addition, the noise filtering cap on the

TTSENSE pin should also be as close to that pin as possible.

The output capacitors should be connected as closely as possible

to the load (or connector) that receives the power (for example,

a microprocessor core). If the load is distributed, then the

capacitors should also be distributed, and generally in

proportion to where the load tends to be more dynamic.

V

TRANREL

V

DROOP

Figure 16. Transient Setting Waveform, Load Release

Rev. 0 | Page 28 of 32

ADP3207

For best EMI containment, use a solid power ground plane as one

of the inner layers extending fully under all the power components.

Power Circuitry

Avoid crossing any signal lines over the switching power path

loop. This path should be routed on the PCB to encompass the

shortest possible length in order to minimize radiated switching

noise energy (that is, EMI) and conduction losses in the board.

Failure to take proper precautions often results in EMI

problems for the entire PC system as well as noise-related

operational problems in the power converter control circuitry.

The switching power path is the loop formed by the current

path through the input capacitors and the power MOSFETs,

including all interconnecting PCB traces and planes. The use of

short and wide interconnection traces is especially critical in this

path for two reasons: it minimizes the inductance in the switching

loop, which can cause high energy ringing, and it accommodates

the high current demand with minimal voltage loss.

It is important for conversion efficiency that MOSFET drivers,

such as ADP3419, are placed as close to the MOSFETs as

possible. Thick and short traces are required between the driver

and MOSFET gate, especially for the SR MOSFETs. Ground the

MOSFET driver’s GND pin through immediately close vias.

Signal Circuitry

The output voltage is sensed and regulated between the FB pin

and the FBRTN pin, which connects to the signal ground at the

load. To avoid differential mode noise pickup in the sensed

signal, the loop area should be small. Thus, route the FB and

FBRTN traces adjacent to each other atop the power ground

plane back to the controller. To filter any noise from the FBRTN

trace, using a 1000 pF MLCC is suggested. It should be placed

between the FBRTN pin and local ground and as close to the

FBRTN pin as possible.

Whenever a power-dissipating component (for example, a

power MOSFET) is soldered to a PCB, the liberal use of vias,

both directly on the mounting pad and immediately

surrounding it, is recommended. Two important reasons for

this are: improved current rating through the vias, and

improved thermal performance from vias extended to the

opposite side of the PCB where a plane can more readily

transfer the heat to the air. Make a mirror image of any pad

being used to heat sink the MOSFETs on the opposite side of

the PCB to achieve the best thermal dissipation to the air

around the board. To further improve thermal performance, the

largest possible pad area should be used.

Connect the feedback traces from the switch nodes as close as

possible to the inductor. The CSREF signal should be Kelvin

connected to the center point of the copper bar, which is the

V_COREcommon node for the inductors of all phases.

In the back side of the ADP3207 package, a metal pad can be

used as the device heat sink. In addition, running vias under the

ADP3207 is not recommended because the metal pad can cause

shorting between vias.

The output power path should also be routed to encompass a

short distance. The output power path is formed by the current

path through the inductor, the output capacitors, and the load.

Rev. 0 | Page 29 of 32

ADP3207

OUTLINE DIMENSIONS

6.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

31

40

1

30

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

4.25

4.10 SQ

3.95

5.75

BCS SQ

EXPOSED

PAD

(BOT TOM VIEW)

0.50

0.40

0.30

21

10

20

0.25 MIN

4.50

REF

12° MAX

0.80 MAX

0.65 TYP

EXPOSED PADDLE CAN

BE GROUNDED.

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 17. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm x 6 mm Body, Very Thin Quad

(CP-40)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range Package Description

Package Option Order Quantity

ADP3207JCPZ-RL¹0°C to 100°C

40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40

2,500

¹Z = Pb-free part.

Rev. 0 | Page 30 of 32

ADP3207

NOTES

Rev. 0 | Page 31 of 32

ADP3207

NOTES

registered trademarks are the property of their respective owners.

D05782-0-1/06(0)

Rev. 0 | Page 32 of 32


型号：	ADP3207JCPZ-RL
厂家：	ADI
描述：	IC,SMPS CONTROLLER,CURRENT/VOLTAGE,MOS,LLCC,40PIN,PLASTIC
文件：	总32页 (文件大小：575K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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