ADP3208AJCPZ-RL [ADI]
7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller;
| 型号： | ADP3208AJCPZ-RL |
| 厂家： | 
ADI |
| 描述： | 7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller |
| 文件： | 总38页 (文件大小：784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
7-Bit, Programmable, Dual-Phase, Mobile,
CPU, Synchronous Buck Controller
ADP3208A
General Description
FEATURES
The ADP3208 is a highly efficient, multiphase, synchronous
Single-chip solution
Fully compatible with the Intel® IMVP-6+™ specifications
Integrated MOSFET drivers
Selectable 1- or 2-phase operation with up to 1 MHz per
phase switching frequency
Guaranteed 8 mV worst-case differentially sensed core
voltage error over temperature
Automatic power-saving mode maximizes efficiency with
light load during deeper sleep operation
Soft transient control reduces inrush current and audio noise
Active current balancing between output phases
Independent current limit and load line setting inputs for
additional design flexibility
buck switching regulator controller. With its integrated drivers,
the ADP3208 is optimized for converting the notebook battery
voltage into the core supply voltage required by high performance
Intel processors. An internal 7-bit DAC is used to read a VID code
directly from the processor and to set the CPU core voltage to a
value within the range of 0.3 V to 1.5 V. The phase relationship
of the output signals ensures interleaved 2-phase operation.
The ADP3208 uses a multimode architecture run at a program-
mable switching frequency and optimized for efficiency depending
on the output current requirement. The ADP3208 switches
between single- and dual-phase operation to maximize efficiency
with all load conditions. The chip includes a programmable
load line slope function to adjust the output voltage as a
function of the load current so that the core voltage is always
optimally positioned for a load transient. The ADP3208 also
provides accurate and reliable short-circuit protection, adjustable
current limiting, and a delayed power good output. The IC
supports on-the-fly output voltage changes requested by the
CPU.
Built-in power good blanking supports
voltage identification (VID) on-the-fly transients
7-bit, digitally programmable DAC with 0.3 V to 1.5 V output
Short-circuit protection with programmable latch-off delay
Clock enable output delays the CPU clock until the core
voltage is stable
Output power or current monitor options
48-lead LFCSP
ADP3208A version has 1.0V Boot voltage
APPLICATIONS
Notebook power supplies for next-generation Intel
processors
ADP3208 is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 48-lead
LFCSP
FUNCTIONAL BLOCK DIAGRAM
RAMP VRPM RPM
RT
OSCILLATOR
PWM
BST2
DRVH2
SW2
PVCC2
DRVL2
PGND2
DRV2
IN
RAMP
GENER-
ATOR
PWM
LATCH
PHASE
CMPS
OD2
CONTROL
SP
BST1
DRVH1
SW1
PVCC1
DRVL1
PGND1
PSI
DRV1
IN
SWITCH
AMPS
OD1B
OD1A
VREF
VID6, VID5,
VID4, VID3,
VID2, VID1,
VID0
+
–
REFER-
ENCE
SELECT
VDAC
VID
DAC
–
+
COMP
FB
LLINE
CSCOMP
CSSUM
CSREF
ERR AMP
–
+
+
–
FBRTN
SS
ST
VARFREQ
DPRSTP
DPRSLP
SS
PWRGD
PGDELAY
CLKEN
CSAMP
CLIM
CMP
–
+
CLREF
CLTHSEL
OVTH
–
+
HOUSE-
KEEPING
+
+
–
–
PSI
UVTH
CLIM
VCC
REFTH
REF
VREF
BIAS
EN
VRTT
TTSNS
VCC
UVLO
BIAS
+
–
GND
CSAVG
–
+
PMON
PWM
ADP3208
FBRTN
PMON PMONFS
Figure 1.
©2008 SCILLC. All rights reserved.
January 2008 – Rev. 2
Publication Order Number:
ADP3208A/D
ADP3208A
TABLE OF CONTENTS
Features...............................................................................................1
Reverse Voltage Protection........................................................23
Output Enable and UVLO.........................................................23
Thermal Throttling Control......................................................23
Power Monitor Function ...........................................................24
Application Information ................................................................27
Setting the Clock Frequency for PWM....................................27
Applications .......................................................................................1
General Description..........................................................................1
Functional Block Diagram...............................................................1
Revision History................................................................................2
Specifications .....................................................................................3
Timing Diagram................................................................................7
Absolute Maximum Ratings ............................................................8
ESD Caution ..................................................................................8
Pin Configuration and Function Descriptions .............................9
Test Circuits .....................................................................................11
Typical Performance Characteristics............................................12
Theory of Operation.......................................................................15
Number of Phases .......................................................................15
Operation Modes ........................................................................15
Differential Sensing of Output Voltage....................................18
Output Current Sensing.............................................................18
Active Impedance Control Mode .............................................18
Current Control Mode and Thermal Balance.........................19
Voltage Control Mode ................................................................19
Power Good Monitoring............................................................19
Power-Up Sequence and Soft Start...........................................19
Soft Transient...............................................................................20
Current Limit, Short-Circuit, and Latch-Off Protection.......20
Changing VID on the Fly...........................................................21
Output Crowbar..........................................................................23
Setting the Switching Frequency for
RPM Operation of Phase 1........................................................27
Soft Start and Current Limit Latch-Off Delay Times ............27
PWRGD Delay Timer ................................................................28
Inductor Selection.......................................................................28
COUT Selection..............................................................................30
Power MOSFETs .........................................................................31
Ramp Resistor Selection ............................................................32
COMP Pin Ramp........................................................................32
Current Limit Setpoint...............................................................32
Power Monitor ............................................................................33
Feedback Loop Compensation Design....................................33
CIN Selection and Input Current di/dt Reduction ..................34
Soft Transient Setting .................................................................34
Selecting Thermal Monitor Components................................34
Tuning Procedure for ADP3208 ...............................................35
Layout and Component Placement..........................................36
Outline Dimension .........................................................................38
Ordering Guide...........................................................................38
REVISION HISTORY
01/08—Rev 2: Conversion to ON Semiconductor
08/07—Rev Sp1: Changed to ADP3208A
10/05—Rev Sp0: Initial Version
Rev. 2 | Page 2 of 38 | www.onsemi.com
ADP3208A
SPECIFICATIONS
VCC = PVCC1 = PVCC2 = BST1 = BST2 = high = 5 V, FBRTN = GND = SW1 = SW2 = PGND1 = PGND2 = low = 0 V, EN = VARFREQ =
high, DPRSLP = 0 V, PSI = 1.05 V, DPRSTP = 0 V, VVID = 1.2000 V, TA = 0°C to 100°C, unless otherwise noted.1 Current entering a pin
(sunk by the device) has a positive sign.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VOLTAGE ERROR AMPLIFIER
Output Voltage Range
DC Accuracy
VCOMP
VFB
0.8
3.6
V
Relative to nominal VVID
LLINE = CSREF
,
VVID = 0.5000 V to 1.5000 V
VVID = 0.3000 V to 0.4875 V
Start-up
LLINE − CSREF = −80 mV
LLINE − CSREF = −200 mV
−8
+8
mV
mV
V
mV
mV
nA
−10
0.992
78
+10
1.008
82
Boot Voltage
LLINE Positioning Accuracy
VBOOT(FB)
1.0
80
ΔVFB
180
−80
−1
200
220
+80
+1
LLINE Input Bias Current
Differential Nonlinearity2
Line Regulation
ILLINE
LSB
%
VCC = 4.75 V to 5.25 V
0.005
ΔVFB
IFB
Input Bias Current
FBRTN Current
−1
+1
μA
μA
mA
IFBRTN
ICOMP
60
400
Output Current
FB forced to VVID − 3%
FB forced to VVID + 3%
COMP = FB
−4
900
20
μA
MHz
V/μs
Gain Bandwidth Product2
Slew Rate2
GBW
CCOMP = 10 pF
25
VID DAC INPUTS
Input Low Voltage
Input High Voltage
Input Current
VID Transition Delay Time2
PWM OSCILLATOR
Frequency Range2
Frequency
VIL
VIH
IIN(VID)
VID(x)
VID(x)
Sink current
0.52
0.52
1
0.3
V
V
0.7
400
0.3
μA
ns
VID code change to FB change
3
MHz
kHz
PSI DPRSTP
=
= 1.05 V, DPRSLP = 0 V
fOSC
TA = 25°C, RT = 250 kΩ, PWM mode,
VARFREQ = high, VVID = 1.5000 V
TA = 25°C, RT = 125 kΩ, PWM mode,
VARFREQ = high, VVID = 1.5000 V
RT = 250 kΩ to GND, VVID = 1.5000 V
VARFREQ = low
400
750
1.25
kHz
V
RT Voltage
VRT
1.08
1.32
VRPM Reference Voltage
VVRPM
IVRPM = 0
IVRPM = 120 μA
0.95
0.95
1
1
1.05
1.16
V
V
RPM Output Current
RPM Comparator Offset
RAMP Input Voltage
RAMP Input Current Range
RAMP Input Current in Shutdown
CURRENT SENSE AMPLIFIER
Offset Voltage
IRPM
VVID = 1.5000 V, RT = 250 kΩ
−5
−1
1.0
μA
mV
V
VOS(RPM)
VRAMP
IRAMP
−20
0.9
1
+15
1.1
50
PSI
|VCOMP − VRPM|,
= 0 V
EN = high
μA
μA
EN = low or UVLO, RAMP = 19 V
CSSUM − CSREF
1
VOS(CSA)
ICSSUM
−2.0
−65
0
+2.0
+65
3.5
mV
nA
V
V
mA
mA
Input Bias Current
Input Common-Mode Range2
Output Voltage Range
Output Current
CSSUM and CSREF
VCSCOMP
ICSCOMP
0.05
2.7
Sink current
Source current
1
−15
Rev. 2 | Page 3 of 38 | www.onsemi.com
ADP3208A
Parameter
Gain Bandwidth Product2
Slew Rate2
Symbol
GBWCSA
Conditions
Min
Typ
10
10
Max
Unit
MHz
V/μs
CCSCOMP = 10 pF
CURRENT BALANCE AMPLIFIER
Common-Mode Voltage Range2
Input Resistance
VSW(x)
RSW(x)
ISW(x)
−600
30
+200
60
mV
kΩ
μA
%
50
−3.5
Input Current
SW(x) = 0 V
Input Current Matching
SW(x) = 0 V
−5
+5
ΔISW(x)
VZCS(SW1)
Zero Current Switching Threshold
Voltage
DPRSLP = 3.3 V, DCM
−6
mV
DCM Minimum Off Time Masking
CURRENT LIMIT COMPARATOR
Output Current
tOFFMASK
DPRSLP = 3.3 V, SW1 falling
450
ns
ICLIM
RCLIM = 125 kΩ
10
μA
Current Limit Threshold Voltage
VCLTH
VCSREF − VCSCOMP, RCLIM = 125 kΩ,
111
54
125
139
74
mV
SP = low (2-phase),
= 1.05 V
PSI
VCSREF − VCSCOMP, RCLIM = 125 kΩ, SP = low
(2-phase), = 0 V or DPRSLP = low
62.5
125
mV
mV
PSI
VCSREF − VCSCOMP, RCLIM = 125 kΩ,
SP = high (1-phase)
111
139
Current Limit Setting Ratio
VCL/VILIM PSI
,
= 1.05 V
0.1
VCL/VILIM PSI
,
= low, SP = low
0.05
SOFT START/LATCH-OFF TIMER
Output Current
ISS
VSS < 1.7 V, start-up
−10
−8
−48
−2
1.7
2.9
1.65
−6
μA
μA
μA
V
VSS > 1.7 V, normal mode
VSS > 1.7 V, current limit
Start-up, SS rising
−2.5
1.6
−1.5
1.8
Termination Threshold Voltage
Normal Mode Operating Voltage
Current Limit Latch-Off Voltage
SOFT TRANSIENT CONTROL
ST Sourcing Current
VTH(SS)
V
CLKEN
= low
VLOFF(SS)
ISOURCE(ST)
Current limit or PWRGD failure, SS falling
1.55
1.8
V
Fast exit from deeper sleep mode,
DPRSLP = 0 V, ST = VDAC − 0.3 V
Slow exit from deeper sleep mode,
−9
μA
μA
−2.5
DPRSLP = 3.3 V,
= 0,
DPRSTP
ST = VDAC − 0.3 V
ST Sinking Current
ST Offset Voltage
ISINK(ST)
VOS(ST)
Slow entry to deeper sleep,
DPRSLP = 3.3 V, ST = VDAC + 0.3 V
|ST − VVID| at the end of PWRGD
masking
2.5
μA
−25
100
+25
mV
Minimum Capacitance2
CST
pF
Extended PWRGD Masking
Comparator Voltage Threshold
VTH(ST)
|ST − VVID|, DPRSLP = 3.3 V, ST falling
170
mV
DIGITAL CONTROL INPUTS
Input Low Voltage
VIL
VIH
IIN
0.3
0.7
1.0
V
PSI DPRSTP
,
VARFREQ, SP
DPRSLP, EN
V
V
V
Input High Voltage
Input Current
0.7
4
2.3
PSI DPRSTP
,
VARFREQ, SP
DPRSLP, EN
V
V
nA
nA
μA
20
20
60
DPRSTP
, VARFREQ, DPRSLP, SP
EN = low or EN = high
EN = VTH(EN), high-to-low or low-to-high
transition
Rev. 2 | Page 4 of 38 | www.onsemi.com
ADP3208A
Parameter
Symbol
Conditions
= high,
Min
Typ
1
Max
Unit
μA
= high
PSI
DPRSTP
= low
−100
nA
PSI
THERMAL THROTTLING/CROWBAR
DISABLE CONTROL
TTSNS Voltage Range2
Temperature sensing
Crowbar disable threshold disable
VCC = 5 V, TTSNS falling
0.4
0
2.45
50
5
50
2.55
V
mV
V
mV
mV
TTSNS VRTT Threshold Voltage
TTSNS VRTT Threshold Hysteresis
TTSNS Crowbar Disable Threshold
Voltage
VVRTT(TTSNS)
VCBDIS(TTSNS)
2.5
95
50
+1
TTSNS Input Current
TTSNS > 1.0 V, temperature sensing
TTSNS = 0 V, disabling overvoltage
protection
ISINK(VRTT) = 400 μA
ISOURCE(VRTT) = −400 μA
−1
4
μA
μA
−3
VRTT Output Low Voltage
VRTT Output High Voltage
POWER GOOD
VOL(VRTT)
VOH(VRTT)
50
5
100
mV
V
CSREF Undervoltage Threshold
VUV(CSREF)
Relative to VVID = 0.5 V to 1.5 V
Relative to VVID = 0.3125 V to 0.4875 V
Relative to VVID = 0.5 V to 1.5 V
Relative to FBRTN
−300
mV
mV
mV
V
−160
150
1.65
CSREF Overvoltage Threshold
CSREF Crowbar (Overvoltage
Protection) Threshold
VOV(CSREF)
VCB(CSREF)
200
1.7
250
1.75
CSREF Reverse Voltage Detection
Threshold
VRVP(CSREF)
Relative to FBRTN
CSREF falling
CSREF rising
ISINK(PWRGD) = 4 mA
VPWRDG = 5 V
−400
−300
−60
70
mV
mV
mV
μA
−5
200
3
PWRGD Output Low Voltage
PWRGD Output Leakage Current
Power Good Delay Timer
VOL(PWRGD)
0.03
PGDELAY Voltage Detection
Threshold
VTH(PGDELAY)
2.9
V
PGDELAY Charge Current
PGDELAY Discharge Resistance
PWRGD Masking Time
CLOCK ENABLE
IPGDELAY
RPGDELAY
VPGDELAY = 2.0 V
VPGDELAY = 0.2 V
−3
600
130
μA
Ω
μs
Output Low Voltage
Output Leakage Current
ISINK = 4 mA
100
400
1
mV
μA
CLKEN
= 5 V, VSS = GND
POWER MONITOR
PMON Output Resistance
PMON Leakage Current
PMON Oscillator Frequency
PMONFS Voltage Range2
PMONFS Output Current
HIGH-SIDE MOSFET DRIVERS
ISINK = 2 mA
PMON = 5 V
PMONFS = 2 V
16
Ω
1
4
μA
kHz
V
320
−10
1.5
PMONFS = 2.5 V
μA
DRVH Output Resistance, Sourcing
Current
DRVH Output Resistance, Sinking
Current
BST − SW = 4.6 V
BST − SW = 4.6 V
1.9
1.5
3.3
3
Ω
Ω
Transition Times
trDRVH,
tfDRVH
tpdhDRVH
BST − SW = 4.6 V, CL = 3 nF, see Figure 2
BST − SW = 4.6 V, CL = 3 nF, see Figure 2
BST − SW = 4.6 V, see Figure 2
EN = low, shutdown
10
8
16
5
30
25
70
ns
ns
ns
μA
Propagation Delay Time
BST Quiescent Current
Rev. 2 | Page 5 of 38 | www.onsemi.com
ADP3208A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
EN = high, no switching
120
μA
LOW-SIDE MOSFET DRIVERS
Output Resistance, Sourcing
Current
1.8
3.3
Ω
Output Resistance, Sinking Current
Transition Times
1.4
11
9
13
130
2.2
2.5
30
25
30
300
Ω
trDRVL
tfDRVL
tpdlDRVL
tTO(SW)
VZVS(SW)
CL = 3 nF, see Figure 2
CL = 3 nF, see Figure 2
CL = 3 nF, see Figure 2
BST − SW = 4.6 V
ns
ns
ns
ns
V
Propagation Delay Time
SW Transition Timeout
Zero Voltage Switching Detection
Threshold
80
PVCC Quiescent Current
EN = low, shutdown
EN = high, no switching
13
180
μA
μA
SUPPLY
Supply Voltage Range2
Supply Current
VCC
4.5
5.5
10
150
4.5
V
EN = high, normal mode
EN = low, shutdown
VCC rising
5.5
32
4.4
4.2
mA
μA
V
V
mV
VCC OK Threshold Voltage
VCC UVLO Threshold Voltage
UVLO Hysteresis2
VCCOK
VCCUVLO
VCC falling
4.0
150
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 Guaranteed by design or characterization, not production tested.
Rev. 2 | Page 6 of 38 | www.onsemi.com
ADP3208A
TIMING DIAGRAM
Timing is referenced to the 90% and 10% points, unless otherwise noted.
IN
tf
tpdl
DRVL
DRVL
tpdl
DRVH
tr
DRVL
DRVL
tf
DRVH
tpdh
DRVH
tr
DRVH
DRVH
(WITH RESPECT
TO SW)
V
V
TH
TH
tpdh
DRVL
1V
SW
Figure 2. Timing Diagram
Rev. 2 | Page 7 of 38 | www.onsemi.com
ADP3208A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
VCC, PVCC1, PVCC2
FBRTN, PGND1, PGND2
BST1, BST2
DC
t < 200 ns
BST1 to SW1, BST2 to SW2
DRVH1, DRVH2, SW1, SW2
DC
−0.3 V to +6 V
−0.3 V to +0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−0.3 V to +25 V
−0.3 V to +30 V
−0.3 V to +6 V
−5 V to +20 V
−10 V to +25 V
−0.3 V to +6 V
t < 200 ns
ESD CAUTION
DRVH1 to SW1, DRVH2 to SW2,
DRVL1 to PGND1, DRVL2 to PGND2
DC
-0.3 V to +6 V
-5V to +6V
T < 200 ns
RAMP (in Shutdown)
DC
t < 200 ns
−0.3 V to +20 V
−0.3 V to +25 V
−0.3 V to +6 V
−65°C to +150°C
0°C to 100°C
125°C
All Other Inputs and Outputs
Storage Temperature
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA) 2-Layer Board
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
40°C/W
300°C
260°C
Rev. 2 | Page 8 of 38 | www.onsemi.com
ADP3208A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
EN
PWRGD
PGDELAY
CLKEN
FBRTN
FB
1
2
3
4
5
6
7
8
9
36 BST1
PIN 1
35 DRVH1
34 SW1
INDICATOR
33 PVCC1
32 DRVL1
31 PGND1
30 PGND2
29 DRVL2
28 PVCC2
27 SW2
ADP3208
TOP VIEW
COMP
SS
(Not to Scale)
ST
VARFREQ 10
VRTT 11
26 DRVH2
25 BST2
TTSNS 12
Figure 3. LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
EN
Description
Enable Input. Driving the pin low shuts down the chip, disables the driver outputs, pulls PWRGD and VRTT low,
and pulls high.
CLKEN
2
3
4
5
PWRGD
PGDELAY
CLKEN
Power Good Output. Open-drain output. A low logic state means that the output voltage is outside of the VID
DAC defined range.
Power Good Delay Setting Input/Output. A capacitor connected from this pin to GND sets the power good delay
time.
Clock Enable Output. Open-drain output. A low logic state enables the CPU internal PLL clock to lock to the
external clock.
Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the ground
return for the VID DAC and the voltage error amplifier blocks.
FBRTN
6
7
8
FB
COMP
SS
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
Voltage Error Amplifier Output and Frequency Compensation Point.
Soft Start and Latch-Off Delay Setting Input/Output. An external capacitor from this pin to GND sets the soft start
ramp-up time and the current limit latch-off delay ramp-down time.
9
ST
Soft Transient Slew Rate Timing Input/Output. A capacitor from this pin to GND sets the slew rate of the output
voltage when it transitions from one VID setting to another, including boot-to-active VID, VID on the fly, and
deeper sleep entry and exit transients.
10
11
VARFREQ
VRTT
Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code.
Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator temperature
at the remote sensing point exceeded a set alarm threshold level.
12
TTSNS
Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is connected to
VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is connected to this pin and
acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the thermal throttling function and
disables the crowbar, or overvoltage protection (OVP), feature of the chip.
13
PMON
Power Monitor Output. Open-drain output. A pull-up resistor from PMON to CSREF provides a duty cycle
modulated power output signal. An external RC network can be used to convert the digital signal stream to an
averaged power analog output voltage.
14
15
PMONFS
CLIM
Power Monitor Full-Scale Setting Input/Output. A resistor from this pin to GND sets the full-scale value of the
PMON output signal.
Current Limit Setting Input/Output. An external resistor from this pin to GND sets the current limit threshold of
the converter.
Rev. 2 | Page 9 of 38 | www.onsemi.com
ADP3208A
Pin No.
Mnemonic
Description
16
LLINE
Load Line Programming Input. The center point of a resistor divider connected between CSREF and CSSUM can
be tied to this pin to set the load line slope.
17
18
CSCOMP
CSREF
Current Sense Amplifier Output and Frequency Compensation Point.
Current Sense Reference Input. This pin must be connected to the common point of the output inductors. The
node is shorted to GND through an internal switch when the chip is disabled to provide soft stop transient
control of the converter output voltage.
19
20
CSSUM
RAMP
Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor currents to
provide total current information.
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets the
slope of the internal PWM stabilizing ramp used for phase-current balancing.
21
22
VRPM
RPM
RPM Mode Reference Voltage Output.
Ramp Pulse Modulation Current Source Output. A resistor between this pin and VRPM sets the RPM comparator
upper threshold.
23
RT
PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillator
frequency.
24
25
GND
BST2
Analog and Digital Signal Ground.
High-Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltage while
the high-side MOSFET is on.
26
27
28
29
30
31
32
33
34
35
36
DRVH2
SW2
High-Side Gate Drive Output for Phase 2.
Current Balance Input for Phase 2 and Current Return for High-Side Gate Drive.
Power Supply Input/Output of Low-side Gate Driver for Phase 2.
Low-Side Gate Drive Output for Phase 2.
Low-Side Driver Power Ground for Phase 2.
Low-Side Driver Power Ground for Phase 1.
PVCC2
DRVL2
PGND2
PGND1
DRVL1
PVCC1
SW1
Low-Side Gate Drive Output for Phase 1.
Power Supply Input/Output of Low-Side Gate Driver for Phase 1.
Current Balance Input for Phase 1 and Current Return For High-Side Gate Drive.
High-Side Gate Drive Output for Phase 1.
High-Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltage while
the high-side MOSFET is on.
DRVH1
BST1
37
38
VCC
SP
Power Supply Input/Output of the Controller.
Single-Phase Select Input. Logic high state sets single-phase configuration.
39 to 45 VID6 to
VID0
Voltage Identification DAC Inputs. A 7-bit word (the VID code) programs the DAC output voltage, the reference
voltage of the voltage error amplifier without a load (see the VID code table, Table 6).
46
47
Power State Indicator Input. Driving this pin low forces the controller to operate in single-phase mode.
PSI
Deeper Stop Control Input. The logic state of this pin is usually complementary to the state of the DPRSLP pin;
however, during slow deeper sleep exit, both pins are logic low.
DPRSTP
48
DPRSLP
Deeper Sleep Control Input.
Rev. 2 | Page 10 of 38 | www.onsemi.com
ADP3208A
TEST CIRCUITS
7-BIT CODE
5V
100nF
1μF
ADP3208
48
VCC
37
7
5V
1
1.05V
EN
COMP
FB
BST1
SW1
PWRGD
PGDELAY
CLKEN
FBRTN
FB
COMP
SS
ST
VARFREQ
VRTT
PVCC1
DRVL1
PGND1
PGND2
DRVL2
PVCC2
SW2
10kΩ
6
ADP3208
1kΩ
LLINE
CSREF
GND
10nF
–
+
16
18
24
DRVH2
BST2
ΔV
TTSNS
VID
DAC
1V
20kΩ
250kΩ
ΔV = FB
FB
– FB
ΔV = 0mV
100nF
ΔV = 80mV
Figure 4. Closed-Loop Output Voltage Accuracy
Figure 6. Positioning Accuracy
ADP3208
VCC
37
17
19
18
24
5V
CSCOMP
CSSUM
CSREF
GND
100nF
39kΩ
1kΩ
1V
CSCOMP – 1V
V
=
OS
40
Figure 5. Current Sense Amplifier, VOS
Rev. 2 | Page 11 of 38 | www.onsemi.com
ADP3208A
TYPICAL PERFORMANCE CHARACTERISTICS
VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted.
95
90
88
86
84
82
80
78
76
74
72
70
V
= 8V
IN
90
85
80
75
70
65
60
55
50
PWM
V
= 19V
IN
V
= 12V
IN
RPM AUTOMATIC CCM/DCM
RPM CCM ONLY
fSW = 318kHz
40
V
= 12V
40
IN
0
10
20
30
0
10
20
30
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 7. PWM Mode Efficiency vs. Load Current
Figure 10. Efficiency vs. Load Current in All Modes
95
90
85
80
75
70
65
60
400
350
300
250
200
150
100
50
V
V
= 8V
IN
CCM ONLY
= 19V
IN
V
= 12V
IN
AUTOMATIC CCM/DCM
0
0
10
20
30
0
5
10
15
20
25
30
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 8. RPM Mode Efficiency vs. Load Current in CCM Only
Figure 11. Switching Frequency vs. Load Current in RPM
91
500
V
= 8V
IN
VARFREQ = 0V
89
87
85
83
81
79
77
75
400
300
200
100
0
V
= 12V
IN
V
= 19V
IN
CCM/DCM
TRANSITION
VARFREQ = 5V
RT = 237kΩ
1.25 1.50
0
10
20
30
0
0.25
0.50
0.75
1.00
LOAD CURRENT (A)
VID OUTPUT VOLTAGE (V)
Figure 9. RPM Mode Efficiency vs. Load Current Automatic in CCM/DCM
Figure 12. Switching Frequency vs. VID Output Voltage in PWM
Rev. 2 | Page 12 of 38 | www.onsemi.com
ADP3208A
350
300
250
200
150
100
50
1.54
1.52
1.50
1.48
1.46
1.44
1.42
1.40
1.38
1.36
SPECIFIED LOAD LINE
+2%
MEASURED LOAD LINE
–2%
RT = 237kΩ
RPM = 80.5kΩ
0
0
0.5
1.0
1.5
0
10
20
30
40
50
OUTPUT VOLTAGE (V)
LOAD CURRENT (A)
Figure 13. Switching Frequency vs. Output Voltage in RPM
Figure 16. Load Line Accuracy
1200
180
160
140
120
100
80
1000
800
600
400
200
0
60
40
20
V
= 12V
IN
EN = LOW
0
0
20
40
60
80
0
2
4
6
OUTPUT POWER (W)
VCC VOLTAGE (V)
Figure 14. PMON Voltage vs. Output Power
Figure 17. VCC Current vs. VCC Voltage with Enable Low
10000
1000
100
CLKEN
PWRGD
3
SS
VID = 1.5V
VID = 1.2V
OUTPUT VOLTAGE
VID = 0.675V
2
10
10
CH1 2.00V CH2 1.00V
CH3 2.00V CH4 1.00V
M2.00ms
13.60%
A
CH4
740mV
100
1000
10000
T
RT (kΩ)
Figure 18. Start-Up Waveforms
Figure 15. Per Phase Switching Frequency vs. RT Resistor
Rev. 2 | Page 13 of 38 | www.onsemi.com
ADP3208A
OUTPUT VOLTAGE
4
PSI
2
4
OUTPUT VOLTAGE
L1 CURRENT
L2 CURRENT
2
SWITCH NODE 1
R1
SWITCH NODE 1
1
3
1
SWITCH NODE 2
SWITCH NODE 2
CH1 10.0V
CH3 5.00A
CH2 5.00A
CH4 20.0mV
M1.00μs
20.00%
A
CH3
8.00A
CH1 10.0V CH2 1.00V
CH3 10.0V CH4 20.0mV~
M4.00μs
14.40%
A
CH2
600mV
T
REF1 10.0V 1.00μs
T
Figure 19. Dual-Phase, Interleaved PWM Waveform, 20 A Load
Figure 22. PSI Transition
4
OUTPUT VOLTAGE
OUTPUT VOLTAGE
4
M40.0μs
14.20%
A
CH4
1.02V
M1.00μs
10.40%
A
CH4
2.00mV
CH4 50.0mV
CH4 10.0mV
T
T
Figure 20. Load Transient 9 A to 44 A
Figure 23. PWM Mode Output Ripple, 40 A Load, VIN = 12 V
OUTPUT VOLTAGE
4
M10.0μs
14.20%
A
CH4
1.02V
CH4 50.0mV
T
Figure 21. Load Transient 9 A to 44 A
Rev. 2 | Page 14 of 38 | www.onsemi.com
ADP3208A
THEORY OF OPERATION
The ADP3208 combines multimode pulse width modulated
(PWM) control and ramp pulse modulated (RPM) control with
multiphase logic outputs for use in single- and dual-phase
synchronous buck CPU core supply power converters. The
internal 7-bit VID DAC conforms to the Intel IMVP-6+
specifications.
OPERATION MODES
The number of phases can be static (see the Number of Phases
section) or dynamically controlled by system signals to
optimize the power conversion efficiency with heavy and light
loads.
If SP is set low (user-selected dual-phase mode) during a VID
transient or with a heavy load condition (indicated by DPRSLP
being low and PSI being high), the ADP3208 runs in 2-phase,
interleaved PWM mode to achieve minimal VCORE output voltage
ripple and the best transient performance possible. If the load
becomes light (indicated by PSI being low or DPRSLP being
high), ADP3208 switches to single-phase mode to maximize the
power conversion efficiency.
Multiphase operation is important for producing the high
currents and low voltages demanded by today’s microprocessors.
Handling high currents in a single-phase converter would put
too high of a thermal stress on system components such as the
inductors and MOSFETs.
The multimode control of the ADP3208 is a stable, high
performance architecture that includes
•
•
Current and thermal balance between phases
High speed response at the lowest possible switching
frequency and minimal count of output decoupling capacitors
Minimized thermal switching losses due to lower frequency
operation
In addition to changing the number of phases, the ADP3208 is
also capable of dynamically changing the control method. In
dual-phase operation, the ADP3208 runs in PWM mode, where
the switching frequency is controlled by the master clock. In
single-phase operation (commanded by the PSI low state), the
ADP3208 runs in RPM mode, where the switching frequency is
controlled by the ripple voltage appearing on the COMP pin. In
RPM mode, the DRVH1 pin is driven high each time the
COMP pin voltage rises to a voltage limit set by the VID voltage
and an external resistor connected between the VRPM and
RPM pins. If the device is in single-phase mode and the system
signal DPRSLP is asserted high during the deeper sleep mode of
CPU operation, the ADP3208 continues running in RPM mode
but offers the option of turning off the low-side (synchronous
rectifier) MOSFET when the inductor current drops to 0.
Turning off the low-side MOSFETs at the zero current crossing
prevents reversed inductor current build up and breaks
synchronous operation of high- and low-side switches. Due to
the asynchronous operation, the switching frequency becomes
slower as the load current decreases, resulting in good power
conversion efficiency with very light loads.
•
•
•
•
•
•
High accuracy load line regulation
High current output by supporting 2-phase operation
Reduced output ripple due to multiphase ripple cancellation
High power conversion efficiency with heavy and light loads
Increased immunity from noise introduced by PC board
layout constraints
Ease of use due to independent component selection
Flexibility in design by allowing optimization for either low
cost or high performance
•
•
NUMBER OF PHASES
The number of operational phases can be set by the user. Tying
the SP pin to the VCC pin forces the chip into single-phase
operation; otherwise, dual-phase operation is automatically
selected and the chip switches between single- and dual-phase
modes as the load changes to optimize power conversion
efficiency.
Table 4 summarizes how the ADP3208 dynamically changes the
number of active phases and transitions the operation mode
based on system signals and operating conditions.
In dual-phase configuration, SP is low and the timing
relationship between the two phases is determined by internal
circuitry that monitors the PWM outputs. Because each phase
is monitored independently, operation approaching 100% duty
cycle is possible. In addition, more than one output can be
active at a time, permitting overlapping phases.
Rev. 2 | Page 15 of 38 | www.onsemi.com
ADP3208A
Table 4. Phase Number and Operation Modes1
No. of Phases
Selected by
the User
N [2 or 1]
N [2 or 1]
*
*
*
*
No. of Phases
in Operation
No.
PSI
*
1
0
0
DPRSLP
*
VID Transition2
Current Limit
*
*
No
Yes
No
Yes
Operation Modes3
PWM, CCM only
PWM, CCM only
RPM, CCM only
PWM, CCM only
Yes
No
No
No
No
No
N
N
1
1
1
1
0
0
0
1
1
*
*
RPM, automatic CCM/DCM
PWM, CCM only
1 * = don’t care.
2 VID transient period is the time following any VID change, including entry into and exit from deeper sleep mode. The duration of VID transient period is the same as
that of PWRGD masking time.
3 CCM stands for continuous current mode, and DCM stands for discontinuous current mode.
5V
VRMP
FLIP-FLOP
I
= A × I
RAMP
R
R
S
Q
BST1
VCC
GATE DRIVER
RD
BST
DRVH
R
I
L
DRVH1
SW1
C
R
IN
SW
DCM
FLIP-FLOP
400ns
Q
1V
DRVL
LOAD
S
Q
DRVL1
Q
5V
RD
R2
R1
R1
BST2
VCC
GATE DRIVER
BST
DRVH
DRVH2
SW2
L
R
I
R2
30mV
SW
IN
1V
DCM
DRVL
DRVL2
CSREF
VDC
+–
–
+
+
+
V
CS
CSSUM
CSCOMP
COMP
FBRTN
LLINE
FB
R
R
PH
CS
C
C
B
R
A
A
C
CS
R
PH
C
FB
R
FB
Figure 24. Single-Phase RPM Mode
Rev. 2 | Page 16 of 38 | www.onsemi.com
ADP3208A
5V
BST1
VCC
GATE DRIVER
BST
DRVH
I
= A × I
R RAMP
R
FLIP-FLOP
DRVH1
SW1
R
L
I
CLOCK
OSCILLATOR
SW
IN
S
Q
DRVL
DRVL1
RD
5V
C
LOAD
R
A
D
BST2
VCC
GATE DRIVER
0.2V
BST
DRVH
I
= A × I
R RAMP
R
FLIP-FLOP
DRVH2
SW2
R
I
L
CLOCK
OSCILLATOR
SW
S
Q
DRVL
DRVL2
RD
C
R
VCC
A
D
VDC
+–
CSREF
CSSUM
0.2V
–
+
+
V
CS
RAMP
+
CSCOMP
COMP
FBRTN
LLINE
FB
A
R
R
CS
PH
R
C
C
A
B
C
R
CS
PH
C
FB
R
FB
Figure 25. Dual-Phase PWM Mode
Rev. 2 | Page 17 of 38 | www.onsemi.com
ADP3208A
proper voltage positioning vs. load current and for over current
detection. Sensing the current delivered to the load is an
inherently more accurate method than detecting peak current
or sampling the current across a sense element, such as the low-
side MOSFET. The current sense amplifier can be configured
several ways, depending on system optimization objectives, and
the current information can be obtained by
Setting Switch Frequency
Master Clock Frequency in PWM Mode
When the ADP3208 runs in PWM, the clock frequency of the
ADP3208 is set by an external resistor connected from the RT
pin to GND. The frequency is constant at a given VID code but
varies with the VID voltage: The lower the VID voltage, the
lower the clock frequency. The variation of clock frequency
with VID voltage maintains constant VCORE ripple and improves
power conversion efficiency at lower VID voltages. Figure 15
shows the relationship between clock frequency and VID
voltage, parameterized by RT resistance.
•
Output inductor ESR sensing without the use of a
thermistor for the lowest cost
•
Output inductor ESR sensing with the use of a thermistor
that tracks inductor temperature to improve accuracy
To determine the switching frequency per phase, divide the
clock by the number of phases in use.
•
Discrete resistor sensing for the highest accuracy
At the positive input of the CSA, the CSREF pin is connected to
the output voltage. At the negative input (that is, the CSSUM pin
of the CSA), signals from the sensing element (in the case of
inductor DCR sensing, signals from the switch node side of the
output inductors) are summed together by series summing
resistors. The feedback resistor between the CSCOMP and
CSSUM pins sets the gain of the current sense amplifier, and a
filter capacitor is placed in parallel with this resistor. The current
information is then given as the voltage difference between the
CSCOMP and CSREF pins. This signal is used internally as a
differential input for the current limit comparator.
An additional resistor divider connected between the CSCOMP
and CSREF pins with the midpoint connected to the LLINE pin
can be used to set the load line required by the microprocessor
specification. The current information to set the load line is
then given as the voltage difference between the LLINE and
CSREF pins. This configuration allows the load line slope to be
set independently from the current limit threshold. If the current
limit threshold and load line do not have to be set independently,
the resistor divider between the CSCOMP and CSREF pins can
be omitted and the CSCOMP pin can be connected directly to
LLINE. To disable voltage positioning entirely (that is, to set no
load line), LLINE should be tied to CSREF.
Switching Frequency in RPM Mode—
Single-Phase Operation
In single-phase RPM mode, the switching frequency is
controlled by the ripple voltage on the COMP pin, rather than
by the master clock. Each time the COMP pin voltage exceeds
the RPM pin voltage threshold level determined by the VID
voltage and the external resistor connected between RPM and
VRPM, an internal ramp signal is started and DRVH1 is driven
high. The slew rate of the internal ramp is programmed by the
current entering the RAMP pin. One-third of the RAMP
current charges an internal ramp capacitor (5 pF typical) and
creates a ramp. When the internal ramp signal intercepts the
COMP voltage, the DRVH1 pin is reset low.
In continuous current mode, the switching frequency of RPM
operation is almost constant. While in discontinuous current
conduction mode, the switching frequency is reduced as a
function of the load current.
DIFFERENTIAL SENSING OF OUTPUT VOLTAGE
The ADP3208 combines differential sensing with a high accuracy
VID DAC, referenced by a precision band gap source and a low
offset error amplifier, to meet the rigorous accuracy requirement
of the Intel IMVP-6+ specification. In steady-state mode, the
combination of the VID DAC and error amplifier maintain the
output voltage for a worst-case scenario within 8 mV of the
full operating output voltage and temperature range.
The CPU core output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to the
positive regulation point—the VCC remote sensing pin of the
microprocessor. FBRTN should be connected directly to the
negative remote sensing point—the VSS sensing point of the
CPU. The internal VID DAC and precision voltage reference are
referenced to FBRTN and have a maximum current of 200 μA
for guaranteed accurate remote sensing.
To provide the best accuracy for current sensing, the CSA has a
low offset input voltage and the sensing gain is set by an external
resistor ratio.
ACTIVE IMPEDANCE CONTROL MODE
To control the dynamic output voltage droop as a function of the
output current, the signal that is proportional to the total output
current, converted from the voltage difference between LLINE
and CSREF, can be scaled to be equal to the required droop
voltage. This droop voltage is calculated by multiplying the droop
impedance of the regulator by the output current. This value is
used as the control voltage of the PWM regulator. The droop
voltage is subtracted from the DAC reference output voltage, and
the resulting voltage is used as the voltage positioning setpoint.
The arrangement results in an enhanced feed-forward response.
OUTPUT CURRENT SENSING
The ADP3208 includes a dedicated current sense amplifier
(CSA) to monitor the total output current of the converter for
Rev. 2 | Page 18 of 38 | www.onsemi.com
ADP3208A
the 7-bit VID DAC. The VID codes are listed in Table 6. The
non-inverting input voltage is offset by the droop voltage as a
function of current, commonly known as active voltage
positioning. The output of the error amplifier is the COMP pin,
which sets the termination voltage of the internal PWM ramps.
At the negative input, the FB pin is tied to the output sense
location using RB, a resistor for sensing and controlling the
output voltage at the remote sensing point. The main loop
compensation is incorporated in the feedback network
connected between the FB and COMP pins.
CURRENT CONTROL MODE AND
THERMAL BALANCE
The ADP3208 has individual inputs for monitoring the current
of each phase. The phase current information is combined with
an internal ramp to create a current-balancing feedback system
that is optimized for initial current accuracy and dynamic
thermal balance. The current balance information is
independent from the total inductor current information used
for voltage positioning described in the Active Impedance
Control Mode section.
POWER GOOD MONITORING
The magnitude of the internal ramp can be set so that the
transient response of the system is optimal. The ADP3208
monitors the supply voltage to achieve feed-forward control
whenever the supply voltage changes. A resistor connected from
the power input voltage rail to the RAMP pin determines the
slope of the internal PWM ramp. More detail about
programming the ramp is provided in the Application
Information section.
The ADP3208 should not require external thermal balance
circuitry with good layout. However, if mismatch is desired due
to uneven cooling in phase, external resistors can be added to
individually control phase currents as long as the phase currents
are mismatched by less than 30%. If unwanted mismatch exceeds
30%, a new layout that improves phase symmetry should be
The power good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output that
can be pulled up through an external resistor to a voltage rail—
not necessarily the same VCC voltage rail that is running the
controller. A logic high level indicates that the output voltage is
within the voltage limits defined by a range around the VID
voltage setting. PWRGD goes low when the output voltage is
outside of that range.
Following the IMVP-6+ specification, the PWRGD range is
defined to be 300 mV less than and 200 mV greater than the
actual VID DAC output voltage. For any DAC voltage less than
300 mV, only the upper limit of the PWRGD range is monitored.
To prevent a false alarm, the power good circuit is masked during
various system transitions, including a VID change and entrance
into or exit out of deeper sleep. The duration of the PWRGD
mask is set to approximately 130 μs by an internal timer. If the
voltage drop is greater than 200 mV during deeper sleep entry or
slow deeper sleep exit, the duration of PWRGD masking is
extended by the internal logic circuit.
considered.
ADP3208
RAMP
20
R
R
SW1
SWITCH NODE 1
SWITCH NODE 2
R1
R2
VDC
SW2
C
POWER-UP SEQUENCE AND SOFT START
RESERVED FOR THERMAL BALANCE TUNE
The power-on ramp-up time of the output voltage is set with a
capacitor tied from the SS pin to GND. The capacitance on the
SS pin also determines the current limit latch-off time, as
explained in the Current Limit, Short-Circuit, and
Latch-Off Protection section. The power-up sequence,
including the soft start is illustrated in Figure 27.
Figure 26. Optional Current Balance Resistors
In 2-phase operation, alternate cycles of the internal ramp
control the duty cycle of the separate phases. Figure 26 shows
the addition of two resistors from each switch node to the
RAMP pin; this modifies the ramp-charging current
In VCC UVLO or shutdown mode, the SS pin is held at zero
potential. When VCC ramps to a value greater than the upper
UVLO threshold while EN is asserted high, the ADP3208 enables
internal bias and starts a reset cycle of 50 μs~60 μs. When the
initial reset is complete, the chip detects the number of phases
set by the user and signals to ramp up the SS voltage. During
soft start, the external SS capacitor is charged by an internal 8 μA
current source. The VCORE voltage follows the ramping SS voltage up
to the VBOOT voltage level determined by a burnt-in VID code (1.2V
according to the IMVP-6+ specification). The ADP3208A version
has a VBOOT of 1.0V. All other parameters for the ADP3208A are
identical to ADP3208. While the VCORE is regulated at the VBOOT
voltage, the SS capacitor continues to rise. When the SS pin
individually for each phase. During Phase 1, SW Node 1 is high
(practically at the input voltage potential) and SW Node 2 is low
(practically at the ground potential). As a consequence, the
RAMP pin, through the R2 resistor, sees the tap point of a
divider connected to the input voltage, where RSW1 is the upper
element and RSW2 is the lower element of the divider. During
Phase 2, the voltages on SW Node 1 and SW Node 2 switch and
the resistors swap functions. Tuning RSW1 and RSW2 allows
current to be optimally set for each phase. To increase current
for a given phase, decrease RSW for that phase.
VOLTAGE CONTROL MODE
A high-gain bandwidth error amplifier is used for the voltage
mode control loop. The non-inverting input voltage is set via
Rev. 2 | Page 19 of 38 | www.onsemi.com
ADP3208A
voltage reaches 1.7 V, the ADP3208 immediately asserts the
CLKEN signal low if the VCORE voltage is within the power good
range defined by VBOOT. In addition, the chip reads the VID
codes provided by the CPU on the VID [0:6] input pins. The
VCORE voltage changes from the VBOOT voltage to the VID voltage
by a well-controlled soft transition slope (see the Soft Transient
section). During this transition, the SS capacitor is quickly
charged up to about a 2.9 V SS clamp level, controlled by the SS
source current, which is increased to 48 μA (typical).
The PWRGD signal is asserted after a tCPU_PWRGD delay of
3 ms~10 ms, as specified by IMVP-6+. The power good delay
can be programmed by the capacitor connected from the
PGDELAY pin to GND. Before the CLKEN signal is asserted
low, PGDELAY is reset to 0. Following the assertion of the
CLKEN signal, an internal source current of 2 μA starts
charging up the external capacitor on the PGDELAY pin.
Assuming that the VCORE voltage has settled within the power
good range defined by the VID DAC voltage, the PWRGD
signal is asserted high when the PGDELAY voltage reaches the
2.9 V power good delay termination threshold.
The soft transient feature is implemented with an ST buffer
amplifier that outputs constant sink or source current on the ST
pin that is connected to an external capacitor. The capacitor is
used to program the slew rate of VCORE voltage during a VID
voltage transient. During steady-state operation, the reference
inputs of the voltage error amplifier and the ST amplifier are
connected to the VID DAC output. Consequently, the ST voltage
is a buffered version of VID DAC output. When system signals
trigger a soft transition, the reference input of the voltage error
amplifier switches from the DAC output to the ST output while
the input of the ST amplifier remains connected to the DAC.
The ST buffer input recognizes the almost instantaneous VID
voltage change and tries to track it. However, tracking is not
instantaneous because the slew rate of the buffer is limited by
the source and sink current capabilities of the ST output. Therefore,
the VCORE voltage slew rate is controlled. When the transient period
is complete, the reference input of the voltage amplifier reverts
to the VID DAC output to improve accuracy.
Table 5 lists the source/sink current on the ST pin for various
transitions. Charging/discharging the external capacitor on
the ST pin programs the voltage slew rate of the ST pin and
consequently of the VCORE output. For example, a 390 pF ST
capacitor results in a +10 mV/μs VCORE slew rate for fast exit
from deeper sleep and a 3.3 mV/μs VCORE slew rate for slow
entry into or exit from deeper sleep.
VCC = 5V
EN
ADP3208: VBOOT = 1.2V
ADP3208A: VBOOT = 1.0V
Table 5. Source/Sink Current of ST Pin
1.7V
System Signals1
V
= 1.2V
BOOT
ST Pin
DPRSTP
VID Transient
Current (μA)
DPRSLP
Slow Entry into
Deeper Sleep
High
*
−2.5
V
SS
Fast Exit from
Deeper Sleep
Slow Exit from
Deeper Sleep
Low
High
*
*
+7.5
+2.5
2.5
DAC AND V
CORE
High
*
Transient from
V
BOOT to VID
CLKEN
1 * = do not care.
tCPU_PWRGD
CURRENT LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
PWRGD
Figure 27. Power-Up Sequence of ADP3208
The ADP3208 compares the differential output of a current
sense amplifier to a programmable current limit setpoint to
provide the current-limiting function. The current limit
threshold is set by the user with a resistor connected from the
CLIM pin to GND, utilizing the fixed (10 ꢀA typ) current
sourced by the CLIM pin. The ground-referenced CLIM voltage
is scaled down inside the chip by a factor of 10 in dual-phase
operation and by a factor of 20 in single-phase operation. The
scaled-down and level-shifted VCLTH current limit threshold
floats on top of the CSCOMP voltage. The current limit
comparator monitors the differential voltage appearing across
CSCOMP and CSREF and compares it to the floating VCLTH
threshold. If the sensed current exceeds the threshold, a current
If EN is taken low or VCC drops below the VCC UVLO
threshold, both the SS capacitor and the PGDELAY capacitor
are reset to ground to prepare the chip for a subsequent soft
start cycle.
SOFT TRANSIENT
The ADP3208 provides a soft transient function to reduce
inrush current during various transitions, including entrance
into and exit out of deeper sleep and the transition from VBOOT
to VID voltage. Reducing the inrush current helps decrease the
acoustic noise generated by the MLCC input capacitors and
inductors.
Rev. 2 | Page 20 of 38 | www.onsemi.com
ADP3208A
limit alert is released and the control of the internal COMP
voltage is transferred from the voltage error amplifier to the
current limit amplifier to maintain an average output current
determined by the set current limit level.
When the output voltage is less than 200 mV during start-up, a
secondary current limit is activated. This is necessary because
the voltage swing on the CSCOMP cannot extend below ground.
The secondary current limit circuit clamps the internal COMP
voltage at around 1.6 V, resulting in duty cycle limited operation.
There is also an inherent per phase current limit that protects
individual phases in case any of the phases stop functioning due
to a faulty component. This limit is based on the maximum
normal mode COMP voltage.
If the output current exceeds the current limit threshold or
the output voltage is outside the PWRGD range, the SS pin is
discharged by an internal sink current of 2 μA. A comparator
monitors the SS pin voltage and shuts off the controller when
the voltage drops to less than about 1.65 V. Because the voltage
ramp (2.9 V − 1.65 V = 1.25 V) and the discharge current (2 μA)
are internally fixed, the current limit latch-off delay time is
determined by the external SS pin capacitor selection.
CHANGING VID ON THE FLY
The ADP3208 is designed to track dynamically changing VID
code. As a consequence, the CPU VCC voltage can change
without the need to reset the controller or the CPU. This
concept is commonly referred to as VID on-the-fly (VID OTF)
transient. A VID OTF can occur with either light or heavy load
conditions. The processor alerts the controller that a VID
change is occurring by changing the VID inputs in LSB
incremental steps from the start code to the finish code. The
change can be either upwards or downwards steps.
When a VID input changes, the ADP3208 detects the change
but ignores new code for a minimum of 400 ns. This delay is
required to prevent the device from reacting to digital signal
skew while the 7-bit VID input code is in transition. Additionally,
the VID change triggers a PWRGD masking timer to prevent
a PWRGD failure. Each VID change resets and retriggers the
internal PWRGD masking timer.
As listed in Table 6, during a VID transient, the ADP3208 forces
PWM mode regardless of the state of the system input signals.
For example, this means that if the chip is configured as a dual-
phase controller but is running in single-phase mode due to a
light load condition, a current overload event causes the chip to
switch to dual-phase mode to share the excessive load until the
delayed current limit latch-off cycle terminates.
In user-set single-phase mode, the ADP3208 usually runs in
RPM mode. When a VID transition occurs, however, the
ADP3208 switches to dual-phase PWM mode.
Figure 28 shows how the ADP3208 reacts to a current overload.
OUTPUT VOLTAGE 1V/DIV
4
PWRGD 2V/DIV
1
Light Load RPM DCM Operation
In single-phase normal mode, DPRSLP is pulled low and the
APD3208 operates in continuous conduction mode (CCM)
over the entire load range. The upper and lower MOSFETs are
always running synchronously and in complementary phase.
See Figure 29 for the typical waveforms of the ADP3208
running in CCM with a 7 A load current.
SS PIN 2V/DIV
3
SWITCH NODE 10V/DIV
2
1ms/DIV
CURRENT LIMIT
APPLIED
LATCHED
OFF
OUTPUT VOLTAGE 20mV/DIV
4
Figure 28. Current Overload
The controller cycles the phases during the latch-off delay time.
If the current overload is removed and the PWRGD is recovered
before the 1.65 V threshold is reached, the controller resumes
normal operation and the SS pin voltage recovers to a 2.9 V
clamp level.
INDUCTOR CURRENT 5A/DIV
SWITCH NODE 5V/DIV
2
The latch off can be reset by either removing and reapplying
VCC or by briefly cycling the EN pin low and high. To disable
the current limit latch-off function, an external pull-up resistor
can be tied from the SS pin to the VCC rail. The pull-up current
must override the 2 μA sink current of the SS pin to prevent the
SS capacitor from discharging to a voltage level that is less than
the 1.65 V latch-off threshold.
LOW-SIDE GATE DRIVE 5V/DIV
3
1
400ns/DIV
Figure 29. Single-Phase Waveforms in CCM
If DPRSLP is pulled high, the ADP3208 operates in RPM mode.
If the load condition is light, the chip enters discontinuous con-
duction mode (DCM). Figure 30 shows a typical single-phase
Rev. 2 | Page 21 of 38 | www.onsemi.com
ADP3208A
buck with one upper FET, one lower FET, an output inductor,
an output capacitor, and a load resistor. Figure 31 shows the
path of the inductor current with the upper FET on and the
lower FET off. In Figure 32 the high-side FET is off and the low-
side FET is on. In CCM, if one FET is on, its complementary FET
must be off; however, in DCM, both high- and low-side FETs are
off and no current flows into the inductor (see Figure 7). Figure 34
shows the inductor current and switch node voltage in DCM.
OFF
OFF
L
C
LOAD
Figure 33. Buck Topology Inductor Current During t2 and t3
In DCM with a light load, the ADP3208 monitors the switch
node voltage to determine when to turn off the low-side FET.
Figure 35 shows a typical waveform in DCM with a 1 A load
current. Between t1 and t2 the inductor current ramps down. The
current flows through the source drain of the low-side FET and
creates a voltage drop across the FET with a slightly negative
switch node. As the inductor current ramps down to 0 A, the
switch voltage approaches 0 V, as seen just before t2. When the
switch voltage is approximately −6 mV, the low-side FET is
turned off.
INDUCTOR
CURRENT
SWITCH
NODE
VOLTAGE
Figure 34 shows a small, dampened ringing at t2. This is caused
by the LC created from capacitance on the switch node,
including the CDS of the FETs and the output inductor. This
ringing is normal.
t0 t1
t2
t3 t4
The ADP3208 automatically goes into DCM with a light load.
Figure 35 shows the typical DCM waveform of the ADP3208.
As the load increases, the ADP3208 enters into CCM. In DCM,
frequency decreases with load current. Figure 36 shows
switching frequency vs. load current for a typical design. In
DCM, switching frequency is a function of the inductor, load
current, input voltage, and output voltage.
Figure 34. Inductor Current and Switch Node in DCM
4
OUTPUT VOLTAGE
20mV/DIV
SWITCH NODE 5V/DIV
2
Q1
DRVH
OUTPUT
VOLTAGE
INPUT
VOLTAGE
SWITCH
NODE
L
INDUCTOR CURRENT
5A/DIV
3
1
Q2
C
LOAD
DRVL
LOW-SIDE GATE DRIVE 5V/DIV
Figure 30. Buck Topology
2μs/DIV
Figure 35. Single-Phase Waveforms in DCM with 1 A Load Current
400
ON
350
300
L
OFF
C
LOAD
9V INPUT
250
19V INPUT
Figure 31. Buck Topology Inductor Current During t0 and t1
200
150
100
50
OFF
L
C
LOAD
ON
0
0
2
4
6
8
10
12
14
LOAD CURRENT (A)
Figure 32. Buck Topology Inductor Current During t1 and t2
Figure 36. Single-Phase CCM/DCM Frequency vs. Load Current
Rev. 2 | Page 22 of 38 | www.onsemi.com
ADP3208A
OUTPUT CROWBAR
OUTPUT ENABLE AND UVLO
To prevent the CPU and other external components from
damage due to overvoltage, the ADP3208 turns off the DRVH1
and DRVH2 outputs and turns on the DRVL1 and DRVL2
outputs when the output voltage exceeds the OVP threshold
(1.7 V typical). Turning on the low-side MOSFETs forces the
output capacitor to discharge and the current to reverse, due to
current build up in the inductors. If the output overvoltage is
due to a drain-source short of the high-side MOSFET, turning
on the low-side MOSFET results in a crowbar across the input
voltage rail. The crowbar action blows the fuse of the input rail,
breaking the circuit and thus protecting the microprocessor
from destruction.
For the ADP3208 to begin switching, the VCC supply voltage to
the controller must be greater than the VCCOK threshold and
the EN pin must be driven high. If the VCC voltage is less than
the VCCUVLO threshold or the EN pin is a logic low, the
ADP3208 shuts off. In shutdown mode, the controller holds the
PWM outputs low, shorts the capacitors of the SS and
PGDELAY pins to ground, and drives the DRVH and DRVL
outputs low.
The user must adhere to proper power-supply sequencing
during start-up and shutdown of the ADP3208. All input pins
must be at ground prior to removing or applying VCC, and all
output pins should be left in high impedance state while VCC is
off.
When the OVP feature is triggered, the ADP3208 is latched off.
The latch-off function can be reset by removing and reapplying
VCC to the ADP3208 or by briefly pulling the EN pin low.
THERMAL THROTTLING CONTROL
The ADP3208 includes a thermal monitoring circuit to detect
whether the temperature of the VR has exceeded a user-defined
thermal throttling threshold. The thermal monitoring circuit
requires an external resistor divider connected between the
VCC pin and GND. The divider consists of an NTC thermistor
and a resistor. To generate a voltage that is proportional to
temperature, the midpoint of the divider is connected to the
TTSNS pin. An internal comparator circuit compares the
TTSNS voltage to half the VCC threshold and outputs a logic
level signal at the VRTT output when the temperature trips the
user-set alarm threshold. The VRTT output is designed to drive
an external transistor that in turn provides the high current,
open-drain VRTT signal required by the IMVP-6+
Pulling TTSNS to less than 1 V disables the overvoltage
protection function. In this configuration, VRTT should be tied
to ground.
REVERSE VOLTAGE PROTECTION
Very large reverse current in inductors can cause negative
VCORE voltage, which is harmful to the CPU and other output
components. The ADP3208 provides a reverse voltage
protection (RVP) function without additional system cost. The
VCORE voltage is monitored through the CSREF pin. When
the CSREF pin voltage drops to less than −300 mV, the
ADP3208 triggers the RVP function by disabling all PWM
outputs and driving DRVL1 and DRVL2 low, thus turning off
all MOSFETs. The reverse inductor currents can be quickly
reset to 0 by discharging the built-up energy in the inductor
into the input dc voltage source via the forward-biased body
diode of the high-side MOSFETs. The RVP function is
terminated when the CSREF pin voltage returns to greater than
−100 mV.
specification. The internal VRTT comparator has a hysteresis of
approximately 100 mV to prevent high frequency oscillation of
VRTT when the temperature approaches the set alarm point.
Sometimes the crowbar feature inadvertently causes output
reverse voltage because turning on the low-side MOSFETs
results in a very large reverse inductor current. To prevent
damage to the CPU caused from negative voltage, the ADP3208
maintains its RVP monitoring function even after OVP latch
off. During OVP latch off, if the CSREF pin voltage drops to less
than −300 mV, the low-side MOSFETs is turned off. DRVL
outputs are allowed to turn back on when the CSREF voltage
recovers to greater than −100 mV.
Rev. 2 | Page 23 of 38 | www.onsemi.com
ADP3208A
DC
VOLTAGE
POWER MONITOR FUNCTION
The ADP3208 includes a power monitor. The circuit creates the
product of the output voltage and the output current. The
multiplication is done by converting the differential current
sense signal from CSCOMP to CSREF into a pulse-modulated
periodic signal stream and then scaling that signal with the
output voltage. The duty cycle of the pulse-modulated PMON
signal is proportional to the current, and the amplitude is
proportional to the voltage. The maximum load current that
corresponds to the full-scale (100%) modulated signal can be
adjusted by a resistor, RPMONFS, tied from PMONFS to GND.
RPMONFS also affects the clock frequency of the PWM circuit.
An RC low path filter connected to the PMON output
demodulates the PWM pulse stream and creates averaged
output current or power information, depending on which rail
the open-drain PMON output is pulled up to.
ADP3208
R
PULL UP
CURRENT
SIGNAL
R
FILTER
PMON
13
14
PMON
PWM
C
PMONFS
FILTER
R
PMONFS
Figure 37. PMON Current Monitor Configuration
If PMON is pulled up to the converter output node, the
demodulated voltage becomes proportional to the averaged
power (see Figure 38).
V
CORE
ADP3208
R
PULL UP
POWER
SIGNAL
R
FILTER
If PMON is pulled up to a dc voltage, the RC-filtered voltage is
proportional to the averaged load current. Figure 37 shows the
PMON configuration used to monitor load current.
PMON
13
14
PMON
PWM
C
PMONFS
FILTER
R
PMONFS
Figure 38. PMON Power Monitor Configuration
Rev. 2 | Page 24 of 38 | www.onsemi.com
ADP3208A
Table 6. VID Codes
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OUTPUT
1.5000 V
1.4875 V
1.4750 V
1.4625 V
1.4500 V
1.4375 V
1.4250 V
1.4125 V
1.4000 V
1.3875 V
1.3750 V
1.3625 V
1.3500 V
1.3375 V
1.3250 V
1.3125 V
1.3000 V
1.2875 V
1.2750 V
1.2625 V
1.2500 V
1.2375 V
1.2250 V
1.2125 V
1.2000 V
1.1875 V
1.1750 V
1.1625 V
1.1500 V
1.1375 V
1.1250 V
1.1125 V
1.1000 V
1.0875 V
1.0750 V
1.0625 V
1.0500 V
1.0375 V
1.0250 V
1.0125 V
1.0000 V
0.9875 V
0.9750 V
0.9625 V
0.9500 V
0.9375 V
0.9250 V
0.9125 V
0.9000 V
0.8875 V
0.8750 V
0.8625 V
0.8500 V
0.8375 V
0.8250 V
0.8125 V
0.8000 V
0.7875 V
0.7750 V
0.7625 V
0.7500 V
VID6
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID5
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID4
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
VID3
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
VID2
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OUTPUT
0.7375 V
0.7250 V
0.7125 V
0.7000 V
0.6875 V
0.6750 V
0.6625 V
0.6500 V
0.6375 V
0.6250 V
0.6125 V
0.6000 V
0.5875 V
0.5750 V
0.5625 V
0.5500 V
0.5375 V
0.5250 V
0.5125 V
0.5000 V
0.4875 V
0.4750 V
0.4625 V
0.4500 V
0.4375 V
0.4250 V
0.4125 V
0.4000 V
0.3875 V
0.3750 V
0.3625 V
0.3500 V
0.3375 V
0.3250 V
0.3125 V
0.3000 V
0.2875 V
0.2750 V
0.2625 V
0.2500 V
0.2375 V
0.2250 V
0.2125 V
0.2000 V
0.1875 V
0.1750 V
0.1625 V
0.1500 V
0.1375 V
0.1250 V
0.1125 V
0.1000 V
0.0875 V
0.0750 V
0.0625 V
0.0500 V
0.0375 V
0.0250 V
0.0125 V
0.0000 V
0.0000 V
Rev. 2 | Page 25 of 38 | www.onsemi.com
ADP3208A
VID6
VID5
VID4
VID3
VID2
VID1
VID0
OUTPUT
0.0000 V
0.0000 V
0.0000 V
VID6
VID5
VID4
VID3
VID2
VID1
VID0
OUTPUT
0.0000 V
0.0000 V
0.0000 V
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0 4 0 7 4 - 0 6 3
C C V
P S
D N G
T R
V I D 6
6 D I
5 D I
4 D I
3 D I
2 D I
1 D I
0 D I
V
V
V
V
V
V
V
M P R
V I D 5
V I D 4
V I D 3
V I D 2
V I D 1
V I D 0
M P R V
P M A R
M U S S C
F E R S C
P M O C S C
E N I L L
I
S P
M I L C
P T S R P D
P L S R P D
S F N O M P
N O M P
Figure 39. Typical Dual-Phase Application Circuit
Rev. 2 | Page 26 of 38 | www.onsemi.com
ADP3208A
APPLICATION INFORMATION
To save power with light loads, lower switching frequency is
The design parameters for a typical IMVP-6+-compliant CPU
core VR application are as follows:
usually preferred during RPM operation. However, the VCORE
ripple specification of IMVP-6+ sets a limitation for the lowest
switching frequency. Therefore, depending on the inductor and
output capacitors, the switching frequency in RPM can be equal
to, greater than, or less than its counterpart in PWM.
•
•
•
•
•
•
•
Maximum input voltage (VINMAX) = 19 V
Minimum input voltage (VINMIN) = 8 V
Output voltage by VID setting (VVID) = 1.4375 V
Maximum output current (IO) = 40 A
Droop resistance (RO) = 2.1 mΩ
Nominal output voltage at 40 A load (VOFL) = 1.3535 V
Static output voltage drop from no load to full load
(ΔV = VONL − VOFL = 1.4375 V − 1.3535 V = 84 mV
Maximum output current step (ΔIO) = 27.9 A
Number of phases (n) = 2
Switching frequency per phase (fSW) = 300 kHz
Duty cycle at maximum input voltage (DMAX) = 0.18 V
Duty cycle at minimum input voltage (DMIN) = 0.076 V
A resistor between the VRPM and RPM pins sets the pseudo-
constant frequency as follows:
AR ×(1− D)×VVID
RR ×CR × fSW
4×RT
(VVID +1.0 V)
RRPM
=
×
(2)
•
•
•
•
•
where:
AR is the internal ramp amplifier gain.
CR is the internal ramp capacitor value.
RR is an external resistor on the RAMP pin to set the internal
ramp magnitude (see the Ramp Resistor Selection section for
information about the design of RR resistance).
SETTING THE CLOCK FREQUENCY FOR PWM
If RR = 280 kΩ, the following resistance results in 300 kHz
switching frequency in RPM operation.
In PWM operation, the ADP3208 uses a fixed-frequency control
architecture. The frequency is set by an external timing resistor
(RT). The clock frequency and the number of phases determine
the switching frequency per phase, which relates directly to the
switching losses and the sizes of the inductors and input and
output capacitors. For a dual-phase design, a clock frequency
of 600 kHz sets the switching frequency to 300 kHz per phase.
This selection represents the trade-off between the switching
losses and the minimum sizes of the output filter components.
To achieve a 600 kHz oscillator frequency at a VID voltage of
1.5 V, RT must be 250 kΩ. Alternatively, the value for RT can
be calculated by using the following equation:
4 × 237 kꢁ
1.4375 V +1.0 V 280 kꢁ×5 pF×300 kHz
0.2×(1 − 0.076)×1.4375
RRPM
=
×
= 246 kꢁ
SOFT START AND CURRENT LIMIT
LATCH-OFF DELAY TIMES
The soft start and current limit latch-off delay functions share
the SS pin; consequently, these parameters must be considered
together. First, set CSS for the soft start ramp. This ramp is
generated with an 8 μA internal current source. The value for
CSS can be calculated as
VVID +1.0 V
8 ꢀA ×tSS
VBOOT
RT =
−35 kꢁ
(1)
CSS
=
(3)
2×n × fSW × 7.2 pF
where:
7.2 pF and 35 kΩ are internal IC component values.
VID is the VID voltage in volts.
n is the number of phases.
SW is the switching frequency in hertz for each phase.
where:
BOOT is the boot voltage for the CPU and is defined in IMVP-6+
as 1.2 V.
tSS is the desired soft start time and is recommended in IMVP-6+
to be less than 3 ms.
V
V
f
For good initial accuracy and frequency stability, it is
recommended to use a 1% resistor.
Therefore, assuming a desired soft start time of 2 ms, CSS is 13.3 nF,
and the closest standard capacitance is 12 nF.
SETTING THE SWITCHING FREQUENCY FOR
RPM OPERATION OF PHASE 1
After CSS is set, the current limit latch-off time can be calculated
by using the following equation:
During the RPM operation of Phase 1, the ADP3208 runs in
1.2 V ×CSS
2ꢀA
where CSS is 7.2 ms.
tDELAY
=
(4)
pseudoconstant frequency if the load current is high enough for
continuous current mode. While in DCM, the switching
frequency is reduced with the load current in a linear manner.
Rev. 2 | Page 27 of 38 | www.onsemi.com
ADP3208A
leads to increased measurement error. For this example, an
inductor with a DCR of 0.8 mΩ is used.
PWRGD DELAY TIMER
The PWRGD delay, tCPU_PWRGD, is defined in IMVP-6+ as the
period between the CLKEN assertion and the PWRGD
assertion. It is programmed by a capacitor connected to the
PGDELAY pin and calculated as follows:
Selecting a Standard Inductor
After the inductance and DCR are known, select a standard
inductor that best meets the overall design goals. It is also
important to specify the inductance and DCR tolerance to
maintain the accuracy of the system. Using 20% tolerance for
the inductance and 15% for the DCR at room temperature are
reasonable values that most manufacturers can meet.
2 ꢀA×tCPU _ PWRGD
CPGDELAY
=
(5)
2.9 V
IMVP-6+ specifies that the PWRGD delay is between 3 ms and
20 ms. Assuming a 5 ms PWRGD delay, CPGDELAY is 4.7 nF.
Power Inductor Manufacturers
INDUCTOR SELECTION
The following companies provide surface-mount power inductors
optimized for high power applications upon request.
The choice of inductance determines the ripple current of the
inductor. Less inductance results in more ripple current, which
increases the output ripple voltage and the conduction losses in
the MOSFETs. However, this allows the use of smaller-size
inductors, and for a specified peak-to-peak transient deviation,
it allows less total output capacitance. Conversely, a higher
inductance means lower ripple current and reduced conduction
losses, but it requires larger-size inductors and more output
capacitance for the same peak-to-peak transient deviation. For a
multiphase converter, the practical value for peak-to-peak
inductor ripple current is less than 50% of the maximum dc
current of that inductor. Equation 6 shows the relationship
between the inductance, oscillator frequency, and peak-to-peak
ripple current. Equation 7 can be used to determine the
minimum inductance based on a given output ripple voltage.
•
•
•
•
Vishay Dale Electronics, Inc.
(605) 665-9301
Panasonic
(714) 373-7334
Sumida Electric Company
(847) 545-6700
NEC Tokin Corporation
(510) 324-4110
Output Droop Resistance
The design requires that the regulator output voltage measured
at the CPU pins decreases when the output current increases. The
specified voltage drop corresponds to the droop resistance (RO).
The output current is measured by summing the currents of the
resistors monitoring the voltage across each inductor and by
passing the signal through a low-pass filter. The summing is
implemented by the CS amplifier that is configured with
resistor RPH(x) (summer) and resistors RCS and CCS (filters). The
output resistance of the regulator is set by the following
equations:
V
VID ×(1− DMIN
)
IR
=
(6)
(7)
fSW ×L
V
VID ×RO ×(1−(n×DMIN ))×(1− DMIN
)
L ≥
fSW ×VRIPPLE
Solving Equation 7 for a 16 mV peak-to-peak output ripple
voltage yields
RCS
RPH(x)
RO
=
×RSENSE
(8)
1.4375 V × 2.1 mꢁ ×
(
1−2×0.076
300 kHz ×16 mV
If the resultant ripple voltage is less than the initially selected
)(1− 0.076)
L ≥
= 493 nH
L
CCS
=
(9)
R
SENSE × RCS
value, the inductor can be changed to a smaller value until the
ripple value is met. This iteration allows optimal transient
response and minimum output decoupling.
where RSENSE is the DCR of the output inductors.
Either RCS or RPH(x) can be chosen for added flexibility. Due to
the current drive ability of the CSCOMP pin, the RCS resistance
should be greater than 100 kΩ. For example, initially select RCS
to be equal to 200 kΩ, and then use Equation 9 to solve for CCS:
The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 490 nH inductor is a
good choice for a starting point, and it provides a calculated
ripple current of 9.0 A. The inductor should not saturate at the
peak current of 24.5 A, and it should be able to handle the sum
of the power dissipation caused by the winding’s average current
(20 A) plus the ac core loss. In this example, 330 nH is used.
330 nH
0.8 mꢁ × 200 kꢁ
CCS
=
= 2.1 nF
If CCS is not a standard capacitance, RCS can be tuned. For
example, if the optimal CCS capacitance is 1.5 nF, adjust RCS to
280 kΩ. For best accuracy, CCS should be a 5% NPO capacitor.
In this example, a 220 kΩ is used for RCS to achieve optimal results.
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. Too large of a
DCR causes excessive power losses, whereas too small of a value
Rev. 2 | Page 28 of 38 | www.onsemi.com
ADP3208A
Next, solve for RPH(x) by rearranging Equation 8 as follows:
0.8 mꢁ
3. Find the relative value of RCS required for each of the two
temperatures. The relative value of RCS is based on the
percentage of change needed, which is initially assumed to
be 0.39%/°C in this example.
RPH(x)
≥
×220 kꢁ = 83.8 kꢁ
2.1 mꢁ
The standard 1% resistor for RPH(x) is 86.6 kΩ.
The relative values are called r1 (r1 is 1/(1+ TC × (T1 − 25)))
and r2 (r2 is 1/(1 + TC × (T2 − 25))), where TC is 0.0039,
T1 is 50°C, and T2 is 90°C.
Inductor DCR Temperature Correction
If the DCR of the inductor is used as a sense element and
copper wire is the source of the DCR, the temperature changes
associated with the inductor’s winding must be compensated
for. Fortunately, copper has a well-known temperature
coefficient (TC) of 0.39%/°C.
4. Compute the relative values for rCS1, rCS2, and rTH by using
the following equations:
(A − B)×r1 ×r2 − A×(1− B)×r2 + B×(1− A)×r1
rCS2
rCS1
=
=
(10)
A×(1− B)×r1 − B×(1− A)×r2 −(A − B)
If RCS is designed to have an opposite but equal percentage of
change in resistance, it cancels the temperature variation of the
inductor’s DCR. Due to the nonlinear nature of NTC thermistors,
series resistors RCS1 and RCS2 (see Figure 40) are needed to linearize
the NTC and produce the desired temperature coefficient tracking.
(1− A)
1
A
−
1−rCS2 r1 −rCS2
1
rTH
=
1
1
−
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
OR LOW-SIDE MOSFET
TO
SWITCH
NODES
1−rCS2 rCS1
TO
CORE
SENSE
R
5. Calculate RTH = rTH × RCS, and then select a thermistor of
the closest value available. In addition, compute a scaling
factor k based on the ratio of the actual thermistor value
used relative to the computed one:
TH
V
R
R
PH2
PH1
ADP3208
CSCOMP
R
R
CS1
CS2
17
C
C
CS2
CS1
RTH(ACTUAL)
CSSUM
CSREF
k =
(11)
19
18
RTH(CALCULATED)
KEEP THIS PATH
AS SHORT AS POSSIBLE
AND AWAY FROM SWITCH
NODE LINES
6. Calculate values for RCS1 and RCS2 by using the following
equations:
RCS1 = RCS ×k ×rCS1
(12)
Figure 40. Temperature-Compensation Circuit Values
RCS2 = RCS ×((1−k) +(k ×rCS2 ))
The following procedure and expressions yield values for
For example, if a thermistor value of 100 kΩ is selected in Step 1,
an available 0603-size thermistor with a value close to RCS is the
Vishay NTHS0603N04 NTC thermistor, which has resistance
values of A = 0.3359 and B = 0.0771. Using the equations in
Step 4, rCS1 is 0.359, rCS2 is 0.729, and rTH is 1.094. Solving for rTH
yields 241 kΩ, so a thermistor of 220 kΩ would be a reasonable
selection, making k equal to 0.913. Finally, RCS1 and RCS2 are found
to be 72.1 kΩ and 166 kΩ. Choosing the closest 1% resistor for
RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given
RCS value.
1. Select an NTC to be used based on its type and value.
Because the value needed is not yet determined, start with
a thermistor with a value close to RCS and an NTC with an
initial tolerance of better than 5%.
2. Find the relative resistance value of the NTC at two
temperatures. The appropriate temperatures will depend
on the type of NTC, but 50°C and 90°C have been shown
to work well for most types of NTCs. The resistance values
are called A (A is RTH(50°C)/RTH(25°C)) and B (B is
RTH(90°C)/RTH(25°C)). Note that the relative value of the
NTC is always 1 at 25°C.
RCS2 yields 165 kΩ. To correct for this approximation, 73.3 kΩ
is used for RCS1
.
Rev. 2 | Page 29 of 38 | www.onsemi.com
ADP3208A
For example, if 30 pieces of 10 μF, 0805-size MLC capacitors (CZ
= 300 μF) are used, the fastest VID voltage change is when the
device exits deeper sleep, during which the VCORE change is
220 mV in 22 μs with a setting error of 10 mV. If k = 3.1, solving
for the bulk capacitance yields
COUT SELECTION
The required output decoupling for processors and platforms is
typically recommended by Intel. For systems containing both
bulk and ceramic capacitors, however, the following guidelines
can be a helpful supplement.
⎛
⎜
⎞
⎟
Select the number of ceramics and determine the total ceramic
capacitance (CZ). This is based on the number and type of
capacitors used. Keep in mind that the best location to place
ceramic capacitors is inside the socket; however, the physical
limit is 20 0805-size pieces inside the socket. Additional
ceramic capacitors can be placed along the outer edge of the
socket. A combined ceramic capacitor value of 200 μF to 300 μF
is recommended and is usually composed of multiple 10 μF or
22 μF capacitors.
⎜
⎜
⎜
⎟
330 nH × 27.9 A
⎟
CX
CX
≥
MIN )
−300 ꢀF =1.0 mF
(
(
⎛
⎜
⎝
⎞
⎟
⎟
⎠
⎟
10 mV
27.9 A
⎜
2 × 2.1 mꢁ+
×1.4375 V
⎜
⎜
⎝
⎟
⎟
⎠
330 nH × 220 mV
2 × 3.12 ×(2.1 mꢁ)2 ×1.4375 V
≤
)
MAX
2
⎛
⎜
⎞
⎟
⎛
⎞
⎟
⎟
⎠
22 ꢀs ×1.4375 V × 2 × 3.1× 2.1 mꢁ
220 mV × 490 nH
⎜
⎜
⎝
1+
−1 −300 ꢀF
⎜
⎟
Ensure that the total amount of bulk capacitance (CX) is within
its limits. The upper limit is dependent on the VID on-the-fly
output voltage stepping (voltage step VV in time tV with error of
⎜
⎝
⎟
⎠
= 21 mF
V
ERR); the lower limit is based on meeting the critical
Using six 330 μF Panasonic SP capacitors with a typical ESR of
7 mΩ each yields CX = 1.98 mF and RX = 1.2 mΩ.
capacitance for load release at a given maximum load step, ΔIO.
The current version of the IMVP-6+ specification allows a
maximum VCORE overshoot (VOSMAX) of 10 mV more than the
VID voltage for a step-off load current.
Ensure that the ESL of the bulk capacitors (LX) is low enough to
limit the high frequency ringing during a load change. This is
tested using
⎛
⎜
⎞
⎟
LX ≤ CZ × RO 2 × Q 2
(15)
⎜
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎟
⎠
L × ΔIO
CX
≥
MIN )
−CZ
(13)
(
LX ≤ 300 ꢀF ×
where:
(
2.1 mꢁ
)
2 ×2 = 2 nH
⎛
⎞
⎟
⎟
⎠
VOSMAX
⎜
n × RO +
×VVID
⎜
ΔIO
⎝
Q is limited to the square root of 2 to ensure a critically damped
system.
LX is about 150 pH for the six SP capacitors, which is low
enough to avoid ringing during a load change. If the LX of the
chosen bulk capacitor bank is too large, the number of ceramic
capacitors may need to be increased to prevent excessive
ringing.
2
⎛
⎜
⎞
⎛
⎞
⎟
⎟
⎠
VV
VVID n×k×RO
L
⎟
⎜
CX(MAX)
≤
×
×
1+ tv
×
−1 −CZ
⎜
⎜
⎝
⎟
n×k2 ×RO2 VVID
VV
L
⎜
⎟
⎠
⎝
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VERR
VV
k = − ln
where
(14)
To meet the conditions of these expressions and the transient
response, the ESR of the bulk capacitor bank (RX) should be less
than two times the droop resistance, RO. If the CX(MIN) is greater
than CX(MAX), the system does not meet the VID on-the-fly
and/or the deeper sleep exit specifications and may require less
inductance or more phases. In addition, the switching frequency
may have to be increased to maintain the output ripple.
For this multimode control technique, an all ceramic capacitor
design can be used if the conditions of Equations 13, 14, and 15
are satisfied.
Rev. 2 | Page 30 of 38 | www.onsemi.com
ADP3208A
voltage that are being switched. Basing the switching speed on
the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression provides
POWER MOSFETS
For typical 20 A per phase applications, the N-channel power
MOSFETs are selected for two high-side switches and two or
three low-side switches per phase. The main selection
parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS
and RDS(ON). Because the voltage of the gate driver is 5 V, logic-
level threshold MOSFETs must be used.
an approximate value for the switching loss per main MOSFET:
V
DC × IO
nMF
nMF
n
,
PS(MF) = 2× fSW
×
×RG ×
×CISS
(17)
where:
MF is the total number of main MOSFETs.
RG is the total gate resistance.
ISS is the input capacitance of the main MOSFET.
The maximum output current, IO, determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. In the
ADP3208, currents are balanced between phases; the current in
each low-side MOSFET is the output current divided by the
total number of MOSFETs (nSF). With conduction losses being
dominant, the following expression shows the total power that
is dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and the average total output
current (IO):
n
C
The most effective way to reduce switching loss is to use lower
gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following equation:
2
2
⎡
⎢
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
IO
nMF
n×IR
nMF
1
12
PC(MF) = D×
+
×
×RDS(MF)
(18)
2
2
⎡
⎢
⎤
⎥
⎢
⎣
⎥
⎦
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
IO
nSF
n×IR
nSF
1
12
PSF = (1−D)×
+
×
×RDS(SF)
(16)
⎢
⎣
⎥
⎦
where RDS(MF) is the on resistance of the MOSFET.
where:
Typically, a user wants the highest speed (low CISS) device for a
main MOSFET, but such a device usually has higher on
resistance. Therefore, the user must select a device that meets
the total power dissipation (0.8 W~1.0 W for an 8-lead SOIC)
when combining the switching and conduction losses.
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
IR is the inductor peak-to-peak ripple current and is
approximately
(1− D)×VOUT
For example, an IRF7821 device could be selected as the main
MOSFET (four in total; that is, nMF = 4), with approximately
CISS = 1010 pF (maximum) and RDS(MF) = 18 mΩ (maximum at
Tj = 120°C), and an IR7832 device could be selected as the
synchronous MOSFET (four in total; that is, nSF = 4), with
RDS(SF) = 6.7 mΩ (maximum at Tj = 120°C). Solving for the
power dissipation per MOSFET at IO = 40 A and IR = 9.0 A
yields 630 mW for each synchronous MOSFET and 590 mW
for each main MOSFET. A third synchronous MOSFET is an
option to further increase the conversion efficiency and reduce
thermal stress.
IR
=
L× fSW
Knowing the maximum output current and the maximum
allowed power dissipation, the user can calculate the required
RDS(ON) for the MOSFET. For 8-lead SOIC or 8-lead SOIC-
compatible MOSFETs, the junction-to-ambient (PCB) thermal
impedance is 50°C/W. In the worst case, the PCB temperature is
70°C to 80°C during heavy load operation of the notebook, and
a safe limit for PSF is 0.8 W~1.0 W at 120°C junction temperature.
Therefore, for this example (40 A maximum), the RDS(SF) per
MOSFET is less than 8.5 mΩ for two pieces of low-side
MOSFETs. This RDS(SF) is also at a junction temperature of about
120°C; therefore, the RDS(SF) per MOSFET should be less than
6 mΩ at room temperature, or 8.5 mΩ at high temperature.
Finally, consider the power dissipation in the driver for each
phase. This is best described in terms of the QG for the
MOSFETs and is given by the following equation:
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input must be small (less than 10% is recommended)
to prevent accidentally turning on the synchronous MOSFETs
when the switch node goes high.
f
⎡
⎤
SW
PDRV
=
×
(
n
MF ×QGMF +nSF ×QGSF
)
+ ICC ×VCC
(19)
⎢
⎥
2×n
⎣
⎦
where QGMF is the total gate charge for each main MOSFET, and
GSF is the total gate charge for each synchronous MOSFET.
Q
The previous equation also shows the standby dissipation (ICC
times the VCC) of the driver.
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction losses and
switching losses. Switching loss is related to the time for the
main MOSFET to turn on and off and to the current and
Rev. 2 | Page 31 of 38 | www.onsemi.com
ADP3208A
RAMP RESISTOR SELECTION
CURRENT LIMIT SETPOINT
The ramp resistor (RR) is used to set the size of the internal PWM
ramp. The value of this resistor is chosen to provide the best
combination of thermal balance, stability, and transient response.
Use the following expression to determine a starting value:
To select the current limit setpoint, the resistor value for RCLIM must
be determined. The current limit threshold for the ADP3208 is
set with RCLIM. RCLIM can be found using the following equation:
RCS ×10×RSENSE × ICLIM ×2
RCLIM
=
(23)
AR × L
3× AD × RDS ×CR
RPH ×10 ꢀA×n
RR =
(20)
where:
PH is the resistor connecting the current sense resistor or
0.2×330 nH
3×5×3.4 mꢁ×5 pF
R
RR
where:
=
= 256 kꢁ
inductor switch node to the current sense amplifier.
RCS is the current sense amplifier feedback resistor.
R
SENSE is the sense current resistor or the inductor DCR.
n is the number of phases.
CLIM is the current limit setpoint.
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
RDS is the total low-side MOSFET on resistance.
CR is the internal ramp capacitor value.
I
If RCLIM is greater than 500 kΩ, the current limit may be lower
than expected and require an adjustment of RCLIM. In this
example, ICLIM is the average current limit for the output of the
supply. For this example, choosing 60 A for ICLIM, results in an
RCLIM of 126 kΩ, and the closest 1% standard resistance is 127 kΩ.
Another consideration in the selection of RR is the size of the
internal ramp voltage (see Equation 21). For stability and noise
immunity, keep the ramp size larger than 0.5 V. Taking this into
consideration, the value of RR in this example is selected as 280 kΩ.
The following equation determines the per phase current limit
previously described:
The internal ramp voltage magnitude can be calculated as follows:
AR ×(1 − D)×VVID
RR ×CR × fSW
VR =
(21)
VCOMP(MAX) −VR −VBIAS
AD ×RDS(MAX)
IR
2
IPHLIM
=
−
(24)
0.2×(1−0.076)×1.3475 V
280 kꢁ×5 pF×300 kHz
VR =
= 0.59 V
where:
V
V
COMP(MAX) is the maximum COMP voltage and is 3.3 V.
BIAS is the COMP pin bias voltage and is 1.0 V.
The size of the internal ramp can be increased or decreased. If it
is increased, stability and transient response improves but
thermal balance degrades. Conversely, if the ramp size is
decreased, thermal balance improves but stability and transient
response degrade. In the denominator of Equation 20, the factor
of 3 sets the minimum ramp size that produces an optimal
combination of good stability, transient response, and thermal
balance.
AD is the current-balancing amplifier gain and is 5.
Using a VR of 0.59 V and a RDS(MAX) of 3.8 mΩ (low-side on
resistance at 150°C) results in a per phase limit of 83 A. Although
this number may seem high, this current level can be achieved
using only an absolute short at the output, and the current limit
latch-off function shuts down the regulator before overheating
can occur.
COMP PIN RAMP
This limit can be adjusted by changing the ramp voltage, VR.
However, the per phase limit must be set to be greater than the
average per phase current (ICLIM/n).
In addition to the internal ramp, there is a ramp signal on the
COMP pin due to the droop voltage and output voltage ramps.
This ramp amplitude adds to the internal ramp to produce the
following overall ramp signal at the PWM input:
There is also a per phase initial duty cycle limit at the maximum
input voltage:
VR
VCOMP(MAX) −VBIAS
(22)
VRT
=
DLIM = DMIN
×
(25)
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
2×
(1−n×D)
VR
1−
n× fSW ×CX ×RO
For this example, the duty cycle limit at the maximum input
voltage is 0.3 V when D is 0.076.
where CX is the total bulk capacitance, and RO is the droop
resistance of the regulator.
For this example, the overall ramp signal is 1.85 V.
Rev. 2 | Page 32 of 38 | www.onsemi.com
ADP3208A
POWER MONITOR
GAIN
The PMON duty cycle is proportional to load current. RPMONFS
sets the maximum duty cycle at the maximum current.
–20dB/DEC
(ILOAD × RO ×9) +1V
RPMONFS
=
(26)
10 μA
–20dB/DEC
where ILOAD is the load current in amps when PMON is 100%
duty cycle, and RO is the droop resistance in ohms.
0dB
FREQUENCY
fP1
fZ2 fZ1
fP2
When PMON is connected with a pull-up resistor to the output
voltage, as shown in Figure 38, the average PMON voltage is
given by
Figure 42. Poles and Zeros of Voltage Error Amplifier
The following equations give the locations of the poles and
zeros shown in Figure 42.
VGFX × ILOAD × RO ×9
(RMONFS ×10 μA) -1V
PMON =
(27)
1
fZ1
fZ2
fP1
fP2
=
=
=
=
(28)
(29)
(30)
(31)
2π×CA ×RA
FEEDBACK LOOP COMPENSATION DESIGN
1
Optimized compensation of the ADP3208 allows the best
2π×CFB ×RFB
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resistance
(RO). With the resistive output impedance, the output voltage
droops in proportion with the load current at any load current
slew rate, ensuring the optimal position and allowing the
minimization of the output decoupling.
1
2π(CA +CB )×RFB
CA +CB
2π×RA ×CB ×CA
The expressions that follow compute the time constants for
the poles and zeros in the system and are intended to yield an
optimal starting point for the design; some adjustments may be
necessary to account for PCB and component parasitic effects
(see the Tuning Procedure for ADP3208 section):
With the multimode feedback structure of the ADP3208, it is
necessary to set the feedback compensation so that the
converter’s output impedance works in parallel with the output
decoupling. In addition, it is necessary to compensate for the
several poles and zeros created by the output inductor and
decoupling capacitors (output filter).
RL ×VRT
VVID
RE = n×RO + AD ×RDS
+
+
(32)
2×L×(1−(n×D))×VRT
n×CX ×RO ×VVID
A Type III compensator on the voltage feedback is adequate
for proper compensation of the output filter. Figure 41 shows the
Type III amplifier used in the ADP3208. Figure 42 shows the
locations of the two poles and two zeros created by this amplifier.
VOLTAGE ERROR
LX RO − R'
TA = CX ×
(
RO − R'
)
+
×
(33)
(34)
RO
×CX
RX
TB =
RX + R'−RO
AMPLIFIER
REFERENCE
VOLTAGE
⎛
⎞
⎟
⎟
⎠
AD × RDS
2× fSW
⎜
V
RT × L −
⎜
⎝
TC =
(35)
(36)
V
VID × RE
CX ×CZ ×RO2
RO − R' +CZ ×RO
ADP3208
COMP
FB
6
7
TD
where:
=
OUTPUT
VOLTAGE
CX ×
(
)
C
A
R
R
FB
A
R' is the PCB resistance from the bulk capacitors to the ceramics
C
C
FB
B
and is approximately 0.4 mΩ (assuming an 8-layer motherboard).
Figure 41. Voltage Error Amplifier
R
DS is the total low-side MOSFET for on resistance per phase.
AD is 5.
RT is 1.25 V.
LX is 150 pH for the six Panasonic SP capacitors.
V
Rev. 2 | Page 33 of 38 | www.onsemi.com
ADP3208A
The compensation values can be calculated as follows:
and is defined as 10mV/μA in the IMVP-6+ specification.
CST is 750 pF, and the closest standard capacitance is 680 pF.
n×RO ×TA
RE ×RB
CA
=
=
=
(37)
(38)
SELECTING THERMAL MONITOR COMPONENTS
To monitor the temperature of a single-point hot spot, set
RTTSET1 equal to the NTC thermistor’s resistance at the alarm
temperature. For example, if the alarm temperature for VRTT is
100°C and a Vishey thermistor (NTHS-0603N011003J) with a
resistance of 100 kΩ at 25°C, or 6.8 kΩ at 100°C, is used, the
user can set RTTSET1 equal to 6.8 kΩ (the RTH1 at 100°C).
TC
CA
RA
CB
CFB
TB
RB
(39)
(40)
TD
RA
=
11
5V
VRTT
The standard values for these components are subject to the
tuning procedure described in the Tuning Procedure for
ADP3208 section.
37
VCC
R
TTSET1
R
R
12
TTSNS
CIN SELECTION AND INPUT CURRENT
di/dt REDUCTION
C
R
TT
TH1
ADP3208
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude that is one-nth of
the maximum output current. To prevent large voltage
transients, use a low ESR input capacitor sized for the
maximum rms current. The maximum rms capacitor current
occurs at the lowest input voltage and is given by
Figure 43. Single-Point Thermal Monitoring
To monitor the temperature of multiple-point hot spots, use the
configuration shown in Figure 44. If any of the monitored hot
spots reaches the alarm temperature, the VRTT signal is
asserted. The following calculation sets the alarm temperature:
1
VFD
VREF
VFD
ICRMS = D × IO ×
−1
(41)
1/2 +
n× D
RTTSET1
=
×RTH1AlarmTemperature
(43)
1/2 −
1
ICRMS = 0.18 × 40 A ×
−1 = 9.6 A
VREF
2 × 0.18
where VFD is the forward drop voltage of the parallel diode.
where IO is the output current.
Because the forward current is very small, the forward drop
In a typical notebook system, the battery rail decoupling is
achieved by using MLC capacitors or a mixture of MLC
capacitors and bulk capacitors. In this example, the input
capacitor bank is formed by eight pieces of 10 μF, 25 V MLC
capacitors, with a ripple current rating of about 1.5 A each.
voltage is very low, that is, less than 100 mV. Assuming the same
conditions used for the single-point thermal monitoring
example—that is, an alarm temperature of 100°C and use of an
NTHS-0603N011003J Vishay thermistor—solving Equation 42
gives a RTTSET of 7.37 kΩ, and the closest standard resistor is
7.32 kΩ (1%).
SOFT TRANSIENT SETTING
As described in the Theory of Operation section, during the
soft transient, the slew rate of the VCORE reference voltage
change is controlled by the ST pin capacitance. Because the
11
5V
VRTT
37
VCC
1M
Ω
R
R
R
TTSETn
TTSET1
TTSET2
timing of exiting deeper sleep is critical, the ST pin capacitance
is set to satisfy the slew rate for a fast exit of deeper sleep as
follows:
R
R
12
TTSNS
C
R
R
THn
TT
R
7.5 ꢀA
TH2
TH1
CST
=
(42)
ADP3208
SLEWRATEC4E
where:
7.5 μA is the source/sink current of the ST pin.
SLEWRATEC4E is the voltage slew rate for exiting deeper sleep
Figure 44. Multiple-Point Thermal Monitoring
The number of hot spots monitored is not limited. The alarm
temperature of each hot spot can be individually set by using
different values for RTTSET1, RTTSET2, … RTTSETn
.
Rev. 2 | Page 34 of 38 | www.onsemi.com
ADP3208A
TUNING PROCEDURE FOR ADP3208
Set Up and Test the Circuit
1. Build a circuit based on the compensation values
computed from the design spreadsheet.
2. Connect a dc load to the circuit.
V
ACDRP
3. Turn on the ADP3208 and verify that it operates properly.
4. Check for jitter with no load and full load conditions.
V
DCDRP
Set the DC Load Line
1. Measure the output voltage with no load (VNL) and verify
that this voltage is within the specified tolerance range.
2. Measure the output voltage with a full load when the
device is cold (VFLCOLD). Allow the board to run for ~10
minutes with a full load and then measure the output when
the device is hot (VFLHOT). If the difference between the two
measured voltages is more than a few millivolts, adjust RCS2
using Equation 44.
Figure 45. AC Load Line Waveform
6. If the difference between VACDRP and VDCDRP is more than a
couple of millivolts, use Equation 44 to adjust CCS. It may
be necessary to try several parallel values to obtain the
right one because there are limited standard capacitor
values available (it is a good idea to have locations for two
capacitors in the layout for this reason).
VNL −VFLCOLD
VNL −VFLHOT
RCS2(NEW ) = RCS2(OLD)
×
(44)
VACDRP
VDCDRP
CCS(NEW ) = CCS(OLD)
×
(46)
3. Repeat Step 2 until no adjustment of RCS2 is needed.
4. Compare the output voltage with no load to that with a full
load using 5 A steps. Compute the load line slope for each
change and then find the average to determine the overall
load line slope (ROMEAS).
5. If the difference between ROMEAS and RO is more than 0.05 mΩ,
use the following equation to adjust the RPH values:
7. Repeat Steps 5 and 6 until no adjustment of CCS is needed.
Once this is achieved, do not change CCS for the rest of the
procedure.
8. Set the dynamic load step to its maximum step size (but do
not use a step size that is larger than needed) and verify
that the output waveform is square, meaning VACDRP and
ROMEAS
RO
V
DCDRP are equal.
RPH(NEW) = RPH(OLD)
×
(45)
9. Ensure that the load step slew rate and the power-up slew
rate are set to ~150 A/μs to 250 A/μs (for example, a load
step of 50 A should take 200 ns to 300 ns) with no
overshoot. Some dynamic loads have an excessive
overshoot at power-up if a minimum current is incorrectly
set (this is an issue if a VTT tool is in use).
6. Repeat Steps 4 and 5 until no adjustment of RPH is needed.
Once this is achieved, do not change RPH, RCS1, RCS2, or RTH
for rest of procedure.
7. Measure the output ripple with no load and with a full load
with scope, making sure both are within the specifications.
Set the Initial Transient
Set the AC Load Line
1. With the dynamic load set at its maximum step size,
expand the scope time scale to 2 μs/div to 5 μs/div. This
results in a waveform that may have two overshoots and
one minor undershoot before achieving the final desired
value after VDROOP (see Figure 46).
1. Remove the dc load from the circuit and connect a
dynamic load.
2. Connect the scope to the output voltage and set it to dc
coupling mode with a time scale of 100 μs/div.
3. Set the dynamic load for a transient step of about 40 A at
1 kHz with 50% duty cycle.
4. Measure the output waveform (note that use of a dc offset
on the scope may be necessary to see the waveform). Try to
use a vertical scale of 100 mV/div or finer.
5. The resulting waveform will be similar to that shown in
Figure 45. Use the horizontal cursors to measure VACDRP and
V
DCDRP, as shown in Figure 45. Do not measure the under-
shoot or overshoot that occurs immediately after the step.
Rev. 2 | Page 35 of 38 | www.onsemi.com
ADP3208A
interconnections with optimal placement; power planes for
ground, input, and output; and wide interconnection traces
in the rest of the power delivery current paths. Keep in
mind that each square unit of 1 oz copper trace has a
resistance of ~0.53 mΩ at room temperature.
V
DROOP
2. When high currents must be routed between PCB layers,
vias should be used liberally to create several parallel
current paths so that the resistance and inductance
introduced by these current paths is minimized and the via
current rating is not exceeded.
V
TRAN1
V
TRAN2
3. If critical signal lines (including the output voltage sense
lines of the ADP3208) must cross through power circuitry,
it is best if a signal ground plane can be interposed
between those signal lines and the traces of the power
circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of increasing signal
ground noise.
4. An analog ground plane should be used around and under
the ADP3208 for referencing the components associated
with the controller. This plane should be tied to the nearest
ground of the output decoupling capacitor, but should not
be tied to any other power circuitry to prevent power
currents from flowing into the plane.
5. The components around the ADP3208 should be located
close to the controller with short traces. The most important
traces to keep short and away from other traces are those
to the FB and CSSUM pins. Refer to Figure 40 for more
details on the layout for the CSSUM node.
6. The output capacitors should be connected as closely as
possible to the load (or connector) that receives the power
(for example, a microprocessor core). If the load is
distributed, the capacitors should also be distributed and
generally in proportion to where the load tends to be more
dynamic.
Figure 46. Transient Setting Waveform, Load Step
2. If both overshoots are larger than desired, try the following
adjustments in the order shown
a. Increase the resistance of the ramp resistor
(RRAMP) by 25%.
b. For VTRAN1, increase CB or increase the switching
frequency.
c. For VTRAN2, Increase RA by 25% and decrease CA by 25%.
If these adjustments do not change the response, it is
because the system is limited by the output decoupling.
Check the output response and the switching nodes each
time a change is made to ensure that the output decoupling
is stable.
3. For load release (see Figure 47), if VTRANREL is larger than
the IMVP-6+ specified value, a greater percentage of
output capacitance is needed. Either increase the
capacitance directly or decrease the inductor values. (If
inductors are changed, however, it will be necessary to
redesign the circuit using the spreadsheet and to repeat all
tuning guide procedures).
7. Avoid crossing signal lines over the switching power path
V
TRANREL
loop, as described in the Power Circuitry section.
V
DROOP
Power Circuitry
1. The switching power path on the PCB should be routed to
encompass the shortest possible length to minimize
radiated switching noise energy (that is, EMI) and
conduction losses in the board. Failure to take proper
precautions often results in EMI problems for the entire PC
system as well as noise-related operational problems in the
power-converter control circuitry. The switching power
path is the loop formed by the current path through the
input capacitors and the power MOSFETs, including all
interconnecting PCB traces and planes. The use of short,
wide interconnection traces is especially critical in this
path for two reasons: It minimizes the inductance in the
switching loop, which can cause high energy ringing, and it
Figure 47. Transient Setting Waveform, Load Release
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
1. For best results, use a PCB of four or more layers. This
should provide the needed versatility for control circuitry
Rev. 2 | Page 36 of 38 | www.onsemi.com
ADP3208A
accommodates the high current demand with minimal
voltage loss.
Signal Circuitry
1. The output voltage is sensed and regulated between the FB
and FBRTN pins, and the traces of these pins should be
connect to the signal ground of the load. To avoid
differential mode noise pickup in the sensed signal, the
loop area should be as small as possible. Therefore, the FB
and FBRTN traces should be routed adjacent to each other,
atop the power ground plane, and back to the controller.
2. The feedback traces from the switch nodes should be
connected as close as possible to the inductor. The CSREF
signal should be Kelvin connected to the center point of
the copper bar, which is the VCORE common node for the
inductors of all the phases.
2. When a power-dissipating component (for example, a
power MOSFET) is soldered to a PCB, the liberal use of
vias, both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons
for this are improved current rating through the vias and
improved thermal performance from vias extended to the
opposite side of the PCB, where a plane can more readily
transfer heat to the surrounding air. To achieve optimal
thermal dissipation, mirror the pad configurations used to
heat sink the MOSFETs on the opposite side of the PCB. In
addition, improvements in thermal performance can be
obtained using the largest possible pad area.
3. On the back of the ADP3208 package, there is a metal pad
that can be used to heat sink the device. Therefore, running
vias under the ADP3208 is not recommended because the
metal pad may cause shorting between vias.
3. The output power path should also be routed to encompass
a short distance. The output power path is formed by the
current path through the inductor, the output capacitors,
and the load.
4. For best EMI containment, a solid power ground plane
should be used as one of the inner layers and extended
under all power components.
Rev. 2 | Page 37 of 38 | www.onsemi.com
ADP3208A
OUTLINE DIMENSION
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP3208AJCPZ-RL1
Temperature Range
0°C to +100°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package Option
CP-48-1
Ordering Qty
2,500
1 Z = Pb-free part. 1.0V Boot Voltage Version
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
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Rev. 2 | Page 38 of 38 | www.onsemi.com
相关型号：
ADP3209DJCPZ-RL
SWITCHING CONTROLLER, 20000 kHz SWITCHING FREQ-MAX, QCC32, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, LFCSP-32
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