ADP3367ARZ [ROCHESTER]
FIXED/ADJUSTABLE POSITIVE LDO REGULATOR, 0.5 V DROPOUT, PDSO8, SOP-8;
| 型号： | ADP3367ARZ |
| 厂家： | 
Rochester Electronics |
| 描述： | FIXED/ADJUSTABLE POSITIVE LDO REGULATOR, 0.5 V DROPOUT, PDSO8, SOP-8 光电二极管 输出元件 调节器 |
| 文件： | 总9页 (文件大小：786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+5 V Fixed, Adjustable
Low-Dropout Linear Voltage Regulator
a
ADP3367
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Low Dropout: 150 m V @ 200 m A
Low Dropout: 300 m V @ 300 m A
Low Pow er CMOS: 17 A Quiescent Current
Shutdow n Mode: 0.2 A Quiescent Current
300 m A Output Current Guaranteed
Pin Com patible w ith MAX667
Stable w ith 10 F Load Capacitor
+2.5 V to +16.5 V Operating Range
Low Battery Detector
OUT
DD
IN
ADP3367
SHDN
LBO
A1
SET
C1
Fixed +5 V or Adjustable Output
High Accuracy: ؎2%
C2
Dropout Detector Output
Low Therm al Resistance Package*
ESD > 6000 V
1.255V
REF
50mV
LBI
GND
APPLICATIONS
Handheld Instrum ents
Cellular Telephones
TYP ICAL O P ERATING CIRCUIT
Battery Operated Devices
Portable Equipm ent
Solar Pow ered Instrum ents
High Efficiency Linear Pow er Supplies
+6V
INPUT
+5V
OUTPUT
OUT
IN
+
+
C1
10µF
ADP3367
GENERAL D ESCRIP TIO N
SET GND SHDN
T he ADP3367 is a low-dropout precision voltage regulator that
can supply up to 300 mA output current. It can be used to give
a fixed +5 V output with no additional external components or
can be adjusted from +1.3 V to +16 V using two external
resistors. Fixed or adjustable operation can be selected via the
SET input. T he low quiescent current (17 µA) in conjunction
with the standby or shutdown mode (0.2 µA) makes this device
especially suitable for battery powered systems. T he dropout
voltage when supplying 100 µA is only 15 mV allowing opera-
tion with minimal headroom thereby prolonging the useful bat-
tery life. At higher output current levels the dropout remains
low increasing to just 150 mV when supplying 200 mA. A wide
input voltage range from 2.5 V to 16.5 V is allowable. Addi-
tional features include a dropout detector and a low supply/bat-
tery monitoring comparator. T he dropout detector can be used
to signal loss of regulation while the low battery detector can be
used to monitor the input supply voltage.
400
T
= +50°C
A
300
GUARANTEED 300mA
200
100
0
ADP3367
DISSIPATION LIMIT
STANDARD
SO PACKAGE
DISSIPATION LIMIT
0
5
10
15
T he ADP3367 is a much improved pin-compatible replacement
for the MAX667. Improvements include lower supply current,
tighter voltage accuracy and superior line and load regulation.
Improved ESD protection (>6000 V) is achieved by advanced
voltage clamping structures. T he ADP3367 is specified over the
industrial temperature range –40°C to +85°C and is available in
narrow surface mount (SOIC) packages.
V
–V – V
IN OUT
Load Current vs. Input-Output Differential Voltage
ADI’s proprietary Thermal Coastline leadframe used in ADP3367AR
packaging, has 30% lower thermal resistance than the standard
leadframes. T his improvement in heat flow rate results in lower
die temperature hence improves reliability.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
ADP3367–SPECIFICATIONS (V = +9 V, GND = 0 V, V = +5 V, T = TMIN to TMAX unless otherwise noted)
IN
OUT
Units
V
A
P aram eter
Min
Typ
Max
16.5
5.1
Test Conditions/Com m ents
Input Voltage, VIN
2.5
Output Voltage, VOUT
Maximum Output Current
4.9
200
5.0
V
mA
VSET = 0 V, VIN = 6 V, IOUT = 10 mA
VIN = +9 V, + 4.5 V < VOUT < +5.5 V
Quiescent Current
IGND: Shutdown Mode
IGND: Normal Mode
0.2
0.75
µA
VSHDN = 2 V
VSHDN = 0 V, VSET = 0 V
17
20
5
25
30
14
µA
µA
mA
IOUT = 0 µA
IOUT = 100 µA
IOUT = 200 mA
Dropout Voltage
VOUT = 5 V
15
60
40
mV
mV
mV
mV
mV
mV
mV
mV
mV
IOUT = 100 µA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 200 mA, T A = +25°C
IOUT = 200 mA
IOUT = 300 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 200 mA, T A = +25°C
125
175
250
300
500
140
312
625
100
150
175
300
94
210
430
VOUT = 3.3 V
Load Regulation
Line Regulation
5
10
5
mV
mV
IOUT = 10 mA–100 mA, VIN = 6 V
IOUT = 10 mA–200 mA, VIN = 6 V
VIN = 6 V to 10 V, IOUT = 10 mA
0.1
Reference Voltage, VSET
SET Input T hreshold
SET Input Current, ISET
1.23
1.255 1.28
50
±0.01 ±10
V
mV
nA
VSET = 1.5 V
Output Leakage Current, IOUT
Short Circuit Current, IOUT
0.1
400
450
1
µA
mA
mA
VSHDN = 2 V
T A = +25°C
T A = T MIN to T MAX
Low Battery Detector Input T hreshold, VLBI
LBI Hysteresis
LBI Input Leakage Current, ILBI
Low Battery Detector Output Voltage, VLBO
1.215
1.5
1.255 1.295
6
±0.01 ±10
0.25
V
mV
nA
V
VLBI = 1.5 V
VLBI = 0 V, ILBO = 10 mA, T A = +25°C
VLBI = 0 V, ILBO = 10 mA, T A = TMIN to T MAX
0.40
V
Shutdown Input Voltage, VSHDN
V
VIH
0.4
V
VIL
Shutdown Input Current, ISHDN
Dropout Detector Output Voltage
±0.01 ±10
nA
VSHDN = 0 V to VIN
0.25
V
(VSET = 0 V, VSHDN = 0 V, RDD = 100 kΩ,
VIN = 7 V, IOUT = 10 mA)
4.0
(VSET = 0 V, VSHDN = 0 V, RDD = 100 kΩ,
VIN = 4.5 V, IOUT = 10 mA)
Specifications subject to change without notice.
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 6000 V
ABSO LUTE MAXIMUM RATINGS*
(
T A= +25°C unless otherwise noted)
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18 V
Output Short Circuit to GND Duration . . . . . . . . . . . . . 1 sec
LBO Output Sink Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA
LBO Output Voltage . . . . . . . . . . . . . . . . . . . . . GND to VOUT
SHDN Input Voltage . . . . . . . . . . . . . . –0.3 V to (VIN + 0.3 V)
LBI, SET Input Voltage . . . . . . . . . . . –0.3 V to (VIN + 0.3 V)
Power Dissipation, R-8 . . . . . . . . . . . . . . . . . . . . . . . 960 mW
(Derate 10 mW/°C above +50°C)
*T his is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operation sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
O RD ERING GUID E
θ
JA, T hermal Impedance . . . . . . . . . . . . . . . . . . . . . . 98°C/W
Model
Tem perature Range
P ackage O ption*
Operating T emperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . –65°C to +150°C
ADP3367AR
–40°C to +85°C
SO-8
*SO = Small Outline Package.
REV. 0
–2–
ADP3367
P IN FUNCTIO N D ESCRIP TIO N
Mnem onic Function
GENERAL INFO RMATIO N
T he ADP3367 contains a micropower bandgap reference volt-
age source, an error amplifier A1, two comparators (C1, C2)
and a series PNP output pass transistor.
DD
Dropout Detector Output. PNP collector output
which sources current as dropout is reached.
CIRCUIT D ESCRIP TIO N
VIN
Voltage Regulator Input.
T he internal bandgap voltage reference is trimmed to 1.255 V
and is used as a reference input to the error amplifier A1. T he
feedback signal from the regulator output is supplied to the
other input by an on-chip voltage divider or by two external
resistors. When the SET input is at ground, the internal divider
provides the error amplifier’s feedback signal giving a +5 V out-
put. When SET is at more than 50 mV above ground, compara-
tor C1 switches the error amplifier’s input directly to the SET
pin, and external resistors are used to set the output voltage.
T he external resistors are selected so that the desired output
voltage gives 1.255 V at the SET input.
GND
LBI
Ground Pin. Must be connected to 0 V.
Low Battery Detect Input. Compared with 1.255 V.
LBO
Low Battery Detect Output. Open Drain Output
that goes low when LBI is below the threshold.
SHDN
SET
Digital Input. May be used to disable the device
so that the power consumption is minimized.
Voltage Setting Input. Connect to GND for +5 V
output or connect to resistive divider for adjust-
able output.
T he output from the error amplifier supplies base current to the
PNP output pass transistor which provides output current. Up
to 300 mA output current is available provided that the device
power dissipation is not exceeded.
OUT
Regulated Output Voltage. Connect to filter
capacitor.
D IP & SO IC P IN CO NFIGURATIO N
Comparator C2 compares the voltage on the Low Battery Input
(LBI) pin to the internal +1.255 V reference voltage. T he out-
put from the comparator drives an open drain FET connected
to the Low Battery Output pin, LBO. T he Low Battery T hresh-
old may be set using a suitable voltage divider connected to
LBI. When the voltage on LBI falls below 1.255 V, the open
drain output, LBO, is pulled low.
8
7
6
5
DD
OUT
LBI
1
2
IN
LBO
ADP3367
TOP VIEW
(Not to Scale)
3
4
SET
SHDN
GND
A shutdown (SHDN) input that can be used to disable the
error amplifier and hence the voltage output is also available.
T he supply current in shutdown is less than 0.75 µA.
TERMINO LO GY
D r opout Voltage: T he input/output voltage differential at
which the regulator no longer maintains regulation against fur-
ther reductions in input voltage. It is measured when the output
decreases 100 mV from its nominal value. T he nominal value is
the measured value with VIN = VOUT +2 V.
OUT
IN
DD
ADP3367
SHDN
Line Regulation: T he change in output voltage as a result of a
change in the input voltage. It is specified for a change of input
voltage from 6 V to 10 V.
A1
SET
C1
LBO
Load Regulation: T he change in output voltage for a change
in output current. It is specified for an output current change
from 10 mA to 200 mA.
C2
1.255V
REF
50mV
LBI
Quiescent Cur r ent (IGND ): T he input bias current which
flows into the regulator not including load current. It is mea-
sured on the GND line and is specified in shutdown and also for
different values of load current.
GND
Figure 1. ADP3367 Functional Block Diagram
Shutdown: T he regulator is disabled and power consumption
is minimized.
D r opout D etector : An output that indicates that the regulator
is dropping out of regulation.
Maxim um P ower D issipation: T he maximum total device
dissipation for which the regulator will continue to operate
within specifications.
REV. 0
–3–
ADP3367–Typical Performance Characteristics
500
2.5
2.0
1.5
T
= +25°C
T
V
= +25°C
= 6V
A
A
IN
C
= 10µF
L
250
1.0
0.5
0.0
10
100
200
300
1
0
50
100
150
200
LOAD CURRENT – mA
∆1 – mA
Figure 2. Dropout Voltage vs. Load Current
Figure 5. Load Regulation (DVOUT vs. DIOUT
)
10
T
= +25°C
A
V
T
= 6V
= +25°C
+10V
+6V
IN
A
V
IN
1
0.1
200mV
0V
V
OUT
0.01
0.01
0.1
1
10
– mA
100
1000
CH1 2.00V
CH2 200mV
M 2.00ms
I
OUT
Figure 3. Ground Current vs. Load Current
Figure 6. Dynam ic Response to Input Change
1000
T
= +25°C
A
100mA
10mA
20mV
0V
OUTPUT
CURRENT
100mA
50mA
100
10
1
20mA
10mA
V
OUT
5mA
2mA
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
CH1 1.00V
CH2 20.0mV
M 2.00ms
I-O DIFFERENCE – mV
Figure 7. Dynam ic Response to Load Change
Figure 4. DD Output Current vs. I-O Differential
–4–
REV. 0
ADP3367
AP P LICATIO NS INFO RMATIO N
Low Supply or Low Batter y D etection
Cir cuit Configur ations
T he ADP3367 contains on-chip circuitry for low power supply
or battery detection. If the voltage on the LBI pin falls below
the internal 1.255 V reference, then the open drain output LBO
will go low. T he low threshold voltage may be set to any voltage
above 1.255 V by appropriate resistor divider selection.
For a fixed +5 V output the SET input should be grounded, and
no external resistors are necessary. T his basic configuration is
shown in Figure 8. T he input voltage can range from +5.15 V
to +16.5 V, and output currents up to 300 mA are available
provided that the maximum package power dissipation is not
exceeded.
VBATT
R3 = R4 ×
−1
VLBI
+5V
OUTPUT
where R3 and R4 are the resistive divider resistors and VBAT T is
the desired low voltage threshold.
OUT
IN
+
+
C1
10µF
ADP3367
Since the LBI input leakage current is less than 10 nA, large
values may be selected for R3 and R4 in order to minimize
loading. For example, a 6 V low threshold, may be set using
10 MΩ for R3 and 2.7 MΩ for R4.
SET GND SHDN
T he LBO output is an open-drain output that goes low sinking
current when LBI is less than 1.255 V. A pull-up resistor of
10 kΩ or greater may be used to obtain a logic output level with
Figure 8. Fixed +5 V Output Circuit
O utput Voltage Setting
If the SET input is connected to a resistor divider network, the
output voltage is set according to the following equation:
the pull-up resistor connected to VOUT
.
V
IN
IN
R1 + R2
OUT
V
OUT
VOUT =VSET
where VSET = 1.255 V.
×
R3
R4
+
C1
10µF
R1
ADP3367
10kΩ
LBI
LBO
SHDN GND SET
LOW BATTERY
STATUS OUTPUT
V
IN
IN
OUT
V
OUT
+
C1
ADP3367
R2
10µF
SET
Figure 10. Low Battery/Supply Detect Circuit
D r opout D etector
R1
SHDN
GND
T he ADP3367 features an extremely low dropout voltage mak-
ing it suitable for low voltage systems where headroom is
limited. A dropout detector is also provided. The dropout
detector output, DD, changes as the dropout voltage approaches
its limit. This is useful for warning that regulation can no longer be
maintained. The dropout detector output is an open collector out-
put from a PNP transistor. Under normal operating conditions
with the input voltage more than 300 mV above the output, the
PNP transistor is off and no current flows out the DD pin. As the
voltage differential reduces to less than 300 mV, the transistor
switches on and current is sourced. This condition indicates that
regulation can no longer be maintained. Please refer to Figure 4 in
the “Typical Performance Characteristics.” The current output
can be translated into a voltage output by connecting a resistor
from DD to GND. A resistor value of 100 kΩ is suitable. A digital
status signal can be obtained using a comparator. The on-chip
comparator LBI may be used if it is not being used to monitor a
battery voltage. This is illustrated in Figure 11.
Figure 9. Adjustable Output Circuit
T he resistor values may be selected by first choosing a value for
R1 and then selecting R2 according to the following equation:
VOUT
R2 = R1 ×
−1
VSET
T he input leakage current on SET is 10 nA maximum. T his
allows large resistor values to be chosen for R1 and R2 with
little degradation in accuracy. For example, a 1 MΩ resistor
may be selected for R1, and then R2 may be calculated accord-
ingly. T he tolerance on SET is guaranteed at less than ±25 mV,
so in most applications fixed resistors will be suitable.
Shutdown Input (SH D N)
T he SHDN input allows the regulator to be switched off with a
logic level signal. T his will disable the output and reduce the
current drain to a low quiescent (0.75 µA maximum) current.
T his is very useful for low power applications. Driving the
SHDN input to greater than 1.5 V places the part in shutdown.
If the shutdown function is not being used, then SHDN should
be connected to GND.
REV. 0
–5–
ADP3367
reached, the DD output starts sourcing current into the SET
input through R3. T his increases the SET voltage so that the
regulator feedback loop does not drive the internal PNP transis-
tor as hard as it otherwise would. As the input voltage continues
to decrease, more current is sourced, thereby reducing the PNP
drive even further. T he advantage of this scheme is that it main-
tains a low quiescent current down to very low values of VIN at
which point the batteries are well outside their useful operating
range. T he output voltage tracks the input voltage minus the
dropout. T he SHDN function is also unaffected and may be
used normally if desired.
+5V
OUTPUT
OUT
IN
+
+
C1
10µF
R2
10kΩ
V
IN
ADP3367
LBO
LBI
DROPOUT
STATUS
OUTPUT
DD
SET GND SHDN
R1
100kΩ
+5V
OUTPUT
Figure 11. Dropout Status Output
O utput Capacitor
IN
OUT
+
+
C1
10µF
R2
2MΩ
V
IN
ADP3367
An output capacitor is required on the ADP3367 to maintain sta-
bility and also to improve the load transient response. Capacitor
values from 10 µF upwards are recommended. Capacitors larger
than 10 µF will further improve the transient response. Tantalum
or aluminum electrolytics are suitable for most applications. For
temperatures below about –25°C, solid tantalums should be used
as many aluminum electrolytes freeze at this temperature.
SET
SHDN
R1
610kΩ
GND
DD
R3
1MΩ
Q uiescent Cur r ent Consider ations
1.2mA
1mA
T he ADP3367 uses a PNP output stage to achieve low dropout
voltages combined with high output current capability. Under
normal regulating conditions the quiescent current is extremely
low. However if the input voltage drops so that it is below the
desired output voltage, the quiescent current increases consider-
ably. T his happens because regulation can no longer be main-
tained and large base current flows in the PNP output transistor
in an attempt to hold it fully on. For minimum quiescent cur-
rent, it is therefore important that the input voltage is main-
tained higher than the desired output level. If the device is being
powered using a battery that can discharge down below the rec-
ommended level, there are a couple of techniques that can be
applied to reduce the quiescent current, but at the expense of
dropout voltage. T he first of these is illustrated in Figure 12. By
connecting DD to SHDN the regulator is partially disabled with
input voltages below the desired output voltage and therefore
the quiescent current is reduced considerably.
900
800
700
600
900µA
500µA
400
300
200
100
0
1
2
3
4
5
6
V
– V
IN
QUIESCENT CURRENT BELOW DROPOUT
Figure 13. IQ Reduction 2
P O WER D ISSIP ATIO N
T he ADP3367 can supply currents up to 300 mA and can oper-
ate with input voltages as high as 16.5 V, but not simultaneously.
It is important that the power dissipation and hence the internal
die temperature be maintained below the maximum limits. Power
Dissipation is the product of the voltage differential across the
regulator times the current being supplied to the load. T he
maximum package power dissipation is given in the Absolute
Maximum Ratings. In order to avoid excessive die temperatures,
these ratings must be strictly observed.
+5V
OUTPUT
IN
OUT
+
+
C1
10µF
V
IN
ADP3367
DD
SET GND SHDN
R1
47kΩ
C2
0.1µF
PD = (VIN – VOUT ) (IL )
Figure 12. IQ Reduction 1
T he die temperature is dependent on both the ambient tempera-
ture and on the power being dissipated by the device. T he inter-
nal die temperature must not exceed 125°C. T herefore, care
must be taken to ensure that, under normal operating condi-
tions, the die temperature is kept below the thermal limit.
Another technique for reducing the quiescent current near drop-
out is illustrated in Figure 13. T he DD output is used to modify
the output voltage so that as VIN drops, the desired output volt-
age setpoint also drops. T his technique only works when exter-
nal resistors are used to set the output voltage. With VIN greater
than VOUT , DD has no effect. As VIN reduces and dropout is
TJ = TA + PD (θJA
)
–6–
REV. 0
ADP3367
perature differential between the die and PC board; remember,
the rate at which heat is transferred is directly proportional to
the temperature differential.
T his may be expressed in terms of power dissipation as follows:
PD = (TJ – TA)/(θJA
)
where:
Various PC board layout techniques could be used to remove
the heat from the immediate vicinity of the package. Consider
the following issues when designing a board layout:
TJ = Die Junction T emperature (°C)
TA = Ambient T emperature (°C)
1. PC board traces with larger copper cross section areas will
remove more heat; use PCs with thicker copper and/or wider
traces.
PD = Power Dissipation (W)
θJA = Junction to Ambient T hermal Resistance (°C/W)
If the device is being operated at the maximum permitted ambi-
ent temperature of 85°C, the maximum power dissipation per-
mitted is:
2. Increase the surface area exposed to open air so heat can be
removed by convection or forced air flow.
3. Use larger masses such as heat sinks or thermally conductive
enclosures to distribute and dissipate the heat.
PD (max) = (TJ (max) – TA)/(θJA
)
PD (max) = (125 – 85)/(θJA
= 40/θJA
)
4. Do not solder mask or silk screen the heat dissipating traces;
black anodizing will significantly improve heat dissipation by
means of increased radiation.
where:
H igh P ower D issipation Recom m endations
θJA = 98°C/W for the 8-pin SOIC (R-8) package
T herefore, for a maximum ambient temperature of 85°C
PD (max) = 408 mW for R-8
Where excessive power dissipation due to high input-output
differential voltages and/or high current conditions exists, the
simplest method of reducing the power requirements on the
regulator is to use a series dropper resistor. In this way the
excess power can be dissipated in the external resistor. As an
example, consider an input voltage of +12 V and an output
voltage requirement of +5 V @ 100 mA with an ambient tem-
perature of +85°C. T he package power dissipation under these
conditions is 700 mW which exceeds the maximum ratings. By
using a dropper resistor to drop 4 V, the power dissipation
requirement for the regulator is reduced to 300 mW which is
within the maximum specifications for the SO-8 package at
85°C. T he resistor value is calculated as R = 4/0.1 = 40 Ω. A
resistor power rating of 1/2 W or greater may be used.
At lower ambient temperatures the maximum permitted power
dissipation increases accordingly up to the maximum limits
specified in the absolute maximum specifications.
T he thermal impedance (θJA) figures given are measured in still
air conditions and are reduced considerably where fan assisted
cooling is employed. Other techniques for reducing the thermal
impedance include large contact pads on the printed circuit
board and wide traces. T he copper will act as a heat exchanger
thereby reducing the effective thermal impedance.
P O WER D ISSIP ATIO N
40Ω
0.5W
Low Ther m al Resistance P ackage
V
+5V
OUTPUT
IN
12V
T he ADP3367 utilizes a patented and proprietary T hermal
Coastline Leadframe which offers significantly lower resistance
to heat flow from die to the PC board.
OUT
IN
+
+
C1
1µF
C2
10µF
ADP3367
Heat generated on the die is removed and transferred to the PC
board faster resulting in lower die temperature than standard
packages. T able II is a performance comparison between and
standard and T hermal Coastline package.
SET GND SHDN
Figure 14. Reducing Regulator Power Dissipation
Table I. Therm al Resistance P erform ance Com parison*
Tr ansient Response
T he ADP3367 exhibits excellent transient performance as illus-
trated in the “T ypical Performance Characteristics.” Figure 6
shows that an input step from 10 V to 6 V results in a very small
output disturbance (50 mV). Adding an input capacitor would
improve this even more.
Standard P ackage (SO -8)
Therm al Coastline P ackage
θJC
θJA
PD
44°C/W
170°C/W
235 mW
40°C/W
98°C/W
408 mW
Figure 7 shows how quickly the regulator recovers from an out-
put load change from 10 mA to 100 mA. T he offset due to the
load current change is less than 1 mV.
*Data presented in T able II is obtained using SEMI Standard Method G38-47
and SEMI Standard Specification G42-88.
A device operating at room temperature, +25°C, and +125°C
junction temperature can dissipate 1.15 W.
Monitor ed µP P ower Supply
Figure 15 shows the ADP3367 being used in a monitored µP
supply application. T he ADP3367 supplies +5 V for the micro-
T o maintain this high level of heat removal efficiency, once heat
is removed from the die to the PC board, it should be dissipated
to the air or other mediums to maintain the largest possible tem-
REV. 0
–7–
ADP3367
UNREGULATED
DC
processor. Monitoring the supply, the ADM705 will generate a
reset if the supply voltage falls below 4.65 V. Early warning of
an impending power fail is generated by a power fail comparator
on the ADM705. A resistive divider network samples the pre-
regulator input voltage so that failing power is detected while
the regulator is still operating normally. An interrupt is gener-
ated so that a power-down sequence can be completed before
power is completely lost. T he low dropout voltage on the
ADP3367 maximizes the available time to carry out the power-
down sequence. T he resistor divider network R1 and R2 should
be selected so that the voltage on PFI is 1.25 V at the desired
warning voltage.
IN
ADP3367
+5V
+
OUT
10µF
GND SET SHDN
V
V
CC
CC
RESET
µP
RESET
ADM705
GND
R1
R2
PFI
PFO
INTERRUPT
Figure 15. µP Regulator with Supply Monitoring and Early
Power-Fail Warning
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-Lead Nar r ow-Body SO IC
(SO -8)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.2440 (6.20)
0.2284 (5.80)
0.1968 (5.00)
0.1890 (4.80)
0.0196 (0.50)
0.0099 (0.25)
x 45
°
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8
0
°
°
0.0500 (1.27)
0.0160 (0.41)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
–8–
REV. 0
相关型号：
ADP3404ARUZ-REEL7
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO28, ROHS COMPLIANT, TSSOP-28, Power Management Circuit
ADI
ADP3405ARU-REEL
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO28, 4.40 MM, TSSOP-28, Power Management Circuit
ADI
©2020 ICPDF网 联系我们和版权申明