ADP3402ARU [ADI]
GSM Power Management System; GSM电源管理系统
| 型号： | ADP3402ARU |
| 厂家： | 
ADI |
| 描述： | GSM Power Management System |
| 文件： | 总12页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
GSM Power Management System
ADP3402
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Handles all GSM Baseband Power Management
Functions
VBAT
Four LDOs Optimized for Specific GSM Subsystems
Charges Back-Up Capacitor for Real-Time Clock
Charge Pump and Logic Level Translators for 3 V and 5 V
GSM SIM Modules
ADP3402
DIGITAL
VCC
LDO
Thermally Enhanced 6.1 mm 28-Lead TSSOP Package
RESET
APPLICATIONS
PWRONKEY
GSM/DCS/PCS Handsets
TeleMatic Systems
ICO/Iridium Terminals
RTC LDO
VRTC
ROWX
POWER-UP
SEQUENCING
AND
PROTECTION
LOGIC
XTAL OSC
LDO
PWRONIN
ANALOGON
RESCAP
VTCXO
VCCA
GENERAL DESCRIPTION
ANALOG
LDO
CHRON
The ADP3402 is a multifunction power management system IC
optimized for GSM cell phones. The wide input voltage range of
3.0 V to 7.0 V makes the ADP3402 ideal for both single cell
Li-Ion and three cell NiMH designs. The current consumption of
the ADP3402 has been optimized for maximum battery life,
featuring a ground current of only 230 µA when the phone is in
standby (digital LDO, analog LDO, and SIM card supply active).
An undervoltage lockout (UVLO) prevents the startup when
there is not enough energy in the battery. All four integrated
LDOs are optimized to power one of the critical sub-blocks of the
phone. Their novel anyCAP™ architecture requires only very
small output capacitors for stability, and the LDOs are insensitive
to the capacitors’ equivalent series resistance (ESR). This makes
them stable with any capacitor, including ceramic (MLCC) types
for space-restricted applications.
SIMBAT
CAP+
CAP؊
CHARGE
PUMP
VSIM
SIMPROG
SIMON
BUFFER
REFOUT
DGND
REF
SIMGND
+
RESETIN
CLKIN
LOGIC LEVEL
TRANSLATION
AGND
DATAIO
CLK RST
I/O
A step-up converter is implemented to supply both the SIM
module and the level translation circuitry to adapt logic signals
for 3 V and 5 V SIM modules. Sophisticated controls are avail-
able for power-up during battery charging, keypad interface and
charging of an auxiliary back-up capacitor for the real-time clock.
These allow an easy interface between ADP3402, GSM proces-
sor, charger, and keypad. The 28-lead TSSOP package has been
thermally enhanced to maximize power dissipation capability.
Furthermore, a reset circuit and a thermal shutdown function
have been implemented to support reliable system design.
anyCAP is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(–20°C ≤ TA ≤ +85°C, VBAT = 3 V to 7 V, CVBAT = CSIMBAT = CVSIM = 10 F,
VCC = CVCCA = 2.2 F, CVRTC = 0.1 F, CVTCXO = 0.22 F, CVCAP = 0.1 F, minimum loads
applied on all outputs, unless otherwise noted)
C
ADP3402–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS1
Parameter
Symbol
Conditions
Min
Typ Max
Unit
SHUTDOWN SUPPLY CURRENT
VBAT = Low (UVLO Low)
VBAT = High (UVLO High)
IBAT
VBAT = 2.7 V
VBAT = 3.6 V, VRTC On
3
12
20
30
µA
µA
OPERATING GROUND CURRENT
VCC, VRTC, VCCA, REFOUT On
VCC, VRTC, VCCA, REFOUT
and VSIM On
IGND
Minimum Loads, VBAT = 3.6 V
175 240
µA
Minimum Loads, VBAT = 3.6 V
Minimum Loads, VBAT = 3.6 V
Maximum Loads, VBAT = 3.6 V
230 340
260 400
15
µA
µA
mA
All LDOs and VSIM On
All LDOs and VSIM On
UVLO CHARACTERISTICS
UVLO On Threshold
UVLO Hysteresis
VBATUVLO
3.2
200
3.3
V
mV
INPUT CHARACTERISTICS
Input High Voltage
PWRONIN and ANALOGON
PWRONKEY
Input Low Voltage
VIH
VIL
2
V
V
0.7 ϫ VBAT
PWRONIN and ANALOGON
PWRONKEY
0.4
V
V
0.3 ϫ VBAT
PWRONKEY INPUT PULLUP
RESISTANCE TO VBAT
15
20
25
kΩ
CHRON CHARACTERISTICS
CHRON Threshold
CHRON Hysteresis Resistance
CHRON Input Bias Current
VT
RIN
IB
2.38
108
2.48 2.58
125 138
0.5
V
kΩ
µA
2.38 < CHRON < VT
CHRON > VT
ROWX CHARACTERISTICS
ROWX Output Low Voltage
VOL
IIH
PWRONKEY = Low
IOL = 200 µA
PWRONKEY = High
V(ROWX) = 5 V
0.4
1
V
ROWX Output High Leakage
Current
µA
SHUTDOWN
Thermal Shutdown Threshold2
Thermal Shutdown Hysteresis
Junction Temperature
Junction Temperature
160
35
ºC
ºC
DIGITAL LDO (VCC)
Output Voltage
Line Regulation
VCC
∆VCC
∆VCC
Line, Load, Temp
2.400
2.450 2.500
2
15
V
mV
mV
3 V < VBAT < 7 V, Min Load
50 µA < ILOAD < 100 mA,
VBAT = 3.6 V
Load Regulation
Output Capacitor3
CO
2.2
µF
ANALOG LDO (VCCA)
Output Voltage
Line Regulation
Load Regulation
VCCA
∆VCCA
∆VCCA
Line, Load, Temp
2.710
2.765 2.820
2
15
V
mV
mV
3 V < VBAT < 7 V, Min Load
200 µA < ILOAD < 130 mA,
VBAT = 3.6 V
Output Capacitor3
Dropout Voltage
CO
VDO
2.2
65
µF
mV
VO = VINITIAL – 100 mV
ILOAD = 130 mA
f = 217 Hz (t = 4.6 ms)
VBAT = 3.6 V
f = 10 Hz to 100 kHz
ILOAD = 130 mA, VBAT = 3.6 V
215
Ripple Rejection
∆VBAT/
∆VCCA
VNOISE
70
75
dB
Output Noise Voltage
µV rms
–2–
REV. 0
ADP3402
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CRYSTAL OSCILLATOR LDO (VTCXO)
Output Voltage
Line Regulation
VTCXO
∆VTCXO
∆VTCXO
Line, Load, Temp
2.710
2.765 2.820
2
1
V
mV
mV
3 V < VBAT < 7 V, Min Load
100 µA < ILOAD < 5 mA,
VBAT = 3.6 V
Load Regulation
Output Capacitor3
Dropout Voltage
CO
VDO
0.22
65
µF
mV
VO = VINITIAL – 100 mV
ILOAD = 5 mA
f = 217 Hz (t = 4.6 ms)
VBAT = 3.6 V
f = 10 Hz to 100 kHz
ILOAD = 5 mA, VBAT = 3.6 V
150
Ripple Rejection
∆VBAT/
∆VTCXO
VNOISE
72
80
dB
Output Noise Voltage
µV rms
VOLTAGE REFERENCE (REFOUT)
Output Voltage
Line Regulation
VREFOUT
∆VREFOUT
∆VREFOUT
Line, Load, Temp
1.192
1.210 1.228
2
0.5
V
mV
mV
3 V < VBAT < 7 V, Min Load
0 µA < ILOAD < 50 µA,
VBAT = 3.6 V
Load Regulation
Ripple Rejection
∆VBAT/
∆VREFOUT
CO
f = 217 Hz (t = 4.6 ms),
VBAT = 3.6 V
65
75
dB
Maximum Capacitive Load
Output Noise Voltage
100
pF
µV rms
VNOISE
f = 10 Hz to 100 kHz
VBAT = 3.6 V
40
REAL-TIME CLOCK LDO/BATTERY
CHARGER (VRTC)
Maximum Output Voltage
Current Limit
VRTC
IMAX
IL
ILOAD ≤ 10 µA
2.400
2.450 2.500
175
1
V
µA
µA
Off Reverse Leakage Current
2.0 V < VBAT < UVLO
SIM CHARGE PUMP (VSIM)
Output Voltage for 5 V SIM Modules
VSIM
VSIM
0 mA ≤ ILOAD ≤ 10 mA
SIMPROG = High
0 mA ≤ ILOAD ≤ 6 mA
SIMPROG = Low
4.70
2.82
5.00
3.00
5.30
3.18
V
V
Output Voltage for 3 V SIM Modules
GSM/SIM LOGIC TRANSLATION
(GSM INTERFACE)
Input High Voltage (SIMPROG, SIMON, VIH
RESETIN, CLKIN)
Input Low Voltage (SIMPROG, SIMON,
RESETIN, CLKIN)
DATAIO
VCC – 0.6
V
V
V
V
VIL
0.6
VIL
VOL (I/O) = 0.4 V,
IOL (I/O) = 1 mA
VOL (I/O) = 0.4 V,
IOL (I/O ) = 0 mA
IIH, IOH = ±10 µA
VIL = 0 V
0.230
0.335
VIH, VOH
IIL
VOL
VCC – 0.4
16
V
mA
V
–0.9
0.420
24
VIL (I/O) = 0.4 V
DATAIO Pull-Up Resistance to VCC
RIN
20
kΩ
REV. 0
–3–
ADP3402–SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SIM INTERFACE
VSIM = 5 V
RST
RST
CLK
CLK
I/O
I/O
I/O
I/O
VOL
VOH
VOL
VOH
VIL
VIH, VOH
IIL
I = +200 µA
I = –20 µA
I = +200 µA
I = –20 µA
0.6
0.5
0.4
V
V
V
V
V
V
mA
V
VSIM – 0.7
0.7 ϫ VSIM
VSIM – 0.4
IIH, IOH = ±20 µA
VIL = 0 V
IOL = 1 mA
–0.9
0.4
VOL
DATAIO ≤ 0.23 V
VSIM = 3 V
RST
RST
CLK
CLK
I/O
VOL
VOH
VOL
VOH
VIL
I = +200 µA
I = –20 µA
I = +20 µA
I = –20 µA
0.2 ϫ VSIM
0.2 ϫ VSIM
0.4
V
V
V
V
V
V
mA
V
0.8 ϫ VSIM
0.7 ϫ VSIM
VSIM – 0.4
I/O
I/O
I/O
VIH, VOH
IIL
VOL
IIH, IOH = ±20 µA
VIL= 0 V
IOL = 1 mA
–0.9
0.4
DATAIO ≤ 0.23 V
I/O Pull-Up Resistance to VSIM
Max Frequency (CLK)
Prop Delay (CLK)
Output Rise/Fall Times (CLK)
Output Rise/Fall Times (I/O, RST)
Duty Cycle (CLK)
RIN
fMAX
tD
tR, tF
tR, tF
D
8
5
10
12
kΩ
MHz
ns
ns
µs
CL = 30 pF
30
9
50
18
1
CL = 30 pF
CL = 30 pF
D CLKIN = 50%
f = 5 MHz
47
53
%
RESET GENERATOR (RESET)
Output High Voltage
Output Low Voltage
Delay Time per Unit Capacitance
Applied to RESCAP Pin
VOH
VOL
tD
IOH = –15 µA
IOL = –15 µA
VCC – 0.3
1.0
V
V
ms/nF
0.3
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods .
2This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC
could cause permanent damage to the device.
3Required for stability.
Specifications subject to change without notice.
–4–
REV. 0
ADP3402
PIN FUNCTION DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin with Respect to Any
Pin
Mnemonic
Function
GND Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +10 V
Voltage on Any Pin May Not Exceed VBAT,
with the Following Exceptions: VRTC,
1
2
3
4
5
VBAT
VCC
PWRONKEY
ANALOGON
PWRONIN
Battery Input Voltage
Digital Low Dropout Regulator
Power On/Off Key
VTCXO Enable
Power On/Off Signal from
Microprocessor
Microprocessor Keyboard Output
Charger On/Off Input
Real-Time Clock Supply/Coin
Cell Battery Charger
Negative Side of Boost Capacitor
Battery Input for the SIM
Charge Pump
Non-Level-Shifted Bidirectional
Data I/O
Non-Level-Shifted SIM Reset
Non-Level-Shifted Clock
Charge Pump Ground
Level-Shifted Bidirectional SIM
Data Input/Output
Level-Shifted SIM Reset
VSIM Programming:
Low = 3 V, High = 5 V
VSIM Enable
Level-Shifted SIM Clock
SIM Supply
Positive Side of Boost Capacitor
Reset Delay Timing Cap
Digital Ground
Crystal Oscillator Low Dropout
Regulator
VSIM, CAP+, PWRONIN, I/O, CLK, RST
Storage Temperature Range . . . . . . . . . . . . –65
Operating Temperature Range . . . . . . . . . . . –20
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125
θJA, Thermal Impedance (TSSOP-28) . . 2-Layer Board 90 C/W
θJA, Thermal Impedance (TSSOP-28) . . 4-Layer Board 60 C/W
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300
°
C to +150
°C
°C to +85
°C
°C
°
°
6
7
8
ROWX
CHRON
VRTC
°C
*This is a stress rating only, operation beyond these limits can cause the device to
be permanently damaged.
9
10
CAP–
SIMBAT
PIN CONFIGURATION
11
DATAIO
1
2
28
27
26
25
24
23
22
VBAT
AGND
12
13
14
15
RESETIN
CLKIN
SIMGND
I/O
VCCA
VCC
PWRONKEY
ANALOGON
3
REFOUT
RESET
VTCXO
DGND
4
5
PWRONIN
ROWX
6
16
17
RST
SIMPROG
7
CHRON
VRTC
RESCAP
ADP3402
8
21 CAP+
20 VSIM
CAP؊
9
18
19
20
21
22
23
24
SIMON
CLK
VSIM
10
11
12
13
14
19
18
17
16
15
SIMBAT
DATAIO
RESETIN
CLKIN
CLK
SIMON
SIMPROG
RST
CAP+
RESCAP
DGND
VTCXO
SIMGND
I/O
ORDERING GUIDE
25
26
27
28
RESET
REFOUT
VCCA
Main Reset
Reference Output
Analog Low Dropout Regulator
Analog Ground
Temperature
Range
Package
Description
Package
Option
Model
AGND
ADP3402ARU –20°C to +85°C 28-Lead TSSOP RU-28A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3402 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
ADP3402
Table I. LDO Control Logic
OUTPUTS
INPUTS
UVLO
CHRON
PWRONKEY
PWRONIN
ANALOGON
VRTC
Off
VCC VCCA REFOUT VTCXO
L
X
H
X
L
X
X
L
X
X
X
L
X
X
X
X
L
Off
On
On
Off
On
On
Off
On
On
Off
On
On
Off
On
On
Off
On
On
Off
On
On
Off
Off
On
H
H
H
H
H
On
On
H
H
H
On
L
H
H
On
L
H
On
X = Don't care
Bold denotes the active control signal.
Table II. VSIM Control Logic
INPUTS
VCC
OUTPUTS
VSIM
RESET
SIMON
SIMPROG
Off
On
On
On
On
L
L
H
H
H
X
X
L
H
H
X
X
X
L
Off
Off
Off
3 V
5 V
H
X = Don't care
VBAT
ADP3402
DIGITAL LDO
VBAT
VREF
VCC
2.45V
OUT
PG
20k⍀
ADJ
EN
UVLO
GND
UVLO
DGND
POWER GOOD
RTC LDO
OUT
PWRONKEY
ROWX
OVER
TEMP
VRTC
2.45V
VBAT
EN
GND
PWRONIN
RESCAP
RESET
GENERATOR
RESET
XTAL OSC LDO
VBAT
VTCXO
2.765V
CHARGER
VREF
EN
OUT
ON
CHRON
THRESHOLD
GND
ANALOGON
SIMBAT
CAP+
ANALOG LDO
VBAT
EN
CHARGE
PUMP
CAP؊
VCCA
2.765V
VREF
EN
OUT
3V/5V
EN
SIMPROG
SIMON
GND
SIMGND
RESETIN
CLKIN
EN
LOGIC
LEVEL
TRANSLATION
REF
BUFFER
REFOUT
AGND
DATAIO
+
1.210V
I/O CLK RST
VSIM
Figure 1. Functional Block Diagram
–6–
REV. 0
ADP3402
200
180
160
140
120
100
80
350
300
250
200
150
100
+85؇C
PWRONIN, SIMON, AND ANALOGON
PWRONIN AND SIMON
+25؇C
؊20؇C
60
PWRONIN
40
20
0
0
3
4
5
6
7
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
VRTC – V
VBAT – V
Figure 2. Ground Current vs. Battery Voltage
Figure 5. RTC I/V Characteristic
160
MLCC CAPS
VBAT 100 mV/DIV
140
120
100
80
3.2
3.0
VCC 10 mV/DIV
VCCA 10 mV/DIV
VTCXO 10 mV/DIV
60
40
20
0
0
20
40
60
80
100
120
140
LOAD CURRENT – mA
TIME – 100s/DIV
Figure 3. VCCA Dropout Voltage vs. Load Current
Figure 6. Line Transient Response, Maximum Loads
80
70
60
50
40
30
20
10
0
MLCC CAPS
VBAT (100 mV/DIV)
3.2
3.0
VCC (10 mV/DIV)
VCCA (10 mV/DIV)
VTCXO (10 mV/DIV)
0
1
2
3
4
5
TIME – 100s/DIV
LOAD CURRENT – mA
Figure 4. VTCXO Dropout Voltage vs. Load Current
Figure 7. Line Transient Response, Minimum Loads
REV. 0
–7–
ADP3402
MLCC CAPS
I = 100mA
I
LOAD
PWRONIN AND ANALOGON (2V/DIV)
VCCA (100mV/DIV)
I = 200A
VCC
REFOUT (100mV/DIV)
VCC (100mV/DIV)
VTCXO (100mV/DIV)
TIME – 200s/DIV
TIME – 50s/DIV
Figure 8. VCC Load Step
Figure 11. Turn-On Transients, Maximum Loads
80
MLCC CAPS
I = 130mA
70
60
50
40
30
20
10
0
VTCXO
I
VCCA
LOAD
I = 50A
REFOUT
MLCC OUTPUT CAPS
VBAT = 3.2V, FULL LOADS
VCC
VCCA
4
10
100
1k
10k
100k
TIME – 100s/DIV
FREQUENCY – Hz
Figure 12. Ripple Rejection vs. Frequency
Figure 9. VCCA Load Step
80
REFOUT
70
60
50
40
30
20
10
0
PWRONIN AND ANALOGON (2V/DIV)
VCCA (100mV/DIV)
VCC
VTCXO (100mV/DIV)
VCC (100mV/DIV)
VTCXO
VCCA
FREQUENCY = 217Hz
MAX LOADS
2.5
2.6
2.7
2.8
2.9
VBAT – V
3.0
3.1
3.2
3.3
TIME – 50s/DIV
Figure 13. Ripple Rejection vs. Battery Voltage
Figure 10. Turn-On Transients, Minimum Loads
–8–
REV. 0
ADP3402
These functions have traditionally been done either as a discrete
implementation or as a custom ASIC design. ADP3402 combines
the benefits of both worlds by providing an integrated standard
product solution where every block is optimized to operate in a
GSM environment while maintaining a cost competitive solution.
600
500
FULL LOAD
MLCC CAPS
VCCA
TCXO
400
300
200
100
0
Figure 15 shows the external circuitry associated with the ADP3402.
Only a few support components, mainly decoupling capacitors,
are required.
Input Voltage
REF
The input voltage range for ADP3402 is 3 V to 7 V and optimized
for a single Li-Ion cell or three NiMH/NiCd cells. The ADP3402
uses Analog Devices’ patented package thermal enhancement tech-
nology, which allows 15% improvement in power handling capabil-
ity over standard plastic packages. The thermal impedance (θJA) of
10
100
1k
10k
100k
FREQUENCY – Hz
the ADP3402 is 60°C/W. The charging voltage for a high capacity
Figure 14. Output Noise Density
THEORY OF OPERATION
The ADP3402 is a power management chip optimized for use
with GSM baseband chipsets in handset applications. Figure 1
shows a block diagram of the ADP3402.
NiMH cell can be as high as 5.5 V. Power dissipation should be
calculated at maximum ambient temperatures and battery voltage in
order not to exceed the 125°C maximum allowable junction tem-
perature. Figure 16 shows the maximum total LDO output current
as a function of ambient temperature and battery voltage.
However, high battery voltages normally occur only when the
battery is being charged and the handset is not in conversation
mode. In this mode there is a relatively light load on the LDOs.
A fully charged Li-Ion battery is 4.25 V, where the LDOs deliver
The ADP3402 contains several blocks:
• Four Low Dropout Regulators (Digital, Analog, Crystal
Oscillator, Real-Time Clock)
• Reset Generator
the maximum 240 mA up to the max 85
°
C ambient temperature.
• Buffered Precision Reference
• SIM Interface Logic Level Translation (3 V/5 V)
• SIM Voltage Supply
• Power On/Off Logic
• Undervoltage Lockout
CHARGER INPUT
R1
1
2
3
4
5
6
7
8
9
VBAT
AGND
VCCA
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10F
1 Li-ION OR
3 NiMH
VCC
2.2F
CELLS
2.2F
10F
100⍀
PWRONKEY
ANALOGON
PWRONIN
ROWX
REFOUT
RESET
VTCXO
DGND
RESCAP
CAP+
GSM
PROCESSOR
0.22F
ANALOG GND
DIGITAL AND
SIM GND
R2
CHRON
VRTC
100nF
ADP3402
CAPACITOR-TYPE
BACKUP COIN CELL
100nF
CAP–
VSIM
10F
CLK TO SIMCARD
10 SIMBAT
11 DATAIO
12 RESETIN
13 CLKIN
CLK
100nF
10F
SIMON
SIMPROG
RST
GSM
PROCESSOR
SIM PIN OF
GSM PROCESSOR
RST TO SIMCARD
I/O TO SIM CARD
14 SIMGND
I/O
Figure 15. Typical Application Circuit
REV. 0
–9–
ADP3402
300
The ADP3402 supplies current both for charging the coin cell and
for the RTC module when the digital supply is off. The nominal
charging voltage is 2.45 V, which ensures long cell life while obtain-
ing in excess of 90% of the nominal capacity. In addition, it features
a very low quiescent current (10 µA) since this LDO is running all
the time, even when the handset is switched off. It also has reverse
current protection with low leakage which is needed when the main
battery is removed and the coin cell supplies the RTC module.
4-LAYER BOARD
= 60؇C/W
JA
VBAT = 5V
250
200
150
100
50
VBAT = 5.5V
VBAT = 6V
VBAT = 7V
Reference Output (REFOUT)
The reference output is a low noise, high precision reference with a
guaranteed accuracy of 1.5% over temperature. The reference can
be fed to the baseband converter, such as the AD6425, improving
the absolute accuracy of the converters from 5% to 1.5%. This
significantly reduces calibration time needed for the baseband
converter during production.
0
؊20
0
20
40
60
80 85
AMBIENT TEMPERATURE – ؇C
Figure 16. Total LDO Load Current vs. Temperature and VBAT
SIM Interface
The SIM interface generates the needed SIM voltage—either 3 V
or 5 V, dependent on SIM type, and also performs the needed
logic level translation. Quiescent current is low, as the SIM card
will be powered all the time. Note that DATAIO and I/O have
integrated pull-up resistors as shown in Figure 18. See Table II for
the control logic of the charge pump output, VSIM.
Low Dropout Regulators (LDOs)
The ADP3402 high-performance LDOs are optimized for their
given functions by balancing quiescent current, dropout voltage,
line/load regulation, ripple rejection, and output noise. 2.2 µF
tantalum or MLCC ceramic capacitors are recommended for
use with the digital and analog LDOs, and 0.22 µF for the
TCXO LDO.
Digital LDO (VCC)
ADP3402
The digital LDO (VCC) supplies all the digital circuitry in the
handset (baseband processor, baseband converter, external
memory, display, etc). The LDO has been optimized for very
low quiescent current (30 µA maximum) at light loads as this
LDO is on at all times.
VCC
VSIM
LEVEL
SHIFT
RESETIN
CLKIN
RST
CLK
VCC
VCC
VSIM
VSIM
LEVEL
SHIFT
Analog LDO (VCCA)
This LDO has the same features as the digital LDO. It has further-
more been optimized for good low frequency ripple rejection for use
with analog sections in order to reject the ripple coming from the RF
power amplifier. VCCA is rated to 130 mA load which is sufficient
to supply the complete analog section of a baseband converter such
as the AD6421/AD6425, including a 32 Ω earpiece.
DATAIO
I/O
Figure 18. Schematic for Level Translators
Power-On/-Off
ADP3402 handles all issues regarding power-on/-off of the hand-
set. It is possible to turn on the ADP3402 in three different ways:
TCXO LDO (VTCXO)
The TCXO LDO is intended as a supply for temperature com-
pensated crystal oscillator, which needs its own ultralow noise
supply. The output current is rated to 5 mA for the TCXO LDO.
• Pulling PWRONKEY Low
• Pulling PWRONIN High
• CHRON exceeds threshold
RTC LDO (VRTC)
The RTC LDO charges a capacitor-type backup coin cell to run
the real-time clock module. It has been targeted to charge elec-
tric double layer capacitors such as the PAS621 from Kanebo.
The PAS621 has a small physical size (6.8 mm diameter) and a
nominal capacity of 0.3 F, giving many hours of backup time.
Pulling PWRONKEY key low is the normal way of turning on the
handset. This will turn on all the LDOs as long as PWRONKEY is
held low. The microprocessor then starts and pulls PWRONIN
high after which PWRONKEY can be released. PWRONIN going
high will also turn on the handset. This is the case when the alarm
in the RTC module expires.
GSM PROCESSOR
ADP3402
An external charger can also turn on the phone. The turn-on
threshold and hysteresis can be programmed via external resistors
to allow full flexibility with any external charger and battery chem-
istry. These resistors are referred to as R1 and R2 in Figure 15.
VRTC
VRTC
COIN
CELL
RTC
MODULE
Undervoltage Lockout (ULVO)
PWRONIN
PWRON
The UVLO function in the ADP3402 prevents startup when the
initial voltage of the main battery is below the 3.2 V threshold.
If the battery is this low with no load, there will be little or no
capacity left. When the battery is greater than 3.2 V, as with the
insertion of a fresh battery, the UVLO comparator trips, the
Figure 17. Connecting VRTC and POWERONIN to the Chipset
–10–
REV. 0
ADP3402
RTC LDO is enabled, and the threshold is reduced to 3.0 V.
This allows the handset to start normally until the battery volt-
age decays to 3.0 V open circuit. Once the 3.2 V threshold is
exceeded, the RTC LDO is enabled. If, however, if the backup
coin cell is not connected, or is damaged or discharged below
1.5 V, the RTC LDO will not start on its own. In this situation,
the RTC LDO will be started by enabling the VCC LDO.
All the LDOs are stable with a wide range of capacitor types and
ESR due to Analog Devices’ anyCAP technology. The ADP3402
is stable with extremely low ESR capacitors (ESR ~ 0), such as
multilayer ceramic capacitors, but care should be taken in their
selection. Note that the capacitance of some capacitor types show
wide variations over temperature or with dc voltage. A good quality
dielectric, X7R or better, is recommended.
Once the system is started, i.e., the phone is turned on and the
VCC LDO is up and running, the UVLO function is entirely
disabled. The ADP3402 is then allowed to run down to very low
battery voltages, typically around 2 V. The battery voltage is
normally monitored by the microprocessor and usually shuts the
phone off at around 3.0 V.
The RTC LDO has a rechargeable coin cell or an electric double-
layer capacitor as a load, but a 0.1 µF ceramic capacitor is recom-
mended for stability and best performance.
Charge Pump Capacitor Selection
For the input (SIMBAT) and output (VSIM) of the SIM charge
pump, use 10 µF low ESR capacitors. The use of low ESR capaci-
tors improves the noise and efficiency of the SIM charge pump.
Multilayer ceramic chip capacitors provide the best combination of
low ESR and small size but may not be cost effective. A lower cost
alternative may be to use a 10 µF tantalum capacitor with a small
(1 µF to 2 µF) ceramic capacitor in parallel.
If the phone is off, i.e., the VCC LDO is off, and the battery
voltage drops below 3.0 V, the UVLO circuit disables startup
and the RTC LDO. This is implemented with very low quies-
cent current, typically 3 µA, to protect the main battery against
any damage. NiMH batteries can reverse polarity if the 3-cell
battery voltage drops below 3.0 V and a current of more than
about 40 µA continues to flow. Lithium ion batteries will lose
their capacity, although the built-in safety circuits normally
present in these cells will most likely prevent any damage.
For the lowest ripple and best efficiency, use a 0.1 µF, ceramic
capacitor for the charge pump flying capacitor (CAP+ and CAP–).
A good quality dielectric, such as X7R is recommended.
Setting the Charger Turn-On Threshold
RESET
The ADP3402 can be turned on when the charger input exceeds
a programmable threshold voltage. The charger’s threshold and
hysteresis are set by selecting the values for R1 and R2 shown in
Figure 15.
ADP3402 contains reset circuitry that is active both at power-up
and at power-down. RESET is held low at power-up. An inter-
nal power-good signal starts the reset delay. The delay is set by
an external capacitor on RESCAP:
The turn-on threshold for the charger is calculated using:
tRESET = 1.0 ms/nF ×CRESCAP
R2 + RHYS
R2 × RHYS
VCHR
=
× R1 +1 ×VT
A 100 nF capacitor will produce a 100 ms reset time. At power-
off, RESET will be kept low to prevent any spurious microproces-
sor starts. The current capability of RESET is low (a few hundred
nA) when VCC is off, to minimize power consumption. There-
fore, RESET should only be used to drive a single CMOS input.
When VCC is on, RESET will drive about 15 µA.
Where VT is the CHRON threshold voltage and RHYS is the
CHRON hysteresis resistance.
The hysteresis is determined using:
VT
RHYS
Overtemperature Protection
The maximum die temperature for ADP3402 is 125
VHYS
=
× R1
°C. If the die
temperature exceeds 160 C, the ADP3402 will disable all the LDOs
°
Combining the above equations and solving for R1 and R2 gives
except the RTC LDO, which has very limited current capabilities.
The LDOs will not be re-enabled before the die temperature is
the following formulas:
below 125°C, regardless of the state of PWRONKEY, PWRONIN,
and CHRON. This ensures that the handset will always power-off
before the ADP3402 exceeds its absolute maximum thermal ratings.
RHYS
VT
R1 =
×VHYS
R1× RHYS
R2 =
APPLICATIONS INFORMATION
Input Capacitor Selection
VCHR
VT
−1 × RHYS − R1
For the input voltage, VBAT, of the ADP3402, a local bypass
capacitor is recommended. Use a 5 µF to 10 µF, low ESR capaci-
tor. Multilayer ceramic chip capacitors provide the best combina-
tion of low ESR and small size, but may not be cost effective. A
lower cost alternative may be to use a 5 µF to 10 µF tantalum
capacitor with a small (1 µF to 2 µF) ceramic in parallel.
Example: R1 = 10 kΩ and R2 = 30.2 kΩ gives a charger thresh-
old (not counting the drop in the power Schottky diode) of
3.5 V ± 160 mV with a 200 mV ± 30 mV hysteresis.
Charger Diode Selection
The diode shown in Figure 15 is used to prevent the battery from
discharging into the charger turn-on setting resistors, R1 and R2. A
Schottky diode is recommended to minimize the voltage difference
from the charger to the battery and the power dissipation. Choose
a diode with a current rating high enough to handle both the bat-
tery charging current and the current the ADP3402 will draw if
powered up during charging. The battery charging current is de-
pendent on the battery chemistry, and the charger circuit. The
ADP3402 current will be dependent on the loading.
LDO Capacitor Selection
The performance of any LDO is a function of the output capaci-
tor. The digital and analog LDOs require a 2.2 µF capacitor and
the TCXO LDO requires a 0.22 µF capacitor. Larger values
may be used, but the overshoot at startup will increase slightly.
If a larger output capacitor is desired, be sure to check that the
overshoot and settling time are acceptable for the application.
REV. 0
–11–
ADP3402
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
3. VCCA and VTCXO capacitors should be returned to
AGND.
4. VCC and VRTC capacitors should be returned to DGND.
1. Split the battery connection to the VBAT and SIMBAT pins
of the ADP3402. Use separate traces for each connection
and locate the input capacitors as close to the pins as possible.
5. Split the ground connections. Use separate traces or planes for
the analog, digital, and power grounds, and tie them together
at a single point, preferably close to the battery return.
2. SIM input and output capacitors should be returned to the
SIMGND and kept as close as possible to the ADP3402 to
minimize noise. Traces to the SIM charge pump capacitor
should be kept as short as possible to minimize noise.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Thin Shrink Small Outline (TSSOP)
(RU-28A)
0.386 (9.80)
0.378 (9.60)
15
28
0.244 (6.20)
0.236 (6.00)
0.325 (8.25)
0.313 (7.95)
1
14
PIN 1
0.0374 (0.95)
0.0335 (0.85)
0.0433 (1.10)
MAX
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.030 (0.75)
0.020 (0.50)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0078 (0.200)
0.0035 (0.090)
–12–
REV. 0
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