ADP3502 [ADI]
CDMA Power Management System; CDMA电源管理系统
| 型号： | ADP3502 |
| 厂家： | 
ADI |
| 描述： | CDMA Power Management System |
| 文件： | 总36页 (文件大小：671K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
CDMA Power Management System
ADP3502
FEATURES
FUNCTIONAL BLOCK DIAGRAM
11 LDOs Optimized for Specific CDMA Subsystems
4 Backup LDOs for Standby Mode Operation
Ultra Low Standby Supply Current
High Accuracy Battery Charger (0.7%)
3 Li-Ion Battery Charge Modes
5 mA Precharge
Low Current Charge
Full Current Charge
Integrated RTC
LOGIC
ANALOG
BLOCK
BLOCK
BATTERY
CHARGER
POWER ON
KEYPAD I/F
GPIO
DELAY 10ms
INTERRUPT
CONTROL
REFERENCE
LDO
CONTROL
LDO1TO LDO11
Ambient Temperature: –30؇C to +85؇C
64-Lead 7 mm
؋
7 mm ؋
1 mm TQFP Package VOLTAGE
DETECTOR
SERIAL I/F
RESET
APPLICATIONS
CDMA/CDMA2000/PCS Handsets
RTC
COUNTER
32kHz OUTPUT
CONTROL
ADP3502
RESET
OUTPUT
STAY-ALIVE
TIMER
GENERAL DESCRIPTION
The ADP3502 is a multifunction chip optimized for CDMA-1x
cell phone power management. It offers a total power solution
for the handset baseband and RF section, including LDOs to
power 11 subsystems. Also integrated are a real-time clock
(RTC), serial bus interface, and charging control for Li-Ion/
Li-Polymer batteries. Sophisticated controls are available for
power-up during battery charging, keypad interface, GPIO/INT
function, and RTC function.
The ADP3502 is optimized for CDMA handsets powered by
single-cell Li-Ion batteries. Its high level of integration sig-
nificantly reduces the design effort, number of discrete
components, and solution size/cost. The main-sub LDO
structure reduces the standby current consumption, and as a
result, greatly extends the standby time of the phone. System
operation has been proven to be fully compatible with
MSM51xx-based designs.
The ADP3502 comes in a 64-lead 7 mm × 7 mm × 1 mm
TQFP package and is specified over a wide temperature range of
–30°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
ADP3502–SPECIFICATIONS
(TA = –30؇C to +85؇C, CVBAT = 1 F MLCC, VBAT = 3.6 V, unless otherwise noted. See Table II for COUT.)
MAIN FUNCTIONS
Parameter
Symbol Conditions
Min
Typ Max
Unit
SHUTDOWN GND CURRENT
Power OFF
IGND
TA = –20°C to +60°C
25
45
µA
LDO3b: ON, Connect to RTCV
through Schottky Diode
RTC/32K OSC: Active
All Other LDOs: OFF
All Logic Inputs: VBAT or GND
MVBAT: OFF
OPERATING GND CURRENT
Standby Mode Operation (Light Load)
IGND
LDO1b, LDO2b, LDO3b,
LDO6b: ON
60
125
µA
IO = 1 mA for LDO3b and LDO6b
IO = 3 mA for LDO1b
I
O = 300 µA for LDO2b
All Other LDOs: OFF
RTC/32K OSC: Active
MVBAT: OFF
All Logic Output: No Load
LDO1, LDO2, LDO3, LDO6,
All Sub-LDOs: ON, IO = 70% Load
All Other LDOs: OFF
RTC/32K OSC: Active
MVBAT: ON
Standby Mode Operation (Midload)
300
700
µA
µA
All Logic Outputs: No Load
LDO5: OFF
Active Operation
All Other LDOs: ON, 70% Load
RTC/32K OSC: Active
All Logic Outputs: No Load
MVBAT: ON
THERMAL SHUTDOWN THRESHOLD
THERMAL SHUTDOWN HYSTERESIS
160
35
°C
°C
V
ADAPTER/ADPSUPPLY VOLTAGE RANGE VADP
VBAT VOLTAGE RANGE VBAT
5
12
3.3
5.5
V
LDO SPECIFICATIONS (TA = 25؇C, CVBAT = 1 F MLCC, VBAT = VOUT + 1 V, NRCAP = 0.1 F. See Table II for COUT.)
Parameter
Symbol Conditions
Min
Typ Max
Unit
BASEBAND VDD MAIN-LDO (LDO1a)
Output Voltage
VLDO1a
IO = 1 mA to 150 mA
TA = –30°C to +85°C
2.81
2.2
2.90 2.99
V
Output Capacitor Required for Stability
Dropout Voltage
Start-Up Time from Shutdown
CLDO1a
VDO
µF
mV
µs
IO = 150 mA
200
250
BASEBAND VDD SUB-LDO (LDO1b)
Output Voltage
VLDO1b
IO = 3 mA
2.8
2.87 3.0
V
TA = –30°C to +85°C
–2–
REV. 0
ADP3502
Parameter
Symbol
Conditions
Min
Typ Max
Unit
BASEBAND AVDD MAIN-LDO (LDO2a)
Output Voltage
VLDO2a
16 Steps, 20 mV/Step, IO = 50 mA
Code: 1000
2.30
2.60
2.36 2.43
2.66 2.74
V
V
Code: 0111
TA = 25°C
Output Default Voltage
Output Voltage
VLDO2a
VLDO2a
IO = 50 mA, TA = 25°C
16 Steps, 20 mV/Step, IO = 50 mA
Code: 1000
2.46
2.52 2.6
V
2.29
2.57
2.36 2.47
2.66 2.81
V
V
Code: 0111
TA = –30°C to +85°C
Output Default Voltage
Output Capacitor Required for Stability
Dropout Voltage
VLDO2a
CLDO2a
VDO
IO = 50 mA, TA = –30°C to +85°C
2.42
1
2.52 2.66
V
µF
mV
dB
IO = 50 mA
f = 1 kHz
210
60
Ripple Rejection
Output Noise Voltage
Start-Up Time from Shutdown
VNOISE
f = 100 Hz to 100 kHz
120
250
µV rms
µs
BASEBAND AVDD SUB-LDO (LDO2b)
Output Voltage
VLDO2b
IO = 300 µA, VLDO2MAIN = 2.6 V
TA = –30°C to +85°C
2.50
2.57 2.70
V
REFO SWITCH
On Resistance
Off Leak
RON
ILEAK
TA = –30°C to +85°C, IO = 500 µA
LDO2: ON, Switch: OFF
50
0.01
130
1
Ω
µA
COIN CELL MAIN-LDO (LDO3a)
Output Voltage
VLDO3a
IO = 1 mA to 50 mA
TA = –30°C to +85°C
IO = 50 mA
2.90
1
3.0
3.09
V
Dropout Voltage
Output Capacitor Required for Stability
Start-Up Time from Shutdown
VDO
CLDO3a
140
250
mV
µF
µs
COIN CELL SUB-LDO (LDO3b)
Output Voltage
VLDO3b
IO = 1 mA
TA = –30°C to +85°C
2.85
2.97 3.15
V
V
AUDIO LDO (LDO4)
Output Voltage
VLDO4
IO = 1 mA to 180 mA
TA = –30°C to +85°C
2.81
2.2
2.9
2.99
Output Capacitor Required for Stability
Dropout Voltage
Ripple Rejection
CLDO4
VDO
µF
mV
dB
IO = 180 mA
f = 1 kHz
200
60
Output Noise Voltage
Start-Up Time from Shutdown
VNOISE
f = 100 Hz to 10 kHz
50
250
µV rms
µs
VIBRATOR LDO (LDO5)
Output Voltage
VLDO5
IO = 1 mA to 150 mA
TA = –30°C to +85°C
IO = 150 mA
2.75
2.2
2.9
3.05
V
Dropout Voltage
Output Capacitor Required for Stability
VDO
CLDO5
200
mV
µF
BASEBAND CORE MAIN-LDO (LDO6a)
Output Voltage
VLDO6a
IO = 1 mA to 150 mA
TA = –30°C to +85°C
2.75
2.2
2.85 2.95
V
Output Capacitor Required for Stability
Dropout Voltage
Start-Up Time from Shutdown
CLDO6a
VDO
µF
mV
µs
IO = 150 mA
200
250
REV. 0
–3–
ADP3502
LDO SPECIFICATIONS (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
BASEBAND CORE SUB-LDO (LDO6b)
Output Voltage
VLDO6b
IO = 1 mA
TA = –30°C to +85°C
2.70
2.80
2.90
V
RF RX1 LDO (LDO7)
Output Voltage
VLDO7
IO = 1 mA to 100 mA
TA = –30°C to +85°C
2.81
1.5
2.9
2.99
2.99
2.99
2.99
1.58
V
Output Capacitor Required for Stability
Dropout Voltage
Ripple Rejection
Output Noise Voltage
Start-Up Time from Shutdown
CLDO7
VDO
µF
mV
dB
µV rms
µs
IO = 100 mA
f = 1 kHz
f = 100 Hz to 100 kHz
200
60
40
VNOISE
250
RF TX LDO (LDO8)
Output Voltage
VLDO8
IO = 1 mA to 150 mA
TA = –30°C to +85°C
2.81
2.2
2.9
V
Output Capacitor Required for Stability
Dropout Voltage
Ripple Rejection
Output Noise Voltage
Start-Up Time from Shutdown
CLDO8
VDO
µF
mV
dB
µV rms
µs
IO = 150 mA
f = 1 kHz
f = 100 Hz to 100 kHz
200
60
40
VNOISE
250
RF RX2 LDO (LDO9)
Output Voltage
VLDO9
IO = 1 mA to 50 mA
TA = –30°C to +85°C
2.81
1
2.9
V
Output Capacitor Required for Stability
Dropout Voltage
Ripple Rejection
Output Noise Voltage
Start-Up Time from Shutdown
CLDO9
VDO
µF
mV
dB
µV rms
µs
IO = 50 mA
f = 1 kHz
f = 100 Hz to 100 kHz
150
60
40
VNOISE
250
RF OPTIONAL LDO (LDO10)
Output Voltage
VLDO10
IO = 1 mA to 50 mA
TA = –30°C to +85°C
2.81
1
2.9
V
Output Capacitor Required for Stability
Dropout Voltage
Ripple Rejection
Output Noise Voltage
Start-Up Time from Shutdown
CLDO10
VDO
µF
mV
dB
µV rms
µs
IO = 50 mA
f = 1 kHz
f = 100 Hz to 100 kHz
150
60
40
VNOISE
250
OPTIONAL LDO (LDO11)
Output Voltage
VLDO11
CLDO11
VNOISE
IO = 1 mA to 100 mA
TA = –30°C to +85°C
1.42
2.2
1.5
V
Output Capacitor Required for Stability
Ripple Rejection
Output Noise Voltage
µF
dB
µV rms
µs
f = 1 kHz
f = 100 Hz to 100 kHz
60
50
250
Start-Up Time from Shutdown
VOLTAGE DETECTOR FOR LDO1
AND LDO6
LDO1 Detect Voltage
LDO1 Release Voltage
LDO1 Hysteresis
LDO6 Detect Voltage
LDO6 Release Voltage
LDO6 Hysteresis
VDET1
VDET1
VHYS1
VDET6
VDET6
VHYS6
TA = –30°C to +85°C
TA = –30°C to +85°C
TA = –30°C to +85°C
TA = –30°C to +85°C
TA = –30°C to +85°C
TA = –30°C to +85°C
2.7
2.72
2.77
52
2.58
2.67
90
V
V
mV
V
V
VLDO1–NOM
35
2.50
VLDO6–NOM
45
mV
–4–
REV. 0
ADP3502
(TA = –30؇C to +85؇C, CVBAT = 10 F MLCC, CADAPTER = 1 F MLCC, unless
otherwise noted.)
BATTERY VOLTAGE DIVIDER: MVBAT
Parameter
Symbol
Conditions
Min
Typ Max
Unit
MVBAT OUTPUT VOLTAGE
5-Bit Programmable
VBAT = 4.35 V, MVEN = 1
VMVBAT
TA = 25°C
Code: 10000
Code: 01111
2.459 2.508 2.538
2.648 2.697 2.732
V
V
MVBAT OUTPUT VOLTAGE
STEP
VSTEP
VBAT = 4.35 V, MVEN = 1
6
mV/LSB
OUTPUT DRIVE CURRENT
CAPABILITY
IOUT
1
2
mA
MVBAT LOAD REGULATION
ꢁMVBAT
0 < IOUT < 100 µA
3
5
mV
OPERATING BATTERY
CURRENT
VBAT = 4.35 V, MVEN = 1
78
97
µA
SHUTDOWN CURRENT
VBAT = 4.35 V, MVEN = 0
1
µA
(TA = –30؇C to +85؇C, CVBAT = 10 F MLCC, CADAPTER = 1 F MLCC, 4.0 V ꢀ ADAPTER ꢀ 12 V, unless
otherwise noted.)
BATTERY CHARGER
Parameter
Symbol
Conditions
Min
Typ Max
Unit
CHARGER CONTROL VOLTAGE
RANGE
VBAT
TA = 25°C
2-Bit Programmable
SENSE
VR_SENSE = 30 mV, CHI = 1
4.8 V ≤ ADAPTER ≤ 12 V
Code: 00 (Default)
Code: 01
3.440 3.500 3.560
4.175 4.205 4.235
4.195 4.225 4.255
4.215 4.245 4.275
V
V
V
V
Code: 10
Code: 11
CHARGER CONTROL VOLTAGE
RANGE1
VBAT
TA = –20°C to +55°C
2-Bit Programmable
SENSE
VR_SENSE = 160 mV, CHI = 1
4.8 V ≤ ADAPTER ≤ 12 V (Note 1)
Code: 00 (Default)
Code: 01
3.440 3.500 3.560
4.155 4.205 4.255
4.175 4.225 4.275
4.195 4.245 4.295
V
V
V
V
Code: 10
Code: 11
CHARGER VOLTAGE
+25°C to +55°C or +25°C to –20°C
VR_SENSE = 30 mV, Constant Adapter
Voltage between 4.8 V and 12 V
–20
+20
mV
TEMPERATURE DRIFT1
CHARGER DETECT ON
THRESHOLD
ADAPTER-VBAT
ADAPTER-VBAT
110
0
165
25
225
60
2
mV
mV
mA
CHARGER DETECT OFF
THRESHOLD
CHARGER SUPPLY CURRENT
IADAPTER
ADAPTER = 5 V, VBAT = 4.3 V
CURRENT LIMIT THRESHOLD
High Current Limit
(Full Charge Current Enabled)
Low Current Limit
ADAPTER-VISNS
ADAPTER = 5 V
VBAT = 3.6 V
170
40
210
60
255
75
mV
mV
VBAT = 3.0 V
(Full Charge Current Disabled)
PRECHARGE CURRENT SOURCE
BASE PIN DRIVE CURRENT
VBAT ≤ DDLO
3
5
7
mA
mA
V
20
35
DEEP DISCHARGE LOCK-OUT
(Releasing Voltage)
DDLO
VBAT< DDLO, TA = 25°C,
(5 mA Precharge), VBAT Ramping Up
2.650 2.80
DEEP DISCHARGE LOCK-OUT
HYSTERESIS2
100
200
1
mV
ISENSE BIAS CURRENT
IISNS
VISNS = 5 V
µA
REV. 0
–5–
ADP3502
BATTERY CHARGER (continued)
Parameter
Symbol
CHG – ILKG
Conditions
Min
Typ Max
Unit
CHARGE TRANSISTOR REVERSE
LEAKAGE CURRENT3
I
No Adapter Present
1
µA
MINIMUM LOAD FOR STABILITY1 IL
CBAT = 10 µF MLCC, No Battery
10
mA
NOTES
1Guaranteed but not tested.
2DDLO hysteresis is dependent on DDLO threshold value. If DDLO threshold is at maximum, DDLO hysteresis is at maximum at the same time.
3This includes the total reverse current from battery to BVS, BASE, ISENSE, and ADAPTER pins with no adapter present. No signal path between ADAPTER pin
and ADPSUPPLY pin.
Specifications subject to change without notice.
LOGIC
DC SPECIFICATIONS
(TA = 25؇C, CVBAT = 1 F MLCC, VBAT = 3.6 V, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CS, CLKIN, RESETIN–,
TCXOON, SLEEP–
Input Current H/L
Input High Voltage
Input Low Voltage
Hysteresis
IIL/IIH
VIH
VIL
VIN = VLDO1 or 0 V
–1
2.25
+1
µA
V
V
0.5
520
470
260
mV
KEYPADROW
(Internal 20 kΩ Pull-Up)
Input High Voltage
Input Low Voltage
Hysteresis
VIH
VIL
2.25
V
V
mV
0.5
GPIO, DATA
Input Current H/L
Input High Voltage
Input Low Voltage
Hysteresis
Output High Voltage
Output Low Voltage
IIL/IIH
VIH
VIL
VIN = VLDO1 or 0 V
–1
2.25
+1
µA
V
V
mV
V
V
0.5
VOH
VOL
IOH = 400 µA
IOL = –1.8 mA
2.69
2.69
0.28
INT–
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = 400 µA
IOL = –1.8 mA
V
V
0.28
0.4
BLIGHT (Open-Drain Output)
Output Low Voltage
VOL
IOL = –100 mA
IOL = –1.8 mA
V
V
KEYPADCOL
(Open-Drain Output)
Output Low Voltage
VOL
0.15
PWRONKEY–, OPT1
(Internal 140 kΩ Pull-Up)
Input High Voltage
Input Low Voltage
Hysteresis
VIH
VIL
VHYS
0.8 ꢂ VBAT
0.8 ꢂ VBAT
V
V
mV
0.2 ꢂ VBAT
950
950
OPT2– (Input/Open-Drain Output)
Input Current H
Input High Voltage
Input Low Voltage
Hysteresis
IIH
VIH
VIL
VHYS
VOL
VIN = VBAT
1
µA
V
V
mV
V
0.2 ꢂ VBAT
0.1 ꢂ VBAT
IOL = –1.8 mA
Output Low Voltage
–6–
REV. 0
ADP3502
LOGIC (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OPT3
Input Current H/L
Input High Voltage
Input Low Voltage
Hysteresis
IIL/IIH
VIH
VIL
VIN = VBAT or 0 V
–1
+1
µA
0.7 ꢂ VBAT
V
0.2 ꢂ VBAT
V
mV
VHYS
300
32K OUT
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = 400 mA
IOL = –1.8 mA
0.9 ꢂ RTCV
V
V
0.1 ꢂ RTCV
RESET+ (Open-Drain Output)
Output Low Voltage
OFF Leak
VOL
OFFLEAK
IOL = –1.8 mA
0.28
1
V
µA
0.005
1
RSTDELAY–, RESETOUT–
(Open-Drain Output)
Output Low Voltage
VOL
IOSC
IOL = –1.8 mA
0.28
V
SUPPLY CURRENT OR RTCV
RTCV = 3 V,
VBAT = 2 V
µA
All Logic: No Load
AC SPECIFICATIONS
(All specifications include temperature, unless otherwise noted.)
Parameter
Symbol
RTCV
Conditions
Min
Typ
Max
Unit
V
OPERATIONAL SUPPLY RANGE
OSCILLATOR FREQUENCY
START-UP TIME
2
3.1
FCLK
32.768
kHz
ms
tSTART
RTCV = 0 V to 3 V
100
200
FREQUENCY JITTER
Cycle to Cycle
>100 Cycles
fJITTER/SEC
RTCV = 3 V, TA = 25°C
40
50
ns
ns
FREQUENCY DEVIATION
RTCV = 3 V, 3 Minutes
1000
ppm
SERIAL INTERFACE
Parameter
Min
Typ
Max
Unit
Test Condition/Comments
tCKS
tCSS
tCKH
tCKL
tCSH
tCSR
tDS
tDH
tRD
tRZ
tCSZ
50
50
100
100
100
62
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
CLK Setup Time
CS Setup Time
CLK High Duration
CLK Low Duration
CS Hold Time
CS Recovery Time
Input Data Setup Time
Input Data Hold Time
Data Output Delay Time
Data Output Floating Time
50
40
50
50
50
Data Output Floating Time after CS Goes Low
REV. 0
–7–
ADP3502
ABSOLUTE MAXIMUM RATINGS*
Voltage on ADAPTER, ADPSUPPLY Pin
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C
ꢃJA Thermal Impedance (TQFP-64)
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 15 V
Voltage on VBAT Pin to GND . . . . . . . . . . . . –0.3 V, +6.5 V
Voltage on Pins 6–13, 21–28
to GND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VLDO1 + 0.3 V
Voltage on Pins 1, 62–64 . . . . . . . . . . . –0.3 V, VBAT + 0.3 V
Voltage on Pins 20, 32 . . . . . . . . . . . . . –0.3 V, VRTCV + 0.3 V
Voltage on Pin 60 . . . . . . . . . . . . . . –0.3 V, VADAPTER + 0.3 V
Voltage on Pins 2–5, 14, 30, 31, 33 . . . . . . . . . –0.3 V, +6.5 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . –30°C to +85°C
(2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . .87.4°C/W
ꢃJA Thermal Impedance (TQFP-64)
(4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . 56.2°C/W
Lead Temperature Range
(Soldering, 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified all
other voltages are referenced to GND.
ORDERING GUIDE
Model
Temperature Range
Package
ADP3502ASU
–30°C to +85°C
64-Lead TQFP
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3502 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–8–
REV. 0
ADP3502
PIN CONFIGURATION
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OPT3
KEYPADCOL0
KEYPADCOL1
KEYPADCOL2
KEYPADCOL3
KEYPADROW0
KEYPADROW1
KEYPADROW2
KEYPADROW3
KEYPADROW4
KEYPADROW5
TCXOON
VBAT
LDO7 (REF Rx1)
LDO6 (BASEBAND CORE)
VBAT
3
4
5
LDO5 (VIBRATOR)
LDO4 (AUDIO)
VBAT
6
7
ADP3502
8
LDO2 (BASEBAND AVDD)
REFO
TOP VIEW
9
(Not to Scale)
10
11
12
13
14
15
16
AGND
LDO3 (RTC/COIN-CELL)
VBAT
SLEEP–
LDO1 (BASEBAND VDD)
LDO11 (OPTION)
VBAT
BLIGHT
DGND
INT–
RSTDELAY–
PIN FUNCTION DESCRIPTION
Pin
No. Mnemonic
I/O Supply Function
1
2
OPT3
I
VBAT
LDO1
LDO1
LDO1
LDO1
LDO1
LDO1
LDO1
LDO1
LDO1
LDO1
LDO1
Optional Power ON Input. ADP3502 will keep power ON when this pin goes high.
Keypad Column Strobe 0 (Open-Drain, Pull Low)
Keypad Column Strobe 1 (Open-Drain, Pull Low)
Keypad Column Strobe 2 (Open-Drain, Pull Low)
Keypad Column Strobe 3 (Open-Drain, Pull Low)
Keypad Row Input 0. Pulled up internally, 20 kΩ.
Keypad Row Input 1. Pulled up internally, 20 kΩ.
Keypad Row Input 2. Pulled up internally, 20 kΩ.
Keypad Row Input 3. Pulled up internally, 20 kΩ.
Keypad Row Input 4. Pulled up internally, 20 kΩ.
Keypad Row Input 5. Pulled up internally, 20 kΩ.
KEYPADCOL0
KEYPADCOL1
KEYPADCOL2
KEYPADCOL3
KEYPADROW0
KEYPADROW1
KEYPADROW2
KEYPADROW3
KEYPADROW4
KEYPADROW5
TCXOON
O
O
O
O
I
3
4
5
6
7
I
8
I
9
I
10
11
12
I
I
I
Logic Input Pin for Main LDOs (LDO1, LDO2, LDO3, LDO6) Turning On Control.
L: OFF, H: ON.
13
SLEEP–
I
LDO1
Logic Input Pin for LDO7 and LDO9. This input gates register data for these LDOs.
LDO7 and LDO9 are turned OFF when SLEEP goes low even if the registers are set
to ON. If register of SLEEP7 and SLEEP9 are set to “1,” the SLEEP signal is ignored.
14
15
16
BLIGHT
DGND
INT–
O
O
VBAT
LDO1
LED Drive. Open-drain output.
Digital Ground
Interrupt Signal Output
REV. 0
–9–
ADP3502
PIN FUNCTION DESCRIPTION (continued)
Pin
No. Mnemonic
I/O Supply Function
17
RTCV
Supply input for RTC, 32 kHz OSC, and other logic. Connects to coin cell battery in
typical operation.
18
19
20
21
OSC IN
AGND
RTCV
Connect to 32.768 kHz crystal
Analog Ground
OSC OUT
GPIO0
RTCV
LDO1
Connect to 32.768 kHz crystal
I/O
I/O
I/O
I/O
General-purpose input and output port. Integrated interrupt function. Interrupt occurs
on both the falling and rising edges.
22
23
24
GPIO1
GPIO2
GPIO3
LDO1
LDO1
LDO1
General-purpose input and output port. Integrated interrupt function. Interrupt occurs
on both the falling and rising edges.
General-purpose input and output port. Integrated interrupt function. Interrupt occurs
on both the falling and rising edges.
General-purpose input and output port. Integrated interrupt function. Interrupt occurs
on both the falling and rising edges.
25
26
27
28
29
30
31
32
33
DATA
I/O
I
LDO1
LDO1
LDO1
LDO1
RTCV
RTCV
RTCV
RTCV
RTCV
Serial interface data input and output
CS
Serial interface chip select input. Active high input.
Serial interface clock input
CLKIN
I
RESETIN–
32K OUT
RESET+
RESETOUT–
TEST
I
Reset input signal for internal reset signal; Starts stay-alive timer.
32.768 kHz output. Output after 30 ms when reset is released.
Reset output. Invert signal of RESETOUT–. Open-drain and low leakage.
Reset output. Follows voltage detector operation. Open-drain output.
Test pin. Reserved for ADI use. Connect to GND for normal operation.
O
O
O
I
RSTDELAY–
O
Reset output. 50 ms delayed. Connect to baseband’s reset input in typical application.
Open-drain output.
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
VBAT
LDO11
LDO1
VBAT
LDO3
AGND
REFO
LDO2
VBAT
LDO4
LDO5
VBAT
LDO6
LDO7
VBAT
LDO8
AGND
LDO9
VBAT
LDO10
Supply input. Connect to battery.
O
O
VBAT
VBAT
Regulator No. 11 output. General-purpose supply.
Regulator No. 1 output. Use for baseband I/O supply.
Supply input. Connect to battery.
O
VBAT
Regulator No. 3 output. If VBAT > 2.7 V, the output is always active. Use for coin cell supply.
Analog ground
O
O
VBAT
VBAT
Output of LDO2 through FET switch
Regulator No. 2 output. Use for baseband analog supply.
Supply input. Connect to battery.
O
O
VBAT
VBAT
Regulator No. 4 output. Use for general analog supplies, for example, speaker amp.
Regulator No. 5 output. Use for vibrator.
Supply input. Connect to battery.
O
O
VBAT
VBAT
Regulator No. 6 output. Use for baseband core supply.
Regulator No. 7 output. Use for RF Rx IC supply. Gated with SLEEP– signal input.
Supply input. Connect to battery.
O
O
O
VBAT
VBAT
VBAT
Regulator No. 8 output. Use for RF Tx IC supply.
Analog Ground
Regulator No. 9 output. Use for RF Rx IC supply. Gated with SLEEP– input signal.
Supply input. Connect to battery.
Regulator No. 10 output. General-purpose supply.
–10–
REV. 0
ADP3502
PIN FUNCTION DESCRIPTION (continued)
Function
Pin
No. Mnemonic
I/O Supply
54
BVS
Battery voltage sense input for charger. Connect to battery with a separate low current
trace
55
56
57
58
59
60
61
62
63
64
NRCAP
O
VBAT
Noise reduction capacitor, 0.1 µF MLCC
AGND
Analog Ground
MVBAT
BASE
O
O
VBAT
Battery voltage divider output. Buffered internally. Connect to baseband ADC.
Base drive output for PNP pass transistor
ADAPTER
ADAPTER
ADPSUPPLY
ISENSE
AC Adapter Input
I
I
I
I
ADAPTER
ADAPTER
VBAT
Supply bias current to charging related blocks
Charge current sense input
PWRONKEY–
OPT1–
Power ON/OFF key input. Pulled up internally with 140 kΩ.
Optional power ON input. ADP3502 will keep power on when this pin goes low.
VBAT
OPT2–
I/O VBAT
Optional power ON input. ADP3502 will keep power on when this pin goes low.
While the part is powered up, the input is pulled low (GND) internally. Do not con-
nect to any supply or signal source.
REV. 0
–11–
ADP3502
AGND
VBAT
ADAPTER ISENSE BASE BVS
61
48 45
37 34
56
50
39 19
52
42
59
58
54
VBAT
CHARGER_DETECT
CHARGER CONTROL
60
57
ADPSUPPLY
BATOV
140k⍀
BATTERY CHARGER
MVBAT (VBAT MEASURE)
POWERON N
OPT1_N
OPT2_N
OPT3
62
63
64
1
PWRONKEY–
OPT1–
DDLO
LDO_EN
POWER ON
BATID
40
REFO
DDLO CONTROL
SIGNALS
REF
LPF
OPT2–
REF
OPT3
RTC
ALARM
55
NRCAP
LDO1
MAIN
VOLTAGE_DETECT
PWROFF
36 LDO1 (BASEBAND VDD)
41 LDO2 (BASEBAND AVDD)
ON/OFF
LDO1
LDO2
LDO3
LDO6
LDO4
LDO5
LDO7
LDO8
SUB
LOGIC
DELAY
10ms
MAIN
SYNC
CLK
ON/OFF
LOGIC
CLK
SUB
5
MAIN
ON/OFF
LOGIC
DATA
IN
38 LDO2 (RTC/COIN-CELL)
46 LDO6 (BASEBAND CORE)
BATOV
MAIN
SUB
INT_IN
ON/OFF
LOGIC
LEVEL
TRANS
16
INT–
5
43 LDO4 (AUDIO)
LDO1
2
3
4
5
KEYPADCOL0
KEYPADCOL1
44 LDO5 (VIBRATOR)
47 LDO7 (RF Rx1)
49 LDO8 (RF Tx)
LEVEL
TRANS
INT
KEYPADCOL2
KEYPADCOL3
LDO7
SLEEP7
4
KEYPAD
I/F
6
7
KEYPADROW0
KEYPADROW1
6
LDO9
SLEEP9
51 LDO9 (RF Rx2)
53 LDO10 (RF OPTION)
35 LDO11 (OPTION)
8
KEYPADROW2
LDO9
LDO10
LEVEL
TRANS
9
KEYPADROW3
KEYPADROW4
10
11
GPIO INT/GPI INTRST
–LDO1
KEYPADROW5
LDO11
BLIGHT 14
15
DGND
VOLTAGE
DETECTOR
26
27
CS
SERIAL
I/F
DATA
CLKIN
13 SLEEP–
12 TCXOON
LEVEL
TRANS
DATA 25
LEVEL
TRANS
21
GPIO0
GPIO
+
INT
GPIO1
GPIO2
22
23
DATA
CLKs
28 RESETIN–
LEVEL
LDO1
LDO1
RTCV
TRANSLATOR
VBAT
GPIO3 24
DGND
AND
RTCV
LEVELTRANSLATOR
RTCV
17 RTCV
OSC IN
18
20
DGND
32kHz
OSC OUT
29
32K OUT
DELAY
30ms
32 TEST
OPEN DRAIN
RTC
/CLOCK
DELAY
50ms
CLKs
DATA
33 RSTDELAY–
31 RESETOUT–
30 RESET+
STAY/ALIVE
TIMER
0.25SEC–8SEC
DATA
RESETIN N
Figure 1. Overall Block Diagram
–12–
REV. 0
Typical Performance Characteristics–
ADP3502
2.928
2.926
2.924
2.922
2.920
2.918
2.916
2.914
2.872
2.870
2.868
2.866
2.864
2.862
2.860
2.858
2.856
2.854
2.914
2.912
2.910
2.908
2.906
2.904
2.902
2.900
2.898
2.896
2.894
2.892
VBAT = 4V
VBAT = 4V
VBAT = 4V
10 20 40 60 80 100 120 140 160 180
OUTPUT CURRENT – mA
10 20 40 60 80 100 120 140 160 180
OUTPUT CURRENT – mA
10 20 40 60 80 100 120 140 160 180
OUTPUT CURRENT – mA
TPC 1. LDO1 Load Regulation
TPC 2. LDO4 Load Regulation
TPC 3. LDO6 Load Regulation
2.928
2.916
2.908
I
= 1mA
LOAD
I
= 1mA
LOAD
VBAT = 4V
2.926
2.924
2.922
2.920
2.918
2.916
2.914
2.912
2.906
2.914
2.912
2.910
2.908
2.906
2.904
2.904
2.902
2.900
2.898
2.896
2.894
2.892
4.0
4.5
5.0
5.5
6.0
6.5
7.0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
10 20 40 60 80 100 120 140 160 180
SUPPLY INPUT FOR LDOs –V
SUPPLY INPUT FOR LDOs –V
OUTPUT CURRENT – mA
TPC 5. LDO1 Line Regulation
TPC 6. LDO4 Line Regulation
TPC 4. LDO8 Load Regulation
2.908
200
180
160
140
120
100
80
2.876
I
= 1mA
LOAD
I
= 1mA
LOAD
2.906
2.904
2.902
2.900
2.898
2.896
2.894
2.874
2.872
2.870
2.868
2.866
2.864
2.862
60
40
20
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0
25
50
75
100
125
150
4.0
4.5
5.0
5.5
6.0
6.5
7.0
SUPPLY INPUT FOR LDOs –V
OUTPUT CURRENT – mA
SUPPLY INPUT FOR LDOs –V
TPC 8. LDO8 Line Regulation
TPC 9. LDO1 Dropout Voltage
TPC 7. LDO6 Line Regulation
REV. 0
–13–
ADP3502
200
180
160
140
120
100
80
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
60
60
40
40
40
20
20
20
0
0
0
0
30
60
90
120
150
180
0
25
50
75
100
125
150
0
25
50
75
100
125
150
OUTPUT CURRENT – mA
OUTPUT CURRENT – mA
OUTPUT CURRENT – mA
TPC 10. LDO4 Dropout Voltage
TPC 11. LDO6 Dropout Voltage
TPC 12. LDO8 Dropout Voltage
4.24
4.22
4.20
CODE 01
4.211
R
= 0.2⍀
SENSE
2.91V
4.210
4.209
4.208
4.207
4.206
2.9V
V
R
= 5.5V
ADAPTER
= 0.2⍀
4.18
4.16
4.14
4.12
4.10
2.89V
SENSE
I
C
= 180mA
= 2.2F
LOAD
OUT
5V
4V
LINETRANSIENT RESPONSE
TIME BASE: 100s/DIV
0
100 200 300 400 500 600 700 800 900
CHARGING CURRENT – mA
ADAPTERVOLTAGE –V
TPC 14. Charger Line Regulation
TPC 13. Charger Load Regulation
TPC 15. LDO4 Line Transient
I
C
= 150mA
= 2.2F
VBAT = 4V
VBAT = 4V
LOAD
OUT
C
= 2.2F
C
= 2.2F
OUT
OUT
2.86V
2.85V
2.85V
2.9V
2.885V
2.836V
2.84V
180mA
20mA
150mA
20mA
5V
4V
LINETRANSIENT RESPONSE
TIME BASE: 100s/DIV
LOADTRANSIENT RESPONSE
TIME BASE: 100s/DIV
LOADTRANSIENT RESPONSE
TIME BASE: 100s/DIV
TPC 17. LDO6 Line Transient
TPC 16. LDO4 Load Transient
TPC 18. LDO6 Load Transient
–14–
REV. 0
ADP3502
40
35
30
25
20
15
10
5
I
C
= 150mA
= 2.2F
VBAT = 4V
C = 2.2F
OUT
LOAD
OUT
LDO 1
LDO 4
LDO 8
2.91V
2.9V
2.9V
2.886V
2.89V
150mA
20mA
5V
4V
LINETRANSIENT RESPONSE
TIME BASE: 100s/DIV
LOADTRANSIENT RESPONSE
TIME BASE: 100s/DIV
0
0
10
20
30
40
50
OUTPUT CAPACITOR – F
TPC 19. LDO8 Line Transient
TPC 20. LDO8 Load Transient
TPC 21. RMS Noise vs. COUT
0
0
0
C
= 2.2F
= 180mA
C = 2.2F
OUT
C
= 2.2F
= 150mA
OUT
OUT
–10
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
I = 150mA
I
I
LOAD
LOAD
LOAD
VBAT = 4V
VBAT = 4V
VBAT = 4V
–20
–30
–40
–50
–60
–70
–80
–90
–100
50 100
1k
10k
100k
1M
10M
50 100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
50 100
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
TPC 22. LDO1 PSRR
TPC 23. LDO4 PSRR
TPC 24. LDO8 PSRR
800
66
ACTIVE MODE
700
600
500
400
300
200
64
62
60
58
56
54
LIGHT LOAD STANDBY MODE
MIDLOAD STANDBY MODE
–30–20–10
0
10 20 30 40 50 60 70 80
–30–20–10
0
10 20 30 40 50 60 70 80
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 25. IGND vs. Temperature
TPC 26. IGND vs. Temperature
REV. 0
–15–
ADP3502
THEORY OF OPERATION
ANALOG BLOCKS
As illustrated in the Functional Block Diagram, the ADP3502
can be divided into two high level blocks—analog and logic.
The analog block consists mainly of LDO regulators, a battery
charger, reference voltage, and voltage detector subblocks, all of
which are powered by the main battery or the charging adapter.
On the other hand, VBAT powers all the logic subblocks
except the RTC counter, 32 kHz output control, RESET
output, and stay-alive timer. The RTCV pin powers these
subblocks (see the shaded area of Figure 2).
Low Drop-Out (LDO) Regulators
There are four sub-LDOs for LDO1, LDO2, LDO3, and LDO6,
in order to meet low power consumption at light load (standby
operation). They are used at low load condition, but they are
continuously on even if each of the main LDOs are on. LDO3 and
LDO3b are used for the coin cell, and LDO3b is always on until
the main battery (VBAT) is decreased to 2.5 V, the DDLO
threshold. LDO7 and LDO9 are gated by a control signal
from SLEEP or register setting of SLEEP7/SLEEP9. LDO4 and
LDO11 are initially on. For details of LDO on/off control, refer
to the LDO Control section.
[VBAT]
5
4
3
2
1
POWER ON
KEYPAD I/F
GPIO
6
7
DELAY 10ms
INTERRUPT
CONTROL
SERIAL I/F
ANALOG
BLOCK
8
LDO CONTROL
RESET
[RTCV]-RTC BLOCK
32K OUTPUT
CONTROL
9
RTC COUNTER
10
RESET OUTPUT
11
STAY-ALIVETIMER
Figure 2. Power Partitioning of Subblocks
Table I. Ground Currents of LDOs with Each Handset Operation
Total
LDO
IGND
Baseband Baseband Coin
Baseband RF
RF
Tx
RF
Rx2
RF
Main
LDO Names
LDO Number
Power OFF
VDD
Core
Cell
Audio Vibrator AVDD
Rx1
Option Option REF
1
6
3
4
5
2
7
8
9
10
11
OFF
OFF
5 µA
55 µA
55 µA
55 µA
55 µA
10 µA
10 µA
60 µA
60 µA
60 µA
60 µA
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
5 µA
55 µA
55 µA
55 µA
55 µA
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
20 µA
20 µA
20 µA
20 µA
20 µA
20 µA
30 µA
Light Load 10 µA
Midload 60 µA
50 µA
Standby
Mode
250 µA
570 µA
675 µA
744 µA
Active Load 60 µA
60 µA
80 µA 80 µA 80 µA 80 µA OFF
80 µA 80 µA 80 µA 80 µA 80 µA
80 µA 80 µA 80 µA 80 µA 80 µA
Talk
Ring
55 µA OFF
60 µA
55 µA 69 mA
–16–
REV. 0
ADP3502
Table II. LDO Operation Overview
Current
Rating (mA)
Voltage (Typ)
or Range (V)
Program
Steps
Step
Size (mV)
Regulator
Names
Default
COUT (F)
LDO1a
LDO1b
LDO2a
LDO2b
LDO3a
LDO3b
LDO4
Baseband VDD
Baseband VDD Sub
Baseband AVDD
Baseband AVDD Sub
RTC/Coin Cell
RTC/Coin Cell Sub
Audio
150
3
50
0.3
50
1
180
150
150
1
100
150
50
2.90
2.87
2.36 ~ 2.66
2.33 ~ 2.63
3.0
2.97
2.9
2.9
2.85
2.80
2.9
2.9
2.9
N/A
N/A
16
N/A
N/A
20
2.2
2.2
1
1
1
2.52 V
2.49 V
16
20
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
2.2
2.2
2.2
2.2
1.5
2.2
1
LDO5
Vibrator
LDO6a
LDO6b
LDO7
LDO8
LDO9
Baseband Core
Baseband Core Sub
RF Rx1
RF Tx
RF Rx2
LDO10
LDO11
RF Option
Option
50
100
2.9
1.5
1
2.2
C
VBAT
R
SENSE
AC ADAPTER
C
ADAPTER
ISENSE
BASE
BVS
ADAPTER
Li-ION
BATTERY
5mA
PRECHARGE
+
1k⍀
V(ISENSE)
–
g
g
m
m
EN
EN
ADPSUPPLY
MVBAT
DDLO
MVBAT
EN
EN
REF
BVS
V
BIAS
CHARGER DETECT
CHI LDO EN CHEN
CHV MVEN
0/1
MV4:0
Figure 3. Battery Charger Block Diagram
REV. 0
–17–
ADP3502
BATTERY CHARGER START
N
V
> VBAT
Y
ADAPTER
?
SET CHARGER DETECT FLAG
PRECHARGE 5mA
N
VBAT > DDLO
?
Y
LDO3b: ON
SET LOW CURRENT CHARGE
I
= 275mA
DETERMINED BY EXTERNAL
SENSE RESISTOR.
ADAPTER
(55mV ON R
)
SENSE
PRECHARGE: OFF
LDO1, LDO1b, LDO2, LDO2b,
LDO3, LDO6, LDO6b
VOLTAGE DETECTOR
ALL ENABLED
VOLTAGE DETECTOR
VLDO6 > 2.67V
AND
N
VLDO1 > 2.77V
?
Y
A
Figure 4. Charger Flow Chart A
–18–
REV. 0
ADP3502
A
RESET SEQUENCE RUNS
BASEBAND SETS CHARGEVOLTAGE
BASEBAND SETS MVBAT GAIN
BASEBAND ENABLES
FULL CHARGE CURRENT?
(CHI = 1?)
CHI = 0: FULL CURRENT CHARGE OFF
CHI = 1: FULL CURRENT CHARGE ON
N
Y
LOW CURRENT CHARGE: OFF
SET FULL CURRENT CHARGE
I
= 850mA MIN.
ADAPTER
(170mV MIN. ON R
)
SENSE
N
BASEBAND
CHEN = 0?
Y
CHARGINGTERMINATED
Figure 5. Charger Flow Chart B
REV. 0
–19–
ADP3502
Adapter Connection
Reference
There are two adapter connections on the ADP3502, Pins
ADAPTER and ADPSUPPLY. The ADPSUPPLY pin only
provides bias current to the charger detect comparator and
precharge block. With a diode placed on the adapter side of the
PNP transistor, as shown in Figure 3, the reverse battery current
will be blocked.
The ADP3502 has an internal temperature compensated and
trimmed band gap reference. The battery charger and LDOs all
use this system reference. This reference is not available for use
externally. However, to reduce thermal noise in the LDOs, the
reference voltage is brought out to the NRCAP pin through a
50 kΩ internal resistor. A cap on the NRCAP pin will complete
a low-pass filter that will reduce the noise on the reference volt-
age. All the LDOs, with the exception of LDO3, use the filtered
reference.
Charger Detect Function
The ADP3502 will detect that a charging adapter has been applied
when the voltage at the ADAPTER pin exceeds the voltage at
BVS. The ADAPTER pin voltage must exceed the BVS voltage
by a small positive offset. This offset has hysteresis to prevent
jitter at the detection threshold. The charger detection comparator
will set the charger detect flag in the 20h register and generate
an interrupt to the system. If the ADAPTER input voltage drops
below the detection threshold, charging will stop automatically,
and the charger detect flag will be cleared and generate an
interrupt also.
Since the reference voltage appears at NRCAP through a 50 kΩ
series internal impedance, it is very important to never place any
load current on this pin. Even a voltmeter with 10 MΩ input
impedance will affect the resulting reference voltage by about
6 mV or 7 mV, affecting the accuracy of the LDOs and charger.
If for some reason the reference must be measured, be certain to
use a high impedance range on the voltmeter or a discrete high
impedance buffer prior to the measurement system.
DDLO Function and Operation
LOGIC BLOCKS
ADP3502 includes the following functions:
The ADP3502 contains a comparator that will lock out system
operation if the battery voltage drops to the point of deep dis-
charge. When the battery voltage exceeds 2.675 V, the reference
will start as will the sub-LDO3b. If the battery voltage drops
below the hysteresis level, the reference and LDOs will be shut
down if for some reason they are still active. Since LDO1 will be in
deep drop-out and well below the voltage detector threshold at this
point, the reset generator will have already shut down the rest of
the system via RESET+, RESETOUT–, and RSTDELAY–.
• 3-wire serial interface (CS, CLK, DATA)
• RTC counter section has year, month, day, week, hour,
minute, and second and controls leap year and days in month
automatically.
• Detect alarms based on RTC counter
• Periodically constant interrupt feature (2 Hz, 1 Hz, 1/60 Hz,
1/3600 Hz, once a month)
• GPIO and INT ports control
If a charging adapter has been applied to the system, the DDLO
comparator will force the charging current to trickle charge if
the battery is below the DDLO threshold. During this time, the
charging current is limited to 5 mA. When the battery voltage
exceeds the upper threshold, the low current charging is enabled,
which allows 55 mV (typical) across the external charge current
sense resistor (see Figure 4).
• Keypad interface
• LED light control
• LDO functions
• Clock and reset output control
• Stay-alive timer
Figure 6 is a block diagram based on the logic circuit.
MVBAT
The ADP3502 provides a scaled buffered output voltage for use
in reading the battery voltage with an A/D converter. The bat-
tery voltage is divided down to be nominally 2.600 V at the
full-scale battery of 4.35 V. To assist with calibrating out system
errors in the ADP3502 and the external A/D converter, this full-
scale voltage may be trimmed digitally with five bits stored in
register 12h. At full-scale input voltage, the output voltage of
MVBAT can be scaled in 6 mV steps, allowing a very fine cali-
bration of the battery voltage measurement. The MVBAT buffer is
enabled by the MVEN bit of register 11h and will consume less
than 1 µA of leakage current when disabled.
–20–
REV. 0
ADP3502
[VBAT]
VOLTAGE DETECT
DELAY
10ms
VOLTAGE DETECT DELAY
CHARGER DETECT
SYNC
POWER ON
PWRONKEY N
OPT1 N
INTERRUPT
REGISTER
BLOCK
OPT2 N
OPT3
POWER
OFF
PWRONKEY N SYNC
OPT1 N SYNC
OPT3 SYNC
BATOV
SYNC
DATA
IN
ANALOG BLOCK
LED CONTROL
KEYPAD
I/F
BLIGHT
DGND
BL
INT
CONTROL
REGISTER
(RESET
AND
KEYPAD INT
KEYPADCOL[3:0]
KEYPADROW[5:0]
KEYPAD
I/F
MASK)
GPIO
CONTROL
GPIO [3:0]
GPIO
INT N
TCXOON
SLEEP N
LDO CONTROL REGISTER
WRITE ENABLE
CS
CLKIN
DATA
WRITE DATA [7:0]
ANALOG
BLOCKS
ANALOG
CONTROL
REGISTERS
SERIAL
I/F
SP ADDR [4:0]
DATA
SELECT
RESETIN N
RESETIN N
LDO
CONTROL
(RESET FOR REGISTERS)
RTC RESETIN N
RTC CLK32K
32K OSC
OSC OUT
OSC IN
CLK32K
32K CLK
32K OUT
OUTPUT
OUTPUT DATA
SELECT
CLK512
CONTROL
RTC
ADDRESS
DECODE
TEST MODE
REGISTER
BLOCK
CLK1K
STAY-ALIVE
TIMER
RTC
TEST IDOENABLE
REGISTER
BLOCK
RTC TEST
TEST MODE
TEST
RTC VOLTAGE DETECT
RTCVOLTAGE DETECT
RESETOUT N
RSTDELAY N
RESET
RESET OUTPUT
CONTROL
[RTCV]
Figure 6. LOGIC Block Diagram
–21–
REV. 0
ADP3502
RESET
RESETIN– Signal
The internal reset function is activated by the external reset input,
RESETIN–, and is an asynchronous signal. The internal reset
signal is used in the following blocks:
cause the system to have an unexpected result. Take care to avoid
this situation. RESETIN– is level translated from LDO1 to both
VBAT and RTCV supplies.
RESET Output Control and 32 kHz Output Control
Using a voltage detect signal, the device generates 32K OUT,
RSTDELAY–, RESETOUT–, and RESET signals. About 32 ms
after the RTC Voltage Detect (voltage detect signal in RTCV
supply) signal goes from “0” to “1,” the 32K OUT signal is
generated from the internal RTC_CLK32K signal. RSTDELAY
N (RSTDELAY–) goes to “0” when the RTC Voltage Detect is
“0,” and it goes to “1” at 50 ms after the “0” to “1” transition of
the RTC Voltage Detect. RESETOUT N (RESETOUT–) and
RESET toggle their states. Signal CLK512 is a 512 Hz, which
is generated in USEC counter block.
• Serial I/F
• Interrupt control
• Stay-alive timer
• Registers (refer to the Register section for additional
information).
LDOs, controlled by Serial I/F, are applied “RESET” by
RESETIN–. LDO5, LDO7, LDO8, LDO9, LDO10, and REFO
are set to “0,” and LDO4 and LDO11 are set to “1.” In case
RESETIN– has noise, the internal circuit may be in reset and
SERIAL INTERFACE
tCSR
CS
tCKL
tCKS
tCKH
tCSH
CLKIN
tCSS
tDH
tDS
SERIAL
DATA
ADDR5
ADDR4
0
CTRL1 (W) CTRL2 (W)
DATA7
1
DATA0
SERIAL I/FWRITETIMING
tCSR
CS
tCKL
tCKS
tCKH
CLKIN
tCSS
tDH
tDS
SERIAL
DATA
ADDR5
ADDR4
0
CTRL2 (R)
CTRL1 (R)
DATA7
1
DATA0
tRD
tCSZ
SERIAL I/F READTIMING SINGLE MODE
CS
tCKL
tCKS
tCKH
CLKIN
tCSS
tDH
tDS
SERIAL
DATA
CTRL2 (R)
ADDR4
0
CTRL1 (R)
ADDR5
DATA0
ADDR5
ADDR4
DATA7
1
tRD
tRZ
SERIAL I/F READTIMING CONTINUOUS MODE
Figure 7. Serial Interface Signal
–22–
REV. 0
ADP3502
Table III. Setup and Hold Specifications
Parameter*
Min
Typ
Max
Unit
Test Condition/Comments
tCKS
tCSS
tCKH
tCKL
tCSH
tCSR
tDS
tDH
tRD
tRZ
tCSZ
50
50
100
100
100
62
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
CLK Setup Time
CS Setup Time
CLK High Duration
CLK Low Duration
CS Hold Time
CS Recovery Time
Input Data Setup Time
Input Data Hold Time
Data Output Delay Time
Data Output Floating Time
50
40
50
50
50
Data Output Floating Time after CS Goes Low
*These parameters are not tested.
Function Block
DATA, all data is canceled, and the DATA line would be high
impedance. In this case, users need to input the data again.
The ADP3502 integrates the serial bus interface for easy com-
munication with the system. The data bus consists of three
wires (CLK, CS, and DATA) and is capable of serial-to-
parallel/parallel-to-serial conversion of data, as well as clock
transfer.
Note that CLKIN should stay “L” when CS goes “H.” RTC
counter registers should be accessed at a certain time (>62 µs) after
CS assertion. Asserting RESETIN N (RESETIN–), signal
resets the block.
Serial interface block works during the time period at CS signal
enable. After the falling edge of CLKIN, signals right after the
rising edge of the CS signal, address, transfer control signal,
and write data are held in sequentially. In case of DATA READ,
data will be prepared by the rising edge of CLKIN, and the base-
band chip may want to read or latch the data at the falling
edge of CLKIN. While CS is not asserted, CLKIN is ignored.
If CS goes “L” while CLKIN is continuously applied or input
Notes:
• CLKIN should be “L” when CS goes “H.”
• In case of RTC counter access, the access should be approxi-
mately 62 µs (two clock cycles of CLK32K) after the CS signal
is asserted to hold the RTC value.
• The CS should not be asserted for 62 µs (2 clock cycles of
CLK32K) after the CS is released.
• CS signal should never be asserted for 1 sec or longer; other-
wise the RTC counter makes an error.
• CLKIN should be chosen as a multiple of 16 if CS < 31 µs.
RESETIN N
CS
CLKIN
DATAIN
SP ADDR [5:0]
CREATION OF
WRITE ENABLE
SERIAL-TO-PARALLEL
WRITE DATA
RW SEL
CONVERSION
SP DATA [7:0]
PS DATA [7:0]
PARALLEL-TO-SERIAL
CONVERSION
SYNCHRONIZATION
AND DATA SELECTION
DATA
Figure 8. Serial Interface Block Diagram
REV. 0
–23–
ADP3502
DATA INPUT/OUTPUT TIMING
5
4
3
2
1
0
1
0
7
6
5
4
3
2
1
0
R/W (2-BIT)
ADDRESS (6-BIT)
READ DATA (8-BIT)
Figure 9. Serial I/F Data Read/Write Timing
In Figure 9:
• SP ADDR[5:0]: 6-Bit Address
SP CTRL[1:0]: 2-Bit Read/Write Control (01: Write, 10: Read)
Keypad Control and LED Drive
KEYPADCOL[3:0] are open-drain outputs. The
KEYPADROW[5:0] are falling edge trigger inputs (input state
transition from “1” to “0”) and generate interrupt signal and are
pulled up to LDO1. By providing four keypad-column outputs and
six keypad-row inputs, the ADP3502 can monitor up to 24 keys
with the baseband chip. Writing column outputs and reading row
inputs are controlled through a serial interface. The address of the
KEYPADROW is 19h, and KEYPADCOL is 18h. The initial
register value is “1,” which means the output of KEYPADCOL
is low. Three-stage flip-flop synchronizes signals into interrupt
circuit to 1 kHz clock.
•
• SP DATA[7:0]: 8-Bit Input/Output Data
All transfers will be done MSB first.
GPIO + INT
The GPIO block has 4-channel I/O function and interrupt.
With the GPIO CONTROL register (1Ah), it is possible to
control the input or output setting of each channel individually.
The output data is set in the GPIO register (1Ch). When the
port is set in input mode, the input signal transitions from “1”
to “0” and from “0” to “1” and then generates an interrupt
signal with edge detection. The held interrupt signals are reset
by the GPIO INT RESET register (1Dh). Setting the GPIO
MASK register (1Bh) to “1” enables the interrupt of GPIO.
(Not MASKED, “1” at default in reset.)
The back-light drive is an open-drain output. The maximum
current of the internal FET is 100 mA. The initial register value
is “0,” which means the output of BLIGHT is high impedance.
Power ON Input
PWRONKEY and OPT1 have pull-up resistors, and others do
not. In addition to these inputs, other internal input signals, such
as charger detect and alarm signal (alarm int) from RTC, enable
the main and sub-LDOs of LDO1, LDO2, LDO3, LDO4, LDO6,
and LDO11. The Power ON status is held by latch data in the
delay circuit, called voltage detect delay (see 10 ms Delay section
for more information). OPT3 has a lower voltage threshold. OPT2
has a different structure than the other inputs and is pulled
down to zero by the internal signal when the phone is in Power ON
status, in order to ensure Power ON status, even if short-term
disconnection happens. Figure 11 is a block diagram of the
Power ON sequence.
INT Register
If the interrupt event occurs, “1,” the signal is held in this register.
INT detect and reset are synchronized at the rising edge of
CLK32K. If the interrupt event and reset signal occur at the
same time, the interrupt event has priority. The RESETIN N
signal resets the INT register (1Eh) to “0” (no INT detected),
except alarm int and pic int. The INT MASK register (1Fh)
goes to “1” (not masked). This block masks alarm int and pic int,
which generated in RTCV block, but these signals are reset with
the ALARM CONTROL register (0Dh) and PIC CONTROL
register (0Eh). The interrupt signal, INT N, is an inverted OR
signal of the value in the INT register and GPIO register.
VBAT
The DATA-IN register is a port to read an interrupt status. The
input data are through the SYNC block, except the alarm signal.
Since this is for just readback purposes, the user cannot write
any data.
140k⍀
VOLTAGE DETECT DELAY
140k⍀
CHARGER DETECT
ALARM INT
PWRONKEY–
POWER ON
SYNC BLOCK
OPT1–
OPT2–
OPT3
BATOV
RTC ALARM
CHARGER DETECT
OPT3
REGISTER
INT
BLOCK
DATA-IN REGISTER
(ADDR: 20h)
Figure 11. Power ON Input Block Diagram
OPT1–
PWRONKEY–
Figure 10. DATA-IN Block
–24–
REV. 0
ADP3502
In Figure 11:
the voltage detect signal is asserted, the voltage detect delay
signal is asserted. If the duration of the voltage detect signal is
less than 10 ms, the voltage detect delay signal will not be
asserted. When the voltage detect signal is released, the voltage
detect delay signal is released simultaneously. The voltage detect
delay signal can be reset by writing “1” in the POWER OFF
register (21h).
• Voltage Detect Delay: Voltage Detect Signal (10 ms Delay)
(1: Assert)
• Charger detect: Charger Detect Signal (1: Assert)
• Alarm INT: Alarm Detect Signal (Alarm 1 or Alarm 2)
(1: Assert)
• PWRONKEY–: Power On Key Input (0: Assert)
• OPT1–: Power On Signal (0: Assert)
• OPT2–: Power On Signal (0: Assert)
• OPT3: Power On Signal (1: Assert)
If users want to go back to a Power ON state, users should set
“1” to address 22h within a time constant of the external R/C
network, which is suppose to be connected to OPT2.
Note that users just need to write a “1” in the Power OFF regis-
ter to reset the voltage detect delay and do not need to overwrite
it with a “0.”
10 ms Delay
This block generates a 10 ms delayed signal after the reset of the
voltage detect signal is released. 10 ms (11 clocks of 1024 Hz) after
POWER ON
POWER OFF
POWERONKEY
POWER ON
LDO1, LDO2, LDO3,
LDO4, LDO6, LDO11
LDO1b, LDO2b, LDO6b
VOLTAGE DETECTOR
10ms
VOLTAGE DETECT DELAY
50ms
RSTDELAY–
OPT2
INT–
CLEAR INT
SERIAL I/F
CLEAR INT– AND SET PWROFF (21h) = 1
Figure 12. Power ON Sequence
REV. 0
–25–
ADP3502
LDO Control
Logic controls the remainder of the LDOs, including LDO1,
LDO2, and LDO6. A sub-LDO called LDO3b is independently
controlled, and this LDO control block doesn’t control LDO3b.
Also, the main LDO3, called LDO3a, is turned on by the Power
ON signal, but the sub-LDO3, called LDO3b, is always ON
while the battery supplies, and only the DDLO controls LDO3b.
A DDLO is the control signal from the battery charger block and
is monitoring the battery voltage. When VBAT is under 2.5 V
(200 mV hysteresis from VBAT = 2.7 V), DDLO minimizes
(DDLO enable) the current flow from the Li-Ion battery.
The LDO control block controls Power ON/OFF of the LDO
block. The function in this block has:
• Hardware control using external signals
• Software control using serial interface
• A mixture of the hardware and software above
LDO1, LDO2, LDO3, and LDO6 are structured with main and
sub-LDOs. LDO4, LDO5, LDO7, LDO8, LDO9, LDO10, and
LDO11 are set through the serial interface, but LDO7 and LDO9
are gated (AND gate) with SLEEP– signal in order to get into
the SLEEP mode. If the SLEEP– signal is enabled (goes low), the
outputs of LDO7 and LDO9 are turned OFF. The Power ON
Main LDOs: LDO1a, LDO2a, LDO3a, LDO6a
Sub-LDOs: LDO1b, LDO2b, LDO3b, LDO6b
Table IVa. DDLO Status Table
Status LDO1a
LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO LDO5
LDO6a
LDO6b LDO7 LDO8 LDO9 LDO10 LDO11
RF
Baseband VDD
Baseband AVDD Coin Cell
Audio REFO Vibrator Baseband Core
Rx1
Tx
Rx2
Option Option
DDLO OFF
Enable
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
X
OFF
OFF
OFF
OFF
X
OFF
X
DDLO
Disable
X
X
X
X
X
X
X
X
X
X
X
X
X means a status of LDO depends on other conditions.
Table IVb. LDO Control Event Table1
Event
LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO LDO5
LDO6a LDO6b LDO7 LDO8 LDO9 LDO10 LDO11
RF
Baseband VDD Baseband AVDD Coin Cell
Audio REFO Vibrator Baseband Core
Rx1
Tx
Rx2
Option Option
Power ON2
TCXOON3
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON/
OFF
ON/
OFF
ON/
OFF
ON/
OFF
SLEEP–4
ON/
OFF
ON/
OFF
RESETIN–
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ALLOFF Bit
Goes “H”
PWROFF Bit
Goes “H”
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
NOTES
1This table indicates only the status change caused by an event. Blank cells mean no change and keep previous status.
2Power-ON Event: Indicating a status just after the power-ON event. After the event, a status of LDO1a, LDO2a, LDO3a, and LDO6a are changed by the TCXOON signal.
3TCXOON: Hardware control, change all main LDOs’ ON/OFF status.
4SLEEP–: The LDO7 and LDO9 can be controlled by software if SLEEP = “H” level. If SLEEP– goes “L,” these LDOs are turned OFF immediately.
Table IVc. Software Controllability of LDOs
LDO
LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO LDO5
LDO6a LDO6b LDO7 LDO8 LDO9 LDO10
LDO11
Description Baseband VDD Baseband AVDD Coin Cell
Audio REFO Vibrator Baseband Core
Rx1
Tx
Rx2
RF Option Option
Software
Turn ON
√
√
√
√*
√
√*
√
√
√
√
Software
√
√
√
√
√
√
√
√
√
√
√
√
√
Turn OFF
*LDO7 and LDO9 have a gate with SLEEP–. If SLEEP– is in “L” (active) status, users cannot control it and both LDOs are kept in an OFF status. Users may want to use this
function as an immediate control to get OFF status by using SLEEP– hardware control when setting Register “1” to the LDO control register.
–26–
REV. 0
ADP3502
RTC Block
counter until the CS signal is released. In case the CPU writes
data into the SEC counter, the USEC counter is reset to zero.
The calendar registers are set through the serial interface.
Function
Note the following:
• RTC counter using binary
• In case of RTC counter access, the access should wait approxi-
mately 62 µs, (two clock cycles of CLK32K) after the CS signal
is asserted, to hold the RTC value.
• Reading out and writing settings of year, month, day, week,
hour, minute, and second data
• Leap year controls, number of days in a month control
• Alarm function (week, hour, minute)
• Periodic interrupt function—2 Hz, 1 Hz, 1/60 Hz, 1/3600 Hz,
each month (first day of each month)
• The CS signal should never be asserted 1 sec or longer since
this effects counter operation.
USEC Counter Operation
The USEC counter counts up synchronizing with the
RTC CLK32K clock. It generates a 1 sec timing signal and is
used as an increment clocking of the RTC counter. In case the
1 sec signal is generated during the CS signal asserted, the incre-
ment clock is delayed until the CS signal is released.
• Protection of wrong data readout during RTC data update
Operation
Synchronizing with the RTC CLK32K clock, the USEC counter
generates a 1 sec timing clock, which hits the RTC counter.
Through the serial interface, the CPU can write the setting
value and read the RTC counter value. In case the RTC counter
toggles during the serial interface access to the RTC counter,
the wrong data can be read/written between the RTC counter
and the interface. The CS signal stops the clocking to the RTC
RTC Counter Operation
The RTC counter uses the increment signal from the USEC
counter to control the counting operation, including the leap
year control and numbers of days in a month control.
RTC CLK32K
LOADING
ALARM
TIMES
RTC SP ADDR [5:0]
RTC
REGISTER
BLOCK
RTCWRITE ENABLE
RTCWRITE DATA [7:0]
(FROM SERIAL I/F)
ALARM
RTC ALARM INT
RTC CTFG INT
COMPARATOR
PERIODIC
INTERRUPT
RTC
COUNTER
LEAPYEAR
AND
RESETWILL BE ASSERTEDWHEN
RTC COUNTER IS WRITTEN.
DATA
SELECT
DATE
RTC DATA [7:0]
CONTROL
RTC CS
SEC COUNTER
INCREMENT
CONTROL
USEC
COUNTER
REGISTERS FOR
TEST MODE
RESETTO RTC AND USEC COUNTERS
WRITE INITIAL DATA OF USEC COUNTER
Figure 13. RTC Counter Block
REV. 0
–27–
ADP3502
ENABLED SIGNALS
CREATED
BY DECODING OF
RTC SP ADDR [5:0]
06h
05h
04h
03h
02h
01h
00h
100 SCALE
12 SCALE
31 SCALE
7 SCALE
YEAR
MONTH
DATE
ADDR 06h WRITE
ADDR 00h WRITE
INITIAL DATA
LEAPYEAR
AND
DAYS IN MONTH
CONTROL
TO
FOLLOWING
COUNTERS
WEEK
YEAR COUNT
MONTH COUNT
DAY COUNT
12 SCALE
60 SCALE
60 SCALE
HOUR
WEEK COUNT
HOUR COUNT
MIN COUNT
MINUTE
SECOND
INC ENB
USEC
INC CLK
COUNTER
SEC COUNT
Figure 14. RTC Counter Block Diagram
Periodic Interrupt Function
Definition of Leap Year
For this device, the following definition of a leap year is used instead:
This function generates interrupt periodically. The timing of
the cycle can be selected from 2 Hz (0.5 sec clock pulse), 1 Hz
(1 sec clock pulse), 1/60 Hz (minutes), 1/3600 Hz (hour), and
month (first day of each month).
“A year that can be divided by 4.”
Note:
• Year counter = “00” means year 2000 and is a leap year,
because it can be divided by 400.
• Actual covered year period is from 1901 to 2099.
The cycle is set using the PI2–PI0 value in the periodic interrupt
control, PIC register (0Eh). The state when interrupt is gener-
ated is indicated at the INTRA bit of PIC register (0Eh). The
INT MASK register (1Fh) only masks the periodic interrupt
signal. There are two periodic interrupt signal output patterns:
Number of Days of Month Control
• Months 1, 3, 5, 7, 8, 10, and 12 have 31 days.
• Months 4, 6, 9, and 11 have 30 days.
1. Hold the value when the interrupt occurs (level).
2. After the interrupt event happens, assert the interrupt signal
in a certain time period and then release it (pulse).
• Month 2 has 28 days but has 29 days in a leap year.
Alarm Function
Comparing the RTC counter value with the setting value in the
alarm setting register (07h–09h), the alarm condition is de-
tected. Setting of week uses seven bits for each day of the
week and works with multiple day settings. There is a delay of
62 µs from alarm detection to setting up the AOUT/BOUT
registers.
In level case, interrupt occurs at each 0 min (1/60 Hz), 0 o’clock
(1/3600 Hz), or the first day of the month. Because they
happen in long cycles, the value is held at the register. After the
CPU checks the state, it is released by writing a “1” to the PIC
Bit of the PIC Register. If 2 Hz and 1 Hz, the interrupt is not
held because the event happens in short cycles. These event
signals output the pulse signal 2 Hz or 1 Hz in the RTC counter
directly. The interrupt release operation doesn’t affect the inter-
rupt signal in this case.
The ALA EN flag in the ALARM CONTROL register (0Dh)
sets the enable/disable of the alarm detection. The INT register
(1Eh) indicates the interrupt signals, ALARM INT of ALA or/
and ALB. The INT MASK register (1Fh) does mask the
alarm interrupt signal. The alarm detection state is indicated as
AOUT of the ALARM CONTROL register (0Dh), and the
alarm can be released by writing a “1” at the bit. Alarm B is
controlled the same as Alarm A.
Stay-Alive Timer
This is a counter that increments each 250 ms after
RTC RESETIN N is asserted. It holds its value when the counter
counts full up. Signal CLK4 is a 4 Hz (250 ms) clock that was
generated in the USEC counter. The counter can be reset by
writing a “1” at the CLR of the Stay-Alive TIMER CONTROL
register (0Fh). The RTC RESETIN N signal is transferred from a
logic input circuit that is supplied by VBAT of RESETIN N.
Note: Users just need to write a “1” to release the alarm and do
not need to write a “0” after the “1.” Users do not need to wait
62 µs from CS assertion.
Note: Users just need to write a “1” to release the interrupt and
do not need to write a “0” after the “1.”
–28–
REV. 0
ADP3502
CLK4
TEST RESET
STAY-ALIVETIMER
RTC RESETIN N
D
SA [4:0]
5-BIT
COUNTER
CLRB
REGISTER
STAY-ALIVETIMER CONTROL REGISTER (0Fh): CLR
STAY-ALIVETIMER CONTROL REGISTER (0Fh): SAx
Figure 15. Stay-Alive Timer Block Diagram
RTCVOLTAGE DETECT
SA CLEAR
CLK4
SA COUNT [4:0]
0
1
2
3
4
5
30
31
0
Figure 16. Stay-Alive Timer Operation Timing
REV. 0
–29–
ADP3502
Table V. Registers
ADDR Description
D7
D6
D5
D4
D3
D2
D1
D0
Comments
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
Second Counter
Minute Counter
Hour Counter
Week Counter
Day Counter
Month Counter
Year Counter
Alarm A Minute
Alarm A Hour
Alarm A Week
Alarm B Minute
Alarm B Hour
S5
M5
S4
M4
H4
S3
M3
H3
S2
M2
H2
W2
D2
MO2
Y2
AM2
AH2
AW2
BM2
BH2
BW2
AOUT
PI2
S1
M1
H1
W1
D1
MO1
Y1
AM1
AH1
AW1
BM1
BH1
BW1
ALB EN
PI1
SA1
CHI
REF0
MV1
LDO5
S0
M0
H0
W0
D0
MO0
Y0
AM0
AH0
AW0
BM0
BH0
BW0
BOUT
PI0
Note 1, 2
Note 1, 2
Note 1, 2
Note 1, 2
Note 1, 2
Note 1, 2
Note 1, 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 3
Note 3
Note 3
Note 3
D4
D3
MO3
Y3
Y6
Y5
AM5
Y4
AM4
AH4
AW4
BM4
BH4
BW4
AM3
AH3
AW3
BM3
BH3
BW3
ALA EN
PIC
AW6
BW6
AW5
BM5
Alarm B Week
Alarm Control
BW5
CLR
Periodic Interrupt Control
Stay-Alive Timer Control
Charger Control
Charger MVBAT Control
Charger MVBAT
LDO Control 1
Not Available
LDO Control 2
LDO Control 3
LDO2 Gain
Keypad Column/LED
Keypad Row Input
GPIO Control
GPIO MASK
GPIO
SA4
SA3
SA2
SA0
CHEN
MVEN
MV0
LDO4
CHV1 CHV0
MV4
MV3
MV2
LDO11
Note 4
Note 3
Note 3
Note 3
Note 5
Note 5
Note 5
Note 5
SLEEP9 SLEEP7 LDO10
G23
LDO9
LDO8
LDO7
ALLOFF
G20
KO0
KI0
GPC0
GPMSK0
GPIO
G22
KO2
KI2
G21
KO1
KI1
GPC1
GPMSK1
GPI1
BL
KI4
KO3
KI3
GPC3
GPMSK3 GPMSK2
GPI3
KI5
GPC2
GPI2
Note 5
GPO3
GPINT3
GPRST3
INT3
IRST3
MSK3
DI3
GPO2
GPINT2
GPRST2
INT2
IRST2
MSK2
DI2
GPO1
GPINT1
GPRST1
INT1
IRST1
MSK1
DI1
GPO0
GPINT0
GPRST0
INT0
IRST0
MSK0
DI0
PWROFF
PWRON
TEST
Note 5
1Dh
1Eh
GPIO INT
INT
Note 5, 6
Note 5, 6
Note 5, 6
Note 5, 6
Note 5
Note 5
Note 5
Note 5
Note 2, 7
INT6 INT5
IRST6 INT5
MSK6 MSK5
DI5
INT4
INT4
MSK4
DI4
1Fh
20h
21h
22h
3Fh
INT MASK
DATA IN
Power OFF
Power ON
TEST Register (Option)
LDOENB USENB
NOTES
1. For RTC counter data protection, access should wait for a certain time period (62 µs) after the CS signal assertion. (Refer to the RTC Counter Operation section
for the wait time).
2. Registers regarding the RTC counter. They are powered by RTCV.
3. Analog block control registers. They control LDO and so on. They are powered by VBAT.
4. Not available.
5. These are the registers for INT, GPIO, KEYPAD I/F, and so on. They are powered by VBAT.
6. The INT reset operation will be valid at 62 µs or later after it’s set.
7. This is a set register for an internal test and should not be accessed at normal operation.
–30–
REV. 0
ADP3502
APPLICATION INFORMATION
Input Capacitor Selection
Input Voltage
For the input (ADAPTER and VBAT) of the ADP3502, a local
bypass capacitor is recommended. Use a 10 µF, low ESR capacitor.
Larger input capacitance and lower ESR provide better supply
noise rejection and line-transient response. Multilayer ceramic
chip (MLCC) capacitors provide the best combination of low
ESR and small size but may not be cost effective. A lower cost
alternative may be to use a 10 µF tantalum capacitor in parallel
with a small (1 µF to 2 µF) ceramic capacitor (ceramic capacitors
will produce the smallest supply ripple).
The input voltage of the ADP3502 is 4.2 V and is optimized for
a single Li-Ion cell. The thermal impedance of the ADP3502 is
56.2°C/W for 4-layer boards. Power dissipation should be
calculated at the maximum ambient temperatures and battery
voltage should not exceed the 125°C maximum allowable
junction temperature. The junction and ambient temperature
limits are selected to prevent both catastrophic package material
deterioration and excessive device power output degradation.
The ADP3502 can deliver the maximum power (0.71 W) up to
85°C ambient temperature. Figure 17 shows the maximum
power dissipation as a function of ambient temperature.
LDO Capacitor Selection
Low dropout regulators need capacitors on both their input and
output. The input capacitor provides bypassing of the internal
amplifier used in the voltage regulation loop. The output capacitor
improves the regulator response to sudden load changes. The
output capacitor determines the performance of any LDO. The
LDO1, LDO4, LDO5, LDO7, LDO8, and LDO11 require a
2.2 µF capacitor, and the LDO2, LDO3, LDO6, LDO9, and
LDO10 require a 1 µF capacitor. Transient response is a func-
tion of output capacitance. Larger values of output capacitance
decrease peak deviations, providing improved transient response
for large load current changes. Choose the capacitors by compar-
ing their lead inductance, ESR, and dissipation factor. Output
capacitor ESR affects stability. Note that the capacitance of
some capacitor types show wide variations over temperature or
with dc voltage. A good quality dielectric, X7R or better, capacitor
is recommended.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–30
0
30
60
90
The RTCV LDO can have a rechargeable coin cell or an electric
double-layer capacitor as a load, but an additional 0.1 µF ceramic
capacitor is recommended for stability and optimal performance.
AMBIENTTEMPERATURE – ؇C
Figure 17. Power Dissipation vs. Temperature
RTCV LDO
Printed Circuit Board Layout Considerations
Use the following guidelines when designing printed circuit
boards:
The RTCV LDO charges a rechargeable coin cell to run the
real-time clock module. It has been targeted to charge manga-
nese lithium batteries, such as the ML series (ML621/ML1220)
from Sanyo. With high energy density and relatively flat discharge
characteristics, the lithium coin cell is widely used in mobile
devices, such as cellular phones, digital cameras, and PDAs.
The ML621 has a small physical size (6.8 mm diameter) and a
nominal capacity of 2.5 mAh, which yields about 250 hours of
backup time.
1. Connect the battery to the VBAT and BVS pins of the
ADP3502. Kelvin-connect the BVS pin by running a separate
trace to the VBAT pin. Locate the input capacitor, C13, in
the Figure 18 as close as possible to these pins.
2. REFO, LDO2, LDO4, LDO8–LDO10, ADAPTER, and
NRCAP capacitors should be returned to AGND.
3. LDO1, LDO3, LDO5–LDO7, LDO11, and VBAT capacitors
should be returned to DGND.
4. Split the ground connections. Use separate traces or planes
for the analog, digital, and power grounds and tie them
together at a single point, preferably close to the battery return.
The nominal charging voltage is 3.0 V. This precise output voltage
regulation charges the cell to more than 90% of its capacity. In
addition, it features a very low quiescent of 50 µA typically. It
requires an external low leakage diode for reverse current pro-
tection that is needed when the main battery is removed, and
the coin cell supplies the RTCV pin.
5. Kelvin-connect the charger’s sense resistor by running sepa-
rate traces to the ADAPTER and ISENSE pins. Make sure the
traces are terminated as close to the resistor’s body as possible.
6. Run a separate trace from the BVS pin to the battery to
prevent a voltage drop error in the MVBAT measurement.
7. Use the best industry practice for thermal considerations
during the layout of the ADP3502 and charger components.
Careful use of the copper area, weight, and multilayer con-
struction all contribute to improved thermal performance.
REV. 0
–31–
ADP3502
Setting the Charge Current
External Pass Transistor Selection
The ADP3502 will control the charging operations when re-
quested by the software. It includes a complete constant current/
voltage single-cell lithium charge controller, as well as input
current monitoring for the charger and voltage regulators. The
ADP3502 will default to the lowest charge voltage of 3.50 V. To
reach final charge on standard lithium batteries, the software
must select one of the programmed values from this data sheet.
The current comparator of the ADP3502 senses the voltage
drop across an external sense resistor to control the average cur-
rent for charging a battery. The voltage drop can be adjusted
from 60 mV to 210 mV, giving a charging current limit from
300 mA to 1.05 A with a 0.2 Ω sense resistor. For lithium
batteries, selecting the sense resistor, RSENSE, programs the
charge current. Use the following equation to select the current
sense resistor, RSENSE. The maximum battery charge current,
The ADP3502 drives an external PNP pass transistor. The
BASE pin drives the base of the transistor. The driver can draw
up to 35 mA from the base of the pass device. The PNP pass
transistor must meet specifications for:
• Current gain
• Power dissipation
• Collector current
The current gain, hfe, influences the maximum output current
the circuit can deliver. The largest guaranteed output current is
given by ICHGR (max) = 35 mA ꢂ hfe (min). To ensure proper
operation, the minimum VBE the ADP3502 can provide must be
enough to turn on the PNP. The available base drive voltage
can be estimated using the following:
VBE =VADAPTER –VDIODE –VBASE
ICHGR, must be known.
where VADAPTER (min) is the minimum adapter voltage, VBASE is
the base drive voltage, and VSENSE is the maximum high current
limit threshold voltage. The difference between the adapter
voltage (VADAPTER) and the final battery voltage (VBAT) must
exceed the voltage drop due to the blocking diode, the sense
resistor, and the saturation voltage of the PNP at the maxi-
mum charge current, where:
210 mV
ICHGR
RSENSE
=
Similarly, the end of charge current can be calculated from the
low current limit threshold of 60 mV.
60 mV
RSENSE
ILOW
=
VCE(SAT) =VADAPTER –VDIODE –VSENSE –VBAT
The thermal characteristics of the PNP must be considered next.
The transistor’s rated power dissipation must exceed the actual
power dissipated in the transistor. The worst-case dissipation
can be determined using:
CHARGER DIODE SELECTION
The diode, D3, shown in the Figure 18, is used to prevent the bat-
tery from discharging through the adapter supply. Choose a diode
with a low leakage current but with a current rating high enough
to handle the battery current and a voltage rating greater than
VBAT. The blocking diode is required for lithium battery types.
PDISS = V
–VDIODE –VBAT × ICHGR
(
)
ADAPTER MAX
(
)
It should be noted that the adapter voltage could be either preregu-
lated or nonregulated. When preregulated, the difference between
the maximum and minimum adapter voltage is probably not
significant. When unregulated, the adapter voltage can have a
wide range specified. However, the maximum voltage specified
is usually with no load applied. Therefore, the worst-case power
dissipation calculation will often lead to an overspecified pass
device. In either case, it is best to determine the load character-
istics of the adapter to optimize the charger design.
–32–
REV. 0
ADP3502
D3
BAS116
R
SENSE
0.2⍀
Q9
FZT788
AC
ADPTER
C13
10F
Li-ION
BATTERY
C18
10F
BASEBAND ADC
VBAT
C17 0.1F
R5
100k⍀
RF OPTIONAL
RF RX2
C16
1.0F
OPT1
C15
1.0F
RFTX
C19
0.1F
64
49
C14
2.2F
1
48
OPT3
OPT3
VBAT
LDO7
LDO6
VBAT
LDO5
LDO4
VBAT
LDO2
REFO
AGND
LDO3
VBAT
LDO1
LDO11
VBAT
KEYPADCOL0
KEYPADCOL1
KEYPADCOL2
KEYPADCOL3
KEYPADROW0
KEYPADROW1
KEYPADROW2
KEYPADROW3
KEYPADROW4
KEYPADROW5
TCXOON
RF RX1
BASEBAND
CORE
VIBRATOR
AUDIO
KEYPAD
INTERFACE
BASEBAND AVDD
REF0
ADP3502
C11
1.0F
C7
2.2F
C12
C8
C9
1.5F
RTC/COIN-CELL
2.2F
2.2F
C10
C6
TCXOON
SLEEP
0.1F
1.0F
SLEEP
BASEBAND VDD
OPTIONAL
VBAT
R4
BLIGHT
C4
C5
D1
2.2F
2.2F
DGND
1.5k⍀
INT
RSTDELAY–
INT
16
D2
BAT54
33
17
X1
32
R2
C3
0.1F
1k⍀
SERIAL
I/F
COIN CELL
32.7kHz
C1
10pF
C2
10pF
Figure 18. Typical Application Circuit
REV. 0
–33–
ADP3502
OUTLINE DIMENSIONS
64-Lead Thin Plastic Quad Flat Package [TQFP]
7 x 7 x 1.00 mm Body
(SU-64)
Dimensions shown in millimeters
9.00 BSC
1.20
MAX
7.00 BSC
0.75
0.60
0.45
64
1
49
48
PIN 1
SEATING
PLANE
9.00
BSC
TOP VIEW
(PINS DOWN)
COPLANARITY
0.08 MAX
16
17
33
32
STANDOFF
0.15 MAX
0.05 MIN
0.23
0.18
0.13
0.40
BSC
0.20
0.09
7
0
1.05
1.00
0.95
COMPLIANT TO JEDEC STANDARDS MS-026ABD
–34–
REV. 0
–35–
–36–
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