ADP5072ACBZ-R7 [ADI]
1 A/0.6 A DC to DC Switching Regulator Independent Positive and Negative Outputs;
| 型号： | ADP5072ACBZ-R7 |
| 厂家： | 
ADI |
| 描述： | 1 A/0.6 A DC to DC Switching Regulator Independent Positive and Negative Outputs |
| 文件： | 总24页 (文件大小：646K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 A/0.6 A DC to DC Switching Regulator with
Independent Positive and Negative Outputs
Data Sheet
ADP5072
FEATURES
TYPICAL APPLICATION CIRCUIT
V
IN
Input supply voltage range: 2.85 V to 5.5 V
Generates well regulated, independently resistor
programmable VPOS and VNEG outputs
Boost regulator to generate VPOS output
Adjustable positive output to 35 V
ADP5072
L1
SS
V
POS
R
C1
SW1
SW1
COMP1
EN1
D1
C
C1
R
FT1
FB1
R
Integrated 1.0 A main switch
Inverting regulator to generate VNEG output
Adjustable negative output to −30 V
FB1
C
OUT1
PVIN
PVIN
AVIN
V
IN
PGND
PGND
VREF
C
IN
C
VREF
Integrated 0.6 A main switch
EN2
1.2 MHz/2.4 MHz switching frequency with optional external
frequency synchronization from 1.0 MHz to 2.6 MHz
Resistor programmable soft start timer
Slew rate control for lower system noise
Individual precision enable and flexible start-up sequence
control for symmetric start, VPOS first, or VNEG first
Out of phase operation
C
R
OUT2
FB2
R
C2
FB2
COMP2
R
FT2
C
C2
SYNC
SLEW
SEQ
SW2
V
NEG
D2
AGND
L2
Figure 1.
UVLO, OCP, OVP, and TSD protection
1.61 mm × 2.18 mm, 20-ball WLCSP
−40°C to +125°C junction temperature range
APPLICATIONS
Bipolar amplifiers, analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), and multiplexers
Charge coupled device (CCD) bias supplies
Optical module supplies
RF power amplifier bias
Time of flight module supplies
GENERAL DESCRIPTION
The ADP5072 is a dual, high performance dc-to-dc regulator that
generates independently regulated positive and negative rails.
Other key safety features in the ADP5072 include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The input voltage range of 2.85 V to 5.5 V supports a wide
variety of applications. The integrated main switch in both
regulators enables generation of an adjustable positive output
voltage up to 35 V and a negative output voltage down to −30 V.
The ADP5072 is available in a 20-ball WLCSP and is rated for a
−40°C to +125°C junction temperature range.
Table 1. Family Models
Boost
Inverter
The ADP5072 operates at a pin selected 1.2 MHz or 2.4 MHz
switching frequency. The ADP5072 can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering
in sensitive applications. Both regulators implement programma-
ble slew rate control circuitry for the MOSFET driver stage to
reduce electromagnetic interference (EMI). Flexible start-up
sequencing is provided with the options of manual enable,
simultaneous mode, positive supply first, and negative supply first.
Model
Switch (A) Switch (A) Package
ADP5070 1.0
0.6
1.2
20-lead LFCSP (4 mm× 4 mm) and
20-lead TSSOP
20-lead LFCSP (4 mm × 4 mm) and
20-lead TSSOP
ADP5071 2.0
ADP5072 1.0
ADP5073 N/A
ADP5074 N/A
ADP5075 N/A
0.6
1.2
2.4
0.8
20-ball WLCSP (1.61 mm × 2.18 mm)
16-lead LFCSP (3 mm × 3 mm)
16-lead LFCSP (3 mm × 3 mm)
12-ball WLCSP (1.61 mm × 2.18 mm)
The ADP5072 includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up.
Rev. 0
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Tel: 781.329.4700
Technical Support
©2019 Analog Devices, Inc. All rights reserved.
www.analog.com
ADP5072
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Precision Enabling...................................................................... 14
Soft Start ...................................................................................... 14
Slew Rate Control....................................................................... 14
Current-Limit Protection ............................................................ 14
Overvoltage Protection.............................................................. 14
Thermal Shutdown .................................................................... 14
Start-Up Sequence...................................................................... 14
Applications Information .............................................................. 16
Component Selection ................................................................ 16
Output Capacitors...................................................................... 17
Loop Compensation .................................................................. 19
Common Applications .............................................................. 21
Layout Considerations............................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 13
PWM Mode................................................................................. 13
PSM Mode................................................................................... 13
Undervoltage Lockout (UVLO) ............................................... 13
Oscillator and Synchronization................................................ 13
Internal Regulator....................................................................... 13
REVISION HISTORY
1/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
ADP5072
SPECIFICATIONS
PVIN = AVIN = 2.85 V to 5.5 V, positive output voltage (VPOS) = 15 V, negative output voltage (VNEG) = −15 V, fSW = 1200 kHz, TJ = −40°C
to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE
QUIESCENT CURRENT
Operating Quiescent Current
PVIN, AVIN (Total)
VIN
2.85
5.5
V
PVIN, AVIN
IQ
3.5
4.0
2.2
mA
mA
No switching, EN1 = EN2 =
high, PVIN = AVIN = 5 V
No switching, EN1 = EN2 =
low, PVIN = AVIN = 5 V
Standby Current
ISTNDBY
2.05
UVLO
System UVLO Threshold
Rising
Falling
AVIN
VUVLO_RISING
VUVLO_FALLING
VHYS
2.8
2.55
0.25
2.85
V
V
V
2.5
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency
fSW
1.130 1.2
2.240 2.4
1.270
2.560
MHz
MHz
SYNC = low
SYNC = high (connect to
PVIN)
SYNC Input
Input Clock Range
fSYNC
1.0
100
100
2.6
1.3
MHz
ns
ns
V
Input Clock Minimum On Pulse Width
Input Clock Minimum Off Pulse Width
Input Clock High Logic
Input Clock Low Logic
tSYNC_MIN_ON
tSYNC_MIN_OFF
VH (SYNC)
VL (SYNC)
0.4
V
PRECISION ENABLING (EN1, EN2)
High Level Threshold
Low Level Threshold
VTH_H
VTH_L
VTH_S
1.125 1.15
1.025 1.05
0.4
1.175
1.075
V
V
V
Shutdown Mode
Internal circuitry disabled to
achieve ISTNDBY
Pull-Down Resistance
BOOST REGULATOR
REN
1.48
MΩ
Adjustable Positive Output Voltage
Feedback Voltage
Feedback Voltage Accuracy
VPOS
VFB1
35
V
V
%
%
µA
V
0.8
−0.5
−1.5
+0.5
+1.5
0.1
TJ = 25°C
TJ = −40°C to +125°C
Feedback Bias Current
Overvoltage Protection Threshold
Load Regulation
IFB1
VOV1
0.86
0.0003
0.002
At FB1 pin
(∆VFB1/VFB1)/ΔILOAD1
(∆VFB1/VFB1)/ΔVPVIN
%/mA ILOAD11 = 5 mA to 150 mA
%/V
Line Regulation
VPVIN = 2.85 V to 5.5 V, ILOAD1
50 mA
=
Error Amplifier (EA) Transconductance
Power FET On Resistance
Power FET Maximum Drain Source
Voltage
Current-Limit Threshold, Main Switch
Minimum On Time
Minimum Off Time
gM1
RDS (ON) BOOST
VDS (MAX) BOOST
260
1.0
300
175
39
340
1.3
µA/V
mΩ
V
ILIM (BOOST)
1.1
50
25
A
ns
ns
Rev. 0 | Page 3 of 24
ADP5072
Data Sheet
Parameter
Symbol
Min
Typ
1.60
0.8
Max
Unit
Test Conditions/Comments
INVERTING REGULATOR
Adjustable Negative Output Voltage
Reference Voltage
VNEG
VREF
−30
V
V
%
%
V
Reference Voltage Accuracy
−0.5
−1.5
+0.5
+1.5
TJ = 25°C
TJ = −40°C to +125°C
Feedback Voltage
VREF − VFB2
Feedback Voltage Accuracy
−0.5
−1.5
+0.5
+1.5
0.1
%
%
µA
V
TJ = 25°C
TJ = −40°C to +125°C
Feedback Bias Current
Overvoltage Protection Threshold
IFB2
VOV2
0.74
At FB2 pin after soft start
has completed
Load Regulation
Line Regulation
(∆(VREF − VFB2)/(VREF − VFB2))/
ILOAD2
(∆(VREF − VFB2)/(VREF − VFB2))/
VPVIN
0.0004
0.003
%/mA ILOAD2 = 5 mA to 75 mA
%/V
VPVIN = 2.85 V to 5.5 V, ILOAD2
25 mA
=
EA Transconductance
Power FET On Resistance
Power FET Maximum Drain Source
Voltage
Current-Limit Threshold, Main Switch
Minimum On Time
gM2
RDS (ON) INVERTER
VDS (MAX) INVERTER
260
600
300
350
39
340
750
µA/V
mΩ
V
ILIM (INVERTER)
660
60
mA
ns
Minimum Off Time
50
ns
SOFT START
Soft Start Timer for DC to DC Regulators
tSS
4
32
8 × tSS
ms
ms
ms
SS = open
SS resistor = 50 kΩ to GND
Hiccup Time
THERMAL SHUTDOWN
Threshold
tHICCUP
TSHDN
THYS
150
15
°C
°C
Hysteresis
1 ILOADx is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).
Rev. 0 | Page 4 of 24
Data Sheet
ADP5072
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
PVIN, AVIN
SW1
Rating
−0.3 V to +6V
−0.3 V to +40 V
PVIN − 40 V to PVIN + 0.3 V
−0.3 V to +0.3 V
−0.3 V to +6 V
SW2
θ
JA is the natural convection junction to ambient thermal
PGND, AGND
EN1, EN2, FB1, FB2, SYNC,
COMP1, COMP2, SLEW, SS,
SEQ, VREF
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance. ψJT is the junction to
case thermal characterization parameter.
−0.3 V to AVIN + 0.3 V
Operating Junction
Temperature Range
Storage Temperature Range
Soldering Conditions
−40°C to +125°C
Table 4. Thermal Resistance
Package Type
θJA
θJC
ΨJT
Unit
−65°C to +150°C
JEDEC J-STD-020
CB-20-141, 2
50
0.54
0.13
C/W
1 θJA and ΨJT are based on a 4-layer printed circuit board (PCB) (two signal and
two power planes) with nine thermal vias connecting the exposed pad to the
ground plane as recommended in the Layout Considerations section. θJC is
measured at the top of the package and is independent of the PCB. The ΨJT
value is more appropriate for calculating junction to case temperature in the
application.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
2 The thermal resistance values specified in Table 4 are simulated based on
JEDEC specifications, unless specified otherwise, and must be used in
compliance with JESD51-12.
ESD CAUTION
Rev. 0 | Page 5 of 24
ADP5072
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
A
B
C
D
E
PVIN
SW2
SW1
PGND
AVIN
EN2
PVIN
SW1
SEQ
SS
PGND
EN1
SYNC
AGND SLEW
COMP2 FB2
FB1
VREF COMP1
Figure 2. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
A1, B2
A2
A3, B3
A4, B4
B1
Mnemonic
Description
PVIN
SW2
SW1
PGND
AVIN
Power Input for the Boost Regulator.
Switching Node for the Inverting Regulator.
Switching Node for the Boost Regulator.
Power Ground for the Boost Regulator.
System Power Supply for the ADP5072.
C1
EN2
Inverting Regulator Precision Enable. The EN2 pin is compared to an internal precision reference to enable
the inverting regulator output.
C2
C3
SYNC
SEQ
Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC pin high.
To set the switching frequency to 1.2 MHz, pull the SYNC pin low. To synchronize the switching frequency,
connect the SYNC pin to an external clock.
Start-Up Sequence Control. For manual VPOS/VNEG startup using an individual precision enabling pin, ENx,
leave the SEQ pin open. For simultaneous VPOS/VNEG startup when the EN2 pin rises, connect the SEQ pin to
PVIN (the EN1 pin can be used to enable the internal references early, if required). For a sequenced startup, pull the
SEQ pin low. Either EN1 or EN2 can be used, and the corresponding supply is the first in sequence. Hold the
other enable pin low.
C4
EN1
Boost Regulator Precision Enable. The EN1 pin is compared to an internal precision reference to enable the
boost regulator output.
D1
D2
AGND
SLEW
Analog Ground.
Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the fastest
slew rate (optimal efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to PVIN.
For the slowest slew rate (optimal noise performance), connect the SLEW pin to AGND.
D3
D4
E1
E2
SS
Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft
start time, connect a resistor between the SS pin and AGND.
Feedback Input for the Boost Regulator. Connect a resistor divider between the positive side of the boost
regulator output capacitor and AGND to program the output voltage.
Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this
pin and AGND.
Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the
inverting regulator output capacitor and VREF to program the output voltage.
FB1
COMP2
FB2
E3
E4
VREF
COMP1
Inverting Regulator Reference Output. Connect a 1.0 µF ceramic filter capacitor between the VREF pin and AGND.
Error Amplifier Compensation for the Boost Regulator. Connect the compensation network between this pin
and AGND.
Rev. 0 | Page 6 of 24
Data Sheet
ADP5072
TYPICAL PERFORMANCE CHARACTERISTICS
700
350
300
250
200
150
100
50
V
V
V
V
= 3.3V, L = 6.8µH
= 3.3V, L = 4.7µH
= 5.0V, L = 10.0µH
= 5.0V, L = 6.8µH
V
V
V
V
= 3.3V, L = 10.0µH
= 3.3V, L = 6.8µH
= 5.0V, L = 10.0µH
= 5.0V, L = 15.0µH
IN
IN
IN
IN
IN
IN
IN
IN
600
500
400
300
200
100
0
0
0
5
10
15
20
25
30
35
40
–35
–30
–25
–20
V
–15
(V)
–10
–5
0
V
(V)
POS
NEG
Figure 3. Maximum Output Current (IOUT) vs. VPOS for Boost Regulator,
Figure 6. Maximum Output Current (IOUT) vs. VNEG for Inverting Regulator,
SW = 1.2 MHz, TA = 25°C, Based on Target of 70% ILIM (INVERTER)
f
SW = 1.2 MHz, TA = 25°C, Based on Target of 70% ILIM (BOOST)
f
700
350
300
250
200
150
100
50
V
V
V
V
= 3.3V, L = 6.8µH
= 3.3V, L = 3.3µH
= 5.0V, L = 10.0µH
= 5.0V, L = 3.3µH
V
V
V
V
= 3.3V, L = 10.0µH
= 3.3V, L = 6.8µH
= 5.0V, L = 10.0µH
= 5.0V, L = 15.0µH
IN
IN
IN
IN
IN
IN
IN
IN
600
500
400
300
200
100
0
0
0
5
10
15
20
25
30
35
40
–35
–30
–25
–20
V
–15
(V)
–10
–5
0
V
(V)
POS
NEG
Figure 4. Maximum Output Current (IOUT) vs. VPOS for Boost Regulator,
Figure 7. Maximum Output Current (IOUT) vs. VNEG for Inverting Regulator,
SW = 2.4 MHz, TA = 25°C, Based on Target of 70% ILIM (INVERTER)
f
SW = 2.4 MHz, TA = 25°C, Based on Target of 70% ILIM (BOOST)
f
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
V
V
= 3.3V, fSW = 1.2MHz
= 3.3V, fSW = 2.4MHz
V
V
= 3.3V, fSW = 1.2MHz
= 3.3V, fSW = 2.4MHz
IN
IN
IN
IN
0.001
0.01
0.1
1.0
0.001
0.01
0.1
1.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 5. Efficiency vs. Load Current for Boost Regulator, VIN = 3.3 V,
POS = 5 V, TA = 25°C
Figure 8. Efficiency vs. Load Current for Inverting Regulator, VIN = 3.3 V,
NEG = −5 V, TA = 25°C
V
V
Rev. 0 | Page 7 of 24
ADP5072
Data Sheet
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
V
V
V
V
= 3.3V, fSW = 1.2MHz
= 3.3V, fSW = 2.4MHz
= 5.0V, fSW = 1.2MHz
= 5.0V, fSW = 2.4MHz
V
V
V
V
= 3.3V, fSW = 1.2MHz
IN
IN
IN
IN
IN
IN
IN
IN
= 3.3V, fSW = 2.4MHz
= 5.0V, fSW = 1.2MHz
= 5.0V, fSW = 2.4MHz
0
0.001
0.01
0.1
1.0
0.001
0.01
0.1
1.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 9. Efficiency vs. Load Current for Boost Regulator, VPOS = 9 V, TA = 25°C
Figure 12. Efficiency vs. Load Current for Inverting Regulator, VNEG = −9 V,
TA = 25°C
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
V
V
V
V
= 3.3V, fSW = 1.2MHz
= 3.3V, fSW = 2.4MHz
= 5.0V, fSW = 1.2MHz
= 5.0V, fSW = 2.4MHz
V
V
V
V
= 3.3V, fSW = 1.2MHz
= 3.3V, fSW = 2.4MHz
= 5.0V, fSW = 1.2MHz
= 5.0V, fSW = 2.4MHz
20
10
0
20
10
0
IN
IN
IN
IN
IN
IN
IN
IN
0.001
0.01
0.1
1.0
0.001
0.01
0.1
1.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 10. Efficiency vs. Load Current for Boost Regulator, VPOS = 15 V,
A = 25°C
Figure 13. Efficiency vs. Load Current for Inverting Regulator, VNEG = −15 V,
T
T
A = 25°C
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
V
V
= 3.3V, fSW = 1.2MHz
= 5V, fSW = 1.2MHz
= 5V, fSW = 2.4MHz
IN
IN
IN
V
V
V
= 3.3V, fSW = 1.2MHz
= 5V, fSW = 1.2MHz
= 5V, fSW = 2.4MHz
IN
IN
IN
0.001
0.01
LOAD CURRENT (A)
0.1
0.001
0.01
0.1
LOAD CURRENT (A)
Figure 11. Efficiency vs. Load Current for Boost Regulator, VPOS = 35 V,
A = 25°C
Figure 14. Efficiency vs. Load Current for Inverting Regulator, VNEG = −30 V,
A = 25°C
T
T
Rev. 0 | Page 8 of 24
Data Sheet
ADP5072
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
A
A
A
0
0.001
0.01
0.1
1.0
0.001
0.01
0.1
1.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 15. Efficiency vs. Load Current for Boost Regulator over Temperature,
IN = 5 V, VPOS = 15 V, fSW = 1.2 MHz
Figure 18. Efficiency vs. Load Current for Inverting Regulator over
Temperature, VIN = 5 V, VNEG = −15 V, fSW = 1.2 MHz
V
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
V
V
V
ACCURACY
ACCURACY
ACCURACY
NEG
REF
FB2
–0.4
V
V
ACCURACY
ACCURACY
POS
FB1
–0.5
2.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
V
V
IN
IN
Figure 16. Boost Regulator Line Regulation, VPOS = 15 V,
SW = 1.2 MHz, 15 mA Load, TA = 25°C
Figure 19. Inverting Regulator Line Regulation, VNEG = −15 V,
f
f
SW = 1.2 MHz, 15 mA Load, TA = 25°C
0.5
0.4
0.5
0.4
0.3
0.3
1.2MHz
2.4MHz
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
1.2MHz
2.4MHz
0
0.02
0.04
0.06
0.08
0.10
0.12
0
0.05
0.10
0.15
0.20
0.25
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 17. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V
Figure 20. Inverting Regulator Load Regulation, VIN = 5 V, VNEG = −15 V
Rev. 0 | Page 9 of 24
ADP5072
Data Sheet
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.1
–0.2
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12
INVERTING REGULATOR LOAD (A)
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12
BOOST REGULATOR LOAD (A)
Figure 21. Cross Regulation, Boost Regulator VFB1 Regulation, VIN = 5 V,
POS = 15 V, VNEG = −15 V, fSW = 2.4 MHz, TA = 25°C, Boost Regulator Run in
Continuous Conduction Mode with Fixed Load for Test
Figure 24. Cross Regulation, Inverting Regulator VFB2 Regulation,
VIN = 5 V, VPOS = 15 V, VNEG = −15 V, fSW = 2.4 MHz, TA = 25°C, Inverting
Regulator Run in Continuous Conduction Mode with Fixed Load for Test
V
1.30
1.25
1.20
1.15
1.10
1.05
0.75
0.72
0.69
0.66
0.63
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
A
A
A
1.00
2.5
0.60
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
IN
IN
Figure 25. Inverting Regulator Current Limit (ILIMIT) vs. Input Voltage (VIN
over Temperature
)
Figure 22. Boost Regulator Current Limit (ILIMIT) vs. Input Voltage (VIN
over Temperature
)
1.27
1.25
1.23
1.21
1.19
1.17
2.54
2.49
2.44
2.39
2.34
2.29
1.15
1.13
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
A
A
A
2.24
2.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
IN
IN
Figure 26. Oscillator Frequency vs. Input Voltage (VIN) over Temperature,
SYNC Pin = Low
Figure 23. Oscillator Frequency vs. Input Voltage (VIN) over Temperature,
SYNC Pin = High
Rev. 0 | Page 10 of 24
Data Sheet
ADP5072
3.0
2.5
2.0
1.5
1.0
0.5
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
A
A
A
2.7
3.2
3.7
4.2
(V)
4.7
5.2
5.7
2.7
3.2
3.7
4.2
(V)
4.7
5.2
5.7
V
V
IN
IN
Figure 30. Operating Quiescent Current vs. Input Voltage (VIN) over
Temperature, Both ENx Pins On
Figure 27. Standby Current vs. Input Voltage (VIN) over Temperature, Both
ENx Pins Below Shutdown Threshold
V
IN
V
IN
V
POS
2
1
3
V
V
NEG
FB2
2
1
V
FB1
3
B
B
B
W
B
B
CH2 50.0mV
CH1 1.00V
CH3 20.0mV
CH2 200mV
W
M2.00ms A CH1
5.16V
CH1 1.00V
CH3 10.0mV
M1.00ms A CH1
4.96V
W
W
W
B
T
1.906000ms
T
5.772000ms
W
Figure 31. Inverting Regulator Line Transient, VIN = 4.5 V to 5.5 V Step,
NEG = −15 V, RLOAD2 = 300 Ω, fSW = 2.4 MHz, TA = 25°
Figure 28. Boost Regulator Line Transient, VIN = 4.5 V to 5.5 V Step, VPOS = 15 V,
V
RLOAD1 = 300 Ω, fSW = 2.4 MHz, TA = 25°C
I
LOAD1
I
LOAD2
4
1
4
1
V
V
V
NEG
POS
V
FB2
FB1
3
3
B
B
B
CH1 100mV
CH3 10.0mV
M1.00ms A CH4
20.30%
48.0mA
W
W
CH1 50.0mV
CH3 10.0mV
M100µs A CH4
20.30%
140mA
W
W
B
B
B
W
CH4 20.0mA
T
W
CH4 50.0mA
T
Figure 32. Inverting Regulator Load Transient, VIN = 5 V Step, VNEG = −15 V,
LOAD2 = 35 mA to 45 mA Step, fSW = 2.4 MHz, TA = 25°C
Figure 29. Boost Regulator Load Transient, VIN = 5 V Step, VPOS = 15 V,
LOAD1 = 120 mA to 150 mA Step, fSW = 2.4 MHz, TA = 25°C
I
I
Rev. 0 | Page 11 of 24
ADP5072
Data Sheet
I
INDUCTOR
3
I
INDUCTOR
3
SW1
SW2
V
2
1
1
2
V
NEG
POS
B
B
B
B
CH1 500mV
CH2 10.0V
M2.00µs A CH3
7.960000µs
82.0mA
CH1 5.00V
CH2 500mV
M4.00µs A CH3
12.00000µs
35.0mA
W
W
W
W
B
B
W
CH3 100mA
CH3 50.0mA
T
T
W
Figure 33. Boost Regulator Skip Mode Operation Showing Inductor Current
(IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 12 V, VPOS = 15 V,
Figure 36. Inverting Regulator Skip Mode Operation Showing Inductor
Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V,
I
LOAD1 = 4 mA, fSW = 2.4 MHz, TA = 25°C
VNEG = −5 V, ILOAD2 = 0 mA, fSW = 2.4 MHz, TA = 25°C
I
I
INDUCTOR
INDUCTOR
3
3
SW1
SW2
2
1
1
2
V
V
NEG
POS
B
B
B
B
CH1 500mV
CH2 10.0V
M200ns A CH3
7.960000µs
100mA
CH1 5.00V
CH2 500mV
M200ns A CH3
24.46000µs
42.0mA
W
W
W
W
B
B
W
CH3 200mA
CH3 50mA
T
T
W
Figure 34. Boost Regulator Discontinuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 6 mA, fSW = 2.4 MHz, TA = 25°C
Figure 37. Inverting Regulator Discontinuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VNEG = −5 V, ILOAD2 = 6 mA, fSW = 2.4 MHz, TA = 25°C
I
INDUCTOR
I
INDUCTOR
3
3
SW1
SW2
2
1
1
2
V
V
NEG
POS
B
B
B
B
CH1 500mV
CH2 10.0V
M200ns A CH4
7.960000µs
310mA
CH1 5.00V
CH2 500mV
M100ns A CH3
24.46000µs
84.0mA
W
W
W
W
B
B
W
CH3 500mA
CH3 50mA
T
T
W
Figure 35. Boost Regulator Continuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 90 mA, fSW = 2.4 MHz, TA = 25°C
Figure 38. Inverting Regulator Continuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VNEG = −5 V, ILOAD2 = 35 mA, fSW = 2.4 MHz, TA = 25°C
Rev. 0 | Page 12 of 24
Data Sheet
ADP5072
THEORY OF OPERATION
V
IN
C
IN
SYNC
AVIN
PVIN
CURRENT SENSE
INVERTER
PWM CONTROL
D2
C
V
SW2
L2
NEG
L1
SLEW
REFERENCES
D1
V
OUT2
POS
SW1
SLEW
C
OUT1
PLL
BOOST PWM
CONTROL
R
FT1
R
ERROR
AMP
FT2
REF2
+
OSCILLATOR
PGND
FB1
FB2
CURRENT
–
SENSE
BOOST_ENABLE
SEQUENCE
CONTROL
R
FB2
ERROR
AMP
–
+
INVERTER_ENABLE
VREF
REF_1V6
R
REF1
THERMAL
SHUTDOWN
FB1
COMP1
C
VREF
COMP2
1.5MΩ
1.5MΩ
R
C1
4µA
UVLO
SLEW
TRI-STATE
BUFFER
REF1
REF2
START-UP
TIMERS
REFERENCE
GENERATOR
R
C2
FB1
OVP
FB2
REF_1V6
C
C1
C
C2
SLEW
EN1
EN2 SEQ
SS
R
(OPTIONAL)
SS
AGND
Figure 39. Functional Block Diagram
PWM MODE
OSCILLATOR AND SYNCHRONIZATION
The boost and inverting regulators in the ADP5072 operate at a
fixed frequency set by an internal oscillator. At the start of each
oscillator cycle, the MOSFET switch turns on, applying a positive
voltage across the inductor. The inductor current increases until
the current sense signal crosses the peak inductor current threshold
that turns off the MOSFET switch; this threshold is set by the error
amplifier output. During the MOSFET off time, the inductor
current declines through the external diode until the next
oscillator clock pulse starts a new cycle. It regulates the output
voltage by adjusting the peak inductor current threshold.
The ADP5072 initiates the drive of the boost regulator SW1 pin
and the inverting regulator SW2 pin 180° out of phase to reduce
peak current consumption and noise.
A phase-locked loop (PLL)-based oscillator generates the internal
clock and offers a choice of two internally generated frequency
options or external clock synchronization. The switching frequency
is configured using the SYNC pin options shown in Table 6.
For external synchronization, connect the SYNC pin to a
suitable clock source. The PLL locks to an input clock within
the range specified by fSYNC
.
PSM MODE
Table 6. SYNC Pin Options
During light load operation, the regulators can skip pulses to
maintain output voltage regulation. Skipping pulses increases
the device efficiency.
SYNC Pin
High
Switching Frequency
2.4 MHz
Low
1.2 MHz
UNDERVOLTAGE LOCKOUT (UVLO)
External Clock
1 × clock frequency
The undervoltage lockout circuitry monitors the AVIN pin
voltage level. If the input voltage drops below the VUVLO_FALLING
threshold, both regulators turn off. After the AVIN pin voltage
rises above the VUVLO_RISING threshold, the soft start period initiates,
and the regulators are enabled.
INTERNAL REGULATOR
The VREF regulator provides a reference voltage for the inverting
regulator feedback network to ensure a positive feedback voltage on
the FB2 pin.
A current-limit circuit is included for the VREF regulator to protect
the circuit from accidental loading.
Rev. 0 | Page 13 of 24
ADP5072
Data Sheet
PRECISION ENABLING
CURRENT-LIMIT PROTECTION
TheADP5072 has an individual enable pin for the boost and
inverting regulators: EN1 and EN2. The enable pins feature a
precision enable circuit with an accurate reference voltage. This
reference allows the ADP5072 to be sequenced easily from other
supplies. It can also be used as a programmable UVLO input by
using a resistor divider.
The boost and inverting regulators in the ADP5072 include
current-limit protection circuitry to limit the amount of forward
current through the MOSFET switch.
When the peak inductor current exceeds the overcurrent limit
threshold for a number of clock cycles during an overload or
short-circuit condition, the regulator enters hiccup mode. The
regulator stops switching and then restarts with a new soft start
cycle after tHICCUP and repeats until the overcurrent condition is
removed.
The enable pins have an internal pull-down resistor that defaults
each regulator to off when the pin is floating.
When the voltage at the enable pins is greater than the VTH_H
reference level, the regulator is enabled.
OVERVOLTAGE PROTECTION
An overvoltage protection mechanism is present on the FB1
and FB2 pins for the boost and inverting regulators.
SOFT START
Each regulator in the ADP5072 includes soft start circuitry that
ramps the output voltage in a controlled manner during startup,
thereby limiting the inrush current. The soft start time is internally
set to the fastest rate when the SS pin is open.
On the boost regulator, when the voltage on the FB1 pin exceeds
the VOV1 threshold, the switching on SW1 stops until the voltage
falls below the threshold again. This functionality is permanently
enabled on this regulator.
Connecting a resistor between SS and AGND allows the adjust-
ment of the soft start delay. The delay length is common to both
regulators.
On the inverting regulator, when the voltage on the FB2 pin
drops below the VOV2 threshold, the switching stops until the
voltage rises above the threshold. This functionality is enabled
after the soft start period has elapsed.
SLEW RATE CONTROL
The ADP5072 employs programmable output driver slew rate
control circuitry. This circuitry reduces the slew rate of the
switching node as shown in Figure 40, resulting in reduced
ringing and lower EMI. To program the slew rate, connect the
SLEW pin to the PVIN pin for normal mode, to the AGND pin
for slow mode, or leave it open for fast mode. This configuration
allows the use of an open-drain output from a noise sensitive
device to switch the slew rate from fast to slow, for example,
during ADC sampling.
THERMAL SHUTDOWN
In the event that theADP5072 junction temperature rises above
T
SHDN, the thermal shutdown circuit turns off the IC. Extreme
junction temperatures can be the result of prolonged high current
operation, poor circuit board design, and/or high ambient temper-
ature. Hysteresis is included so that when thermal shutdown occurs,
the ADP5072 does not return to operation until the on-chip
temperature drops below TSHDN minus THYS. When resuming from
thermal shutdown, a soft start is performed on each enabled
channel.
Note that slew rate control causes a trade-off between efficiency
and low EMI.
START-UP SEQUENCE
The ADP5072 implements a flexible start-up sequence to meet
different system requirements. Three different enabling modes
can be implemented via the SEQ pin, as explained in Table 7.
FASTEST
SLOWEST
Table 7. SEQ Pin Settings
SEQ Pin
Open
PVIN
Description
Manual enable mode
Simultaneous enable mode
Sequential enable mode
Low
To configure the manual enable mode, leave the SEQ pin open.
The boost and inverting regulators are controlled separately from
their respective precision enable pins.
Figure 40. Switching Node at Various Slew Rate Settings
Rev. 0 | Page 14 of 24
Data Sheet
ADP5072
V
POS
To configure the simultaneous enable mode, connect the SEQ pin
to the PVIN pin. Both regulators power up simultaneously
when the EN2 pin is taken high. The EN1 pin enable can be
used to enable the internal references ahead of enabling the
outputs, if desired. The simultaneous enable mode timing is
shown in Figure 41.
V
IN
TIME
V
POS
V
V
NEG
1. V
FOLLOWED BY V
NEG
POS
(SEQ = LOW, EN1 = HIGH, EN2 = LOW)
V
IN
POS
TIME
V
IN
TIME
V
NEG
SIMULTANEOUS ENABLE MODE
(SEQ = HIGH, EN2 = HIGH)
V
NEG
Figure 41. Simultaneous Enable Mode
2. V
FOLLOWED BY V
POS
NEG
To configure the sequential enable mode, pull the SEQ pin low.
In this mode, either VPOS or VNEG can be enabled first by using
the EN1 pin or EN2 pin. Keep the other pin low. The secondary
supply is enabled when the primary supply completes soft start and
its feedback voltage reaches approximately 85% of the target
value. The sequential enable mode timing is shown in Figure 42.
(SEQ = LOW, EN2 = HIGH, EN1 = LOW)
Figure 42. Sequential Enable Mode
Rev. 0 | Page 15 of 24
ADP5072
Data Sheet
APPLICATIONS INFORMATION
COMPONENT SELECTION
Feedback Resistors
Set the negative output for the inverting regulator by
R
R
FT2
FB2
VNEG =VFB2
where:
−
V
−VFB2
(
)
REF
The ADP5072 provides an adjustable output voltage for both boost
and inverting regulators. An external resistor divider sets the output
voltage where the divider output must equal the appropriate
feedback reference voltage, VFB1 or VFB2. To limit the output voltage
accuracy degradation due to feedback bias current, ensure that the
V
V
NEG is the negative output voltage.
FB2 is the FB2 reference voltage.
RFT2 is the feedback resistor from VNEG to FB2.
current through the divider is at least 10 times IFB1 or IFB2
.
R
V
FB2 is the feedback resistor from FB2 to VREF.
REF is the VREF pin reference voltage.
Set the positive output for the boost regulator by
FT1
R
VPOS =VFB1 × 1+
RFB1
where:
VPOS is the positive output voltage.
V
FB1 is the FB1 reference voltage.
R
R
FT1 is the feedback resistor from VPOS to FB1.
FB1 is the feedback resistor from FB1 to AGND.
Table 8. Recommended Feedback Resistor Values
Boost Regulator
Calculated
Inverting Regulator
Calculated
Desired Output
Voltage (V)
RFT1 (MΩ)
0.432
0.604
1.24
RFB1 (kΩ)
Output Voltage (V)
RFT2 (MΩ)
0.715
1.15
RFB2 (kΩ)
Output Voltage (V)
4.2
5
9
102
115
121
4.188
5.002
8.998
115
−4.174
158
−5.023
1.62
133
−8.944
12
13
15
18
20
24
30
1.4
2.1
2.43
2.15
2.55
3.09
3.65
100
137
137
100
107
107
100
12.000
13.063
14.990
18.000
19.865
23.903
30.000
1.15
2.8
2.32
2.67
2.94
3.16
4.12
71.5
162
118
113
113
−12.067
−13.027
−14.929
−18.103
−20.014
−23.984
−30.004
102
107
Rev. 0 | Page 16 of 24
Data Sheet
ADP5072
VREF Capacitor
OUTPUT CAPACITORS
A 1.0 μF ceramic capacitor (CVREF) is required between the VREF
pin and AGND.
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
the output voltage dc bias.
Soft Start Resistor
A resistor can be connected between the SS pin and the AGND pin
to increase the soft start time. The soft start time can be set by the
resistor between 4 ms (268 kΩ) and 32 ms (50 kΩ). Leaving the
SS pin open selects the fastest time of 4 ms. Figure 43 shows the
behavior of this operation. Calculate the soft start time using the
following formula:
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure the
minimum capacitance over the necessary temperature range and
dc bias conditions. X5R or X7R dielectrics with a voltage rating of
25 V or 50 V (depending on output) are recommended for optimal
performance. Y5V and Z5U dielectrics are not recommended
for use with any dc-to-dc converter because of their poor
temperature and dc bias characteristics.
tSS = 38.4 × 10−3 − 1.28 × 10−7 × RSS (ꢀ)
where 50 kꢀ ≤ RSS ≤ 268 kꢀ.
SOFT START
TIMER
Calculate the worst case capacitance accounting for capacitor
variation over temperature, component tolerance, and voltage
using the following equation:
32ms
CEFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) ×
(1 − Tolerance)
4ms
where:
SS PIN OPEN
SOFT START
RESISTOR
C
C
EFFECTIVE is the effective capacitance at the operating voltage.
NOMINAL is the nominal data sheet capacitance.
R2
R1
Figure 43. Soft Start Behavior
TEMPCO is the worst-case capacitor temperature coefficient.
DCBIASCO is the dc bias coefficient derating at the output
voltage.
Diodes
A Schottky diode with low junction capacitance is recommended
for D1 and D2, diodes for VPOS and VNEG, respectively. At higher
output voltages and especially at higher switching frequencies, the
junction capacitance is a significant contributor to efficiency.
Higher capacitance diodes also generate more switching noise. As a
guide, a diode with less than 40 pF junction capacitance is preferred
when the output voltage is greater than 5 V.
Tolerance is the worst case component tolerance.
To guarantee the performance of the device, it is imperative that
the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Capacitors with lower effective series resistance (ESR) and
effective series inductance (ESL) are preferred to minimize
output voltage ripple.
Inductor Selection for the Boost Regulator
Note that the use of large output capacitors can require a slower
soft start to prevent reaching the current limit during startup. A
10 μF capacitor is suggested as a ideal balance between perfor-
mance and size.
The inductor stores energy during the on time of the power
switch, and transfers that energy to the output through the
output rectifier during the off time. To balance the tradeoffs
between small inductor current ripple and efficiency, inductance
values in the range of 1 μH to 22 μH are recommended. In general,
lower inductance values have higher saturation current and
lower series resistance for a given physical size. However, lower
inductance results in a higher peak current that can lead to reduced
efficiency and greater input and/or output ripple and noise. A
peak-to-peak inductor ripple current close to 30% of the maximum
dc input current for the application typically yields an optimal
compromise.
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response.
To minimize supply noise, place the input capacitor as close as
possible to the AVIN pin and PVIN pin. A low ESR capacitor is
recommended.
The effective capacitance needed for stability is a minimum of 10 μF.
If the power pins are individually decoupled, it is recommended
to use a minimum of a 5.6 μF capacitor on the PVIN pin and a
3.3 μF capacitor on the AVIN pin to prevent reaching the current
limit. The minimum values specified exclude dc bias, temperature,
and tolerance effects that are application dependent and must be
taken into consideration.
Rev. 0 | Page 17 of 24
ADP5072
Data Sheet
For the inductor ripple current in continuous conduction mode
(CCM) operation, the input (VIN) and output (VPOS) voltages
determine the switch duty cycle (DUTY1) by the following
equation:
Inductor Selection for the Inverting Regulator
The inductor stores energy during the on time of the power
switch, and transfers that energy to the output through the
output rectifier during the off time. To balance the tradeoffs
between small inductor current ripple and efficiency, inductance
values in the range of 1 µH to 22 µH are recommended. In
general, lower inductance values have higher saturation current
and lower series resistance for a given physical size. However,
lower inductance results in a higher peak current that can lead
to reduced efficiency and greater input and/or output ripple and
noise. A peak-to-peak inductor ripple current close to 30% of
the maximum dc current in the inductor typically yields an
optimal compromise.
DIODE1
V
POS −VIN + V
V
DUTY =
1
POS + VDIODE1
where VDIODE1 is the forward voltage drop of the Schottky diode
(D1).
The dc input current in CCM (IIN) can be determined by the
following equation:
IOUT1
(1 − DUTY1)
IIN
=
For the inductor ripple current in continuous conduction mode
(CCM) operation, the input (VIN) and output (VNEG) voltages
determine the switch duty cycle (DUTY2) by the following
equation:
Using the duty cycle (DUTY1) and switching frequency (fSW),
determine the on time (tON1) using the following equation:
DUTY1
tON1
=
|VNEG | + VDIODE2
VIN + |VNEG | + V
fSW
The inductor ripple current (∆IL1) in steady state is calculated by
DUTY =
2
DIODE2
where VDIODE2 is the forward voltage drop of the Schottky diode
(D2).
V
IN ×tON1
∆IL1
=
The dc current in the inductor in CCM (IL2) can be determined
by the following equation:
Solve for the inductance value (L1) using the following equation:
VIN × tON1
L1 =
IOUT2
(1 − DUTY2 )
IL2
=
∆IL1
Assuming an inductor ripple current of 30% of the maximum
dc input current results in
Using the duty cycle (DUTY2) and switching frequency (fSW),
determine the on time (tON2) by the following equation:
VIN × tON1 × (1 − DUTY1 )
DUTY2
L1 =
tON2
=
0.3 × IOUT1
fSW
The inductor ripple current (∆IL2) in steady state is calculated by
Ensure that the peak inductor current (the maximum input
current plus half the inductor ripple current) is less than the
rated saturation current of the inductor. Likewise, ensure that
the maximum rated rms current of the inductor is greater than
the maximum dc input current to the regulator.
VIN ×tON2
∆IL2
=
L2
Solve for the inductance value (L2) by the following equation:
When the ADP5072 boost regulator is operated in CCM at duty
cycles greater than 50%, slope compensation is required to stabilize
the current mode loop. This slope compensation is built in to
the ADP5072. For stable current mode operation, ensure that
the selected inductance is equal to or greater than the minimum
calculated inductance, LMIN1, for the application parameters in
the following equation:
VIN × tON2
L2 =
∆IL2
Assuming an inductor ripple current of 30% of the maximum
dc current in the inductor results in
VIN × tON2 ×(1 − DUTY2 )
L2 =
0.3× IOUT2
0.13
(1 − DUTY1)
Ensure that the peak inductor current (the maximum input current
plus half the inductor ripple current) is less than the rated
saturation current of the inductor. Likewise, ensure that the
maximum rated rms current of the inductor is greater than the
maximum dc input current to the regulator.
L1 > LMIN1 =VIN
×
− 0.16 (µH)
Table 10 suggests a series of inductors to use with the ADP5072
boost regulator.
Rev. 0 | Page 18 of 24
Data Sheet
ADP5072
When the ADP5072 inverting regulator is operated in CCM at
duty cycles greater than 50%, slope compensation is required to
stabilize the current mode loop. For stable current mode operation,
ensure that the selected inductance is equal to or greater than
the minimum calculated inductance, LMIN2, for the application
parameters in the following equation:
Z
OUT1 is the impedance of the load in parallel with the output
capacitor.
To determine the crossover frequency (fC1), it is important to
note that, at that frequency, the compensation impedance (ZCOMP1
is dominated by a resistor (RC1), and the output impedance (ZOUT1
is dominated by the impedance of an output capacitor (COUT1).
Therefore, when solving for the crossover frequency, the equation
(by definition of the crossover frequency) is simplified to
)
)
0.13
(1 − DUTY2 )
L2 > LMIN2 =VIN
×
− 0.16 (µH)
VFB1 VIN
VPOS VPOS
AVL1
=
×
× gM1 × RC1 × gCS1 ×
Table 11 suggests a series of inductors to use with the ADP5072
inverting regulator.
1
=1
LOOP COMPENSATION
2π × fC1 ×COUT1
The ADP5072 uses external components to compensate the
regulator loop, allowing the optimization of the loop dynamics
for a given application.
where fC1 is the crossover frequency.
To solve for RC1, use the following equation:
2
Boost Regulator
2π × fC1 ×COUT1 ×(VPOS
)
RC1
=
VFB1 ×VIN × gM1 × gCS1
The boost converter produces an undesirable right half plane
zero in the regulation feedback loop. This feedback loop requires
compensating the regulator such that the crossover frequency
occurs well below the frequency of the right half plane zero. The
right half plane zero is determined by the following equation:
where gCS1 = 6.25 A/V.
Using typical values for VFB1 and GM1 results in
2
4188 × fC1 ×COUT1 ×(VPOS
)
RC1
=
R
LOAD1(1 − DUTY1)2
2π × L1
VIN
fZ1(RHP) =
For improved accuracy, it is recommended to use the value of the
output capacitance, COUT1, expected for the dc bias conditions
under which it operates in the calculation for RC1.
where:
fZ1(RHP) is the right half plane zero frequency.
LOAD1 is the equivalent load resistance or the output voltage
divided by the load current.
R
After the compensation resistor is known, set the zero formed
by the compensation capacitor and resistor, CC1 and RC1, to one-
fourth of the crossover frequency, or
DIODE1
VPOS −VIN + V
DUTY =
1
2
VPOS + VDIODE1
CC1
=
π × fC1 × RC1
where VDIODE1 is the forward voltage drop of the Schottky
diode (D1).
where CC1 is the compensation capacitor value.
ERROR
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-tenth of the right half
plane zero frequency.
AMPLIFIER
FB1
COMP1
g
M1
REF1
R
C1
The boost regulator loop gain is
C
C1
VFB1 VIN
VPOS VPOS
AVL1
=
×
× gM1 × ROUT1 ||Z COMP1 × gCS1 × ZOUT1
Figure 44. Compensation Components
where:
A
V
V
V
VL1 is the loop gain.
FB1 is the feedback regulation voltage
POS is the regulated positive output voltage.
IN is the input voltage.
gM1 is the error amplifier transconductance gain.
R
Z
OUT1 is the output impedance of the error amplifier and is 33 MΩ.
COMP1 is the impedance of the series resistor/capacitor (RC)
network from COMP1 to AGND.
CS1 is the current sense transconductance gain (the inductor
g
current divided by the voltage at COMP1), which is internally
set by the ADP5072 and is 6.25 A/V.
Rev. 0 | Page 19 of 24
ADP5072
Data Sheet
Inverting Regulator
To determine the crossover frequency, it is important to note
that, at that frequency, the compensation impedance (ZCOMP2) is
The inverting converter, like the boost converter, produces an
undesirable right half plane zero in the regulation feedback loop.
This feedback loop requires compensating the regulator such that
the crossover frequency occurs well below the frequency of the
right half plane zero. The right half plane zero frequency is
determined by the following equation:
dominated by a resistor, RC2, and the output impedance (ZOUT2
)
is dominated by the impedance of the output capacitor, COUT2
.
Therefore, when solving for the crossover frequency, the equation
(by definition of the crossover frequency) is simplified to
VFB2
VIN
AVL2
=
×
× gM2
×
LOAD2(1 − DUTY2 )2
|VNEG | (VIN + 2 ×|VNEG|)
R
fZ2(RHP) =
1
2π × L2 × DUTY2
RC2 × gCS2 ×
=1
2π × fC2 ×COUT2
where fC2 is the crossover frequency.
To solve for RC2, use the following equation:
2π × fC2 ×COUT2 ×|VNEG |×(VIN + (2 ×|VNEG|)
where:
fZ2(RHP) is the right half plane zero frequency.
LOAD2 is the equivalent load resistance or the output voltage
divided by the load current.
R
RC2
=
|VNEG | + VDIODE2
VIN + |VNEG | + VDIODE2
VFB2 ×VIN × gM2 × gCS2
DUTY =
2
where GCS2 = 6.25 A /V.
where VDIODE2 is the forward voltage drop of the Schottky diode
(D2).
Using typical values for VFB2 and GM2 results in
4188× fC2 ×COUT2×|VNEG|×(VIN + (2 ×|VNEG|)
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-tenth of the right half
plane zero frequency.
RC2
=
VIN
For improved accuracy, it is recommended to use the value of the
output capacitance, COUT2, expected for the dc bias conditions
under which it operates in the calculation for RC2.
The inverting regulator loop gain is
VFB2
|VNEG
VIN
AVL2
=
×
× gM2 ×
After the compensation resistor is known, set the zero formed
by the compensation capacitor and resistor, CC2 and RC2, to one-
fourth of the crossover frequency, or
|
(VIN + 2 ×|VNEG|)
ROUT2 ||ZCOMP2 × gCS2 × ZOUT2
2
CC2
=
where:
π × fC2 × RC2
A
V
V
V
VL2 is the loop gain.
where CC2 is the compensation capacitor.
FB2 is the feedback regulation voltage.
NEG is the regulated negative output voltage.
IN is the input voltage.
ERROR
AMPLIFIER
FB2
COMP2
g
M2
gM2 is the error amplifier transconductance gain.
REF2
R
C2
ROUT2 is the output impedance of the error amplifier and is 33 MΩ.
Z
COMP2 is the impedance of the series RC network from COMP2
C
C2
to AGND.
CS2 is the current sense transconductance gain (the inductor
g
Figure 45. Compensation Component
current divided by the voltage at COMP2), which is internally
set by the ADP5072 and is 6.25 A /V.
ZOUT2 is the impedance of the load in parallel with the output
capacitor.
Rev. 0 | Page 20 of 24
Data Sheet
ADP5072
Figure 47 shows the efficiency curves for the boost and
COMMON APPLICATIONS
inverting regulator using the recommended, small size
components described in Table 9, Table 10, and Table 11
for VPOS = 15 V and VNEG = −15 V at VIN = 5 V.
100
Table 9 through Table 11 list a number of common component
selections for typical VIN, VPOS, and VNEG conditions. These
components have been bench tested and are recommended for
customer applications that are suited for these conditions. Note that
when pairing a boost and inverting regulator bill of materials,
choose the same VIN and switching frequency.
V
V
V
V
= +15V, 1.2MHz
= –15V, 1.2MHz
= +15V, 2.4MHz
= –15V, 2.4MHz
POS
NEG
POS
NEG
90
80
70
60
50
40
30
20
10
V
IN
+5V
ADP5072
R
SS
C1
L1
3.3µH
102kΩ
V
D1
POS
COMP1
EN1
PD3S140
+15V
C
C1
1nF
ON
SW1
SW1
FB1
OFF
R
FT1
2.43MΩ
C
OUT1
10µF
R
FB1
137kΩ
0
PVIN
PVIN
AVIN
0.001
0.01
0.1
1
V
IN
+5V
PGND
PGND
VREF
LOAD CURRENT (A)
C
10µF
C
IN
VREF
1µF
Figure 47. Efficiency vs. Load Current for Boost Regulator and Inverting
Regulator, TA = 25°C
ON
OFF
EN2
R
FB2
C
OUT2
10µF
R
C2
61.9kΩ
118kΩ
Table 10 and Table 11 are based on the smallest sized components.
The maximum output current is limited by the ISAT rating of the
2 mm × 2 mm inductor. A higher output current is possible by
using larger inductors with higher ISAT ratings, as long as the
inductor peak current remains below the appropriate current
limit specifications.
FB2
COMP2
R
FT2
V
C
IN
C2
2.32MΩ
SYNC
SLEW
SEQ
+5V
2.2nF
SW2
V
NEG
D2
PD3S140
L2
6.8µF
–15V
AGND
Figure 46. Typical +5 V to 15 V Application
It is important to verify the thermal performance of the small
sized inductor at higher ambient temperature in actual application.
Figure 46 shows the schematic referenced by Table 9 through
Table 11 with example component values for 5 V input voltage
to 15 V output voltage generation. Table 9 shows the
components common to all of the VIN, VPOS, and VNEG
conditions.
Table 9. Recommended Common Components Selections
Reference Designator
Description
Value (µF)
Part Number
Manufacturer
Murata
Murata
CIN
CVREF
Input capacitor on PVIN
VREF capacitor
10
1
GRM21BZ71C106KE15L
GRM188R71C105KA12C
Rev. 0 | Page 21 of 24
ADP5072
Data Sheet
Table 10. Recommended Boost Regulator Small Sized Components
VIN VPOS ILOAD1 (MAX)
Freq.
L1
L1 Manufacturer Part No.
COUT1
(µF)
RFT1
RFB1
CC1
RC1
(V) (V)
(mA)
340
360
180
200
100
110
50
(MHz) (µH) (Coilcraft)
C
OUT1, Murata Part No.
D1
(MΩ) (kΩ) (nF) (kΩ)
3.3
3.3
3.3
3.3
5
5
9
9
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
3.3
2.2
4.7
3.3
4.7
4.7
6.8
6.8
3.3
2.2
4.7
3.3
10
EPL2014-332ML_
EPL2014-222ML_
EPL2014-472ML_
EPL2014-332ML_
EPL2014-472ML_
EPL2014-472ML_
EPL2014-682ML_
EPL2014-682ML_
EPL2014-332ML_
EPL2014-222ML_
EPL2014-472ML_
EPL2014-332ML_
EPL2014-103ML_
EPL2014-682ML_
EPL2014-103ML_
EPL2014-822ML_
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
GRM21BR71A106KA73L
GRM21BR71A106KA73L
GRM21BZ71C106KE15L
GRM21BZ71C106KE15L
GRM31CR71E106MA12L PD3S140
GRM31CR71E106MA12L PD3S140
GRM32ER7YA106MA12L PD3S140
GRM32ER7YA106MA12L PD3S140
GRM21BZ71C106KE15L
GRM21BZ71C106KE15L
GRM31CR71E106MA12L PD3S140
GRM31CR71E106MA12L PD3S140
GRM32ER7YA106MA12L PD3S140
GRM32ER7YA106MA12L PD3S140
PMEG2005AELD 0.604 115
PMEG2005AELD 0.604 115
PMEG2005AELD 1.24
PMEG2005AELD 1.24
0.82 15.8
0.47 29.4
1.2
121
121
137
137
107
107
121
121
137
137
107
107
102
102
26.1
0.82 17.4
3.3 15
3.3 15
3.3 24
3.3 24
2.43
2.43
3.09
3.09
1.5
1.2
1.8
1.8
0.56 16.9
0.39 18.7
14.3
16.9
28.7
16.2
55
5
5
5
5
5
5
5
5
9
140
280
110
170
50
80
40
45
PMEG2005AELD 1.24
PMEG2005AELD 1.24
9
15
15
24
24
34
34
2.43
2.43
3.09
3.09
4.22
4.22
1
18.2
0.56 20.5
1.8
1.2
1.5
1.2
15.8
10
25.5
18.2
6.8
10
8.2
GRM32ER71H106KA12L
GRM32ER71H106KA12L
PD3S140
PD3S140
Table 11. Recommended Inverting Regulator Small Sized Components
VIN VNEG ILOAD2 (MAX)
Freq.
L2
L2 Manufacturer Part No.
COUT2
(µF)
RFT2
RFB2
CC2
RC2
(V) (V)
3.3 −5
3.3 −5
3.3 −9
3.3 −9
3.3 −15
3.3 −15
3.3 −24
3.3 −24
(mA)
120
130
70
(MHz) (µH) (Coilcraft)
C
OUT2, Murata Part No.
D2
(MΩ) (kΩ) (nF) (kΩ)
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
6.8
4.7
4.7
4.7
8.2
6.8
10
6.8
8.2
6.8
8.2
8.2
10
EPL2014-682ML_
EPL2014-472ML_
EPL2014-472ML_
EPL2014-472ML_
EPL2014-822ML_
EPL2014-682ML_
EPL2014-103ML_
EPL2014-682ML_
EPL2014-822ML_
EPL2014-682ML_
EPL3015-822ML_
EPL2014-822ML_
EPL3015-103ML_
EPL2014-103ML_
EPL3015-103ML_
EPL2014-822ML_
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
GRM21BR71A106KA73L
GRM21BR71A106KA73L
GRM21BZ71C106KE15L
GRM21BZ71C106KE15L
PMEG2005AELD 1.15
PMEG2005AELD 1.15
PMEG2005AELD 1.62
PMEG2005AELD 1.62
158
158
133
133
118
118
102
102
133
133
118
118
102
102
75
8.2
3.3
3.9
1.8
3.3
2.2
3.3
1.5
5.6
2.2
4.7
1.8
4.7
2.2
3.9
1.2
7.5
10.5
8.06
8.06
10.5
8.25
10.5
14.3
4.87
10
10
13.3
10
7.15
15.8
1.2
90
50
55
30
30
GRM31CR71E106MA12L PD3S140
GRM31CR71E106MA12L PD3S140
GRM32ER7YA106MA12L PD3S140
GRM32ER7YA106MA12L PD3S140
GRM21BZ71C106KE15L
GRM21BZ71C106KE15L
GRM31CR71E106MA12L PD3S140
GRM31CR71E106MA12L PD3S140
GRM32ER7YA106MA12L PD3S140
GRM32ER7YA106MA12L PD3S140
GRM32ER71H106KA12L
GRM32ER71H106KA12L
2.32
2.32
3.16
3.16
5
5
5
5
5
5
5
5
−9
−9
90
120
60
80
40
50
30
35
PMEG2005AELD 1.62
PMEG2005AELD 1.62
−15
−15
−24
−24
−30
−30
2.32
2.32
3.16
3.16
4.99
4.99
10
10
8.2
PD3S140
PD3S140
75
Rev. 0 | Page 22 of 24
Data Sheet
ADP5072
optimum output voltage sensing, or route traces to the RFT1
and RFT2 resistors as close as possible from the top of
COUT1 and COUT2.
Place the compensation components as close as possible
to COMP1 and COMP2. Do not share vias to the ground
plane with the feedback resistors to avoid coupling high
frequency noise into the sensitive COMP1 and COMP2 pins.
Place the CVREF capacitor as close to the VREF pin as
possible. Ensure that short traces are used between VREF
and RFB2.
LAYOUT CONSIDERATIONS
Layout is important for all switching regulators but is particularly
important for regulators with high switching frequencies. To
achieve high efficiency, proper regulation, stability, and low
noise, a well designed PCB layout is required. Follow these
guidelines when designing PCBs (see Figure 48):
•
•
•
Keep the input bypass capacitor, CIN, close to the PVIN pin
and the AVIN pin.
•
Keep the high current paths as short as possible. These
paths include the connections between the following:
•
•
•
CIN, L1, D1, COUT1, and PGND for the boost
regulator, the connections
L2, D2, COUT2, and PGND for the inverting
regulator
The connections of these components for both the
boost and inverting regulators to the ADP5072.
•
Keep AGND and PGND separate on the top layer of the
board. This separation avoids pollution of AGND with
switching noise. Connect both AGND and PGND to the
board ground plane with vias. Ideally, connect PGND to the
plane at a point between the input and output capacitors.
Keep high current traces as short and wide as possible to
minimize parasitic series inductance, which causes spiking
and EMI.
•
•
Figure 48. Suggested Layout for VIN = 3.3 V, VPOS = 12 V, ILOAD1 = 100 mA and
NEG = −3.2 V, ILOAD2 = 60 mA; Not to Scale
Avoid routing high impedance traces near any node con-
nected to the SW1 and SW2 pins or near Inductors L1and
L2 to prevent radiated switching noise injection.
V
•
•
Place the feedback resistors as close to the FB1 and FB2 pins as
possible to prevent high frequency switching noise injection.
Place the top of the upper feedback resistors, RFT1 and RFT2,
as close as possible to the top of COUT1 and COUT2 for
Rev. 0 | Page 23 of 24
ADP5072
Data Sheet
OUTLINE DIMENSIONS
1.650
1.610
1.570
0.310
0.290
0.270
4
3
2
1
A
B
BALL A1
IDENTIFIER
2.220
2.180
2.140
1.60 REF
C
D
E
0.40
BSC
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
0.225
1.20 REF
0.205
0.185
0.330
0.300
0.270
0.560
0.500
0.440
SIDE VIEW
COPLANARITY
0.04
0.300
0.260
0.220
SEATING
PLANE
0.230
0.200
0.170
Figure 49. 20-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-20-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADP5072ACBZ-R7
ADP5072CB-EVALZ
−40°C to +125°C
20-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
CB-20-14
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16646-0-1/19(0)
Rev. 0 | Page 24 of 24
相关型号：
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ADP5076ACBZ-R7
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