ADRF5731BCCZN [ADI]
2 dB LSB, 4-Bit, Silicon Digital Attenuator,;
| 型号： | ADRF5731BCCZN |
| 厂家： | 
ADI |
| 描述： | 2 dB LSB, 4-Bit, Silicon Digital Attenuator, |
| 文件： | 总17页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 dB LSB, 4-Bit, Silicon Digital Attenuator,
100 MHz to 40 GHz
Data Sheet
ADRF5731
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADRF5731
Ultrawideband frequency range: 100 MHz to 40 GHz
Attenuation range: 2 dB steps to 30 dB
Low insertion loss
1.7 dB to 18 GHz
2.2 dB to 26 GHz
16 15
14
13
3.5 dB to 40 GHz
Attenuation accuracy
± ±0.1 + 2.0%) of attenuation state up to 18 GHz
± ±0.2 + 2.5%) of attenuation state up to 26 GHz
± ±0.5 + 10.0%) of attenuation state up to 40 GHz
Typical step error
1
2
12
11
10
9
VDD
D4/SERIN
D5/CLK
GND
SERIAL/
PARALLEL
INTERFACE
VSS
3
4
GND
4-BIT DIGITAL
ATTENUATOR
ATTOUT
ATTIN
5
6
7
8
± 0.15 dB to 18 GHz
PACKAGE
BASE
± 0.20 dB to 26 GHz
± 0.60 dB to 40 GHz
Figure 1.
High input linearity
P0.1dB insertion loss state: 30 dBm
P0.1dB other attenuation states: 26 dBm
IP3: 50 dBm typical
High RF input power handling: 26 dBm average, 30 dBm peak
Tight distribution in relative phase
No low frequency spurious signals
SPI and parallel mode control, CMOS/LVTTL compatible
RF amplitude settling time ±0.1 dB of final RF output): 230 ns
2.5 mm × 2.5 mm, 16-terminal LGA package
Pin compatible with ADRF5721, low frequency cutoff version
APPLICATIONS
Industrial scanners
Test and instrumentation
Cellular infrastructure: 5G millimeter wave
Military radios, radars, electronic counter measures ±ECMs)
Microwave radios and very small aperture terminals ±VSATs)
GENERAL DESCRIPTION
The ADRF5731 is a silicon, 4-bit digital attenuator with a 30 dB
attenuation control range in 2 dB steps.
The ADRF5731 is pin compatible with the ADRF5721 low
frequency cutoff version, which operates from 9 kHz to 40 GHz.
This device operates from 100 MHz to 40 GHz with better than
3.5 dB of insertion loss. The ATTIN port of the ADRF5720 has
a radio frequency (RF) input power handling capability of 26 dBm
average and 30 dBm peak for all states.
The ADRF5731 RF ports are designed to match a characteristic
impedance of 50 Ω.
The ADRF5731 comes in a 16-terminal, 2.5 mm × 2.5 mm,
RoHS compliant, land grid array (LGA) package and operates
from −40°C to +105°C.
The ADRF5731 requires a dual supply voltage of +3.3 V and
−3.3 V. The device features serial peripheral interface (SPI),
parallel mode control, and complementary metal-oxide
semiconductor (CMOS)-/low voltage transistor to transistor
logic (LVTTL) compatible controls.
Rev. 0
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Tel: 781.329.4700
Technical Support
©2018 Analog Devices, Inc. All rights reserved.
www.analog.com
ADRF5731
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Power Compression and Third-Order Intercept......... 10
Theory of Operation ...................................................................... 11
Power Supply............................................................................... 11
RF Input and Output ................................................................. 11
Serial or Parallel Mode Selection ............................................. 11
Serial Mode Interface................................................................. 12
Using SEROUT........................................................................... 12
Parallel Mode Interface.............................................................. 13
Applications Information.............................................................. 14
Evaluation Board........................................................................ 14
Probe Matrix Board ................................................................... 16
Packaging and Ordering Information ......................................... 17
Outline Dimensions................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ....................................................... 6
Thermal Resistance ...................................................................... 6
Power Derating Curves................................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Interface Schematics..................................................................... 7
Typical Performance Characteristics ............................................. 8
Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase................................................................................ 8
REVISION HISTORY
9/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 17
Data Sheet
ADRF5731
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.3 V, VSS = −3.3 V, digital voltages = 0 V or VDD, case temperature (TCASE) = 25°C, and a 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RANGE
INSERTION LOSS (IL)
100
40,000 MHz
100 MHz to 10 GHz
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
1.3
1.7
2.2
2.8
3.5
dB
dB
dB
dB
dB
RETURN LOSS
ATTIN and ATTOUT, all attenuation states
100 MHz to 10 GHz
10 GHz to 18 GHz
22
22
16
15
14
dB
dB
dB
dB
dB
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
ATTENUATION
Range
Between minimum and maximum attenuation
states
Between any successive attenuation states
Referenced to insertion loss
100 MHz to 10 GHz
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
30
2
dB
dB
Step Size
Accuracy
(0.05 + 1.0%)
dB
dB
dB
dB
dB
(0.1 + 2.0%)
(0.2 + 2.5%)
(0.2 + 6.0%)
(0.5 + 10.0%)
Step Error
Between any successive attenuation states
100 MHz to 10 GHz
0.05
0.15
0.20
0.35
0.60
dB
dB
dB
dB
dB
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
RELATIVE PHASE
Referenced to insertion loss
100 MHz to 10 GHz
15
Degrees
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
25
40
55
80
Degrees
Degrees
Degrees
Degrees
SWITCHING CHARACTERISTICS
Rise and Fall Time (tRISE and tFALL
All attenuation states at input power (PIN) = 10 dBm
10% to 90% of RF output
50% triggered control (CTL) to 90% of RF output
)
35
110
ns
ns
On and Off Time (tON and tOFF
)
RF Amplitude Settling Time
0.1 dB
0.05 dB
Overshoot
Undershoot
50% triggered CTL to 0.1 dB of final RF output
50% triggered CTL to 0.05 dB of final RF output
230
250
0.5
−1
ns
ns
dB
dB
RF Phase Settling Time
f = 5 GHz
5°
1°
50% triggered CTL to 5° of final RF output
50% triggered CTL to 1°of final RF output
100
125
ns
ns
Rev. 0 | Page 3 of 17
ADRF5731
Data Sheet
Parameter
INPUT LINEARITY1
Test Conditions/Comments
Min
Typ
Max
Unit
10 MHz to 30 GHz
0.1 dB Power Compression (P0.1dB)
Insertion Loss State
Other Attenuation States
Third-Order Intercept (IP3)
30
26
50
dBm
dBm
dBm
Two-tone input power = 14 dBm per tone,
Δf = 1 MHz, all attenuation states
DIGITAL CONTROL INPUTS
Voltage
LE, PS, D2, D3/SEROUT,2 D4/SERIN, D5/CLK pins
Low (VINL
High (VINH
Current
Low (IINL
High (IINH
)
0
1.2
0.8
3.3
V
V
)
)
<1
33
<1
μA
μA
μA
)
D2
LE, PS, D3/SEROUT,2 D4/SERIN, D5/CLK pins
D3/SEROUT pin2
DIGITAL CONTROL OUTPUT
Voltage
Low (VOUTL
)
0
0.3
V
High (VOUTH
)
VDD 0.3
V
Low and High Current (IOUTL, IOUTH
SUPPLY CURRENT
Positive
)
0.5
mA
VDD and VSS pins
117
−117
μA
μA
Negative
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Positive (VDD
Negative (VSS)
Digital Control Voltage
)
3.15
−3.45
0
3.45
−3.15
VDD
V
V
V
RF Input Power3
ATTIN
f = 10 MHz to 30 GHz, TCASE = 85°C,4
all attenuation states
Steady state average
Steady state peak
Hot switching average
Hot switching peak
Steady state average
Steady state peak
Hot switching average
Hot switching peak
26
30
24
27
18
21
15
18
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
°C
ATTOUT (Bidirectional Use)
Case Temperature (TCASE
)
−40
+105
1 Input linearity performance degrades over frequency (see Figure 20 and Figure 21).
2 The D3/SEROUT pin is an input in parallel control mode and an output in serial control mode. See Table 5 for the pin function descriptions.
3 For power derating over frequency, see Figure 2 and Figure 3. Applicable for all ATTIN and ATTOUT power specifications.
4 For 105°C operation, the power handling degrades from the TCASE = 85°C specifications by 3 dB.
Rev. 0 | Page 4 of 17
Data Sheet
ADRF5731
TIMING SPECIFICATIONS
See Figure 24, Figure 25, and Figure 26 for the timing diagrams.
Table 2.
Parameter
Description
Min
70
15
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCK
tCS
tCH
tLN
tLEW
tLES
tCKN
tPH
Minimum serial period, see Figure 24
Control setup time, see Figure 24
Control hold time, see Figure 24
LE setup time, see Figure 24
Minimum LE pulse width, see Figure 24 and Figure 26
Minimum LE pulse spacing, see Figure 24
Serial clock hold time from LE, see Figure 24
Hold time, see Figure 26
20
15
10
630
0
10
2
tPS
tCO
Setup time, see Figure 26
Clock to output (SEROUT) time, see Figure 25
20
Rev. 0 | Page 5 of 17
ADRF5731
Data Sheet
ABSOLUTE MAXIMUM RATINGS
POWER DERATING CURVES
Table 3.
Parameter
2
Rating
0
–2
Positive Supply Voltage (VDD)
Negative Supply Voltage (VSS)
Digital Control Input Voltage
RF Input Power1 (f = 10 MHz to 30 GHz,
−0.3 V to +3.6 V
−3.6 V to +0.3 V
−0.3 V to VDD + 0.3 V
–4
T
CASE = 85°C2)
ATTIN
Steady State Average
–6
–8
27 dBm
31 dBm
25 dBm
28 dBm
–10
–12
–14
–16
Steady State Peak
Hot Switching Average
Hot Switching Peak
ATTOUT
Steady State Average
Steady State Peak
Hot Switching Average
Hot Switching Peak
19 dBm
22 dBm
16 dBm
19 dBm
1k
10k
100k
1M
10M
100M
1G
10G
100G
FREQUENCY (Hz)
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85°C
2
Temperature
Junction (TJ)
Storage
Reflow
0
–2
135°C
−65°C to +150°C
260°C
–4
Continuous Power Dissipation (PDISS
)
0.5 W
–6
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
ATTIN and ATTOUT Pins
Digital Pins
–8
–10
–12
–14
500 V
2000 V
1250 V
Charged Device Model (CDM)
1 For power derating over frequency, see Figure 2 and Figure 3. Applicable for
all ATTIN and ATTOUT power specifications.
–16
26 28 30 32 34 36 38 40 42 44 46 48 50
2 For 105°C operation, the power handling derates from the TCASE = 85°C
specifications by 3 dB.
FREQUENCY (GHz)
Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θ
JC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 4. Thermal Resistance
Package Type
θJC
Unit
CC-16-6
100
°C/W
Rev. 0 | Page 6 of 17
Data Sheet
ADRF5731
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16 15
14
13
1
2
3
4
12
11
10
9
VDD
D4/SERIN
D5/CLK
GND
VSS
ADRF5731
TOP VIEW
(Not to Scale)
GND
ATTOUT
ATTIN
5
6
8
7
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO THE RF AND DC GROUND OF THE PCB.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
D4/SERIN
D5/CLK
Parallel Control Input for 8 dB Attenuator Bit (D4).
Serial Data Input (SERIN). See the Theory of Operation section for more information.
Parallel Control Input for 16 dB Attenuator Bit (D5).
2
Serial Clock Input (CLK). See the Theory of Operation section for more information.
Ground. These pins must be connected to the RF and dc ground of the PCB.
Attenuator Input. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is needed
when the RF line potential is equal to 0 V dc.
3, 5 to 8, 10
4
GND
ATTIN
9
ATTOUT
Attenuator Output. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is needed
when the RF line potential is equal to 0 V dc.
11
12
13
14
15
16
VSS
VDD
LE
PS
D2
Negative Supply Input.
Positive Supply Input.
Latch Enable Input. See the Theory of Operation section for more information.
Parallel or Serial Control Interface Selection Input. See the Theory of Operation section for more information.
Parallel Control Input for 2 dB Attenuator Bit. See the Theory of Operation section for more information.
D3/SEROUT Parallel Control Input for 4 dB Attenuator Bit (D3).
Serial Data Output (SEROUT). See the Theory of Operation section for more information.
17
EPAD
Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.
INTERFACE SCHEMATICS
VDD
VDD
VDD
VDD
LE, PS, D3/SEROUT,
D4/SERIN, D5/CLK
D2
100kΩ
Figure 5. Digital Input Interface Schematic for LE, PS, D3/SEROUT, D4/SERIN,
and D5/CLK
Figure 7. Digital Input Interface Schematic for D2
ATTIN,
ATTOUT
Figure 6. ATTIN and ATTOUT Interface Schematic
Rev. 0 | Page 7 of 17
ADRF5731
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE
VDD = 3.3 V, VSS = −3.3 V, digital voltages = 0 V or VDD, TCASE = 25°C, and a 50 Ω system, unless otherwise noted. Measured on probe
matrix board using ground signal ground (GSG) probes close to the RF pins (ATTIN and ATTOUT). See the Applications Information
section for details on evaluation and probe matrix boards.
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
STATE 0dB
STATE 4dB
STATE 16dB
STATE 2dB
STATE 8dB
STATE 30dB
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–40°C
+25°C
+85°C
+105°C
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Insertion Loss vs. Frequency over Temperature
Figure 11. Output Return Loss vs. Frequency (Major States Only)
0
1.5
–5
1.0
0.5
0
–10
–15
–20
–25
–30
–35
–0.5
STATE 0dB
STATE 4dB
STATE 16dB
STATE 2dB
STATE 8dB
STATE 30dB
–1.0
–1.5
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Normalized Attenuation vs. Frequency for All States at Room
Temperature
Figure 12. Step Error vs. Frequency (Major States Only)
0
1.5
1.0
–5
–10
–15
–20
–25
–30
–35
–40
0.5
0
–0.5
–1.0
–1.5
5GHz
10GHz
25GHz
40GHz
15GHz
30GHz
45GHz
STATE 0dB
STATE 4dB
STATE 16dB
STATE 2dB
STATE 8dB
STATE 30dB
20GHz
35GHz
–45
–50
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
ATTENUATION STATE
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
Figure 13. Step Error vs. Attenuation State over Frequency
Figure 10. Input Return Loss vs. Frequency (Major States Only)
Rev. 0 | Page 8 of 17
Data Sheet
ADRF5731
9
100
90
80
70
60
50
40
30
20
10
0
STATE 0dB
STATE 4dB
STATE 16dB
STATE 2dB
STATE 8dB
STATE 30dB
8
7
STATE 0dB
STATE 4dB
STATE 16dB
STATE 2dB
STATE 8dB
STATE 30dB
6
5
4
3
2
1
0
–1
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. State Error vs. Frequency (Major States Only)
Figure 16. Relative Phase vs. Frequency (Major States Only)
9
100
90
80
70
60
50
40
30
20
10
0
5GHz
20GHz
35GHz
10GHz
25GHz
40GHz
15GHz
30GHz
45GHz
5GHz
20GHz
35GHz
10GHz
25GHz
40GHz
15GHz
30GHz
45GHz
8
7
6
5
4
3
2
1
0
–1
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
ATTENUATION STATE
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
ATTENUATION STATE
Figure 15. State Error vs. Attenuation State over Frequency
Figure 17. Relative Phase vs. Attenuation State over Frequency
Rev. 0 | Page 9 of 17
ADRF5731
Data Sheet
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
35
30
25
20
15
10
5
35
30
25
20
15
10
STATE 0dB
STATE 4dB
STATE 16dB
STATE 2dB
STATE 8dB
STATE 30dB
STATE 0dB
STATE 4dB
STATE 16dB
STATE 2dB
STATE 8dB
STATE 30dB
5
0
0
10k
100k
1M
10M
100M
1G
0
5
10
15
20
25
30
35
40
FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 18. Input P0.1dB vs. Frequency (Major States Only)
Figure 20. Input P0.1dB vs. Frequency (Major States Only), Low Frequency Detail
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
STATE 0dB
STATE 4dB
STATE 16dB
STATE 2dB
STATE 8dB
STATE 30dB
STATE 0dB
STATE 4dB
STATE 16dB
STATE 2dB
STATE 8dB
STATE 30dB
10
0
0
5
10
15
20
25
30
35
40
10k
100k
1M
10M
100M
1G
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 21. Input IP3 vs. Frequency (Major States Only), Low Frequency Detail
Figure 19. Input IP3 vs. Frequency (Major States Only)
Rev. 0 | Page 10 of 17
Data Sheet
ADRF5731
THEORY OF OPERATION
The ADRF5731 incorporates a 4-bit fixed attenuator array that
offers an attenuation range of 30 dB in 2 dB steps. An integrated
driver provides both serial and parallel mode control of the
attenuator array (see Figure 22).
RF INPUT AND OUTPUT
Both RF ports (ATTIN and ATTOUT) are dc-coupled to 0 V.
DC blocking is not required at the RF ports when the RF line
potential is equal to 0 V.
Note that when referring to a single function of a multifunction
pin in this section, only the portion of the pin name that is
relevant is mentioned. For full pin names of the multifunction
pins, refer to the Pin Configuration and Function Descriptions
section.
The RF ports are internally matched to 50 Ω. Therefore,
external matching components are not required.
The ADRF5731 supports bidirectional operation at a lower
power level. The power handling of the ATTIN and ATTOUT
ports are different. Therefore, the bidirectional power handling
is defined by the ATTOUT port. Refer to the RF input power
specifications in Table 1.
POWER SUPPLY
The ADRF5731 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
filter high frequency noise.
SERIAL OR PARALLEL MODE SELECTION
The ADRF5731 can be controlled in either serial or parallel
mode by setting the PS pin to high or low, respectively (see
Table 6).
The power-up sequence is as follows:
1. Power up GND.
2. Power up VDD.
3. Power up VSS.
4. Apply the digital control inputs. The relative order of the
digital control inputs is not important. However, powering
the digital control inputs before the VDD supply can
inadvertently forward bias and damage the internal ESD
protection structures.
Table 6. Mode Selection
PS
Control Mode
Low
High
Parallel
Serial
5. Apply an RF input signal to ATTIN or ATTOUT.
The power-down sequence is the reverse order of the power up
sequence.
Table 7. Truth Table
Digital Control Input1
D5
D4
D3
D2
D1
D0
Attenuation State (dB)
Low
Low
Low
Low
High
High
Low
Low
Low
High
Low
High
Low
Low
High
Low
Low
High
Low
High
Low
Low
Low
High
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
0 (reference)
2
4
8
16
30
1 Any combination of the control voltage input states shown in Table 7 provides an attenuation equal to the sum of the bits selected.
D2
D3
D4
D5
SERIN
CLK
PS
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D Q
SEROUT
PARALLEL OR SERIAL SELECT
6-BIT OR 8-BIT LATCH
LE
RF
INPUT
RF
OUTPUT
2dB
4dB
8dB
16dB
Figure 22. Simplified Circuit Diagram
Rev. 0 | Page 11 of 17
ADRF5731
Data Sheet
When using the attenuator in a daisy-chain operation, 8-bit
SERIN data must be used due to the 8-clock cycle delay
between SERIN and SEROUT.
SERIAL MODE INTERFACE
The ADRF5731 supports a 3-wire SPI: serial data input (SERIN),
clock (CLK), and latch enable (LE). The serial control interface
is activated when PS is set to high.
It is optional to use a 1 kΩ resistor between SEROUT on the
first attenuator and SERIN of the next attenuator to filter the
signal (see Figure 23).
The ADRF5731 attenuation state is controlled by Bits[D5:D2].
Bit D0 and Bit D1 are don't care bits but must be input.
Therefore, at least a 6-bit SERIN must be used to control the
attenuation states. If using an 8-bit word to control the state of the
attenuator, [D7:D6] and [D1:D0] are don’t care bits. It does not
matter if these bits are held low or high. Refer to Table 7 and
Figure 24 for additional information.
4
3
2
In serial mode, the SERIN data is clocked most significant bit
(MSB) first on the rising CLK edges into the shift register. Then,
LE must be toggled high to latch the new attenuation state into
the device. LE must be set to low to clock new SERIN data into
the shift register as CLK is masked to prevent the attenuator
value from changing if LE is kept high. See Figure 24 in
conjunction with Table 2 and Table 7.
1
WITHOUT 1kΩ
WITH 1kΩ
0
0
50
100 150 200 250 300 350 400 450 500
TIME (ns)
USING SEROUT
Figure 23. Using a Resistor on SEROUT
The ADRF5731 also features a serial data output, SEROUT.
SEROUT outputs the serial input data at the eighth clock cycle
and can control a cascaded attenuator using a single SPI bus.
Figure 25 shows the serial output timing diagram.
[FIRST IN]
[LAST IN]
DON’T CARE
DON’T
CARE
PS
X
OPTIONAL OPTIONAL
MSB
D5
LSB
D2
tCS tCH
D[7:0]
NEXT WORD
SERIN
X
D7
D6
D4
D3
D1
D0
X
X
tLN
tLEW
tCKN
CLK
LE
tSCK
tLES
Figure 24. Serial Control Timing Diagram
PS
X
SERIN
X
D5
D4
D3
D2
D1
D0
6
X
1
2
3
4
5
7
8
9
10
11
12
13
14
CLK
LE
X
D5
D4
D3
D2
D1
D0
X
SEROUT
tCO
Figure 25. Serial Output Timing Diagram
Rev. 0 | Page 12 of 17
Data Sheet
ADRF5731
Latched Parallel Mode
PARALLEL MODE INTERFACE
To enable latched parallel mode, keep the LE pin low when
changing the control voltage inputs (D2 to D5) to set the
attenuation state. When the desired state is set, toggle LE high
to transfer the 4-bit data to the bypass switches of the attenuator
array and then toggle LE low to latch the change into the device
until the next desired attenuation change (see Figure 26 in
conjunction with Table 2).
The ADRF5731 has four digital control inputs, D2 (LSB) to D5
(MSB), to select the desired attenuation state in parallel mode,
as shown in Table 7. The parallel control interface is activated
when PS is set to low.
There are two modes of parallel operation: direct parallel and
latched parallel.
Direct Parallel Mode
PS
X
To enable direct parallel mode, keep the LE pin high. To change
the attenuation state, use the control voltage inputs (D2 to D5)
directly. This mode is ideal for manual control of the attenuator.
tPS
tPH
D5 TO D2
LE
X
X
tLEW
Figure 26. Latched Parallel Mode Timing Diagram
Rev. 0 | Page 13 of 17
ADRF5731
Data Sheet
APPLICATIONS INFORMATION
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
EVALUATION BOARD
The ADRF5731-EVALZ is a 4-layer evaluation board. The top
and bottom copper layer are 0.5 oz (0.7 mil) plated to 1.5 oz
(2.2 mil) and are separated by dielectric materials. The stackup
for this evaluation board is shown in Figure 27.
G = 6mil
W = 16mil
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
RO4003
1.5oz Cu (2.2mil)
T = 2.2mil
H = 12mil
THRU LOSS
DE-EMBEDDED INSERTION LOSS
EMBEDDED INSERTION LOSS
0.5oz Cu (0.7mil)
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
Figure 28. Insertion Loss vs. Frequency
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil)
Figure 29 shows the actual ADRF5731-EVALZ evaluation board
with component placement.
Figure 27. Evaluation Board Stackup, Cross Sectional View
All RF and dc traces are routed on the top copper layer, whereas
the inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. The top dielectric
material is 12 mil Rogers RO4003, offering optimal high
frequency performance. The middle and bottom dielectric
materials provide mechanical strength. The overall board
thickness is 62 mil, which allows 2.4 mm RF launchers to be
connected at the board edges.
Figure 29. Evaluation Board Layout, Top View
Two power supply ports are connected to the VDD and VSS test
points, TP1 and TP2, and the ground reference is connected to
the GND test point, TP4. On the supply traces, VDD and VSS,
use a 100 pF bypass capacitor to filter high frequency noise.
Additionally, unpopulated components positions are available
for applying extra bypass capacitors.
The RF transmission lines are designed using a coplanar
waveguide (CPWG) model, with a trace width of 16 mil and
ground clearance of 6 mil to have a characteristic impedance of
50 Ω. For optimal RF and thermal grounding, as many through
vias as possible are arranged around transmission lines and
under the exposed pad of the package.
All the digital control pins are connected through digital signal
traces to the 2 × 9-pin header, P1. There are provisions for a
resistor capacitor (RC) filter that helps eliminate dc-coupled
noise. The ADRF5731 was evaluated without an external RC
filter, the series resistors are 0 Ω, and shunt capacitors are
unpopulated on the evaluation board.
Thru calibration can be used to calibrate out the board loss effects
from the ADRF5731-EVALZ evaluation board measurements to
determine the device performance at the pins of the IC. Figure 28
shows the typical board loss (THRU) for the ADRF5731-EVALZ
evaluation board at room temperature, the embedded insertion
loss, and the de-embedded insertion loss for the ADRF5731.
The RF input and output ports (ATTIN and ATTOUT) are
connected through 50 Ω transmission lines to the 2.4 mm RF
launchers, J1 and J2, respectively. These high frequency RF
launchers are connected by contact and are not soldered onto
the board.
A thru calibration line connects the unpopulated J3 and J4
launchers. This transmission line is used to estimate the loss of
the PCB over the environmental conditions being evaluated.
The schematic of the ADRF5731-EVALZ evaluation board is
shown in Figure 30.
Rev. 0 | Page 14 of 17
Data Sheet
ADRF5731
P1
R6
0Ω
R5
0Ω
D5_CLK
D4_SERIN
D3_SEROUT
1
3
5
7
9
11
13
15
17
2
6
4
8
10
12
14
16
18
R1
D2
PS
LE
0Ω
R2
D2
PS
LE
D3_SEROUT
0Ω
VDD
TP1
VSS
TP2
17
1
C1
100pF
EPAD
R4
D4_SERIN
D5_CLK
C2
12
11
10
9
0Ω
100pF
D4/SERIN
D5/CLK
GND
VDD
VSS
R3
2
3
4
0Ω
GND
TP4
ADRF5731
GND
J2
J1
ATTOUT
ATTIN
ATTOUT
ATTIN
J3
DNI
J4
DNI
THRU CAL
Figure 30. Evaluation Board Schematic
Table 8. Evaluation Board Components
Component
Default Value
Description
C1, C2
100 pF
Capacitors, C0402 package
J1, J2
P1
R1 to R6
TP1, TP2, TP4
U1
Not applicable
Not applicable
0 Ω
Not applicable
ADRF5731
2.4 mm end launch connectors (Southwest Microwave: 1492-04A-6)
2 × 9-pin header
Resistors, 0402 package
Through hole mount test points
ADRF5731 digital attenuator, Analog Devices, Inc.
Rev. 0 | Page 15 of 17
ADRF5731
Data Sheet
PROBE MATRIX BOARD
The probe matrix board is a 4-layer board. Similar to the
evaluation board, the probe matrix board also uses a 12 mil
Rogers RO4003 dielectric. The top and bottom copper
layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil). The RF
transmission lines are designed using a CPWG model with
a width of 16 mil and ground spacing of 6 mil to have a
characteristic impedance of 50 Ω.
Figure 31 and Figure 32 show the cross sectional view and the
top view of the board, respectively. Measurements are made
using GSG probes at close proximity to the RF pins (ATTIN
and ATTOUT). Unlike the evaluation board, probing reduces
reflections caused by mismatch arising from connectors, cables,
and board layout, resulting in a more accurate measurement of
the device performance.
G = 6mil
W = 16mil
Figure 32. Probe Matrix Board Layout (Top View)
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
RO4003
1.5oz Cu (2.2mil)
T = 2.2mil
H = 12mil
The probe matrix board includes a thru reflect line (TRL)
calibration kit, allowing board loss de-embedding. The actual
board duplicates the same layout in matrix form to assemble
multiple devices at one time. Figure 33 is a detailed image of
the trace to pin transition with corresponding dimensions. All
S parameters were measured on this board.
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil)
Figure 31. Probe Matrix Board (Cross Sectional View)
16mil
8mil
Figure 33. Probe Board Layout Dimensions (Top View)
Rev. 0 | Page 16 of 17
Data Sheet
ADRF5731
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
2.60
2.50 SQ
2.40
0.250
0.200
0.150
0.325
0.275
0.225
PIN 1
CHAMFERED
CORNER AREA
PIN 1 (0.1 × 45°)
13
16
12
1
1.10
1.00 SQ
0.90
1.20 REF
EXPOSED
PAD
9
4
0.40
BSC
5
8
TOP VIEW
BOTTOM VIEW
0.125
REF
0.850
0.750
0.650
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.530 REF
SIDE VIEW
SECTION OF THIS DATA SHEET.
0.260
0.220
0.180
Figure 34. 16-Terminal Land Grid Array [LGA]
2.5 mm × 2.5 mm Body and 0.75 mm Package Height
(CC-16-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
CC-16-6
CC-16-6
Marking Code
ADRF5731BCCZN
ADRF5731BCCZN-R7
ADRF5731-EVALZ
16-Terminal Land Grid Array [LGA]
16-Terminal Land Grid Array [LGA]
Evaluation Board
31
31
1 Z = RoHS Compliant Part.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17000-0-9/18(0)
www.analog.com/ADRF5731
Rev. 0 | Page 17 of 17
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