ADRF6516ACPZ-R7 [ADI]
31 MHz, Dual Programmable Filters; 31 MHz的双通道可编程滤波器
| 型号： | ADRF6516ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | 31 MHz, Dual Programmable Filters |
| 文件： | 总32页 (文件大小：1048K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
31 MHz, Dual Programmable Filters
and Variable Gain Amplifiers
ADRF6516
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ENBL INP1 INM1 VPS COM VICM OFS1 VPS
Matched pair of programmable filters and VGAs
Continuous gain control range: 50 dB
Digital gain control: 15 dB
VPSD
COMD
LE
OPP1
OPM1
COM
6-pole Butterworth filter: 1 MHz to 31 MHz
in 1 MHz steps, 1 dB corner frequency
Preamplifier and postamplifier gain steps
IMD3: >65 dBc for 1.5 V p-p composite output
HD2, HD3: >65 dBc for 1.5 V p-p output
Differential input and output
Flexible output and input common-mode ranges
Optional dc offset compensation loop
SPI programmable filter corners and gain steps
Power-down feature
CLK
GAIN
VOCM
COM
SPI
DATA
SDO
COM
VPS
OPM2
OPP2
ADRF6516
Single 3.3 V supply operation
COM INP2 INM2 VPS COM OFDS OFS2 VPS
APPLICATIONS
Figure 1.
Baseband IQ receivers
Diversity receivers
ADC drivers
Point-to-point and point-to-multipoint radio
Instrumentation
Medical
GENERAL DESCRIPTION
The ADRF6516 is a matched pair of fully differential, low noise
and low distortion programmable filters and variable gain
amplifiers (VGAs). Each channel is capable of rejecting large
out-of-band interferers while reliably boosting the desired signal,
thus reducing the bandwidth and resolution requirements on the
analog-to-digital converters (ADCs). The excellent matching
between channels and their high spurious-free dynamic range
over all gain and bandwidth settings make the ADRF6516 ideal
for quadrature-based (IQ) communication systems with dense
constellations, multiple carriers, and nearby interferers.
The variable gain amplifiers that follow the filters provide 50 dB
of continuous gain control with a slope of 15.5 mV/dB. Their
maximum gains can be programmed to various values through
the SPI. The output buffers provide a differential output impedance
of 30 Ω and are capable of driving 2 V p-p into 1 kΩ loads. The
output common-mode voltage defaults to VPS/2, but it can be
adjusted down to 700 mV by driving the high impedance VOCM
pin. Independent, built-in dc offset compensation loops can be
disabled if fully dc-coupled operation is desired. The high-pass
corner frequency is defined by external capacitors on the OFS1
and OFS2 pins and the VGA gain.
The filters provide a six-pole Butterworth response with 1 dB
corner frequencies programmable through the SPI port from
1 MHz to 31 MHz in 1 MHz steps. The preamplifier that precedes
the filters offers a SPI-programmable option of either 3 dB or 6 dB
of gain. The preamplifier sets a differential input impedance of
1600 Ω and has a common-mode voltage that defaults to VPS/2
but can be driven from 1.1 V to 1.8 V.
The ADRF6516 operates from a 3.15 V to 3.45 V supply
and consumes a maximum supply current of 360 mA when
programmed to the highest bandwidth setting. When disabled,
it consumes <9 mA. The ADRF6516 is fabricated in an advanced
silicon-germanium BiCMOS process and is available in a 32-lead,
exposed paddle LFCSP. Performance is specified over the −40°C
to +85°C temperature range.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
ADRF6516
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Key Parameters for Quadrature-Based Receivers.................. 20
Applications Information .............................................................. 21
Basic Connections...................................................................... 21
Supply Decoupling ..................................................................... 21
Input Signal Path ........................................................................ 21
Output Signal Path..................................................................... 21
DC Offset Compensation Loop Enabled ................................ 21
Common-Mode Bypassing ....................................................... 21
Serial Port Connections............................................................. 22
Enable/Disable Function........................................................... 22
Error Vector Magnitude (EVM) Performance........................... 22
EVM Test Setup.......................................................................... 22
Effect of Filter Bandwidth on EVM......................................... 22
Effect of Output Voltage Levels on EVM................................ 23
Effect of COFS Value on EVM..................................................... 23
Evaluation Board ............................................................................ 24
Evaluation Board Control Software......................................... 24
Schematics and Artwork ........................................................... 25
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Register Map and Codes................................................................ 15
Theory of Operation ...................................................................... 16
Input Buffers ............................................................................... 16
Programmable Filters................................................................. 16
Variable Gain Amplifiers (VGAs) ............................................ 17
Output Buffers/ADC Drivers ................................................... 17
DC Offset Compensation Loop................................................ 17
Programming the Filters and Gains......................................... 18
Noise Characteristics ................................................................. 18
Distortion Characteristics ......................................................... 19
Maximizing the Dynamic Range.............................................. 19
REVISION HISTORY
2/12—Rev. A to Rev. B
Changes to Figure 57...................................................................... 24
Changes to Figure 58...................................................................... 25
Added Figure 59.............................................................................. 26
Changes to Figure 60 and Figure 61............................................. 27
Changes to Table 6 .......................................................................... 27
9/11—Revision A: Initial Version
Rev. B | Page 2 of 32
Data Sheet
ADRF6516
SPECIFICATIONS
VPS = 3.3 V, TA = 25°C, ZLOAD = 1 kΩ, digital gain code = 111, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RESPONSE
Low-Pass Corner Frequency, fC
Step Size
Corner Frequency Absolute
Accuracy
6-pole Butterworth filter, 0.5 dB bandwidth
Over operating temperature range
1
31
MHz
MHz
% fC
1
15
Corner Frequency Matching
Channel A and Channel B at same gain and
bandwidth settings
0.5
% fC
Pass-Band Ripple
Gain Matching
0.5
0.1
dB p-p
dB
Channel A and Channel B at same gain and
bandwidth settings
Group Delay Variation
From midband to peak
Corner Frequency = 1 MHz
Corner Frequency = 31 MHz
Group Delay Matching
Corner Frequency = 1 MHz
Corner Frequency = 31 MHz
Stop-Band Rejection
135
11
ns
ns
Channel A and Channel B at same gain
5
0.2
ns
ns
Relative to Pass Band
2 × fC
5 × fC
30
75
dB
dB
INPUT STAGE
INP1, INM1, INP2, INM2, VICM pins
At minimum gain, VGAIN = 0 V
Maximum Input Swing
Differential Input Impedance
Input Common-Mode Range
1
V p-p
Ω
V
V
kΩ
1600
1.65
VPS/2
7
0.4 V p-p input voltage, HD3 > 65 dBc
Input pins left floating
1.1
−5
1.8
VICM Output Impedance
GAIN CONTROL
Voltage Gain Range
Gain Slope
GAIN pin
VGAIN from 0 V to 1 V
+45
dB
mV/dB
dB
15.5
0.2
Gain Error
VGAIN from 300 mV to 800 mV
OPP1, OPM1, OPP2, OPM2, VOCM pins
At maximum gain, RLOAD = 1 kΩ
HD2 > 65 dBc, HD3 > 65 dBc
OUTPUT STAGE
Maximum Output Swing
2
1.5
30
V p-p
V p-p
Ω
mV
V
Differential Output Impedance
Output DC Offset
Output Common-Mode Range
Inputs shorted, offset loop disabled
VOCM pin left floating
35
0.7
1.65
VPS/2
23
2.8
V
kΩ
VOCM Input Impedance
NOISE/DISTORTION
Corner Frequency = 1 MHz
Output Noise Density
Gain = 0 dB at fC/2
Gain = 20 dB at fC/2
Gain = 40 dB at fC/2
−141
−131
−112
dBV/√Hz
dBV/√Hz
dBV/√Hz
Second Harmonic, HD2
Third Harmonic, HD3
250 kHz fundamental, 1.5 V p-p output voltage
Gain = 5 dB
Gain = 40 dB
250 kHz fundamental, 1.5 V p-p output voltage
Gain = 5 dB
Gain = 40 dB
82
68
dBc
dBc
71
56
dBc
dBc
Rev. B | Page 3 of 32
ADRF6516
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
IMD3
f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite
output voltage
Gain = 5 dB
Gain = 35 dB
f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite
output, gain = 5 dB; blocker at 5 MHz, 10 dBc
relative to two-tone composite output voltage
61
42.5
40
dBc
dBc
dBc
IMD3 with Input CW Blocker
Corner Frequency = 31 MHz
Output Noise Density
Midband, gain = 0 dB
Midband, gain = 20 dB
Midband, gain = 40 dB
8 MHz fundamental, 1.5 V p-p output voltage
Gain = 5 dB
Gain = 40 dB
8 MHz fundamental, 1.5 V p-p output voltage
Gain = 5 dB
−143.5
−139
−125
dBV/√Hz
dBV/√Hz
dBV/√Hz
Second Harmonic, HD2
Third Harmonic, HD3
IMD3
68
70
dBc
dBc
55
75
dBc
dBc
Gain = 40 dB
f1 = 14 MHz, f2 = 15 MHz, 1.5 V p-p composite
output voltage
Gain = 5 dB
Gain = 35 dB
f1 = 14 MHz, f2 = 15 MHz, 1.5 V p-p composite
output, gain = 5 dB; blocker at 150 MHz, 10 dBc
relative to two-tone composite output voltage
55
77.5
55
dBc
dBc
dBc
IMD3 with Input CW Blocker
DIGITAL LOGIC
LE, CLK, DATA, SDO, OFDS pins
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
>2
<0.8
<1
2
V
V
µA
pF
SPI TIMING
fSCLK
LE, CLK, DATA, SDO pins (see Figure 2 and Figure 3)
1/tSCLK
20
5
MHz
ns
tDH
DATA hold time
tDS
DATA setup time
5
ns
tLH
LE hold time
5
ns
tLS
LE setup time
5
ns
tPW
tD
CLK high pulse width
CLK to SDO delay
5
5
ns
ns
POWER AND ENABLE
Supply Voltage Range
Total Supply Current
VPS, VPSD, COM, COMD, ENBL pins
3.15
3.3
3.45
V
ENBL = 3.3 V
Corner frequency = 31 MHz
Corner frequency = 1 MHz
ENBL = 0 V
360
330
9
1.6
20
mA
mA
mA
V
µs
ns
Disable Current
Disable Threshold
Enable Response Time
Disable Response Time
Delay following ENBL low-to-high transition
Delay following ENBL high-to-low transition
300
Rev. B | Page 4 of 32
Data Sheet
ADRF6516
TIMING DIAGRAMS
tCLK
tPW
CLK
tLH
tLS
LE
tDS
tDH
LSB
B2
B3
B4
B5
B6
DATA
WRITE BIT
B7
MSB
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A WRITE
OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 8-BIT WORD IS THEN WRITTEN TO THE DATA PIN ON CONSECUTIVE RISING
EDGES OF THE CLOCK.
Figure 2. Write Mode Timing Diagram
tCLK
tPW
tD
CLK
LE
tLH
tLS
tDS
tDH
READ BIT
DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’TCAREADON’T CARE
LSB B2 B4 B5 B7 MSB
DATA
SDO
B3
B6
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A READ
OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE 8-BIT WORD IS THEN REGISTERED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES
OF THE CLOCK.
Figure 3. Read Mode Timing Diagram
Rev. B | Page 5 of 32
ADRF6516
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltages, VPS, VPSD
ENBL, OFDS, LE, CLK, DATA, SDO
INP1, INM1, INP2, INM2
OPP1, OPM1, OPP2, OPM2
OFS1, OFS2
3.45 V
VPSD + 0.5 V
VPS + 0.5 V
VPS + 0.5 V
VPS + 0.5 V
VPS + 0.5 V
1.25 W
37.4°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
GAIN
Internal Power Dissipation
θJA (Exposed Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
ESD CAUTION
Rev. B | Page 6 of 32
Data Sheet
ADRF6516
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPSD
COMD
LE
1
2
3
4
5
6
7
8
24 OPP1
23 OPM1
22 COM
21 GAIN
20 VOCM
19 COM
18 OPM2
17 OPP2
PIN 1
INDICATOR
CLK
ADRF6516
TOP VIEW
(Not to Scale)
DATA
SDO
COM
VPS
NOTES
1. CONNECT THE EXPOSED PADDLE TO
A LOW IMPEDANCE GROUND PAD.
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
VPSD
COMD
LE
CLK
DATA
SDO
Description
Digital Positive Supply Voltage: 3.15 V to 3.45 V.
Digital Common. Connect to external circuit common using the lowest possible impedance.
Latch Enable. SPI programming pin. TTL levels: VLOW < 0.8 V, VHIGH > 2 V.
SPI Port Clock. TTL levels: VLOW < 0.8 V, VHIGH > 2 V.
1
2
3
4
5
6
SPI Data Input. TTL levels: VLOW < 0.8 V, VHIGH > 2 V.
SPI Data Output. TTL levels: VLOW < 0.8 V, VHIGH > 2 V.
7, 9, 13, 19, 22, 28 COM
Analog Common. Connect to external circuit common using the lowest possible impedance.
Analog Positive Supply Voltage: 3.15 V to 3.45 V.
Differential Inputs. 1600 Ω input impedance.
8, 12, 16, 25, 29
10, 11, 30, 31
VPS
INP2, INM2,
INM1, INP1
14
15, 26
OFDS
OFS2, OFS1
Offset Compensation Loop Disable. Pull high to disable the offset compensation loop.
Offset Compensation Loop Capacitors. Connect capacitors to circuit common.
17, 18, 23, 24
OPP2, OPM2,
OPM1, OPP1
Differential Outputs. 30 Ω output impedance. Common-mode range is 0.7 V to 2.8 V; default is VPS/2.
20
21
27
VOCM
GAIN
VICM
Output Common-Mode Setpoint. Defaults to VPS/2 if left floating.
Analog Gain Control. 0 V to 1 V, 15.5 mV/dB gain scaling.
Input Common-Mode Voltage. VPS/2 V reference. Use to reference the optimal common-mode drive
to the differential inputs.
32
ENBL
EP
Chip Enable. Pull high to enable.
Exposed Paddle. Connect the exposed paddle to a low impedance ground pad.
Rev. B | Page 7 of 32
ADRF6516
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VPS = 3.3 V, TA = 25°C, ZLOAD = 1 kΩ, digital gain code = 111, unless otherwise noted.
50
45
40
35
30
25
20
15
10
5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
BANDWIDTH = 31MHz
BANDWIDTH = 31MHz
+85°C
+25°C
VPS = 3.15V, 3.3V, 3.45V
VPS = 3.15V, 3.3V, 3.45V
–40°C
VPS = 3.15V, 3.3V, 3.45V
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
+85°C
VPS = 3.15V, 3.3V, 3.45V
+25°C
VPS = 3.15V, 3.3V, 3.45V
–40°C
VPS = 3.15V, 3.3V, 3.45V
0
–5
–10
0
100 200 300 400 500 600 700 800 900 1000
(mV)
0
100 200 300 400 500 600 700 800 900 1000
(mV)
V
V
GAIN
GAIN
Figure 5. In-Band Gain vs. VGAIN over Supply and Temperature
(Bandwidth Setting = 31 MHz)
Figure 8. Gain Conformance vs. VGAIN over Supply and Temperature
(Bandwidth Setting = 31 MHz)
50
45
40
35
30
8
–5
–6
BANDWIDTH = 31MHz
BANDWIDTH = 31MHz
DIGITAL GAIN = 111
7
6
–7
25
20
5
–8
15
10
4
–9
5
0
–5
–10
–11
–12
–13
–14
–15
3
–10
–15
–20
–25
–30
–35
–40
–45
–50
2
DIGITAL GAIN = 011
1
0
–1
–2
1
10
FREQUENCY (MHz)
100
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
Figure 6. Gain vs. Frequency over VGAIN (Bandwidth Setting = 31 MHz)
Figure 9. Gain Step and Gain Error vs. Frequency
(Bandwidth Setting = 31 MHz, VGAIN = 0 V)
0.25
0
14
BANDWIDTH = 31MHz
BANDWIDTH = 31MHz
0.20
–5
13
12
11
10
9
0.15
0.10
DIGITAL GAIN = 011
–10
0.05
0
–15
–20
–25
–30
–0.05
–0.10
–0.15
–0.20
–0.25
DIGITAL GAIN = 000
8
35
0
100 200 300 400 500 600 700 800 900 1000
(mV)
0
5
10
15
20
25
30
V
GAIN
FREQUENCY (MHz)
Figure 7. Gain Matching vs. VGAIN (Bandwidth Setting = 31 MHz)
Figure 10. Gain Step and Gain Error vs. Frequency
(Bandwidth Setting = 31 MHz, VGAIN = 0 V)
Rev. B | Page 8 of 32
Data Sheet
ADRF6516
20
40
38
36
34
32
30
28
26
24
22
20
BANDWIDTH = 31MHz
BANDWIDTH = 31MHz
15
10
–40°C, VPS = 3.15V, 3.3V, 3.45V
DIGITAL GAIN = 111
5
0
–5
+25°C,
VPS = 3.15V, 3.3V, 3.45V
DIGITAL GAIN = 000
–10
–15
–20
+85°C,
VPS = 3.15V, 3.3V, 3.45V
0
5
10
15
20
25
30
35
40
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
(mV)
GAIN (dB)
V
GAIN
Figure 11. Output P1dB vs. Gain at 15 MHz (Bandwidth Setting = 31 MHz)
Figure 14. Frequency Response over Supply and Temperature
(Bandwidth Setting = 31 MHz, Gain = 30 dB)
40
35
30
25
20
15
10
5
1000
GAIN = 20dB
900
800
700
600
500
400
300
200
100
0
BW = 1MHz
BW = 31MHz
BW = 10MHz
BW = 20MHz
BW = 5MHz
0
–5
–10
0.3
3
30
50
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Frequency Response vs. Bandwidth Setting (Gain = 30 dB),
Log Scale
Figure 15. Group Delay vs. Frequency (Gain = 20 dB)
40
35
30
25
20
15
10
5
2.0
1.5
BANDWIDTH = 31MHz
1.0
0.5
0
GAIN = 20dB
GAIN = 40dB
–0.5
–1.0
–1.5
–2.0
0
–5
–10
0
10
20
30
40
50
60
70
80
90
100
0.3
3
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. Frequency Response vs. Bandwidth Setting (Gain = 30 dB),
Linear Scale
Figure 16. Group Delay Matching vs. Frequency
(Bandwidth Setting = 31 MHz)
Rev. B | Page 9 of 32
ADRF6516
Data Sheet
5
90
80
70
60
50
40
30
VOCM = 0.9V
VOCM = 1.2V
VOCM = 1.4V
VOCM = 1.65V
BANDWIDTH = 1MHz
4
3
GAIN = 0dB
2
1
0
–1
–2
–3
–4
–5
GAIN = 20dB
0
5
10
15
20
25
30
35
40
45
0.2
0.4
0.6
0.8
1.0
1.2
1.4
FREQUENCY (MHz)
GAIN (dB)
Figure 17. IQ Group Delay Matching vs. Frequency
(Bandwidth Setting = 1 MHz)
Figure 20. HD2 vs. Gain over Output Common-Mode Voltage
(Bandwidth Setting = 31 MHz, 1.5 V p-p, 8 MHz CW Fundamental Output)
90
80
70
60
50
FREQUENCY (MHz)
0
0.5
1.0
1.5
2.0
2.5
3.0
0.50
0.25
0
BANDWIDTH = 1MHz
BANDWIDTH = 30MHz
40
+25°C, VPS = 3.3V
+25°C, VPS = 3.15V
+25°C, VPS = 3.45V
+85°C, VPS = 3.3V
+85°C, VPS = 3.15V
+85°C, VPS = 3.45V
–40°C, VPS = 3.3V
–40°C, VPS = 3.15V
–40°C, VPS = 3.45V
30
20
10
0
–0.25
–0.50
0
5
10
15
20
25
30
35
40
45
GAIN (dB)
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 18. IQ Amplitude Matching vs. Frequency
Figure 21. HD3 vs. Gain over Supply and Temperature
(Bandwidth Setting = 31 MHz, 1.5 V p-p, 8 MHz CW Fundamental Output)
90
90
80
70
60
50
40
30
20
10
0
VOCM = 0.9V
VOCM = 1.2V
VOCM = 1.4V
VOCM = 1.65V
80
70
60
50
40
30
+25°C, VPS = 3.3V
+25°C, VPS = 3.15V
+25°C, VPS = 3.45V
+85°C, VPS = 3.3V
+85°C, VPS = 3.15V
+85°C, VPS = 3.45V
–40°C, VPS = 3.3V
–40°C, VPS = 3.15V
–40°C, VPS = 3.45V
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
GAIN (dB)
GAIN (dB)
Figure 22. HD3 vs. Gain over Output Common-Mode Voltage
(Bandwidth Setting = 31 MHz, 1.5 V p-p, 8 MHz CW Fundamental Output)
Figure 19. HD2 vs. Gain over Supply and Temperature
(Bandwidth Setting = 31 MHz, 1.5 V p-p, 8 MHz CW Fundamental Output)
Rev. B | Page 10 of 32
Data Sheet
ADRF6516
80
110
100
90
80
70
60
50
40
30
20
10
GAIN = 0dB, HD2
GAIN = 0dB, HD3
GAIN = 10dB, HD2
GAIN = 10dB, HD3
75
70
65
60
55
50
GAIN = 30dB
GAIN = 20dB
GAIN = 10dB
GAIN = 0dB
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
COMPOSITE OUTPUT VOLTAGE (V p-p)
VICM (V)
Figure 23. HD2 and HD3 vs. Input Common-Mode Voltage
(Bandwidth Setting = 31 MHz, 0.4 V p-p Input Level)
Figure 26. In-Band Third-Order Intermodulation Distortion
(Bandwidth Setting = 31 MHz, Digital Gain = 000)
100
45
BANDWIDTH = 31MHz
f1 = 14MHz, f2 = 15MHz
DIGITAL GAIN = 000
DIGITAL GAIN = 111
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
GAIN = 40dB
GAIN = 30dB
GAIN = 20dB
GAIN = 10dB
GAIN = 0dB
0
0
5
10
15
20
25
30
35
40
45
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
COMPOSITE OUTPUT VOLTAGE (V p-p)
GAIN (dB)
Figure 27. In-Band Third-Order Intermodulation Distortion
(Bandwidth Setting = 31 MHz, Digital Gain = 111)
Figure 24. In-Band OIP3 vs. Gain (Bandwidth Setting = 31 MHz)
45
70
60
BANDWIDTH = 31MHz
–40°C
BANDWIDTH = 31MHz
50
40
f1 = 14MHz, f2 = 15MHz
40
DIGITAL GAIN = 111
30
20
35
10
0
+85°C
+25°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
30
25
20
15
10
5
2:1 SLOPE
OUT-OF-BAND IIP2
PREAMP GAIN = 6dB
PREAMP GAIN = 3dB
0
0
5
10
15
20
25
30
35
40
45
50
–55 –45 –35 –25 –15 –5
5
15 25 35 45 55 65
GAIN (dB)
INPUT LEVEL AT 115MHz AND 130MHz (dBV/TONE)
Figure 28. Out-of-Band IIP2, IMD2 Tone at Midband
(Bandwidth Setting = 31 MHz)
Figure 25. In-Band OIP3 vs. Gain over Temperature
(Bandwidth Setting = 31 MHz)
Rev. B | Page 11 of 32
ADRF6516
Data Sheet
–110
–115
–120
–125
–130
10
0
–10
BANDWIDTH = 31MHz
–20
–30
DIGITAL GAIN = 000
DIGITAL GAIN = 100
DIGITAL GAIN = 110
DIGITAL GAIN = 111
–40
–50
3:1 SLOPE
–60
–70
–135
–140
–80
–90
–100
–110
–120
–130
–140
–150
–160
–145
–150
OUT-OF-BAND IIP3
–155
–160
PREAMP GAIN = 6dB
PREAMP GAIN = 3dB
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT LEVEL AT 115MHz AND 215MHz (dBV/TONE)
0
5
–20
–10
0
10
20
30
40
50
GAIN (dB)
Figure 29. Out-of-Band IIP3, IMD3 Tone at Midband
(Bandwidth Setting = 31 MHz)
Figure 32. Output Noise Density vs. Analog Gain over Digital Gain
(Bandwidth Setting = 31 MHz, Measured at 1/2 Bandwidth)
60
55
50
45
40
35
30
25
20
15
10
–100
–105
–110
DIGITAL GAIN = 000
DIGITAL GAIN = 100
DIGITAL GAIN = 110
DIGITAL GAIN = 111
1MHz
–115
2MHz
4MHz
8MHz
16MHz
–120
–125
–130
–135
–140
–145
–150
31MHz
–20
–10
0
10
20
30
40
50
–5
0
5
10
15
20
25
30
35
40
45
50
GAIN (dB)
GAIN (dB)
Figure 33. Output Noise Density vs. Gain over Bandwidth Setting
(Digital Gain = 111, Measured at 1/2 Bandwidth)
Figure 30. Noise Figure vs. Analog Gain over Digital Gain
(Bandwidth Setting = 31 MHz, Noise Figure at 1/2 Bandwidth)
–100
50
1MHz
2MHz
4MHz
8MHz
16MHz
31MHz
GAIN = 40dB
BANDWIDTH = 1MHz
DIGITAL GAIN = 111
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
45
40
35
30
25
20
GAIN = 20dB
GAIN = 0dB
–5
5
15
25
35
45
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
FREQUENCY (MHz)
GAIN (dB)
Figure 34. Output Noise Density vs. Frequency
(Bandwidth Setting = 1 MHz, Digital Gain = 111)
Figure 31. Noise Figure vs. Gain over Bandwidth Setting
(Digital Gain = 111, Noise Figure at 1/2 Bandwidth)
Rev. B | Page 12 of 32
Data Sheet
ADRF6516
–110
–115
–120
–125
–130
–135
–140
–145
–150
50
40
30
20
10
0
35
30
25
20
15
BANDWIDTH = 31MHz
BANDWIDTH = 31MHz
DIGITAL GAIN = 111
GAIN = 40dB
GAIN = 20dB
GAIN = 0dB
10
30
5
10
15
20
25
5
15
25
35
45
55
65
75
85
95
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 35. Output Noise Density vs. Frequency
(Bandwidth Setting = 31 MHz, Digital Gain = 111)
Figure 38. Output Impedance vs. Frequency
(Bandwidth Setting = 31 MHz)
120
100
80
60
40
20
0
–90
–95
BANDWIDTH = 31MHz
DIGITAL GAIN = 111
–100
–105
–110
–115
–120
–125
–130
–135
GAIN = 40dB
GAIN = 20dB
GAIN = 0dB
GAIN = 40dB
GAIN = 20dB
GAIN = 0dB
–140
–145
BANDWIDTH = 31MHz
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
FREQUENCY (MHz)
BLOCKER LEVEL AT 150MHz (dBV rms)
Figure 36. Output Noise Density vs. Input CW Blocker Level
(Bandwidth Setting = 31 MHz, Blocker at 150 MHz)
Figure 39. Channel Isolation, Output to Output, vs. Frequency
(Bandwidth Setting = 31 MHz)
2500
2000
1500
1000
500
40
365
360
355
350
345
340
335
BANDWIDTH = 31MHz
20
0
–20
DIGITAL GAIN = 000
DIGITAL GAIN = 111
330
–40
30
325
0
5
10
15
20
25
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
BANDWIDTH (MHz)
Figure 37. Input Impedance vs. Frequency
(Bandwidth Setting = 31 MHz)
Figure 40. Current Consumption at Minimum and Maximum Digital Gain
vs. Bandwidth (Bandwidth Setting = 31 MHz, Gain = 30 dB)
Rev. B | Page 13 of 32
ADRF6516
Data Sheet
370
70
60
50
40
30
20
10
0
BANDWIDTH = 31MHz
BANDWIDTH = 31MHz
GAIN = 40dB
GAIN = 20dB
368
366
364
362
360
358
356
354
352
DIGITAL GAIN = 000
DIGITAL GAIN = 111
0
5
10
15
20
25
30
–40
–20
0
20
40
60
80
100
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 41. Current Consumption at Minimum and Maximum Digital Gain
vs. Temperature (Bandwidth Setting = 31 MHz, Gain = 30 dB)
Figure 43. Common-Mode Rejection Ratio (CMRR) vs. Frequency
(Bandwidth Setting = 31 MHz)
BANDWIDTH = 31MHz
20dB GAIN STEP
V
= 750mV TO 450mV
GAIN
28MHz SIGNAL = 60mV p-p
TO 600mV p-p
200ns/DIV
Figure 42. Gain Step Response
Rev. B | Page 14 of 32
Data Sheet
ADRF6516
REGISTER MAP AND CODES
The filter frequency, preamplifier gain, postamplifier gain, and VGA maximum gain can be programmed using the SPI interface. Table 4
provides the bit map for the internal 8-bit register of the ADRF6516. The preamplifier, postamplifier, and VGA maximum gain code bits
(Bits[B3:B1]) are referred to elsewhere in this data sheet as Digital Gain Code 000 through Digital Gain Code 111.
Table 4. Register Map
MSB
LSB
B8
B7
B6
B5
B4
B3
B2
B1
Filter frequency code
Preamplifier gain Postamplifier gain VGA max gain
code
code
code
See Table 5
0 = 3 dB
1 = 6 dB
0 = 6 dB
1 = 12 dB
0 = 22 dB
1 = 28 dB
Table 5. Frequency Code vs. Corner Frequency Lookup Table
5-Bit Binary Frequency Code1
Corner Frequency (MHz)
5-Bit Binary Frequency Code1
Corner Frequency (MHz)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
No signal
1
2
3
4
5
6
7
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
8
9
10
11
12
13
14
15
1 MSB first.
Rev. B | Page 15 of 32
ADRF6516
Data Sheet
THEORY OF OPERATION
The ADRF6516 consists of a matched pair of buffered, program-
mable filters followed by a cascade of two variable gain amplifiers
and output ADC drivers. The block diagram of a single channel
is shown in Figure 44.
The input buffers in both channels can be configured simul-
taneously for a gain of 3 dB or 6 dB through the SPI (see the
Register Map and Codes section). When configured for a 3 dB
gain, the buffers support a 400 mV p-p differential input level
with ~70 dBc harmonic distortion. For a 6 dB gain setting, the
buffers support 280 mV p-p inputs.
The programmability of the bandwidth and of the pre- and post-
filtering gain through the SPI interface offers great flexibility
when coping with signals of varying levels in the presence of
noise and large, undesired signals nearby. The entire differential
signal chain is dc-coupled with flexible interfaces at the input
and output. The bandwidth and gain setting controls for the two
channels are shared, ensuring close matching of their magnitude
and phase responses. The ADRF6516 can be fully disabled
through the ENBL pin.
PROGRAMMABLE FILTERS
The integrated programmable filter is the key signal processing
function in the ADRF6516. The filters follow a six-pole Butter-
worth prototype response that provides a compromise between
band rejection, ripple, and group delay. The 0.5 dB bandwidth is
programmed from 1 MHz to 31 MHz in 1 MHz steps via the serial
programming interface (SPI), as described in the Programming
the Filters and Gains section.
1MHz TO 31MHz
PROG.
6dB/12dB
ADC
3dB/6dB
PREAMP
25dB
VGA
25dB
VGA
FILTERS
DRIVER
The filters are designed so that the Butterworth prototype filter
shape and group delay responses vs. frequency are retained for
any bandwidth setting. Figure 45 and Figure 46 illustrate the ideal
six-pole Butterworth magnitude and group delay responses,
respectively. The group delay, τg, is defined as
BASEBAND
INPUTS
BASEBAND
OUTPUTS
τg = −∂φ/∂ω
SPI
INTERFACE
where:
φ is the phase in radians.
ω = 2πf (the frequency in radians/sec).
GAIN AND FILTER
PROGRAMMING
SPI BUS
ANALOG
GAIN CONTROL COMMON-MODE
15mV/dB CONTROL
OUTPUT
Note that for a frequency scaled filter prototype, the absolute
magnitude of the group delay scales inversely with the band-
width; however, the shape is retained. For example, the peak
group delay for a 28 MHz bandwidth setting is 14× less than
for a 2 MHz setting (see Figure 46).
Figure 44. Signal Path Block Diagram for a Single Channel of the ADRF6516
Filtering and amplification are fundamental operations in any
signal processing system. Filtering is necessary to select the
intended signal while rejecting out-of-band noise and inter-
ferers. Amplification increases the level of the desired signal
to overcome noise added by the system. When used together,
filtering and amplification can extract a low level signal of
interest in the presence of noise and out-of-band interferers.
Such analog signal processing alleviates the requirements on
the analog, mixed signal, and digital components that follow.
0
–20
–40
–60
–80
INPUT BUFFERS
–100
–120
–140
–160
–180
The input buffers provide a convenient interface to the sensitive
filter sections that follow. They set a differential input impedance
of 1600 Ω and float to a common-mode voltage near VPS/2. The
inputs can be dc-coupled or ac-coupled. If using direct dc coupling,
the common-mode voltage presented to the inputs should be
approximately VPS/2 to maximize the input swing capacity.
1M
10M
100M
1G
FREQUENCY (Hz)
For a 3.3 V supply, the common-mode voltage can range
from 1.1 V to 1.8 V while maintaining a >65 dBc HD3 for a
400 mV p-p input signal. The VICM pin provides the optimal
midsupply common-mode voltage and can be used as a refer-
ence for the driving circuit. The VICM voltage is not buffered
and must be sensed at a high impedance point to prevent it
from being loaded down.
Figure 45. Sixth-Order Butterworth Magnitude Response for 0.5 dB
Bandwidths Programmed from 2 MHz to 29 MHz in 1 MHz Steps
Rev. B | Page 16 of 32
Data Sheet
ADRF6516
500
0.3
0.2
0.1
0
50
40
30
20
10
0
15mV/dB
400
BW = 2MHz
BW = 28MHz
300
200
100
0
14×
–0.1
–0.2
–0.3
–100
100k
–10
1M
10M
100M
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00
FREQUENCY (Hz)
V
(V)
GAIN
Figure 46. Sixth-Order Butterworth Group Delay Response for
0.5 dB Bandwidths Programmed to 2 MHz and 28 MHz
Figure 47. Linear-in-dB Gain Control Response of the X-AMP VGA Cascade
Showing Consistent Slope and Low Error
The corner frequency of the filters is defined by RC products,
which can vary by ±±30 in a typical process. Therefore, all the
parts are factory calibrated for corner frequency, resulting in
a residual ±ꢀ10 corner frequency variation over the −43°C to
+81°C temperature range. Although absolute accuracy requires
calibration, the matching of RC products between the pair of
channels is better than ꢀ0 by observing careful design and
layout practices. Calibration and excellent matching ensure
that the magnitude and group delay responses of both channels
track together, a critical requirement for digital IQ-based
communication systems.
OUTPUT BUFFERS/ADC DRIVERS
The low impedance (±3 Ω) output buffers of the ADRF61ꢀ6
are designed to drive either ADC inputs or subsequent amplifier
stages. They are capable of delivering up to ꢀ.1 V p-p composite
two-tone signals into ꢀ kΩ differential loads with >61 dBc
IMD±. The output common-mode voltage defaults to VPS/2,
but it can be adjusted from 733 mV to 2.8 V without loss of
drive capability by presenting the VOCM pin with the desired
common-mode voltage. The high input impedance of VOCM
allows the ADC reference output to be connected directly. Even
though the output common-mode voltage is adjustable and the
offset compensation loop can null the accumulated dc offsets
(see the DC Offset Compensation Loop section), it may still be
desirable to ac couple the outputs by selecting the coupling cap-
acitors according to the load impedance and desired bandwidth.
VARIABLE GAIN AMPLIFIERS (VGAs)
The cascaded VGAs are based on the Analog Devices, Inc.,
patented X-AMP® architecture, consisting of tapped 21 dB
attenuators followed by programmable gain amplifiers. The
X-AMP architecture generates a continuous linear-in-dB
monotonic gain response with low ripple. The analog gains of
both cascaded VGA sections are controlled through the high
impedance GAIN pin with an accurate slope of ꢀ1 mV/dB.
DC OFFSET COMPENSATION LOOP
In many signal processing applications, no information is
carried in the dc level. In fact, dc voltages and other low
frequency disturbances can often dominate the intended signal
and consume precious dynamic range in the analog path and
bits in the data converters. These dc voltages can be present
with the desired input signal or can be generated inside the
signal path by inherent dc offsets or other unintended signal-
dependent processes such as self-mixing or rectification.
The gain response shown in Figure 47 shows the GAIN pin
voltage range and the absence of gain foldback at high VGAIN
.
By changing the gains of both VGAs simultaneously, a more
gradual variation in noise and distortion is achieved. The fixed
gain following each of the variable gain sections can also be pro-
grammed to two different values to maximize dynamic range.
Because the ADRF61ꢀ6 is fully dc-coupled, it may be necessary
to remove these offsets to realize the maximum signal-to-noise
ratio (SNR). This can be achieved with ac coupling capacitors at
the input and output pins; however, large value capacitors with
low impedance values are required because the high-pass corners
must be <ꢀ3 Hz. To address the issue of dc offsets, the ADRF61ꢀ6
provides an offset compensation loop that nulls the output differ-
ential dc level, as shown in Figure 48. If the compensation loop
is not required, it can be disabled by pulling the OFDS pin high.
Rev. B | Page 17 of 32
ADRF6516
Data Sheet
NOISE CHARACTERISTICS
C
OFS
OFDS
OFSx
The output noise behavior of the ADRF6516 depends on the gain
and bandwidth settings. Figure 49 and Figure 50 show the total
output noise spectral density vs. frequency for different band-
width settings and VGA gains.
BASEBAND
OUTPUTS
FROM
FILTERS
–110
BANDWIDTH = 31MHz
50dB
VGA
OUTPUT ADC
DRIVER
DIGITAL GAIN = 111
–115
–120
–125
–130
–135
–140
–145
–150
GAIN = 40dB
GAIN
Figure 48. Offset Compensation Loop Operates Around the VGA
and Output Buffer
The offset compensation loop creates a high-pass corner, fHP
,
that is superimposed on the normal Butterworth filter response.
Typically, fHP is many orders of magnitude lower than the lowest
programmed filter bandwidth so that there is no interaction
between them. Setting fHP is accomplished with capacitors,
GAIN = 20dB
GAIN = 0dB
C
OFS, from the OFS1 and OFS2 pins to ground. Because the
compensation loop works around the VGA sections, fHP is also
dependent on the total gain of the cascaded VGAs. In general,
the expression for fHP is given by
5
15
25
35
45
55
65
75
85
95
FREQUENCY (MHz)
Figure 49. Total Output Noise Density with a 31 MHz Corner Frequency
for Three Different Gain Settings
f
HP (Hz) = 6.7 × (Post Filter Linear Gain/COFS (µF))
–100
GAIN = 40dB
where Post Filter Linear Gain is expressed in linear terms, not
in decibels (dB), and is the gain following the filters, which
excludes the preamplifier gain of 1.4 (3 dB) or 2 (6 dB).
BANDWIDTH = 1MHz
DIGITAL GAIN = 111
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
Note that fHP increases in proportion to the gain. For this reason,
C
OFS should be chosen at the highest operating gain to guarantee
GAIN = 20dB
GAIN = 0dB
that fHP is always below the maximum limit required by the system.
PROGRAMMING THE FILTERS AND GAINS
The 0.5 dB corner frequencies for both filters and the gains of
the preamplifiers and postamplifiers are programmed simulta-
neously through the SPI port. An 8-bit register stores the 5-bit
code for corner frequencies of 1 MHz through 31 MHz, as well
as the 1-bit codes for the preamplifier gain, the VGA maximum
gain, and the postamplifier gain (see Table 4). The SPI protocol
not only allows frequency and gain codes to be written to the
DATA pin, but it also allows the stored code to be read back via
the SDO pin.
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
FREQUENCY (MHz)
Figure 50. Total Output Noise Density with a 1 MHz Corner Frequency
for Three Different Gain Settings
Both the filter sections and the VGAs contribute to the total noise
at the output. The filter contributes a noise spectral density profile
that is flat at low frequencies, peaks near the corner frequency, and
then rolls off as the filter poles roll off the gain and noise. The
magnitude of the noise spectral density contributed by the filter,
expressed in nV/√Hz, varies inversely with the square root of the
bandwidth setting, resulting in a total integrated noise in nV that is
nearly constant with bandwidth setting. At higher frequencies,
after the filter noise rolls off, the noise floor is set by the VGAs.
The latch enable (LE) pin must first go to a Logic 0 for a read or
write cycle to begin. On the next rising edge of the clock (CLK),
a Logic 1 on the DATA pin initiates a write cycle, whereas a
Logic 0 on the DATA pin initiates a read cycle. In a write cycle,
the next eight CLK rising edges latch the desired 8-bit code, LSB
first. When LE goes high, the write cycle is completed and the
frequency and gain codes are presented to the filter and ampli-
fiers. In a read cycle, the next eight CLK falling edges present
the stored 8-bit code, LSB first. When LE goes high, the read
cycle is completed. Detailed timing diagrams are shown in
Figure 2 and Figure 3.
Each of the X-AMP VGA sections used in the ADRF6516 con-
tributes a fixed and flat noise spectral density to its respective
output, independent of the gain setting. Because the VGAs are
cascaded in the ADRF6516, the total noise contributed by the
VGAs at the output increases gradually with higher gain. This
is apparent in the noise floor variation at high frequencies at
different VGA gain settings.
Rev. B | Page 18 of 32
Data Sheet
ADRF6516
The exact relationship depends on the programmed fixed gain of
the amplifiers. At minimum gain, only the last VGA contributes
to the −144 dBV/√Hz minimum noise floor, which is equivalent
to 63 nV/√Hz. At lower frequencies within the filter bandwidth
setting, the VGAs translate the filter noise directly to the output
by a factor equal to the gain following the filter.
As noted in the Input Buffers section, the input section can
handle a total signal level of 400 mV p-p for a 3 dB preamplifier
gain and 280 mV p-p for a 6 dB preamplifier gain with >70 dBc
harmonic distortion. This includes both in-band and out-of-band
signals.
To distinguish and quantify the distortion performance of the
input section, two different IP3 specifications are presented. The
first is called in-band IP3 and refers to a two-tone test where the
signals are inside the filter bandwidth. This is exactly the same
figure of merit familiar to communications engineers in which
the third-order intermodulation level, IMD3, is measured.
At low values of VGA gain, the noise at the output is the flat
spectral density contributed by the last VGA. As the gain
increases, more noise from the filter and first VGA appears at
the output. Because the intrinsic filter noise density increases
at lower bandwidth settings, it is more pronounced than it is
at higher bandwidth settings. In either case, the noise density
asymptotically approaches the limit set by the VGAs at the
highest frequencies. For other values of VGA gain and bandwidth
setting, the detailed shape of the noise spectral density changes
according to the relative contributions of the filters and VGAs.
To quantify the effect of out-of-band signals, a new out-of-band
(OOB) IIP3 figure of merit is introduced. This test also involves
a two-tone stimulus; however, the two tones are placed out-of-
band so that the lower IMD3 product lands in the middle of the
filter pass band. At the output, only the IMD3 product is visible
because the original two tones are filtered out. To calculate the
OOB IIP3 at the input, the IMD3 level is referred to the input
by the overall gain. The OOB IIP3 allows the user to predict the
impact of out-of-band blockers or interferers at an arbitrary
signal level on the in-band performance. The ratio of the desired
input signal level to the input-referred IMD3 at a given blocker
level represents a signal-to-distortion limit imposed by the out-
of-band signals.
Because the noise spectral density outside the filter bandwidth
is limited by the VGA output noise, it may be necessary to use
an external, fixed-frequency, passive filter prior to analog-to-
digital conversion to prevent noise aliasing from degrading the
signal-to-noise ratio. A higher sampling rate relative to the maxi-
mum required ADRF6516 corner frequency setting reduces the
order and complexity of this external filter.
DISTORTION CHARACTERISTICS
MAXIMIZING THE DYNAMIC RANGE
The distortion performance of the ADRF6516 is similar to its
noise performance. The filters and the VGAs contribute to the
overall distortion and signal handling capabilities. Furthermore,
the front end must also cope with out-of-band signals that can be
larger than the in-band signals. These out-of-band signals are
filtered before reaching the VGA. It is important to understand
the signals presented to the ADRF6516 and to match these
signals with the input and output characteristics of the part.
The role of the ADRF6516 is to increase the level of a variable
in-band signal while minimizing out-of-band signals. Ideally,
this is achieved without degrading the SNR of the incoming
signal or introducing distortion to the incoming signal.
The first goal is to maximize the output signal swing, which can
be defined by the ADC input range or the input signal capacity
of the next analog stage. For the complex waveforms often encoun-
tered in communication systems, the peak-to-average ratio, or
crest factor, must be considered when selecting the peak-to-peak
output. From the selected output signal and the maximum gain
of the ADRF6516, the minimum input level can be defined.
Lower signal levels do not yield the maximum output and suffer
a greater degradation in SNR.
When the gain is low, the distortion is typically limited by the
input section because the output is not driven to its maximum
capacity. When the gain is high, the distortion is likely limited
by the output section because the input is not driven to its
maximum capacity. An exception to this is when the input is
driven with a small desired signal in combination with a large
out-of-band signal. In this case, the out-of-band signal may
drive the input to distort. As long as the input is not overdriven,
the out-of-band signal is removed by the filter. A high VGA
gain is still needed to raise the small desired signal to a higher
level at the output. The overall distortion introduced by the part
depends on the input drive level, including the out-of-band
signals, and the desired output signal level.
As the input signal level increases, the VGA gain is reduced from
its maximum gain point to maintain the desired fixed output
level. The output noise, initially dominated by the filter, follows
the gain reduction, yielding a progressively better SNR. At some
point, the VGA gain drops sufficiently that the VGA noise
becomes dominant, resulting in a slower reduction in SNR from
that point. From the perspective of SNR alone, the maximum
input level is reached when the VGA reaches its minimum gain.
Rev. B | Page 19 of 32
ADRF6516
Data Sheet
Distortion must also be considered when maximizing the dynamic
range. At low and moderate signal levels, the output distortion
is constant and assumed to be adequate for the selected output
level. At some point, the input signal becomes large enough that
distortion at the input limits the system. The maximum tolerable
input signal depends on whether the input distortion becomes
unacceptably large or the minimum gain is reached.
KEY PARAMETERS FOR QUADRATURE-BASED
RECEIVERS
The majority of digital communication receivers makes use of
quadrature signaling, in which bits of information are encoded
onto pairs of baseband signals that then modulate in-phase (I)
and quadrature (Q) sinusoidal carriers. Both the baseband and
modulated signals appear quite complex in the time domain with
dramatic peaks and valleys. In a typical receiver, the goal is to
recover the pair of quadrature baseband signals in the presence
of noise and interfering signals after quadrature demodulation.
In the process of filtering out-of-band noise and undesired inter-
ferers and restoring the levels of the desired I and Q baseband
signals, it is critical to retain their gain and phase integrity over
the bandwidth.
The most challenging scenario in terms of dynamic range is the
presence of a large out-of-band blocker accompanying a weaker
in-band desired signal. In this case, the maximum input level is
dictated by the blocker and its inclination to cause distortion.
After filtering, the weak desired signal must be amplified to the
desired output level, possibly requiring maximum gain. Both
the distortion limits associated with the blocker at the input and
the SNR limits created by the weaker signal and higher gains are
present simultaneously. Furthermore, not only does the blocker
scenario degrade the dynamic range, it also reduces the range
of input signals that can be handled because a larger part of the
gain range is used to simply extract the weak desired signal
from the stronger blocker.
The ADRF6516 delivers flat in-band gain and group delay,
consistent with a six-pole Butterworth prototype filter, as
described in the Programmable Filters section. Furthermore,
careful design ensures excellent matching of these parameters
between the I and Q channels. Although absolute gain flatness
and group delay can be corrected with digital equalization,
mismatch introduces quadrature errors and intersymbol inter-
ference that degrade bit error rates in digital communication
systems.
Rev. B | Page 20 of 32
Data Sheet
ADRF6516
APPLICATIONS INFORMATION
For example, the high impedance VOCM input pin of the
BASIC CONNECTIONS
ADRF6806 quadrature demodulator can be directly connected
to the VICM pin of the ADRF6516. This gives the ADRF6806
the optimal common-mode voltage reference to drive the
ADRF6516.
Figure 51 shows the basic connections for a typical ADRF6516
application.
SUPPLY DECOUPLING
A nominal supply voltage of 3.3 V should be applied to the
supply pins. The supply voltage should not exceed 3.45 V
or drop below 3.15 V. Each supply pin should be decoupled
to ground with at least one low inductance, surface-mount
ceramic capacitor of 0.1 µF placed as close as possible to the
ADRF6516 device.
OUTPUT SIGNAL PATH
The low impedance (30 Ω) output buffers are designed to drive
a high impedance load, such as an ADC input or another amplifier
stage. The output pins—OPP1, OPM1, OPP2, and OPM2—sit
at a nominal output common-mode voltage of VPS/2, but can
be driven to a voltage of 0.7 V to 2.8 V by applying the desired
common-mode voltage to the high impedance VOCM pin.
The ADRF6516 has two separate supplies: an analog supply and
a digital supply. Care should be taken to separate the analog and
digital supplies with a large surface-mount inductor of 33 µH.
Each supply should then be decoupled separately to its respective
ground through a 10 μF capacitor.
DC OFFSET COMPENSATION LOOP ENABLED
When the dc offset compensation loop is enabled via the OFDS
pin, the ADRF6516 can null the output differential dc level. The
loop is enabled by pulling the OFDS pin low to ground. The
offset compensation loop creates a high-pass corner frequency,
which is proportional to the value of the capacitors that are
connected from the OFS1 and OFS2 pins to ground. For more
information about setting the high-pass corner frequency, see
the DC Offset Compensation Loop section.
INPUT SIGNAL PATH
Each signal path has input buffers, accessed through the
INP1, INM1, INP2, and INM2 pins, that set a differential input
impedance of 1600 Ω. These inputs sit at a nominal common-
mode voltage around midsupply.
The inputs can be dc-coupled or ac-coupled. If using direct
dc coupling, the common-mode voltage, VCM, can range from
1.1 V to 1.8 V. The VICM pin can be used as a reference common-
mode voltage for driving a high impedance sensing node of the
preceding cascaded part (VICM has a 7 kΩ impedance).
COMMON-MODE BYPASSING
The ADRF6516 common-mode pins, VICM and VOCM, must
be decoupled to ground. At least one low inductance, surface-
mount ceramic capacitor with a value of 0.1 μF should be used
to decouple the common-mode pins.
INPUT1 (–)
0.1µF
VPS
0.1µF
INPUT1 (+)
VPS
VPS
0.1µF
OUTPUT1 (+)
ENBL INM1
INP1
VPSD
COM OFS1
VPS VPS
VICM
OPP1
VPSD
0.1µF
OPM1
COM
COMD
LE
OUTPUT1 (–)
OUTPUT2 (–)
SERIAL
CONTROL
INTERFACE
GAIN
VOCM
COM
CLK
DATA
SDO
COM
VPS
ADRF6516
0.1µF
0.1µF
OPM2
0.1µF
VPS
OPP2
VPS
VPS
INM2
OFDS
COM
OFS2
INP2
COM
VPS
0.1µF
INPUT2 (+)
OUTPUT2 (+)
VPS
0.1µF
VPS
INPUT2 (–)
Figure 51. Basic Connections
Rev. B | Page 21 of 32
ADRF6516
Data Sheet
SERIAL PORT CONNECTIONS
EFFECT OF FILTER BANDWIDTH ON EVM
The ADRF6516 has a SPI port to control the gain and filter band-
width settings. Data can be written to the internal 8-bit register
and read from the register. It is recommended that low-pass RC
filtering be placed on the SPI lines to filter out any high frequency
glitches. See Figure 58, the evaluation board schematic, for an
example of a low-pass RC filter.
Care should be taken when selecting the filter bandwidth. In
a digital transceiver, the modulated signal is filtered by a pulse
shaping filter (such as a root-raised cosine filter) at both the
transmit and receive ends to guard against intersymbol inter-
ference (ISI). If additional filtering of the modulated signal is
done, the signal must be within the pass band of the filter. When
the corner frequency of the ADRF6516 filter begins to encroach
on the modulated signal, ISI is introduced and degrades EVM,
which can lead to loss of signal lock.
ENABLE/DISABLE FUNCTION
To enable the ADRF6516, the ENBL pin must be pulled high.
Driving the ENBL pin low disables the device, reducing current
consumption to approximately 9 mA at room temperature.
Figure 52 shows that a digitally modulated QAM baseband
signal with a bandwidth at 9.45 MHz has excellent EVM even
at a filter corner frequency of 8 MHz. Further reduction in the
corner frequency leads to complete loss of lock. As RF input
power was swept, the ADRF6516 attained an EVM of less than
−45 dB over an input power range of approximately 20 dB.
ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE
Error vector magnitude (EVM) is a measure used to quantify
the performance of a digital radio transmitter or receiver by
measuring the fidelity of the digital signal transmitted or
received. Various imperfections in the link, such as magnitude
and phase imbalance, noise, and distortion, cause the
constellation points to deviate from their ideal locations.
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–5
30MHz
15MHz
10MHz
9MHz
–10
–15
–20
–25
–30
–35
–40
–45
–50
In general, a receiver exhibits three distinct EVM limitations
vs. received input signal power. As signal power increases, the
distortion components increase.
8MHz
GAIN VOLTAGE
•
At large enough signal levels, where the distortion compo-
nents due to the harmonic nonlinearities in the device are
falling in-band, EVM degrades as signal levels increase.
At medium signal levels, where the signal chain behaves
in a linear manner and the signal is well above any notable
noise contributions, EVM has a tendency to reach an opti-
mal level determined dominantly by either the quadrature
accuracy and IQ gain match of the signal chain or the
precision of the test equipment.
•
–25
–20
–15
–10
–5
0
5
RF INPUT POWER (dBm)
Figure 52. EVM vs. RF Input Power at Several Filter Corner Settings
(256-QAM, 14 MSPS Signal with α = 0.35; Output Differential Signal Level
Held to 700 mV p-p; OFDS Pulled High)
•
As signal levels decrease, such that noise is a major con-
tributor, EVM performance vs. the signal level exhibits
a decibel-for-decibel degradation with decreasing signal
level. At these lower signal levels, where noise is the
dominant limitation, decibel EVM is directly proportional
to the SNR.
Figure 53 shows the degradation that a fixed filter corner has
on EVM as the signal bandwidth corner is increased in fine
increments until loss of signal lock occurs.
0
–5
–10
EVM TEST SETUP
FILTER BANDWIDTH CORNER
–15
The basic setup to test EVM for the ADRF6516 consisted of an
Agilent E4438C used as a signal source and a Hewlett-Packard
89410A vector signal analyzer (VSA) used to sample and calculate
the EVM of the signal. The E4438C IQ baseband differential
outputs drove the ADRF6516 inputs. The I and Q outputs of the
ADRF6516 were loaded with 1 kΩ differential impedances and
connected differentially to two AD8130 differential amplifiers to
convert the signals into single-ended signals. The single-ended
signals were connected to the input channels of the VSA.
–20
–25
–30
–35
–40
–45
–50
3
4
5
6
7
8
9
10
SIGNAL BANDWIDTH CORNER (MHz)
Figure 53. EVM vs. Signal Bandwidth Corner at a Filter Corner of 5 MHz
and a 16-QAM Signal with α = 0.35
Rev. B | Page 22 of 32
Data Sheet
ADRF6516
Figure 55 shows degradation of the EVM vs. RF input power as
the COFS capacitor value becomes smaller, which increases the
high-pass corner for the dc offset compensation loop.
0
EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM
Output voltage level can affect EVM greatly when the signal is
compressed. When changing the output voltage levels of the
ADRF6516, take care that the output signal is not in compres-
sion, which causes EVM degradation.
–5
–10
–15
–20
–25
Figure 54 show EVM performance vs. RF input power for
several maximum differential I and Q output voltage levels
of 350 mV p-p up to 2.4 V p-p. For the lower maximum differ-
ential output voltage levels, the EVM is less than −45 dB over
approximately 20 dB of input power range.
C
C
C
= 1µF
OFS
OFS
OFS
–30
–35
–40
–45
–50
= 220nF
= 1nF
0
–5
–10
–15
–20
–35
–30
–25
–20
–15
–10
–5
0
5
RF INPUT POWER (dBm)
350mV p-p MAX
–25
700mV p-p MAX
Figure 55. EVM vs. RF Input Power at Several COFS Values (Filter Corner = 10 MHz,
256-QAM, 14 MSPS Signal with α = 0.35; Output Differential Signal Level
Held to 700 mV p-p; OFDS Pulled Low)
1500mV p-p MAX
–30
2400mV p-p MAX
–35
Figure 56 shows the effect that COFS has on several modulated
signal bandwidths. The modulated bandwidth was swept while
using 1000 pF and 1 µF values for COFS. Total gain was set to
15 dB, so the high-pass filter corner of the 1000 pF capacitor is
26.67 kHz, and the high-pass filter corner of the 1 µF capacitor
is 26.67 Hz. It is recommended that at moderate signal band-
widths, a 1 µF capacitor for COFS be used to obtain the best EVM
when using the dc offset compensation loop.
–40
–45
–50
–25
–20
–15
–10
–5
0
5
RF INPUT POWER (dBm)
Figure 54. EVM vs. RF Input Power at Several Output Maximum Differential
Voltage Levels (Filter Corner = 10 MHz, OFDS Pulled High)
For the largest tested maximum differential output voltage level
of 2.4 V p-p, the ADRF6516 begins to compress the signal. This
compression causes EVM to degrade, but it still remains below
−40 dB, albeit over a truncated input power range. At the high
end of the input power range, the signal is in full compression
and EVM is large. Given that the gain is near its minimum, the
input signal level must be lowered to bring the output signal out
of full compression and into the proper linear operating region.
0
–5
–10
–15
–20
–25
–30
EFFECT OF COFS VALUE ON EVM
C
= 1000pF
= 1µF
OFS
–35
–40
–45
–50
When enabled, the dc offset compensation loop effectively
nulls any information below the high-pass corner set by the
OFS capacitor. However, loss of the low frequency information
C
C
OFS
of the modulated signal can degrade the EVM in some cases.
0
1
2
3
4
5
6
7
8
9
10
As the signal bandwidth becomes larger, the percentage of
information that is corrupted by the high-pass corner becomes
smaller. In such cases, it is important to select a COFS capacitor
that is large enough to minimize the high-pass corner frequency,
which prevents loss of information and degraded EVM.
SIGNAL BANDWIDTH CORNER (MHz)
Figure 56. EVM vs. Signal Bandwidth Corner with COFS = 1 µF
and COFS = 1000 pF (Filter Corner = 10 MHz)
Rev. B | Page 23 of 32
ADRF6516
Data Sheet
EVALUATION BOARD
An evaluation board is available for testing the ADRF6516.
The evaluation board schematic is shown in Figure 58. Table 6
provides the component values and suggestions for modifying
the component values for the various modes of operation.
When the user clicks the Write Bits button, a write operation is
executed, immediately followed by a read operation. The updated
information is displayed in the Current Pre-Amp Gain, Current
Frequency, Current VGA Max Gain, and Current Post-Amp
Gain fields.
EVALUATION BOARD CONTROL SOFTWARE
When the parallel port is updated with a read/write operation,
the current cumulative maximum gain of all the amplifiers is
displayed in the Maximum Gain field. (The analog VGA gain
is not included in this value.)
The ADRF6516 evaluation board is controlled through the
parallel port on a PC. The parallel port is programmed via the
ADRF6516 evaluation software. This software controls the filter
corner frequency, as well as the minimum and maximum gains
for each amplifier in the ADRF6516. For information about the
register map, see Table 4 and Table 5. For information about SPI
port timing and control, see Figure 2 and Figure 3.
Because the speed of the parallel port varies from PC to PC,
the Clock Stretch function can be used to change the effective
frequency of the CLK line. The CLK line has a scalar range from
1 to 10; 10 is the fastest speed, and 1 is the slowest.
After the evaluation software is downloaded and installed, start
the basic user interface to program the filter corner and gain
values (see Figure 57).
To program the filter corner, do one of the following:
•
•
Click the arrow in the Frequency Select section of the
window, select the desired corner frequency from the
menu, and click Write Bits.
Click Freq +1 MHz or Freq −1 MHz to increment or
decrement the corner frequency in 1 MHz steps from
the current corner frequency.
To program the preamplifier gain, the VGA maximum gain,
and the postamplifier gain, move the slider switch in the
appropriate section of the window to the desired gain.
•
•
•
The preamplifier gain can be set to 3 dB or 6 dB.
The VGA maximum gain can be set to 22 dB or 28 dB.
The postamplifier gain can be set to 6 dB or 12 dB.
Figure 57. ADRF6516 Evaluation Software
Rev. B | Page 24 of 32
Data Sheet
ADRF6516
SCHEMATICS AND ARTWORK
VPOSD VPOS
R45
OPEN
L2
33µH
INM1_SE_P
DIG_VPOS
VPOS
VPS
R55
R31
R47
VICM
C1
C2
OPEN
0Ω
0Ω
C9
100nF
R57
1
3
10µF
10µF
6
C27
0Ω
COMD
COM
2
0.1µF
L1
T1
R56
OPEN
33µH
C6
4
C12
0.1µF
R58
0Ω
0.1µF
C10
100nF
R48
0Ω
INP1
C14
1000pF
R37
OPEN
OPP1
R43
OPEN
VPS
VPS
R19
0Ω
R41
0Ω
R12
OPEN
C16
0.1µF
R7
0Ω
P2
R29
100Ω
C19
100nF
ENBL INM1
INP1
COM OFS1
VICM VPS
OPP1
T3
LE
VPS
VPSD
COMD
LE
VPSD
R11
OPEN
C29
330pF
VGAIN
C23
0.1µF
R20
0Ω
R8
0Ω
C4
OPM1
COM
0.1µF
C30
330pF
R30
100Ω
R5
0Ω
C17
0.1µF
C20
OPM1_SE_P
OPM2_SE_P
VGAIN
VOCM
100nF
GAIN
VOCM
COM
CLK
DATA
SDO
COM
VPS
CLK
ADRF6516
R33
R39
OPEN
DATA
SDO
C18
0.1µF
C21 R6
0Ω
0Ω
100nF
R38
OPEN
C5
0.1µF
OPM2
R14
OPEN
R35
0Ω
R42
0Ω
R34
VOCM
OPP2
VPS
R9
0Ω
VPS
INP2
INM2
COM
OFDS
COM
OFS2
R1
10kΩ
VPS
0Ω
C22
100nF
T4
R46
OPEN
R13
OPEN
C24
0.1µF
R36
0Ω
VPS
R10
0Ω
INP2
C13
1000pF
C15
0.1µF
OPP2
R51
OPEN
R32
0Ω
6
R49
0Ω
C11
0.1µF
C7
100nF
R53
0Ω
1
3
R40
2
OPEN
T2
R3
VPS
R52
OPEN
C3
0.1µF
R50
0Ω
10kΩ
4
R54
0Ω
C8
100nF
P4
INM2_SE_P
R44
OPEN
VPS
Figure 58. Evaluation Board Schematic
Rev. B | Page 25 of 32
ADRF6516
Data Sheet
Y1
24MHz
3V3_USB
3
1
C54
22pF
C51
22pF
4
2
R62
100kΩ
3V3_USB
R64
0Ω
C45
0.1µF
C37
0.1µF
56 55 54 53 52 51 50 49 48 47 46 45 44 43
RDY0_SLRD
1
2
3
RESET_N
GND
42
41
40
C48
10pF
RDY1_SLWR
AVCC
PA7_FLAGD_SCLS_N
4
5
6
PA6_PKTEND 39
38
5V_USB
XTALOUT
XTALIN
PA5_FIFOARD1
PA4_FIFOARD0 37
C49
P5
1
0.1µF
AGND
AVCC
3V3_USB
2
3
7
8
9
PA3_WU2
36
LE
CY7C68013A-56LTXC
U4
4
5
35
34
DPLUS
PA2_SLOE
CLK
PA1_INT1_N
G1
G2
G3
G4
DMINUS
DATA
10
11
12
PA0_INT0_N
AGND
VCC
33
SDO
3V3_USB
VCC 32
3V3_USB
GND
CTL2_FLAGC
31
30
13
IFCLK
CTL1_FLAGB
14 RESERVED
R61
2kΩ
CTL0_FLAGA 29
15
16 17 18 19 20 21 22 23 24 25 26 27 28
CR2
3V3_USB
3V3_USB
R59
2kΩ
C38
10pF
24LC64-I_SN
C39
0.1µF
U2
5V_USB
ADP3334
R60
U3
1
2
3
4
5
6
SDA
SCL
A0
3V3_USB
2kΩ
1
2
3
4
IN2
IN1
8
7
6
5
3V3_USB
OUT1
A1
C47
1.0µF
C50
C52
1.0µF
R70
140kΩ
OUT2
FB
1000pF
WC_N
VCC
7
8
A2
R65
2kΩ
SD
GND
NC
3V3_USB
GND
R69
78.7kΩ
CR1
DGND
3V3_USB
C40
0.1µF
C41
0.1µF
C42
0.1µF
C35
0.1µF
C36
0.1µF
C44
0.1µF
C46
0.1µF
Figure 59. USB Evaluation Board Schematic
Rev. B | Page 26 of 32
Data Sheet
ADRF6516
Figure 60. Top Layer Silkscreen
Figure 61. Component Side Layout
Table 6. Evaluation Board Configuration Options
Components
Function
Default Conditions
C1, C2, C4, C5, C11, C12, C15,
C16, L1, L2, R2
Power supply and ground decoupling. Nominal supply decoupling
consists of a 0.1 µF capacitor to ground.
C1, C2 = 10 µF (Size 1210)
C4, C5, C11, C12, C15, C16 =
0.1 µF (Size 0402)
L1, L2 = 33 µH (Size 1812)
R2 = 1 kΩ (Size 0402)
T1, T2, C3, C6, C7 to C10, R31,
R32, R43 to R58
Input interface. Input SMAs INP1, INM1_SE_P, INP2_SE_P, and INM2
are used to drive the part differentially by bypassing the baluns.
Using only INM1_SE_P and INP2_SE_P in conjunction with the baluns
enables single-ended operation. The default configuration of the
evaluation board is for single-ended operation.
T1 and T2 are 8:1 impedance ratio baluns that transform a single-
ended signal in a 50 Ω system into a balanced differential signal in a
400 Ω system.
T1, T2 = ADT8-1T+ (Mini-Circuits)
C3, C6 = 0.1 µF (Size 0402)
C7 to C10 = 100 nF (Size 0602)
R31, R32, R47 to R50, R53, R54,
R57, R58 = 0 Ω (Size 0402)
R43 to R46, R51, R52, R55, R56 =
open (Size 0402)
R31, R32, R47, R48, R49, and R50 are populated for appropriate balun
interface. R51 to R58 are provided for generic placement of matching
components.
To bypass the T1 and T2 baluns for differential interfacing, remove
the balun interfacing resistors R31, R32, R47, R48, R49, and R50, and
populate R43, R44, R45, and R46 with 0 Ω resistors.
T3, T4, C19 to C24,
R7 to R14, R19, R20,
R35 to R42
Output interface. Output SMAs OPP1_SE_P, OPM1, OPP2, and
OPM2_SE_P are used to obtain differential signals from the part
when the output baluns are bypassed. Using OPP1_SE_P,
OPM2_SE_P, and the baluns, the user can obtain single-ended output
signals. The default configuration of the evaluation board is for
single-ended operation.
T3 and T4 are 8:1 impedance ratio baluns that transform a differential
signal in a 400 Ω system into a single-ended signal in a 50 Ω system.
R7, R8, R9, R10, R19, R20, R35, R36, R41, and R42 are populated for
appropriate balun interface. R7 to R14 are provided for generic
placement of matching components.
T3, T4 = ADT8-1T+ (Mini-Circuits)
C19 to C22 = 100 nF (Size 0402)
C23, C24 = 0.1 µF (Size 0402)
R7 to R10, R19, R20, R35, R36,
R41, R42 = 0 Ω (Size 0402)
R11 to R14, R37 to R40 = open
(Size 0402)
To bypass the T3 and T4 baluns for differential interfacing, remove
the balun interfacing resistors R19, R20, R35, R36, R41, and R42, and
populate R37, R38, R39, and R40 with 0 Ω resistors.
Rev. B | Page 27 of 32
ADRF6516
Data Sheet
Components
Function
Default Conditions
P2
Enable interface. The ADRF6516 is powered up by applying a logic
high voltage to the ENBL pin (Jumper P2 is connected to VPS).
P2 = installed for enable
P1, C28, C29, R1, R29, R30, R33, Serial control interface. The digital interface sets the corner
P1 = installed
R34
frequency, the preamplifier gain, the postamplifier gain, and the VGA
maximum gain of the device using the serial interface via the LE, CLK,
DATA, and SDO pins. RC filter networks are provided on the CLK and
LE lines to filter the PC signals. CLK, DATA, and LE signals can be
observed via SMB connectors for debug purposes.
R1 = 10 kΩ (Size 0402)
C28, C29 = 330 pF (Size 0402)
R29, R30 = 100 Ω (Size 0402)
R33, R34 = 0 Ω (Size 0402)
P4, C13, C14, R3
DC offset compensation loop. The dc offset compensation loop is
enabled (low) with Jumper P4. When enabled, the C13 and C14
capacitors are connected to circuit common. The high-pass corner
frequency is expressed as follows:
P4 = installed
C13, C14 = 1000 pF (Size 0402)
R3 = 10 kΩ (Size 0402)
fHP (Hz) = 6.7 × (Post Filter Linear Gain/COFS (µF))
C27
Input common-mode setpoint. The input common-mode voltage
can be set externally when applied to the VICM pin. If the VICM pin is
left open, the input common-mode voltage defaults to VPS/2.
C27 = 0.1 µF (Size 0402)
C18, R6
Output common-mode setpoint. The output common-mode voltage C18 = 0.1 µF (Size 0402)
can be set externally when applied to the VOCM pin. If the VOCM pin
is left open, the output common-mode voltage defaults to VPS/2.
R6 = 0 Ω (Size 0402)
C17, R5
Analog gain control. The range of the GAIN pin is from 0 V to 1 V,
creating a gain scaling of 15 mV/dB.
C17 = 0.1 µF (Size 0402)
R5 = 0 Ω (Size 0402)
U2, U3, U4, P5
Cypress Microcontroller, EEPROM, and LDO
U2 = Microchip MICRO24LC64
U3 = Analog Devices
ADP3334ACPZ
U4 = Cypress Semiconductor
CY7C68013A-56LTXC
P5 = Mini USB connector
C35, C36, C40, C41, C42, C44,
C46
3.3 V supply decoupling. Several capacitors are used for decoupling
on the 3.3 V supply.
C35, C36, C40, C41, C42, C44, C46
= 0.1 µF (0402)
C48, C49, C45, C56, C57, C58,
R59, R60, R61, R62, R64, CR2
Cypress and EEPROM components.
C57, C48 = 10 pF (0402)
C56, C58, C45, C49 = 0.1 µF
(0402)
R59, R60, R61 = 2 kΩ (0402)
R62, R64 = 100 kΩ (0402)
CR2 = ROHM SML-21OMTT86
C47, C50, C52, R65, R69, R70,
CR1
LDO components
C47, C52 = 1 µF (0402)
C50 = 1000 pF (0402)
R65 = 2 kΩ (0402)
R69 = 78.7 kΩ (0402)
R70 = 140 kΩ (0402)
CR1 = ROHM SML-21OMTT86
Y1, C51, C54
Crystal oscillator and components. 24 MHz crystal oscillator.
Y1 = NDK NX3225SA-24MHz
C51, C54 = 22 pF (0402)
Rev. B | Page 28 of 32
Data Sheet
ADRF6516
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
32
1
24
0.50
BSC
PIN 1
INDICATOR
4.75
BSC SQ
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
COPLANARITY
0.08
0.30
0.25
0.18
SEATING
PLANE
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 62. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF6516ACPZ-R7
ADRF6516-EVALZ
Temperature Range
−40°C to +85°C
Package Description
Package Option
32-Lead LFCSP_VQ, 7”Tape and Reel
Evaluation Board
CP-32-2
1 Z = RoHS Compliant Part.
Rev. B | Page 29 of 32
ADRF6516
NOTES
Data Sheet
Rev. B | Page 30 of 32
Data Sheet
NOTES
ADRF6516
Rev. B | Page 31 of 32
ADRF6516
NOTES
Data Sheet
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09422-0-2/12(B)
Rev. B | Page 32 of 32
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