ADRF6510ACPZ-R7 [ADI]
30 MHz Dual Programmable Filters and Variable Gain Amplifiers; 30 MHz双通道可编程滤波器和可变增益放大器
| 型号： | ADRF6510ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | 30 MHz Dual Programmable Filters and Variable Gain Amplifiers |
| 文件： | 总28页 (文件大小：548K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
30 MHz Dual Programmable Filters
and Variable Gain Amplifiers
ADRF6510
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ENBL INP1 INM1 VPS COM GNSW OFS1 VPS
Matched pair of programmable filters and VGAs
Continuous gain control range: −5 dB to +45 dB
6-pole filter
1 MHz to 30 MHz in 1 MHz steps, 0.5 dB corner frequency
SPI programmable
VPSD
COMD
LE
OPP1
OPM1
COM
6 dB front-end gain step
CLK
GAIN
VOCM
COM
SPI
IMD3: >55 dBc for 1.5 V p-p composite output
HD2, HD3: >60 dBc for 1.5 V p-p output
Differential input and output
Adjustable output common-mode voltage
Optional dc output offset correction
Power-down feature
ADRF6510
DATA
SDO
COM
VPS
OPM2
OPP2
Single 5 V supply operation
COM INP2 INM2 VPS COM OFDS OFS2 VPS
APPLICATIONS
Figure 1.
Baseband I/Q receivers
Diversity receivers
ADC drivers
GENERAL DESCRIPTION
The ADRF6510 is a matched pair of fully differential low noise
and low distortion programmable filters and variable gain ampli-
fiers (VGAs). Each channel is capable of rejecting large out-of-
band interferers while reliably boosting the wanted signal, thus
reducing the bandwidth and resolution requirements on the
analog-to-digital converters (ADCs). The excellent matching
between channels and their high spurious-free dynamic range
over all gain and bandwidth settings make the ADRF6510 ideal
for quadrature-based (IQ) communication systems with dense
constellations, multiple carriers, and nearby interferers.
The variable gain amplifiers that follow the filters provide 50 dB
of continuous gain control with a slope of 30 mV/dB. The output
buffers provide a differential output impedance of 20 ꢀ that is
capable of driving 1.5 V p-p into 1 kꢀ loads. The output common-
mode voltage defaults to VPS/2, but it can be programmed via the
VOCM pin. The built-in dc offset correction loop can be disabled
if dc-coupled operation is desired. The high-pass corner frequency
is defined by external capacitors on the OFS1 and OFS2 pins.
The ADRF6510 operates from a 4.75 V to 5.25 V supply and
consumes a maximum supply current of 258 mA when pro-
grammed to the highest bandwidth setting. When disabled, it
consumes 2 mA. The ADRF6510 is fabricated in an advanced
silicon-germanium BiCMOS process and is available in a
32-lead, exposed paddle LFCSP. Performance is specified over
the −40°C to +85°C temperature range.
The filters provide a six-pole Butterworth response with 0.5 dB
corner frequencies programmable through the SPI port from
1 MHz to 30 MHz in 1 MHz steps. The preamplifier that precedes
the filters offers a pin-programmable option of either 6 dB or
12 dB of gain. The preamplifier sets a differential input imped-
ance of 400 Ω and has a common-mode voltage that defaults
to 2.1 V but can be driven from 1.5 V to 2.5 V.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADRF6510
TABLE OF CONTENTS
Features .............................................................................................. 1
Programming the Filters ........................................................... 16
Noise Characteristics ................................................................. 16
Distortion Characteristics......................................................... 17
Maximizing the Dynamic Range.............................................. 17
Key Parameters for Quadrature-Based Receivers.................. 18
Applications Information.............................................................. 19
Basic Connections...................................................................... 19
Error Vector Magnitude (EVM) Performance........................... 19
Low IF Image Rejection............................................................. 20
Example Baseband Interface..................................................... 21
Evaluation Board ............................................................................ 23
Evaluation Board Control Software......................................... 23
Schematics and Artwork ........................................................... 23
Evaluation Board Configuration Options............................... 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 14
Input Buffers ............................................................................... 14
Programmable Filters................................................................. 14
Variable Gain Amplifiers (VGAs) ............................................ 15
Output Buffers/ADC Drivers ................................................... 15
DC Offset Compensation Loop................................................ 15
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADRF6510
SPECIFICATIONS
VPS = 5 V, TA = 25°C, ZSOURCE = 400 ꢀ, ZLOAD = 1 kꢀ, VOUT = 1.5 V p-p, bandwidth setting = 30 MHz, GNSW = 0 V, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RESPONSE
Low-Pass Corner Frequency, fC
Step Size
Corner Frequency Absolute
Accuracy
6-pole Butterworth filter, 0.5 dB bandwidth
Over operating temperature range
1
30
MHz
MHz
% fC
1
15
Corner Frequency Matching
Channel A and Channel B at same gain and
bandwidth settings
0.5
% fC
Pass-Band Ripple
Gain Matching
0.5
0.1
dB p-p
dB
Channel A and Channel B at same gain and
bandwidth settings
Group Delay Variation
From midband to peak
Corner Frequency = 1 MHz
Corner Frequency = 30 MHz
Group Delay Matching
Corner Frequency = 1 MHz
Corner Frequency = 30 MHz
Stop-Band Rejection
135
11
ns
ns
Channel A and Channel B at same gain
5
0.2
ns
ns
Relative to Pass Band
2 × fC
5 × fC
30
75
dB
dB
INPUT STAGE
INP1, INM1, INP2, INM2
At minimum gain, VGAIN = 0 V
Maximum Input Swing
Differential Input Impedance
Input Common-Mode Range
1
V p-p
400
Ω
V
V
1 V p-p input voltage
Input pins left floating
GAIN, GNSW
1.5
VPS/2
VPS/2
GAIN CONTROL
Voltage Gain Range
GNSW = 0 V, VGAIN from 0 V to 2 V
GNSW = 5 V
−5
1
+45
51
dB
dB
Gain Slope
Gain Error
Gain Step
30
0.2
6
mV/dB
dB
dB
VGAIN from 500 mV to 1.7 V
GNSW = 0 V to 5 V
OUTPUT STAGE
Maximum Output Swing
OPP1, OPM1, OPP2, OPM2, VOCM
At maximum gain, RLOAD = 1 kΩ
HD2 > 60 dBc, HD3 > 60 dBc
2
V p-p
V p-p
Ω
mV
V
1.5
20
35
Differential Output Impedance
Output DC Offset
Output Common-Mode Range
Inputs shorted, offset loop disabled
1.5 V p-p output voltage
VOCM left floating
1.5
3.0
VPS/2
V
NOISE/DISTORTION
1 MHz Corner Frequency
Output Noise Density
Gain = 0 dB at fC/2
Gain = 20 dB at fC/2
Gain = 40 dB at fC/2
−129
−127
−111
dBV/√Hz
dBV/√Hz
dBV/√Hz
Second Harmonic, HD2
Third Harmonic, HD3
250 kHz fundamental, 1.5 V p-p output voltage
Gain = 0 dB
Gain = 40 dB
250 kHz fundamental, 1.5 V p-p output voltage
Gain = 0 dB
Gain = 40 dB
46.2
43.2
dBc
dBc
52.2
51.2
dBc
dBc
Rev. 0 | Page 3 of 28
ADRF6510
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
IMD3
f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite
output voltage
Gain = 5 dB
Gain = 35 dB
f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite
output, gain = 5 dB; blocker at 5 MHz, 10 dBc
relative to two-tone composite output voltage
61
57
40
dBc
dBc
dBc
IMD3 with Input CW Blocker
30 MHz Corner Frequency
Output Noise Density
Midband, gain = 0 dB
Midband, gain = 20 dB
Midband, gain = 40 dB
8 MHz fundamental, 1.5 V p-p output voltage
Gain = 0 dB
Gain = 40 dB
8 MHz fundamental, 1.5 V p-p output voltage
Gain = 0 dB
−130
−130
−123
dBV/√Hz
dBV/√Hz
dBV/√Hz
Second Harmonic, HD2
Third Harmonic, HD3
IMD3
63
84
dBc
dBc
54
87
dBc
dBc
Gain = 40 dB
f1 = 15 MHz, f2 = 16 MHz, 1.5 V p-p composite
output voltage
Gain = 5 dB
Gain = 35 dB
f1 = 15 MHz, f2 = 16 MHz, 1.5 V p-p composite
output, gain = 5 dB; blocker at 150 MHz, 10 dBc
relative to two-tone composite output voltage
59
77.5
55
dBc
dBc
dBc
IMD3 with Input CW Blocker
DIGITAL LOGIC
LE, CLK, DATA, SDO, OFDS, GNSW
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
>2
<0.8
<1
2
V
V
μA
pF
SPI TIMING
fSCLK
LE, CLK, DATA, SDO
1/tSCLK
20
5
5
MHz
ns
ns
tDH
tDS
tLH
DATA hold time
DATA setup time
LE hold time
5
ns
tLS
LE setup time
5
ns
tPW
tD
CLK high pulse width
CLK to SDO delay
VPS, VPSD, COM, COMD, ENBL
5
5
ns
ns
POWER AND ENABLE
Supply Voltage Range
Total Supply Current
4.75
5.0
5.25
V
ENBL = 5 V
Maximum bandwidth setting
Minimum bandwidth setting
ENBL = 0 V
258
131
2
2.5
20
mA
mA
mA
V
μs
ns
Disable Current
Disable Threshold
Enable Response Time
Disable Response Time
Delay following ENBL low-to-high transition
Delay following ENBL high-to-low transition
300
Rev. 0 | Page 4 of 28
ADRF6510
TIMING DIAGRAMS
tCLK
tPW
CLK
tLH
tLS
LE
tDS
tDH
DATA
WRITE BIT
LSB
LSB + 1
MSB – 2
MSB – 1
MSB
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL CORNER FREQUENCY
WORD REGISTER. FOR A WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE CORNER FREQUENCY WORD BIT IS THEN
REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.
Figure 2. Write Mode Timing Diagram
tPW
tCLK
tD
CLK
LE
tLH
tLS
tDS
tDH
READ BIT
DC
LSB
DC
DC
MSB – 2
DC
DC
MSB
DC
DC
DATA
SDO
LSB + 1
MSB – 1
NOTES
1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL CORNER FREQUENCY WORD
REGISTER. FOR A READ OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE CORNER FREQUENCY WORD BIT IS THEN UPDATED AT
THE SDO PIN ON CONSECUTIVE FALLING EDGES OF THE CLOCK.
Figure 3. Read Mode Timing Diagram
Rev. 0 | Page 5 of 28
ADRF6510
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltages, VPS, VPSD
ENBL, GNSW, OFDS, LE, CLK, DATA, SDO
INP1, INM1, INP2, INM2
5.25 V
VPS + 0.6 V
VPS + 0.6 V,
GND − 0.6 V
OPP1, OPM1, OPP2, OPM2
OFS1, OFS2
GAIN
Internal Power Dissipation
θJA (Exposed Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
VPS + 0.6 V
VPS + 0.6 V
VPS + 0.6 V
1.4 W
37.4°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
ESD CAUTION
Rev. 0 | Page 6 of 28
ADRF6510
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPSD
COMD
LE
1
2
3
4
5
6
7
8
24 OPP1
23 OPM1
22 COM
21 GAIN
20 VOCM
19 COM
18 OPM2
17 OPP2
PIN 1
INDICATOR
CLK
ADRF6510
TOP VIEW
(Not to Scale)
DATA
SDO
COM
VPS
NOTES
1. CONNECT THE EXPOSED PADDLE TO
A LOW IMPEDANCE GROUND PAD.
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
VPSD
COMD
LE
CLK
DATA
SDO
Description
Digital Positive Supply Voltage: 4.75 V to 5.25 V.
Digital Common. Connect to external circuit common using the lowest possible impedance.
Latch Enable. SPI programming pin. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V.
SPI Port Clock. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V.
1
2
3
4
5
6
SPI Data Input. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V.
SPI Data Output. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V.
7, 9, 13, 19, 22, 28 COM
Analog Common. Connect to external circuit common via a 1 kΩ resistor.
Analog Positive Supply Voltage: 4.75 V to 5.25 V.
Differential Inputs. 400 Ω input impedance. Common-mode range is 1.5 V to 2.5 V; default is 2.1 V.
8, 12, 16, 25, 29
10, 11, 30, 31
VPS
INP2, INM2,
INM1, INP1
14
OFDS
Offset Correction Loop Disable. Pull high to disable the offset correction loop.
15, 26
17, 18, 23, 24
OFS2, OFS1
OPP2, OPM2,
OPM1, OPP1
Offset Correction Loop Compensation Capacitors. Connect capacitors to circuit common.
Differential Outputs. 20 Ω output impedance. Common-mode range is 1.5 V to 3 V; default is VPS/2.
20
21
27
32
VOCM
GAIN
GNSW
ENBL
EP
Output Common-Mode Setpoint. Defaults to VPS/2 if left open.
Analog Gain Control. 0 V to 2 V, 30 mV/dB gain scaling.
Front-End Gain Switch, 6 dB or 12 dB. Pull low for 6 dB; pull high for 12 dB.
Chip Enable. Pull high to enable.
Exposed Paddle. Connect the exposed paddle to a low impedance ground pad.
Rev. 0 | Page 7 of 28
ADRF6510
TYPICAL PERFORMANCE CHARACTERISTICS
VPS = 5 V, TA = 25°C, ZSOURCE = 400 ꢀ, ZLOAD = 1 kꢀ, VOUT = 1.5 V p-p, GNSW = 0 V, unless otherwise noted.
50
45
3.0
2.5
BANDWIDTH = 30MHz
BANDWIDTH = 30MHz
+25°C
VPS = 4.75V, 5V, 5.25V
40
35
30
25
20
15
10
5
2.0
+85°C
VPS = 4.25V, 5V, 5.25V
1.5
1.0
0.5
0
–40°C
VPS = 4.75V, 5V, 5.25V
–0.5
–1.0
–1.5
–2.0
–2.5
+85°C
VPS = 4.75V, 5V, 5.25V
+25°C
VPS = 4.25V, 5V, 5.25V
–40°C
VPS = 4.25V, 5V, 5.25V
0
–5
–10
–3.0
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
(mV)
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
(mV)
V
V
GAIN
GAIN
Figure 5. In-Band Gain vs. VGAIN over Supply and Temperature
(Bandwidth Setting = 30 MHz)
Figure 8. Gain Conformance vs. VGAIN over Supply and Temperature
(Bandwidth Setting = 30 MHz)
50
45
40
35
30
25
20
15
10
5
3
9
8
7
6
5
4
3
2
BANDWIDTH = 30MHz
BANDWIDTH = 30MHz
PREAMP GAIN = 12dB
1
–1
–3
–5
–7
–9
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
PREAMP GAIN = 6dB
1
10
FREQUENCY (MHz)
100
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
Figure 6. Gain vs. Frequency by VGAIN (Bandwidth Setting = 30 MHz)
Figure 9. 6 dB Gain Step and Gain Error vs. Frequency
(Bandwidth Setting = 30 MHz, VGAIN = 0 V)
0.25
40
35
PREAMP GAIN = 6dB
PREAMP GAIN = 12dB
BANDWIDTH = 30MHz
0.20
0.15
30
25
0.10
0.05
0
20
15
–0.05
10
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
(V)
0
5
10
15
20
25
30
35
40
V
GAIN (dB)
GAIN
Figure 10. Output P1dB vs. GAIN at 15 MHz (Bandwidth Setting = 30 MHz)
Figure 7. Gain Matching vs. VGAIN (Bandwidth Setting = 30 MHz)
Rev. 0 | Page 8 of 28
ADRF6510
40
35
1000
900
GAIN = 20dB
800
700
600
500
400
300
200
100
0
30
25
20
15
10
5
BW = 1MHz
BW = 5MHz
BW = 10MHz
BW = 20MHz
BW = 30MHz
0
–5
–10
1M
10M
100M
0.5
5
50
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 11. Frequency Response vs. Bandwidth Setting (Gain = 30 dB),
Log Scale
Figure 14. Group Delay vs. Frequency (Gain = 20 dB)
32
31
1.0
0.5
BANDWIDTH = 30MHz
GAIN = 20dB
30
29
28
27
0
–0.5
–1.0
GAIN = 40dB
1
6
11
16
21
26
31
36
40
0.5
5
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Frequency Response vs. Bandwidth Setting (Gain = 30 dB),
Linear Scale
Figure 15. Group Delay Mismatch vs. Frequency
(Bandwidth Setting = 30 MHz)
30
5
4
29
BANDWIDTH = 1MHz
–40°C
28
+25°C
27
3
GAIN = 20dB
26
25
2
24
1
+85°C
23
22
21
20
19
18
17
16
15
0
–1
–2
–3
–4
GAIN = 0dB
–5
0.2
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
FREQUENCY (MHz)
0.4
0.6
0.8
1.0
1.2
1.4
FREQUENCY (MHz)
Figure 13. Frequency Response over Temperature
(Gain = 26 dB, Bandwidth Setting = 30 MHz)
Figure 16. IQ Group Delay Mismatch vs. Frequency
(Bandwidth Setting = 1 MHz)
Rev. 0 | Page 9 of 28
ADRF6510
FREQUENCY (MHz)
1.0 1.5 2.0
100
90
0
0.5
2.5
3.0
0.75
0.50
80
70
60
50
40
BANDWIDTH = 1MHz
0.25
0
BANDWIDTH = 30MHz
+25°C, VPS = 4.75V
+25°C, VPS = 5V
+25°C, VPS = 5.25V
+85°C, VPS = 4.75V
+85°C, VPS = 5V
+85°C, VPS = 5.25V
–40°C, VPS = 4.75V
–40°C, VPS = 5V
–0.25
–0.50
–0.75
–40°C, VPS = 5.25V
0
40
5
10
15
20
25
30
35
GAIN (dB)
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 20. HD3 vs. Gain over Supply and Temperature
(Bandwidth Setting = 30 MHz)
Figure 17. IQ Amplitude Mismatch vs. Frequency
90
85
100
90
1.5V p-p OUTPUT @ 8MHz
BANDWIDTH = 30MHz
80
75
70
65
60
55
50
45
40
80
70
60
50
40
+25°C, VPS = 4.75V
+25°C, VPS = 5V
+25°C, VPS = 5.25V
+85°C, VPS = 4.75V
+85°C, VPS = 5V
+85°C, VPS = 5.25V
–40°C, VPS = 4.75V
–40°C, VPS = 5V
VOCM = 1.5V
VOCM = 1.75V
VOCM = 2V
VOCM = 2.5V
–40°C, VPS = 5.25V
0
40
0
5
10
15
20
25
30
35
40
5
10
15
20
25
30
35
GAIN (dB)
GAIN (dB)
Figure 18. HD2 vs. Gain over Supply and Temperature
(Bandwidth Setting = 30 MHz)
Figure 21. HD3 vs. Gain over Output Common-Mode Voltage
(Bandwidth Setting = 30 MHz)
100
90
80
70
60
30
1.5V p-p OUTPUT @ 8MHz
BANDWIDTH = 30MHz
BANDWIDTH = 30MHz
f1 = 14MHz, f2 = 15MHz
25
PREAMP
GAIN = 6dB
20
15
PREAMP
GAIN = 12dB
10
50
40
30
VOCM = 1.5V
VOCM = 1.75V
VOCM = 2V
5
0
VOCM = 2.5V
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
45
50
GAIN (dB)
GAIN (dB)
Figure 19. HD2 vs. Gain over Output Common-Mode Voltage
(Bandwidth Setting = 30 MHz)
Figure 22. In-Band OIP3 vs. Gain (Bandwidth Setting = 30 MHz)
Rev. 0 | Page 10 of 28
ADRF6510
30
25
20
15
10
5
65
55
45
35
25
15
5
–5
–15
–25
–35
–45
–55
–65
–75
–85
–95
–105
–115
–125
–135
–145
BANDWIDTH = 30MHz
BANDWIDTH = 30MHz
f1 = 14MHz, f2 = 15MHz
–40°C
+25°C
+85°C
2:1 SLOPE
PREAMP
GAIN = 12dB
OUT-OF-BAND IIP2
PREAMP
GAIN = 6dB
0
0
5
10
15
20
25
30
35
40
–45 –35 –25 –15 –5
5
15
25
35
55 65
GAIN (dB)
INPUT LEVEL @ 115MHz AND 130MHz (dBV/Tone)
Figure 23. In-Band OIP3 vs. Gain over Temperature
(Preamp Gain = 6 dB, Bandwidth Setting = 30 MHz)
Figure 26. Out-of-Band IIP2: IMD2 Tone at Midband
(Bandwidth Setting = 30 MHz)
120
100
80
10
0
GAIN = 0dB
BANDWIDTH = 30MHz
GAIN = 10dB
GAIN = 20dB
GAIN = 30dB
GAIN = 40dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
3:1 SLOPE
60
PREAMP
GAIN = 12dB
OUT-OF-BAND IIP3
40
PREAMP
GAIN = 6dB
20
0
–130
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–45 –40 –35 –30 –25 –20 –15 –10
–5
0
5
COMPOSITE OUTPUT VOLTAGE (V p-p)
INPUT LEVEL @ 115MHz AND 215MHz (dBV/Tone)
Figure 24. In-Band Third-Order Intermodulation Distortion
(Preamp Gain = 6 dB, Bandwidth Setting = 30 MHz)
Figure 27. Out-of-Band IIP3: IMD3 Tone at Midband
(Bandwidth Setting = 30 MHz)
120
70
65
GAIN = 6dB
GAIN = 16dB
GAIN = 26dB
GAIN = 36dB
GAIN = 46dB
1MHz BW
2MHz BW
4MHz BW
6MHz BW
8MHz BW
30MHz BW
100
80
60
40
20
0
60
55
50
45
40
35
30
25
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–5
0
5
10
15
20
25
30
35
40
45
COMPOSITE OUTPUT VOLTAGE (V p-p)
GAIN (dB)
Figure 25. In-Band Third-Order Intermodulation Distortion
(Preamp Gain = 12 dB, Bandwidth Setting = 30 MHz)
Figure 28. Noise Figure vs. Gain over Bandwidth Setting,
Preamp Gain = 6 dB (Noise Figure at 1/2 Bandwidth)
Rev. 0 | Page 11 of 28
ADRF6510
60
55
–90
–95
1MHz BW
2MHz BW
4MHz BW
6MHz BW
8MHz BW
30MHz BW
GAIN = 0dB
GAIN = 20dB
GAIN = 40dB
50
45
40
35
30
25
20
15
–100
–105
–110
–115
–120
–125
–130
–135
10
–140
0
5
10
15
20
25
30
35
40
45
50
0.5
1.0
1.5
2.0
2.5
3.0
GAIN (dB)
FREQUENCY (MHz)
Figure 29. Noise Figure vs. Gain over Bandwidth Setting,
Preamp Gain = 12 dB (Noise Figure at 1/2 Bandwidth)
Figure 32. Output Noise Density vs. Frequency (Bandwidth Setting = 1 MHz)
–100
–105
–110
–115
–120
–125
–130
–110
1MHz BW
2MHz BW
4MHz BW
6MHz BW
8MHz BW
30MHz BW
GAIN = 0dB
GAIN = 20dB
GAIN = 40dB
–115
–120
–125
–130
–135
–140
–135
–5
0
5
10
15
20
25
30
35
40
45
10
12
14
16
18
20
22
24
26
28
30
GAIN (dB)
FREQUENCY (MHz)
Figure 30. Output Noise Density vs. Gain by Bandwidth Setting,
Preamp Gain = 6 dB (Noise at 1/2 Bandwidth)
Figure 33. Output Noise Density vs. Frequency (Bandwidth Setting = 20 MHz)
–100
–90
–95
1MHz BW
2MHz BW
4MHz BW
6MHz BW
–105
–100
8MHz BW
30MHz BW
–110
–105
GAIN = 40dB
–110
–115
–115
–120
–125
–130
–135
–120
GAIN = 20dB
–125
–130
GAIN = 0dB
–135
–140
0
5
10
15
20
25
30
35
40
45
50
–35
–30
–25
–20
–15
–10
GAIN (dB)
BLOCKER LEVEL @ 150MHz (dBV rms)
Figure 31. Output Noise Density vs. Gain by Bandwidth Setting,
Preamp Gain = 12 dB (Noise at 1/2 Bandwidth)
Figure 34. Output Noise Density vs. Blocker Level
(Bandwidth Setting = 30 MHz, Blocker at 150 MHz)
Rev. 0 | Page 12 of 28
ADRF6510
450
440
430
420
410
400
390
380
370
360
10
280
260
5
0
240
220
200
180
160
140
120
100
–5
–10
–15
–20
–25
–30
–35
350
–40
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FREQUENCY (MHz)
BANDWIDTH SETTING (MHz)
Figure 35. Input Impedance vs. Frequency (Bandwidth Setting = 30 MHz)
Figure 38. Current Consumption vs. Bandwidth Setting (Gain = 20 dB)
28
27
200
100
266
264
262
260
258
256
254
26
25
24
23
22
21
20
0
–100
–200
–300
–400
–500
–600
252
VPS = 4.75V
VPS = 5V
VPS = 5.25V
250
248
0
5
10
15
20
25
30
–50
–30
–10
10
30
50
70
90
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 36. Output Impedance vs. Frequency (Bandwidth Setting = 30 MHz)
Figure 39. Current Consumption vs. Temperature over Supply
(Bandwidth Setting = 30 MHz)
90
70
BANDWIDTH = 30MHz
BANDWIDTH = 30MHz
80
60
GAIN = 40dB
70
GAIN = 40dB
50
GAIN = 20dB
60
40
30
20
10
0
50
GAIN = 20dB
40
GAIN = 0dB
30
20
10
0
0.1
1
10
FREQUENCY (MHz)
100
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 37. Channel Isolation, Output to Output, vs. Frequency
(Bandwidth Setting = 30 MHz)
Figure 40. Common-Mode Rejection Ratio vs. Frequency
(Bandwidth Setting = 30 MHz)
Rev. 0 | Page 13 of 28
ADRF6510
THEORY OF OPERATION
The ADRF6510 consists of a matched pair of buffered, program-
mable filters followed by variable gain amplifiers and output
ADC drivers. The block diagram of a single channel is shown
in Figure 41. The programmability of the bandwidth and of the
pre- and post-filtering gain offers great flexibility when coping
with signals of varying levels in the presence of noise and large,
undesired signals nearby. The entire differential signal chain is
dc-coupled with flexible interfaces at the input and output. The
bandwidth and gain setting controls for the two channels are
shared, ensuring close matching of their magnitude and phase
responses. The ADRF6510 can be fully disabled through the
ENBL pin.
band rejection, ripple, and group delay. The 0.5 dB bandwidth is
programmed from 1 MHz to 30 MHz in 1 MHz steps via the serial
programming interface (SPI) as described in the Programming
the Filters section.
The filters are designed so that the Butterworth prototype filter
shape and group delay responses vs. frequency are retained for
any bandwidth setting. Figure 42 and Figure 43 illustrate the
ideal six-pole Butterworth gain and group delay responses,
respectively. The group delay, τg, is defined as
τg = −∂φ/∂ω
where:
φ is the phase in radians.
ω = 2πf is the frequency in radians/second.
6dB/12dB
1MHz TO 30MHz
50dB
OUTPUT ADC
PREAMP
PROG. FILTERS
VGA
DRIVER
BASEBAND
INPUTS
BASEBAND
OUTPUTS
Note that for a frequency scaled filter prototype, the absolute
magnitude of the group delay scales inversely with the band-
width; however, the shape is retained. For example, the peak
group delay for a 28 MHz bandwidth setting is 14× less than
for a 2 MHz setting.
SPI
INTERFACE
ANALOG
OUTPUT
COMMON-MODE
CONTROL
PREAMP
GAIN SWITCH
GAIN CONTROL
30mV/dB
FILTER
PROGRAMMING
SPI BUS
0
–20
–40
Figure 41. Signal Path Block Diagram for a Single Channel of the ADRF6510
Filtering and amplification are fundamental operations in any
signal processing system. Filtering is necessary to select the
intended signal while rejecting out-of-band noise and interferers.
Amplification increases the level of the desired signal to overcome
noise added by the system. When used together, filtering and
amplification can extract a low level signal of interest in the
presence of noise and out-of-band interferers. Such analog
signal processing alleviates the requirements on the analog,
mixed signal, and digital components that follow.
–60
–80
–100
–120
–140
–160
–180
1M
10M
100M
1G
INPUT BUFFERS
FREQUENCY (Hz)
The input buffers provide a convenient interface to the sensitive
filter sections that follow. They set a differential input impedance
of 400 ꢀ and sit at a nominal common-mode voltage of VPS/2.
The inputs can be dc-coupled or ac-coupled. If using direct
dc-coupling, the common-mode voltage, VCM, can range from
1.5 V to 3 V. A current flows into or out of the input pins to
accommodate the difference in common-mode voltages. The
current into each pin is given by
Figure 42. Sixth-Order Butterworth Magnitude Response for 0.5 dB
Bandwidths; Programmed from 2 MHz to 29 MHz in 1 MHz Steps
500
400
2MHz
28MHz
300
200
100
0
(VCM – (VPS/2))/200 ꢀ
14x
The input buffers in both channels can be configured simulta-
neously to a gain of 6 dB or 12 dB through the GNSW pin. When
configured for a 6 dB gain, the buffers support up to a 1 V p-p
differential input level with >50 dBc harmonic distortion. For
a 12 dB gain setting, the buffers support 0.5 V p-p inputs.
–100
100k
1M
10M
FREQUENCY (Hz)
100M
PROGRAMMABLE FILTERS
Figure 43. Sixth-Order Butterworth Group Delay Response for
0.5 dB Bandwidths; Programmed to 2 MHz and 28 MHz
The integrated programmable filter is the key signal processing
function in the ADRF6510. The filters follow a six-pole Butter-
worth prototype response that provides a compromise between
Rev. 0 | Page 14 of 28
ADRF6510
The corner frequency of the filters is defined by RC products,
which can vary by 30ꢁ in a typical process. Therefore, all the
parts are factory calibrated for corner frequency, resulting in
a residual 10ꢁ corner frequency variation over the −40°C to
+85°C temperature range. Although absolute accuracy requires
calibration, the matching of RC products between the pair of
channels is better than 1ꢁ by observing careful design and
layout practices. Calibration and excellent matching ensure
that the magnitude and group delay responses of both channels
track together, a critical requirement for digital IQ-based
communication systems.
DC OFFSET COMPENSATION LOOP
In many signal processing applications, no information is
carried in the dc level. In fact, dc voltages and other low
frequency disturbances can often dominate the intended signal
and consume precious dynamic range in the analog path and
bits in the data converters. These dc voltages can be present
with the desired input signal or can be generated inside the
signal path by inherent dc offsets or other unintended signal-
dependent processes such as self-mixing or rectification.
Because the ADRF6510 is fully dc-coupled, it may be necessary
to remove these offsets to realize the maximum signal-to-noise
ratio (SNR). This can be achieved with ac-coupling capacitors
at the input and output pins, but that would require large values
because the impedances are fairly low, and high-pass corners
may need to be <10 Hz in some cases. To address the issue of dc
offsets, the ADRF6510 provides an offset correction loop that
nulls the output differential dc level as shown in Figure 45. If
the correction loop is not required, it can be disabled through
the OFDS pin.
VARIABLE GAIN AMPLIFIERS (VGAs)
The VGAs are implemented using the Analog Devices, Inc.,
patented X-AMP® architecture, consisting of a tapped 50 dB
attenuator followed by a fixed-gain amplifier. The X-AMP archi-
tecture generates a linear-in-dB monotonic gain response with
low ripple. The gain is controlled through the high impedance
GAIN pin with an accurate slope of 30 mV/dB. The gain response
shown in Figure 44 shows the GAIN pin voltage range and the
absence of gain foldback at high VGAIN
.
C
OFS
OFDS
50
0.3
0.2
0.1
0
OFSx
30mV/dB
40
30
20
10
0
BASEBAND
OUTPUT
FROM
FILTERS
50dB
VGA
OUTPUT ADC
DRIVER
–0.1
–0.2
GAIN
Figure 45. Offset Compensation Loop Operates Around the VGA
and Output Buffer
The offset control loop creates a high-pass corner, fHP, that
is superimposed on the normal Butterworth filter response.
Typically, fHP is many orders of magnitude lower than the lower
programmed filter bandwidth so that there is no interaction
between them. Setting fHP is accomplished with capacitors,
–10
–0.3
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
(V)
GAIN
Figure 44. Linear-in-dB Gain Control Response of the X-Amp VGA
Showing Consistent Slope and Low Error
OUTPUT BUFFERS/ADC DRIVERS
COFS, from the OFS1 and OFS2 pins to ground. Because the
correction loop works around the VGA section, fHP is also
dependent on the gain of the VGA. In general, the expression
for fHP is given by
The low impedance (20 ꢀ) output buffers of the ADRF6510 are
designed to drive either ADC inputs or subsequent amplifier stages.
They are capable of delivering up to 4 V p-p composite two-tone
signals into 500 ꢀ differential loads with >60 dBc IM3. The
output common-mode voltage defaults to VPS/2, but it can be
adjusted from 1.5 V to 3.0 V without loss of drive capability by
presenting the VOCM pin with the desired common-mode
voltage. The high input impedance of VOCM allows the ADC
reference output to be connected directly. Even though the
signal path is fully dc-coupled and the dc offset compensation
loop can remove undesired dc offsets (see the DC Offset
Compensation Loop section), the output buffers can be ac-
coupled to the next stage by properly selecting the coupling
capacitors according to the load impedance.
f
HP (Hz) = 1.2 × (Gain/COFS
where:
Gain is expressed in linear terms, not in decibels (dB).
OFS is expressed in microfarads (μF).
)
C
Note that fHP increases in proportion to the gain. For this
reason, COFS should be chosen at the highest operating gain
to guarantee that fHP is always below the maximum limit
required by the system.
Rev. 0 | Page 15 of 28
ADRF6510
PROGRAMMING THE FILTERS
NOISE CHARACTERISTICS
The 0.5 dB corner frequencies for both filters are programmed
simultaneously through the SPI port. A 5-bit register stores the
codes for corner frequencies of 1 MHz through 30 MHz (see
Table 4). The SPI protocol not only allows frequency codes to
be written to the DATA pin but also allows the stored code to
be read back from the SDO pin.
The output noise behavior of the ADRF6510 depends on the gain
and bandwidth settings. Both the filter sections and the VGAs
contribute to the total noise at the output. The filter contributes
a noise spectral density profile that is flat at low frequencies, peaks
near the corner frequency, and then rolls off as the filter poles
roll off the gain. The magnitude of the noise spectral density,
expressed in nV/√Hz, varies inversely with the square root of
the bandwidth setting, resulting in a total integrated noise in
nV that is nearly constant with bandwidth setting.
The latch enable (LE) pin must first go to a Logic 0 for a read or
write cycle to begin. On the next rising edge of the clock (CLK),
a Logic 1 on the DATA pin initiates a write cycle, whereas a
Logic 0 on the DATA pin initiates a read cycle. In a write cycle,
the next five CLK rising edges latch the frequency code, LSB
first. When LE goes high, the write cycle is completed and the
frequency code is presented to the filter. In a read cycle, the next
five CLK falling edges present the stored frequency code, LSB
first. When LE goes high, the read cycle is completed. Detailed
timing diagrams are shown in Figure 2 and Figure 3.
The X-AMP type VGAs used in the ADRF6510 contribute
a fixed noise spectral density to the output, independent of
the gain setting, of −130 dBV/√Hz, which is equivalent to
316 nV/√Hz. Although the VGA noise contribution to the
output is fixed, the gain of the VGA controls the relative
contribution of the filter noise.
Figure 46 and Figure 47 show the total output noise spectral
density vs. frequency for different bandwidth settings. At low
values of VGA gain, the noise at the output is the flat spectral
density contributed by the VGA because the filter noise is sup-
pressed by the VGA attenuation. As the gain increases, more
of the filter noise appears at the output. Because the filter noise
increases at lower bandwidth settings, it overwhelms the VGA
noise floor. In either case, the noise density asymptotically
approaches the −130 dBV/√Hz limit set by the VGA at the
highest frequencies. For other values of VGA gain and band-
width setting, the detailed shape of the noise spectral density
changes.
Table 4. Frequency Code vs. Corner Frequency Lookup Table
5-Bit Binary Frequency Code1 Corner Frequency (MHz)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
1
2
3
4
5
6
7
8
9
–115
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
30
30
BANDWIDTH = 20MHz
GAIN = 40dB
–120
–125
GAIN = 20dB
–130
GAIN = 0dB
–135
10
15
20
25
30
35
40
45
50
55
60
FREQUENCY (MHz)
Figure 46. Total Output Noise with a 20 MHz Corner Frequency
for Three Different Gain Settings
1 MSB first.
Rev. 0 | Page 16 of 28
ADRF6510
–100
–105
To distinguish and quantify the distortion performance of the
input section, two different IP3 specifications are presented.
The first is called in-band IP3 and refers to a two-tone test
where the signals are inside the filter bandwidth. This is exactly
the same figure of merit familiar to communications engineers
in which the third-order intermodulation level, IM3, is
measured.
BANDWIDTH = 1MHz
GAIN = 40dB
–110
–115
–120
–125
–130
–135
GAIN = 20dB
To quantify the effect of out-of-band signals, a new out-of-band
(OOB) IIP3 figure of merit is introduced. This test also involves
a two-tone stimulus; however, the two tones are placed out-of-
band so that the lower IM3 product lands in the middle of the
filter pass band. At the output, only the IM3 product is visible
because the original two tones are filtered out. To calculate the
OOB IP3 at the input, the IM3 level is referred to the input by
the overall gain. The OOB IIP3 allows the user to predict the
impact of out-of-band blockers or interferers at an arbitrary
signal level on the in-band performance. The ratio of the
desired input signal level to the input-referred IM3 at a given
blocker level represents a signal-to-distortion limit imposed by
the out-of-band signals.
GAIN = 0dB
1.5
0.5
1.0
2.0
2.5
3.0
FREQUENCY (MHz)
Figure 47. Total Output Noise with a 1 MHz Corner Frequency
for Three Different Gain Settings
Note that the noise spectral density outside the filter bandwidth
is limited by the fixed VGA output noise. It may be necessary to
use an external, fixed-frequency, passive filter prior to an analog-
to-digital conversion to prevent noise aliasing from degrading
the signal-to-noise ratio. The higher the sampling rate relative
to the maximum ADRF6510 corner frequency setting to be used,
the lower the order of the external filter.
MAXIMIZING THE DYNAMIC RANGE
The role of the ADRF6510 is to increase the level of a variable
in-band signal while minimizing out-of-band signals. Ideally,
this is achieved without degrading the SNR of the incoming
signal or introducing distortion to the incoming signal.
DISTORTION CHARACTERISTICS
The distortion performance of the ADRF6510 is similar to its
noise performance. The filters and the VGAs contribute to the
overall distortion and signal handling capabilities. Furthermore,
the front end must also cope with out-of-band signals that can be
larger than the in-band signals. These out-of-band signals are
filtered before reaching the VGA. It is important to understand
the signals presented to the ADRF6510 and to match these
signals with the input and output characteristics of the part.
The first goal is to maximize the output signal swing, which can
be defined by the ADC input range or the input signal capacity
of the next analog stage. For the complex waveforms often encoun-
tered in communication systems, the peak-to-average ratio, or
crest factor, must be considered when choosing the peak-to-peak
output. From the chosen output signal and the maximum gain
of the ADRF6510, the minimum input level can be defined.
Lower signal levels do not yield the maximum output and suffer
a greater degradation in SNR.
When the gain is low, the distortion is typically limited by the
input section because the output is not driven to its maximum
capacity. When the gain is high, the distortion is likely limited
by the output section because the input is not driven to its
maximum capacity. An exception to this is when the input is
driven with a small desired signal in combination with a large
out-of-band signal. In this case, the out-of-band signal may
drive the input to distort. As long as the input is not overdriven,
the out-of-band signal is removed by the filter. A high VGA
gain is still needed to raise the small desired signal to a higher
level at the output. The overall distortion introduced by the part
depends on the input drive level, including the out-of-band
signals, and the desired output signal level.
As the input signal level increases, the VGA gain is reduced from
its maximum gain point to maintain the desired fixed output
level. The output noise, initially dominated by the filter, follows
the gain reduction, yielding a progressively better SNR. At some
point, the VGA gain drops sufficiently that the constant VGA
noise becomes dominant, resulting in a constant SNR from that
point. From the perspective of SNR alone, the maximum input
level is reached when the VGA reaches its minimum gain.
Distortion must also be considered when maximizing the dynamic
range. At low and moderate signal levels, the output distortion
is constant and assumed to be adequate for the selected output
level. At some point, the input signal becomes large enough that
distortion at the input limits the system. The maximum tolerable
input signal depends on whether the input distortion becomes
unacceptably large or the minimum gain is reached.
As noted in the Input Buffers section, the input section can
handle a total signal level of 1 V p-p for a 6 dB preamplifier and
500 mV p-p for a 12 dB preamplifier with >50 dBc harmonic
distortion. This includes both in-band and out-of-band signals.
Rev. 0 | Page 17 of 28
ADRF6510
The most challenging scenario in terms of dynamic range is the
presence of a large out-of-band blocker accompanying a weaker
in-band wanted signal. In this case, the maximum input level is
dictated by the blocker and its inclination to cause distortion.
After filtering, the weak wanted signal must be amplified to the
desired output level, possibly requiring maximum gain. Both
the distortion limits associated with the blocker at the input and
the SNR limits created by the weaker signal and higher gains are
present simultaneously. Furthermore, not only does the blocker
scenario degrade the dynamic range, it also reduces the range of
input signals that can be handled because a larger part of the
gain range is used to simply extract the weak desired signal
from the stronger blocker.
and quadrature (Q) sinusoidal carriers. Both the baseband and
modulated signals appear quite complex in the time domain with
dramatic peaks and valleys. In a typical receiver, the goal is to
recover the pair of quadrature baseband signals in the presence
of noise and interfering signals after quadrature demodulation.
In the process of filtering out-of-band noise and unwanted inter-
ferers and restoring the levels of the wanted I and Q baseband
signals, it is critical to retain their gain and phase integrity over
the bandwidth.
The ADRF6510 delivers flat in-band gain and group delay,
consistent with a six-pole Butterworth prototype filter as
described in the Programmable Filters section. Furthermore,
careful design ensures excellent matching of these parameters
between the I and Q channels. Although absolute gain flatness
and group delay can be corrected with digital equalization,
mismatch introduces quadrature errors and intersymbol inter-
ference that degrade bit error rates in digital communication
systems.
KEY PARAMETERS FOR QUADRATURE-BASED
RECEIVERS
The majority of digital communication receivers makes use of
quadrature signaling, in which bits of information are encoded
onto pairs of baseband signals that then modulate in-phase (I)
Rev. 0 | Page 18 of 28
ADRF6510
APPLICATIONS INFORMATION
BASIC CONNECTIONS
ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE
Figure 48 shows the basic connections for operating the
ADRF6510. A voltage from 4.75 V to 5.25 V should be applied
to the supply pins. Each supply pin should be decoupled with at
least one low inductance, surface-mount ceramic capacitor of
0.1 μF placed as close as possible to the device.
Error vector magnitude (EVM) is a measure used to quantify
the performance of a digital radio transmitter or receiver. A
signal received by a receiver has all constellation points at their
ideal locations; however, various imperfections in the implemen-
tation (such as magnitude imbalance, noise floor, and phase
imbalance) cause the actual constellation points to deviate from
their ideal locations.
The input buffers provide an interface to the sensitive filter
sections that follow. They set a differential input impedance
of 400 ꢀ and sit at a nominal common-mode voltage of VPS/2.
The inputs can be dc-coupled or ac-coupled. If using direct
dc-coupling, the common-mode voltage, VCM, can range from
1.5 V to 3 V.
In general, a receiver exhibits three distinct EVM limitations
vs. received input signal power.
•
At strong signal levels, the distortion components falling
in-band due to nonlinearities in the device components
cause strong degradation to EVM as signal levels increase.
At medium signal levels, where the signal chain behaves
in a linear manner and the signal is well above any notable
noise contributions, EVM has a tendency to reach an
optimum level determined dominantly by the quadrature
accuracy and the precision of the test equipment. As signal
levels decrease such that noise is a major contribution, the
EVM performance vs. the signal level exhibits a decibel-
for-decibel degradation with decreasing signal level.
At lower signal levels, where noise proves to be the domi-
nant limitation, the decibel EVM proves to be directly
proportional to the SNR.
The output buffers of the ADRF6510 are low impedance
(~20 ꢀ) designed to drive either ADC inputs or subsequent
amplifier stages. The output common-mode voltage defaults to
VPS/2 but can be adjusted from 1.5 V to 3.0 V without loss of
drive capability by presenting the VOCM pin with the desired
common-mode voltage. The high input impedance of VOCM
allows the ADC reference output to be connected directly.
•
To enable the ADRF6510, the ENBL pin must be pulled high.
Taking ENBL low disables the device, reducing current con-
sumption to approximately 2 mA at ambient temperature.
•
INPUT1(–)
0.1µF
VPS
VPS
INPUT1(+)
VPS
VPS
0.1µF
OUTPUT1(+)
ENBL INM1
INP1
VPSD
COMD
LE
COM OFS1
VPS
VPS
GNSW
VPSD
0.1µF
OPP1
OPM1
COM
OUTPUT1(–)
OUTPUT2(–)
GAIN
VOCM
COM
CLK
DATA
SDO
COM
VPS
ADRF6510
0.1µF
0.1µF
OPM2
0.1µF
VPS
OPP2
VP
S
VPS
OFDS
INP2
INM2
COM
COM
OFS2
VPS
0.1µF
R2
INPUT2(+)
INPUT2(–)
OUTPUT2(+)
VPS
0.1µF
VPS
Figure 48. Basic Connections
Rev. 0 | Page 19 of 28
ADRF6510
An overall RF-to-baseband EVM performance was obtained
with the ADL5387 IQ demodulator preceding the ADRF6510.
An 840 MHz RF signal with a modulation setting of 64 QAM
and a 7 MHz symbol rate was used. The local oscillator (LO) is
set at 1680 MHz to obtain 840 MHz at the quadrature core after
the divide-by-2 stage. The analog gain of the ADRF6510 was
adjusted to maintain 1.5 V p-p into a 1 kꢀ load impedance.
Figure 49 shows EVM vs. input power and the corresponding
analog gain voltage.
Figure 50 shows the image rejection of the ADL5387 and the
ADRF6510 for various baseband frequencies. The modulation
is 64 QAM with a 7 MHz symbol rate. Note the following:
•
To the right of the 5 MHz center frequency, the filter is
programmed to be 5 MHz greater than the centered base-
band frequency. This ensures that the signal edge is well
within the pass band of the filter. In such cases, where the
filter bandwidth is set to be greater than the signal bandwidth,
the image rejection of the ADL5387 tends to be the limiting
factor, and the ADRF6510 has minimal effects.
32
30
28
26
24
22
20
2.5
2.0
1.5
1.0
0.5
0
•
To the left of 5 MHz—specifically at a center frequency
of 3.5 MHz—the filter corner is lowered to the baseband
signal edge, degrading the image rejection. When the
centered baseband frequency is 3.5 MHz and the filter is
set at 7 MHz (instead of a safer 8 MHz), the filter corner
conflicts with the edge of the modulated signal. Channel
mismatch in group delay characteristics and variation in
absolute group delay (from the normal flat response) tend
to degrade image rejection.
45
AT CENTER FREQUENCY = 3.5MHz,
FILTER CORNER IS SET TO 7MHz
40
–65
–5
–55
–45
–35
–25
–15
RF INPUT POWER (dBm)
35
30
Figure 49. EVM vs. RF Input Power Level
LOW IF IMAGE REJECTION
25
AT CENTER FREQUENCIES GREATER
THAN 5MHz, FILTER CORNER IS
The image rejection ratio is the ratio of the intermediate frequency
(IF) signal level produced by the desired input frequency to that
produced by the image frequency. The image rejection ratio is
expressed in decibels (dB). Appropriate image rejection is critical
because the image power can be much higher than that of the
desired signal, thereby plaguing the downconversion process.
20
15
10
SET TO 5MHz HIGHER THAN SIGNAL EDGE
5
0
3
5
7
9
11
13
15
Figure 51 illustrates the image problem. If the upper sideband is
the desired band, a 90° shift to the Q channel cancels the image
at the lower sideband. In the same way, if the lower sideband is
the desired band, a 90° shift to the I channel cancels the image
at the upper sideband. Phase and gain balance between the I
and Q channels are critical for high levels of image rejection.
BASEBAND FREQUENCY (MHz)
Figure 50. Image Rejection of the ADL5387 and ADRF6510
COSω
LO
t
0°
ω
ωIF
IF
0
0
+ω
+ω
IF
0
–90°
+90°
–ω
–ω
+ω
+ω
IF
IF
ω
ωLO
0°
ωUSB
LSB
IF
0
IF
IF
SINω
LO
t
Figure 51. Illustration of the Image Problem
Rev. 0 | Page 20 of 28
ADRF6510
ETC1-1-13
RFC
VPS
1000pF
1000pF
120nH
120nH
VPS
V
POS
VPS
VPS
0.1µF
24 23 22 21 20 19
1VPA
V
POS
ENBLINM1 COM OFS1
INP1 VPS GNSWVPS
VPB18
0.1µF
100pF
100pF
VPSD
0.1µF
VPSD
COMD
LE
OPP1
2COM
3BIAS
4VPL
5VPL
6VPL
VPB17
QHI 16
QLO 15
IHI 14
0.1µF
100pF
OPM1
COM
ADL5387
GAIN
VOCM
COM
CLK
ADRF6510
0.1µF
DATA
SDO
COM
VPS
V
POS
0.1µF
0.1µF
ILO 13
OPM2
OPP2
0.1µF
VPS
INP2 VPS OFDS VPS
INM2
7
8
9
10 11 12
COM
COM OFS2
VPS
R2
1000pF
LO
0.1µF
1000pF
VPS
0.1µF
VPS
Figure 52. ADL5387 and ADRF6510 Interfacing Example—Block Diagram
As an example, a second-order Butterworth, low-pass filter design
is shown in Figure 53 where the differential load impedance is
500 ꢀ and the source impedance is 50 ꢀ. The normalized series
inductor value for the 10-to-1, load-to-source impedance ratio
is 0.074 H, and the normalized shunt capacitor is 14.814 F. For a
10.9 MHz cutoff frequency, the single-ended equivalent circuit
consists of a 0.54 μH series inductor followed by a 433 pF shunt
capacitor.
EXAMPLE BASEBAND INTERFACE
The noise spectral density of the ADRF6510 outside the filter
bandwidth is limited by the fixed VGA output noise. It may be
necessary to use an external, fixed-frequency, passive filter prior
to an analog-to-digital conversion to prevent noise aliasing from
degrading the signal-to-noise ratio. As shown in Figure 46 and
Figure 47, the noise density at higher frequencies tends to be flat,
and any higher IF noise aliasing into the Nyquist zone has minimal
effects. Using the AD9639, a 12-bit ADC with a 210 MSPS sam-
pling rate, the effects of an antialiasing filter present between the
ADRF6510 and the ADC showed a minimal 1.5 dB improvement.
The balanced configuration is realized as the 0.54 μH inductor
is split in half to achieve the network that is shown in Figure 53.
R
= 50Ω
L
= 0.074H
S
N
NORMALIZED
SINGLE-ENDED
CONFIGURATION
When designing an antialiasing filter, it is necessary to consider
the overall source and load impedance presented by the
ADRF6510 and the ADC input to design the filter network. The
differential baseband output impedance of the ADRF6510 is
20 ꢀ and is designed to drive a high impedance ADC input. It
may be desirable to terminate the ADC input to a lower
impedance by using a terminating resistor, such as 500 ꢀ. The
terminating resistor helps to better define the input impedance
at the ADC input at the cost of a slightly reduced gain.
V
C
14.814F
R = 500Ω
L
S
N
R
R
S
L
fC = 1Hz
= 0.1Ω
0.54µH
R
= 50Ω
S
DENORMALIZED
SINGLE-ENDED
EQUIVALENT
V
V
433pF
433pF
R = 500Ω
L
S
fC = 10.9MHz
R
S
= 25Ω
= 25Ω
0.27µH
2
The order and type of filter network depend on the desired high
frequency rejection required, the pass-band ripple, and the
group delay. Filter design tables provide outlines for various
filter types and orders, illustrating the normalized inductor and
capacitor values for a 1 Hz cutoff frequency and 1 ꢀ load. After
scaling the normalized prototype element values by the actual
desired cutoff frequency and load impedance, the series
reactance elements are halved to realize the final balanced filter
network component values.
R
2
L
L
= 250Ω
= 250Ω
BALANCED
CONFIGURATION
S
R
2
R
0.27µH
S
2
Figure 53. Second-Order Butterworth, Low-Pass Filter Design Example
Rev. 0 | Page 21 of 28
ADRF6510
10
5
A complete design example is shown in Figure 54. A third-order
Chebyshev differential filter with a 31 MHz corner frequency
interfaces the output of the ADRF6510 to that of an ADC input.
The 20 ꢀ source impedance reflects the impedance of the
output buffer stage. The 500 ꢀ load resistor defines the input
impedance of the ADC. The filter adheres to a 0.1 dB in-band
flatness and offers sufficient out-of-band rejection to act as an
antialiasing filter.
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
1.8µH
1µH
–50
0
20
40
60
80
100 120 140 160 180 200
BASEBAND FREQUENCY (MHz)
1.8µH
1µH
Figure 55. Third-Order Baseband Filter Response
Figure 54. Third-Order Chebyshev Differential Filter Design Example
20
18
Figure 55 and Figure 56 show the measured frequency response
and group delay of the third-order Chebyshev differential filter.
16
14
12
10
8
6
4
2
0
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
BASEBAND FREQUENCY (MHz)
Figure 56. Third-Order Baseband Filter Group Delay Response
Rev. 0 | Page 22 of 28
ADRF6510
EVALUATION BOARD
The ADRF6510 evaluation board is available with software
control to program the filter bandwidth. It is a 4-layer board
with split ground plane for analog and digital sections. Special
care is taken to place the power decoupling capacitors close to
the device pins. The board is designed for easy single-ended
(through a Mini-Circuits ADT8-1T+ 8:1 balun) or differential
configuration for each channel.
EVALUATION BOARD CONTROL SOFTWARE
The ADRF6510 evaluation board is configured with a USB-
friendly interface to program the filter bandwidth of the
ADRF6510. The software GUI (see Figure 57) allows users to
select a particular frequency to write to the device and also
to read back data from the SDO pin that shows the currently
programmed filter setting. The software setup files can be down-
loaded from the ADRF6510 product page at www.analog.com.
Figure 57. Evaluation Control Software
SCHEMATICS AND ARTWORK
VPS
P3
INM1_SE_P
R4
R17
R45
R47
R31
T1
R55
R56
C12
VPS
C9
R57
R58
C6
R48
C10
C14
OPP1_SE_P
R24 R37
INP1
VPS
P2
VPS
C19
R18
R43
R41
T3
R19
C16
R12
R11
R29
C27
R30
ENBL INM1
INP1
VPSD
COM OFS1
VPS VPS
R7
R8
LE
GNSW
OPP1
OPM1
COM
VPSD
C23
R20
C4
COMD
LE
OPM1
C28
C20
R5
R21
R39
GAIN
VOCM
COM
CLK
CLK
DATA
SDO
COM
VPS
ADRF6510
R6
R33
0.1µF
DATA
C18
R23
C17
R9
R38
0.1µF
C21
OPM2
OPP2
VPS
OFS2
R34
R42
C5
VPS
R35
SDO
R14
R13
VPS
OFDS
COM
INP2
R1
INM2
COM
R10
OPM2_SE_P
OPP2
C22
T4
INP2_SE_P
R2
VPS
C15
C24
R36
R46 R15
R49
R32
C13
R53 C7
R51
R52
R22 R40
VPSD
VPS
T2
R3
L2
C3
R50
R54
VPS
C8
VPS
P4
INM2
C11
C1
C2
R16
R44
L1
Figure 58. Evaluation Board Schematic
Rev. 0 | Page 23 of 28
ADRF6510
XC11
3.3V
10PF
XC6
3.3V
22PF
DGND
XC13
0.1UF
XC14
0.1UF
XC15
0.1UF
XC16
0.1UF
XC17
0.1UF
XC18
0.1UF
XC19
0.1UF
3.3V
3.3V
XU2
8
DGND
1
VCC
XR1
2K
XR2
A0
A1
A2
2
3
6
7
2K
5
SCLSDA
WC_N
GND
4
24LC64-I-SN
XY1
DGND
XU3
ADP3303ARZ-3.3
XC5
1
4
3
XC10
3
NR
3.3V
XC1
XC2
2
7
8
1
2
XC9
0.1UF
IN
OUT
10PF
XC7
22PF
22PF
IN1 OUT1
24MHZ
XC12
6
3.3V
10PF
XC8
ERR_N
DGND
XR3
1K
SD* GND
5
DGND
0.1UF
DGND
4
XU1
0.1UF
DGND
0.1UF
DGND
33
SDO
+5V
PA0/INT0*
DGND
34
DATA
CLK
LE
3.3V
PA1/INT1*
3.3V
XD1
35
PA2/SLOE
LNJ308G8TRA(GREEN)
XJ1
36
PA3/WU2
XU1
37
PA4/FIFOADR0
AVCC
5
4
8
9
VCC
USB_POWER
XTALIN
38
1
2
3
4
5
PA5/FIFOADR1
XR4
XR5
15
16
42
44
DGND
39
SCL
XTALOUT
DPLUS
PA6/PKTEND
100K
100K
40
SDA
PA7/FLAGD/SLCS*
18
RESET*
DMINUS
PB0/FD0
54
13
CLKOUT/PE1/T1OUT
19
WAKEUP
PB1/FD1
1
20
RDY0/SLRD
IFCLK/T0OUT
CTL0/FLAGA
CTL1/FLAGB
PB2/FD2
XC3
XC4
2
29
30
31
21
RDY1/SLWR
RESERVED
6
7
8
9
PB3/TXD1/FD3
0.1UF
0.1UF
14
22
SHIELD
PINS
PB4/FD4
23
CTL2/FLAGC
GND
DGND
DGND
PB5/FD5
PAD AGND
24
PB6/FD6
CY7C68013A-56LFXC
25
PB7/FD7
UX60A-MB-5ST240-0003-4
DGND
45
PD0/FD8
46
PD1/FD9
47
PD2/FD10
DGND
48
PD3/FD11
49
PD4/FD12
50
PD5/FD13
51
PD6/FD14
USB_POWER
52
PD7/FD15
CY7C68013A-56LFXC
XR6
0
+5V
Figure 59. Schematic for the USB Section of the Evaluation Board
Figure 60. Top Layer Silkscreen
Figure 61. Component Side Layout
Rev. 0 | Page 24 of 28
ADRF6510
EVALUATION BOARD CONFIGURATION OPTIONS
Table 5 lists the components of the main section of the ADRF6510 evaluation board.
Table 5.
Components
Function
Default Conditions
C1, C2, C4, C5, C11, C12,
C15, C16, L1, L2, R2
Power supply and ground decoupling. Nominal supply decoupling
consists of a 0.1 μF capacitor to ground.
C1, C2 = 10 μF (Size 0603)
C4, C5, C11, C12, C15, C16 = 0.1 μF
(Size 0603)
L1, L2 = 33 μH (Size 0805)
R2 = 1 kΩ (Size 0402)
T1, T2, C3, C6, C7 to C10, Input interface. Input SMAs INM1_SE_P and INP2_SE_P are used to drive
T1, T2 = ADT8-1T+ (Mini-Circuits)
C3, C6 = 0.1 μF (Size 0402)
C7 to C10 = 100 nF (Size 0402)
R15 to R18, R43 to R46, R51, R52,
R55, R56 = open (Size 0402)
R31, R32, R47 to R50, R53, R54, R57,
R58 = 0 Ω (Size 0402)
R15 to R18, R31, R32,
R43 to R58
the baluns in a single-ended fashion. The default configuration of the
evaluation board is for single-ended operation.
T1 and T2 are 8:1 impedance ratio baluns to transform a 50 Ω, single-ended
input into a 400 Ω balanced differential signal. R31, R32, and R47 to R50
are populated for appropriate balun interface. R51 to R58 are provided
for generic placement of matching components. C3 and C6 are balun
decoupling capacitors.
R15 to R18 and R43 to R46 can be populated with 0 Ω, and the balun
interfacing resistors can be removed to bypass T1 and T2 for differential
interfacing. C7 to C10 can be used for ac coupling with differential
interfacing.
T3, T4, C19 to C24,
R7 to R14, R19 to R24,
R35 to R42
Output interface. Output SMAs OPP1_SE_P and OPM2_SE_P are used to
drive the baluns in a single-ended fashion. The default configuration of
the evaluation board is for single-ended operation.
T3, T4 = ADT8-1T+ (Mini-Circuits)
C19 to C22 = 100 nF (Size 0402)
C23, C24 = 0.1 μF (Size 0402)
R7 to R10 = 300 Ω (Size 0402)
R11 to R14 = open
R19, R20, R35, R36, R41, R42 = 0 Ω
(Size 0402)
R21 to R24, R37 to R40 = open
(Size 0402)
T3 and T4 are 8:1 impedance ratio baluns to transform a 50 Ω, single-ended
output into a 400 Ω balanced differential load. R19, R20, R35, R36, R41, and
R42 are populated for appropriate balun interface. R7 to R14 are provided
for generic placement of matching components. R7 to R10 are set to 300 Ω
to present a 1 kΩ load (with the balun used) at the DUT output.
C19 to C22 are used for ac coupling when differential outputs are used.
C23 and C24 are balun decoupling capacitors. R21 to R24 and R37 to R40
can be populated with 0 Ω, and the balun interfacing resistors can be
removed to bypass T3 and T4 for differential interfacing.
P2
Enable interface. The ADRF6510 is powered up by applying a logic high
voltage to the ENBL pin (Jumper P2 is connected to VPS).
P2 = installed for enable
C27, C28, R1, R29, R30,
R33, R34
Serial interface control. The digital interface sets the corner frequency of
the device using the serial interface via the LE, CLK, DATA, and SDO pins.
R1 = 10 kΩ (Size 0402)
C27, C28 = 330 pF (Size 0402)
R29, R30 = 100 Ω (Size 0402)
R33, R34 = 0 Ω (Size 0402)
P4 = installed
C13, C14 = 1000 pF (Size 0402)
R3 = 10 kΩ (Size 0402)
P4, C13, C14, R3
C18, R6
DC offset correction loop compensation. The dc offset correction loop is
enabled (low) with Jumper P4. When enabled, the capacitors are connected
to circuit common. The high-pass corner frequency is expressed as follows:
f
HP (Hz) = 1.2 × ((Linear Gain)/COFS (μF)).
Output common-mode setpoint. The output common-mode voltage can C18 = 0.1 μF (Size 0402)
be set externally when applied to the VOCM pin. If the VOCM pin is left
open, the output common-mode voltage defaults to VPS/2.
R6 = 0 Ω (Size 0402)
C17, R5
P3, R4
Analog gain control. 0 V to 2 V, 30 mV/dB gain scaling.
C17 = 0.1 μF (Size 0402)
R5 = 0 Ω (Size 0402)
Front-end 6 dB or 12 dB gain switch. Pull low for 6 dB; pull high for 12 dB. P3 = installed
R4 = 10 kΩ (Size 0402)
Rev. 0 | Page 25 of 28
ADRF6510
USB Section Configuration Options
Table 6 lists the components of the USB section of the ADRF6510 evaluation board.
Table 6.
Components
Default Conditions
XC1, XC2, XC6
22 pF (Size 0603)
XC3 to XC5, XC7, XC8, XC12 to XC19
0.1 μF (Size 0402)
XC9 to XC11
XD1
XJ1
XR1, XR2
XR3
10 pF (Size 0402)
Green LED ( Panasonic LNJ308G8TRA)
USB SMT connector (Hirose Electric UX60A-MB-5ST 240-0003-4)
2 kΩ (Size 0603)
1 kΩ (Size 0603)
XR4, XR5
XR6
100 kΩ (Size 0603)
0 Ω (Size 0603)
XU1
XU2
XU3
XY1
USB microcontroller (Cypress CY7C68013A-56LFXC)
64 kb EEPROM (Microchip 24LC64-I/SN)
Low dropout regulator (Analog Devices ADP3303ARZ-3.3)
24 MHz crystal oscillator (AEL Crystals X24M000000S244)
Rev. 0 | Page 26 of 28
ADRF6510
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
0.80 MAX
0.65 TYP
3.50 REF
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 62. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF6510ACPZ-R7
ADRF6510ACPZ-WP
ADRF6510-EVALZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-32-2
CP-32-2
32-Lead LFCSP_VQ, 7”Tape and Reel
32-Lead LFCSP_VQ, Waffle Pack
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
ADRF6510
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09002-0-4/10(0)
Rev. 0 | Page 28 of 28
相关型号：
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