ADRF6520ACPZ-R7 [ADI]
Dual Programmable Filters and VGAs for 2 GHz Channel Spacing for µW Radios;
| 型号： | ADRF6520ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | Dual Programmable Filters and VGAs for 2 GHz Channel Spacing for µW Radios 信息通信管理 |
| 文件： | 总29页 (文件大小：1532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Programmable Filters and VGAs for
2 GHz Channel Spacing for µW Radios
Data Sheet
ADRF6520
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Matched VGAs and programmable filters
Maximum gain: 53 dB
Continuous gain control range: 60 dB
Filter bypass mode I/Q bandwidth
1 dB gain flatness: >1250 MHz
4-pole Butterworth filter I/Q bandwidth: 36 MHz to 720 MHz
RMS detector
IMD3: <−55 dBc for 1.5 V p-p composite output
HD2, HD3: <−55 dBc for 1.5 V p-p output
Noise figure: 10.5 dB at maximum gain
NF < 11 dB over 12 dB of VGA2 gain backoff
100 Ω differential input, low impedance output
Optional dc output offset correction
SPI-programmable filter corners
INP1
INM1
COM
1
2
3
24 OPP1
23 OPM1
22 COM
21 VGN1
20 VGN2
19 COM
18 OPM2
17 OPP2
ADRF6520
CFLT1 4
CFLT2 5
DETECTOR
COM
INM2
INP2
6
7
8
Single 3.3 V supply operation with power-down feature
APPLICATIONS
Figure 1
Point-to-point and point-to-multipoint radios
Baseband IQ receivers
Diversity receivers
ADC drivers
Instrumentation
Medical
GENERAL DESCRIPTION
The ADRF6520 is a matched pair of fully differential low noise and
low distortion programmable filters and variable gain amplifiers
(VGAs). Each channel is capable of rejecting large, out of band
interferers while reliably boosting the wanted signal, thus reducing
the bandwidth and resolution requirements on the analog-to-
digital converters (ADCs). The excellent matching between
channels and their high spurious-free dynamic range over all
gain and bandwidth settings make the ADRF6520 ideal for
quadrature-based (IQ) communication systems with dense
constellations, multiple carriers, and nearby interferers. The
filter corners, enable, and dc offset correction loop enable are
all programmable via a serial peripheral interface (SPI).
up to 1.25 GHz. A wideband rms detector is available to
monitor the signal at the filter inputs. A fixed gain amplifier of
6 dB immediately follows the filter. The postfilter VGA provides
30 dB of continuous gain control with a maximum gain of
12 dB. The output buffers offer an additional 18 dB of gain and
provide a differential output impedance of 20 Ω. The output
buffers are capable of driving 1.5 V p-p into 100 Ω loads at better
than 55 dBc nominal for the third-order intermodulation
distortion (IMD3). Independent, built in, dc offset correction
loops for each channel can be disabled via the SPI if fully dc-
coupled operation is desired. The high-pass corner frequency is
determined by external capacitors on the CHP1 and CHP2 pins
and the postfilter VGA gain.
The first VGA that precedes the filters offers 30 dB of continuous
gain control with a maximum gain of 18 dB and sets a differential
input impedance of 100 Ω. The filters provide a four-pole
Butterworth response with −1 dB corner frequencies: 36 MHz,
72 MHz, 144 MHz, 288 MHz, 432 MHz, 576 MHz, and 720 MHz.
For operation beyond 720 MHz, the filter can be disabled and
completely bypassed, thereby extending the −1 dB bandwidth
The ADRF6520 operates from a 3.15 V to 3.45 V supply and
consumes a maximum supply current of 425 mA. When fully
disabled, it consumes ≤10 mA. The ADRF6520 is fabricated in
an advanced silicon-germanium BiCMOS process and is
available in a 32-lead, exposed pad LFCSP. Performance is
specified over the −40°C to +85°C temperature range.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
ADRF6520
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Distortion Characteristics......................................................... 22
Maximizing the Dynamic Range ............................................. 22
Key Parameters for Quadrature-Based Receivers.................. 23
SPI Register and Timing................................................................ 24
Register Read/Write Timing..................................................... 25
Applications Information .............................................................. 26
Basic Connections...................................................................... 26
Supply Decoupling ..................................................................... 26
Input Signal Path ........................................................................ 26
Output Signal Path..................................................................... 26
DC Offset Compensation Loop Enabled ................................ 26
Serial Port Connections............................................................. 26
Enable/Disable Function........................................................... 27
Gain Pin Decoupling ................................................................. 27
RMS Detector Connections...................................................... 27
VGA2 Gain step response ......................................................... 27
Linear Operation of the ADRF6520 ........................................ 27
Evaluation Board ............................................................................ 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 19
Input VGAs ................................................................................. 19
RMS Detector.............................................................................. 19
Programmable Filters................................................................. 20
Variable Gain Amplifiers........................................................... 20
Output Buffers/ADC Drivers ................................................... 20
DC Offset Compensation Loop................................................ 21
Programming the ADRF6520................................................... 21
Noise Characteristics ................................................................. 21
REVISION HISTORY
4/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 29
Data Sheet
ADRF6520
SPECIFICATIONS
VPS, VPSD = 3.3 V, TA = 25°C, ZLOAD = 100 Ω.
Table 1.
Parameter
Test Conditions/Comments
Min Typ
Max Unit
FREQUENCY RESPONSE, FILTER BYPASS MODE
1 dB Gain Flatness Bandwidth
FREQUENCY RESPONSE
Low-Pass Corner Frequency, fC
Corner Frequencies
I or Q channel
1.25
GHz
Four-pole Butterworth filter, −1 dB bandwidth
36
72
MHz
MHz
MHz
MHz
MHz
MHz
MHz
% fC
144
288
432
576
720
8
Corner Frequency Absolute Accuracy
Corner Frequency Matching
Over operating temperature range
Channel A and Channel B at same gain and bandwidth
settings
0.5
% fC
Pass-Band Flatness
Corner Frequency = 72 MHz
Bypass Mode
Defined as difference between value at 100 kHz and fC
0.2
1.5
0.1
dB
dB
dB
Gain Matching
Channel A and Channel B at same gain and bandwidth
settings; 1 kHz to fC
Group Delay Variation
Corner Frequency = 36 MHz
Corner Frequency = 144 MHz
Corner Frequency = 720 MHz
Bypass Mode
From midband to peak
4
ns
ns
ns
ns
0.8
0.25
0.15
Group Delay Matching
Corner Frequency = 36 MHz
Corner Frequency = 144 MHz
Corner Frequency = 720 MHz
Bypass Mode
At fC/2; Channel A and Channel B at same gain
60
50
15
10
ps
ps
ps
ps
Stop-Band Rejection
Gain = 53 dB
Relative to Pass Band
2 × fC
5 × fC
10 × fC
−20
−50
−80
dB
dB
dB
INPUT STAGE
INP1, INM1, INP2, INM2
At minimum gain, VGN1 = 0 V
Maximum Input Swing
Differential Input Impedance
Input Common Mode
RMS DETECTOR
4.0
100
1.375
V p-p
Ω
V
AC coupling recommended
VRMS, CFLT1, CFLT2
Output Scaling
Relative to the summation of the differential voltage at
filter input of both channels
1
V/V rms
Output Current
Output Load
Source available
To reach full scale
3
mA
kΩ
1
GAIN CONTROL
Gain Range
VGN1, VGN2
Maximum gain
Minimum gain
53
−7
dB
Attenuation Range
Each attenuator; VGN1 or VGN2 = 1.5 V
Each attenuator; VGN1 or VGN2 = 0 V
−30
0
dB
dB
mV/dB
dB
30
30
0.2
Gain Slope
Gain Error
VGAIN from 500 mV to 1000 mV
Rev. 0 | Page 3 of 29
ADRF6520
Data Sheet
Parameter
Test Conditions/Comments
OPP1, OPM1, OPP2, OPM2
At maximum gain, RLOAD = 100 Ω
HD2 > 55 dBc, HD3 > 55 dBc, RLOAD = 100 Ω
Gain = 53 dB
Min Typ
Max Unit
OUTPUT STAGE
Maximum Output Swing
3.5
12
4.5
1.5
14
V p-p
V p-p
dBm
Output 1 dB Compression Point (OP1dB)
re:100 Ω
Differential Output Impedance
Output DC Offset
Output Common-Mode
NOISE/DISTORTION
<20
<20
1.65
Ω
mV
V
Inputs shorted, dc offset correction loop enabled
AC coupling recommended
Corner Frequency = 36 MHz
Output Noise Density
At fC/2, VGA1 gain = 18 dB, VGA2 gain = 0 dB
At fC/2, VGA1 gain = 18 dB, VGA2 gain = 30 dB
Gain = 53 dB
−137.25
−119.5
11
dBV/Hz
dBV/Hz
dB
Noise Figure
Second Harmonic, HD2
10 MHz fundamental, 1.5 V p-p output level
VGA1 gain = 6 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 24 dB
10 MHz fundamental, 1.5 V p-p output level
VGA1 gain = 6 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 24 dB
18 MHz and 19 MHz tones, 1.5V p-p composite output
Gain = 0 dB
−71.7
−71.7
−72.9
dBc
dBc
dBc
Third Harmonic, HD3
IMD3
−74.3
−74.7
−81.2
dBc
dBc
dBc
−70
−71.2
−85
dBc
dBc
dBc
Gain = 24 dB
Gain = 48 dB
Corner Frequency = 720 MHz
Output Noise Density
At fC/2, VGA1 gain = 18 dB, VGA2 gain = 0 dB
At fC/2, VGA1 gain = 18 dB, VGA2 gain = 30 dB
Gain = 53 dB
−137
−119.9
11
dBV/Hz
dBV/Hz
dB
Noise Figure
Second Harmonic, HD2
100 MHz fundamental, 1.5 V p-p output level
VGA1 gain = 6 dB, VGA2 = 0 dB
−72
−75.6
−80.6
dBc
dBc
dBc
VGA1 gain = 18 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 24 dB
100 MHz fundamental, 1.5 V p-p output level
VGA1 gain = 6 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 24 dB
Third Harmonic, HD3
IMD3
−71.3
−71.6
−79.8
dBc
dBc
dBc
356.5 MHz and 363.5 MHz tones, 1.5 V p-p composite
output
VGA1 gain = −6 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 24 dB
−65
−66.5
−81.1
dBc
dBc
dBc
Bypass Mode
Output Noise Density
At 500 MHz, VGA1 gain = 18 dB, VGA2 gain = 0 dB
At 500 MHz, VGA1 gain = 18 dB, VGA2 gain = 30 dB
Gain = 53 dB
−136.8
−119.8
10.5
dBV/Hz
dBV/Hz
dB
Noise Figure
Second Harmonic, HD2
330 MHz fundamental, 1.5 V p-p output level
VGA1 gain = −6 dB, VGA2 = 0 dB
−64.5
−65
−78.4
dBc
dBc
VGA1 gain = 18 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 24 dB
Rev. 0 | Page 4 of 29
Data Sheet
ADRF6520
Parameter
Test Conditions/Comments
Min Typ
−60.5
Max Unit
Third Harmonic, HD3
330 MHz fundamental, 1.5 V p-p output level
VGA1 gain = −6 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 24 dB
dBc
−62.5
−70.4
dBc
IMD3
496.5 MHz and 503.5 MHz tones, 1.5 V p-p composite
output
VGA1 gain = −6 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 0 dB
VGA1 gain = 18 dB, VGA2 = 24 dB
LE, CLK, DATA, SDO
−68.8
−70
−77
dBc
dBc
dBc
DIGITAL LOGIC
Input High Voltage, VHIGH
Input Low Voltage, VLOW
Input Current, IHIGH/ILOW
Input Capacitance, CIN
>2
<0.8
<1
2
V
V
µA
pF
SPI TIMING
fCLK
LE, CLK, DATA, SDO
1/tCLK
20
5
5
MHz
ns
ns
tDH
tDS
tLH
DATA hold time
DATA setup time
LE hold time
5
ns
tLS
LE setup time
5
ns
tPW
tD
CLK high pulse width
CLK to SDO delay
VPS, VPSD, COM, COMD, ENBL
5
5
ns
ns
POWER AND ENABLE
Supply Voltage Range
Total Supply Current
3.15 3.3
3.45
V
ENBL = 3.3 V
Maximum bandwidth setting
Filter bypassed
ENBL = 0 V
425
390
10
1.6
20
mA
mA
mA
V
µs
ns
Disable Current
Disable Threshold
Enable Response Time
Disable Response Time
Delay following ENBL low to high transition
Delay following ENBL high to low transition
300
Rev. 0 | Page 5 of 29
ADRF6520
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Supply Voltages, VPS, VPSD
ENBL, LE, CLK, DATA, SDIO
INP1, INM1, INP2, INM2,
OPP1, OPM1, OPP2, OPM2
OFS1, OFS2, VRMS
3.6 V
VPSD + 0.5 V
VPS + 0.5 V
VPS + 0.5 V
VPS + 0.5 V
VPS + 0.5 V
1.53 W
Table 3. Thermal Resistance
1
2
Package Type
θJA
θJC
2.0
Unit
CP-32-12
29.4
°C/W
VGN1, VGN2
Internal Power Dissipation
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
1 Based on simulation with JEDEC standard JESD51, using a 2S2P board.
2 Based on simulation with JEDEC standard JESD51, using a 1S0P board.
125°C
−40°C to +85°C
−65°C to +150°C
300°C
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 6 of 29
Data Sheet
ADRF6520
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INP1
INM1
COM
CFLT1 4
CFLT2 5
COM
INM2
INP2
1
2
3
24 OPP1
23 OPM1
22 COM
21 VGN1
20 VGN2
19 COM
18 OPM2
17 OPP2
ADRF6520
TOP VIEW
(Not to Scale)
6
7
8
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED
PAD TO A LOW IMPEDANCE GROUND PAD.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
INP1, INM1
COM
Description
Channel 1 Differential Inputs, 100 Ω Differential Input Impedance.
Analog Common. Connect COM to an external circuit common using the lowest possible impedance.
1, 2
3, 6, 19, 22
4, 5
CFLT1, CFLT2 Averaging Capacitors for RMS Detectors. The user can leave these pins open for the fastest response time
and the least amount of rms averaging.
7, 8
9
INM2, INP2
RST
Channel 2 Differential Inputs, 100 Ω Differential Input Impedance.
SPI Reset to Default Bit Values. This pin is active low. Pull the pin high under nonactive conditions. The
transistor-transistor logic (TTL) levels are VLOW < 0.8 V and VHIGH > 2 V.
10
11
SCLK
SDIO
SPI Port Clock. The TTL levels are VLOW < 0.8 V and VHIGH > 2 V.
SPI Data Input and Output. The TTL levels are VLOW < 0.8 V and VHIGH > 2 V.
Analog Positive Supply Voltage: 3.15 V to 3.45 V.
12, 13, 28, 29 VPS
15, 26
16
CHP2, CHP1
VRMS
DC Offset Correction Loop Capacitors. Connect the capacitors to a circuit common.
RMS Detector Output. The output transfer function is 1 V/V rms × (CH1_RMS + CH2_RMS), where CH1_RMS
is the differential rms voltage of the input of the Channel 1 filter, and CH2_RMS is the differential rms
voltage of the input of the Channel 2 filter. The user can leave the pin open if not using the rms detector;
there is no need to terminate this pin. Load this pin with at least 1 kΩ to ground; values lower than this
prevent the detector output from reaching its full-scale value.
17, 18
20, 21
23, 24
25
30
31
OPP2, OPM2 Channel 2 Differential Outputs. These outputs have a 20 Ω differential output impedance.
VGN2, VGN1 VGA2 and VGA1 Analog Gain Control. These pins operate from 0 V to 1.5 V with 30 mV/dB gain scaling.
OPM1, OPP1 Channel 2 Differential Outputs. These outputs have a 20 Ω differential output impedance.
ENBL
COMD
VPSD
CS
Chip Enable. Pull this pin high to enable the chip. Voltages on ENBL of less than 1.6 V disable the device.
Digital Common. Connect this pin to an external circuit common using the lowest possible impedance.
Digital Positive Supply Voltage: 3.15 V to 3.45 V.
Chip Select Bar to Enable SPI Programming. CS is an SPI programming pin and is active low. The TTL levels
are VLOW < 0.8 V and VHIGH > 2 V.
32
EP
Exposed Ground Pad. Connect the exposed pad to a low impedance ground pad.
Rev. 0 | Page 7 of 29
ADRF6520
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VPS, VPSD = 3.3 V, TA = 25°C, ZLOAD = 100 Ω, dc offset correction loop disable bit (B5) = 1 (enabled), noise spectral density (NSD) measured
at fC/2 and at 500 MHz in bypass mode, unless otherwise noted. Noise figure measured with 100 Ω differential input termination. Worst case
IMD3 tone is reported for all IMD3/IP3 plots.
25
20
15
10
5
3
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
2
1
0
–1
–2
–3
0
–5
–10
0
0.25
0.50
0.75
1.00
1.25
1.50
0
0.25
0.50
0.75
1.00
1.25
1.50
VGN1 (V)
VGN1 (V)
Figure 3. Gain at 500 MHz vs. VGN1 over Temperature; Bypass Mode,
VGN2 = 0 V
Figure 6. Gain Error at 500 MHz vs. VGN1 over Temperature; Bypass Mode,
VGN2 = 0 V
60
5
+85°C
+25°C
–40°C
+85°C
+25°C
4
–40°C
3
2
50
40
30
20
1
0
–1
–2
–3
–4
–5
0
0.25
0.50
0.75
1.00
1.25
1.50
0
0.25
0.50
0.75
1.00
1.25
1.50
VGN2 (V)
VGN2 (V)
Figure 7. Gain Error at 500 MHz vs. VGN2 over Temperature; Bypass Mode,
VGN1 = 1.5 V
Figure 4. Gain at 500 MHz vs. VGN2 over Supply; Bypass Mode,
VGN1 = 1.5 V
60
25
3.15V
3.45V
3.3V
3.15V
3.45V
3.3V
20
50
40
30
20
15
10
5
0
–5
–10
0
0.25
0.50
0.75
1.00
1.25
1.50
0
0.25
0.50
0.75
1.00
1.25
1.50
VGN1 (V)
VGN2 (V)
Figure 5. Gain at 500 MHz vs. VGN1 over Supply; Bypass Mode,
VGN2 = 0 V
Figure 8. Gain at 500 MHz vs. VGN2 over Supply; Bypass Mode,
VGN1 = 1.5 V
Rev. 0 | Page 8 of 29
Data Sheet
ADRF6520
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.25
0.50
0.75
1.00
1.25
1.50
0
0.25
0.50
0.75
1.00
1.25
1.50
VGN1 (V)
VGN2 (V)
Figure 9. Channel to Chanel Gain Mismatch vs. VGN1; VGN2 = 0 V,
Bypass Mode at 500 MHz
Figure 12. Channel to Channel Gain Mismatch vs. VGN2; VGN1 = 1.5 V,
Bypass Mode at 500 MHz
60
60
50
VPS = 3.3V
VPS = 3.15V
VPS = 3.45V
50
40
40
BYPASS
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
720MHz
576MHz
30
20
30
10
432MHz
0
20
–10
–20
–30
–40
–50
–60
288MHz
10
0
144MHz
72MHz
36MHz
–10
–20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (GHz)
FREQUENCY (MHz)
Figure 10. Gain vs. Frequency over VGN1/VGN2, 3 dB Gain Steps
Figure 13. Frequency Response over Supply and Temperature for 36 MHz,
144 MHz, 288 MHz, 432 MHz, 576 MHz, and 720 MHz Filter Corners and Bypass
55
55.0
54.5
54.0
53.5
53.0
52.5
36MHz FILTER
72MHz FILTER
144MHz FILTER
288MHz FILTER
432MHz FILTER
576MHz FILTER
720MHz FILTER
FILTER BYPASS
54
53
52
51
52.0
36MHz FILTER
51.5
51.0
50.5
50.0
72MHz FILTER
144MHz FILTER
288MHz FILTER
432MHz FILTER
576MHz FILTER
720MHz FILTER
FILTER BYPASS
1
10
100
1000
100
300
500
700
900
1100
1300
1500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. Gain vs. Frequency over all Bandwidth Settings;
VGN1 = VGN2 = 1.5 V (Logarithmic)
Figure 14. Gain vs. Frequency over all Bandwidth Settings;
VGN1 = VGN2 = 1.5 V (Linear)
Rev. 0 | Page 9 of 29
ADRF6520
Data Sheet
16
14
12
10
8
1.00
0.75
0.50
0.25
0
36MHz FILTER
144MHz FILTER
720MHz FILTER
BYPASS MODE
36MHz FILTER
144MHz FILTER
720MHz FILTER
BYPASS MODE
6
–0.25
–0.50
–0.75
–1.00
4
2
0
5
50
500
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Group Delay vs. Frequency for 36 MHz, 144 MHz,
720 MHz, and Bypass Mode
Figure 18. IQ Amplitude Mismatch vs. Frequency for 36 MHz, 144 MHz,
720 MHz, and Bypass Mode
300
100
BYPASS MODE
720MHz FILTER
36MHz FILTER
144MHz FILTER
250
200
150
100
50
50
0
–50
0
–50
–100
–150
–200
–250
–300
–100
0
125 250 375 500 625 750 875 1000 1125 1250
FREQUENCY (MHz)
3
13 23 33 43 53 63 73 83 93 103 113 123 133 143 153
FREQUENCY (MHz)
Figure 19. IQ Group Delay Mismatch vs. Frequency for 720 MHz and
Bypass Mode
Figure 16. IQ Group Delay Mismatch vs. Frequency for 36 MHz and 144 MHz
440
430
420
410
400
390
380
16
15
14
13
12
11
10
9
60
55
50
45
40
35
30
25
20
3.15V, 144MHz
3.3V, 144MHz
3.45V, 144MHz
3.15V, 720MHz
3.3V, 720MHz
3.45V, 720MHz
370
360
350
3.15V, 36MHz
3.3V, 36MHz
3.45V, 36MHz
3.15V, BYPASS
3.3V, BYPASS
3.45V, BYPASS
OP1dB
GAIN
8
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
VGN2 (V)
Figure 17. OP1dB vs. Gain at a Fundamental of 500 MHz
Figure 20. Current Consumption vs. Temperature for 36 MHz, 144 MHz,
720 MHz, and Bypass Mode
Rev. 0 | Page 10 of 29
Data Sheet
ADRF6520
45
40
35
30
25
20
15
10
5
–115
–120
–125
–130
–135
–140
FILTER BYPASS
720MHz
144MHz
36MHz
FILTER BYPASS
720MHz
144MHz
36MHz
0
0
0.25
0.50
0.75
1.00
1.25
1.50
0
0.25
0.50
0.75
1.00
1.25
1.50
VGN1 (V)
VGN1 (V)
Figure 21. Noise Figure vs. VGN1 for 36 MHz, 144 MHz, 720 MHz, and Bypass;
VGN2 = 1.5 V
Figure 24. Output NSD vs. VGN1 for 36 MHz, 144 MHz, 720 MHz, and Bypass;
VGN2 = 1.5 V
30
–115
–120
–125
–130
–135
36MHz FILTER
144MHz FILTER
720MHz FILTER
25
20
15
10
5
720MHz
144MHz
36MHz
0
–140
0
0.25
0.50
0.75
1.00
1.25
1.50
0
0.25
0.50
0.75
1.00
1.25 1.50
VGN2 (V)
VGN2 (V)
Figure 22. Noise Figure vs. VGN2 for 36 MHz, 144 MHz, 720 MHz;
VGN1 = 1.5 V
Figure 25. Output NSD vs. VGN2 for 36 MHz, 144 MHz, 720 MHz;
VGN1 = 1.5 V
30
–115
–120
–125
–130
100MHz BYPASS
500MHz BYPASS
25
20
15
10
5
–135
NSD AT 100MHz
NSD AT 500MHz
0
–140
0
0.25
0.50
0.75
1.00
1.25
1.50
0
0.25
0.50
0.75
1.00 1.25 1.50
VGN2 (V)
VGN2 (V)
Figure 23. Noise Figure vs. VGN2 for Bypass Mode; NSD at 100 MHz and
500 MHz; VGN1 = 1.5 V
Figure 26. Output NSD vs. VGN2 for Bypass Mode; NSD at 100 MHz and
500 MHz; VGN1 = 1.5 V
Rev. 0 | Page 11 of 29
ADRF6520
Data Sheet
60
50
40
30
20
10
0
–115
–120
–125
–130
–135
–140
VGN2 = 0V
VGN2 = 0.2V
VGN2 = 0.4V
VGN2 = 0.6V
VGN2 = 0.8V
VGN2 = 1V
VGN2 = 1.2V
VGN2 = 1.4V
VGN2 = 1.6V
VGN2 = 0V
VGN2 = 0.6V
VGN2 = 1.2V
VGN2 = 0.2V
VGN2 = 0.8V
VGN2 = 1.4V
VGN2 = 0.4V
VGN2 = 1.0V
VGN2 = 1.6V
0
0.25
0.50
0.75
1.00
1.25
1.50
0
0.25
0.50
0.75
1.00
1.25
1.50
VGN1 (V)
VGN1 (V)
Figure 27. Noise Figure vs. VGN1 over VGN2, Bypass Mode
Figure 30. Output NSD vs. VGN1 over VGN2; Bypass Mode
–80
30
36MHz fC, GAIN = 54dB
144MHz fC, GAIN = 54dB
720MHz fC, GAIN = 54dB
36MHz fC, GAIN = 39dB
144MHz fC, GAIN = 39dB
720MHz fC, GAIN = 39dB
36MHz fC, GAIN = 24dB
144MHz fC, GAIN = 24dB
720MHz fC, GAIN = 24dB
–90
–100
–110
–120
–130
–140
–150
25
20
15
10
5
36MHz fC; VGN1/VGN2 = 1.5V/0V
720MHz fC; VGN1/VGN2 = 1.5V/0V
FILTER BYPASS; VGN1/VGN2 = 1.5V/0V
36MHz fC; VGN1/VGN2 = 1.5V/1.5V
720MHz fC; VGN1/VGN2 = 1.5V/1.5V
FILTER BYPASS; VGN1/VGN2 = 1.5V/1.5V
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10
TEMPERATURE (°C)
INPUT BLOCKER LEVEL (dBV)
Figure 31. Noise Figure vs. Temperature over Bandwidth and Gain
Figure 28. Output NSD vs. Input Blocker Level over VGA2 Gain and
Filter Corners; VGN1 = 1.5 V
–50
–55
–60
–65
–70
–75
–50
–55
–60
–65
–70
–75
–40°C, 3.15V
–40°C, 3.3V
–80
–80
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–85
–85
–90
–90
–95
–100
–95
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
Figure 29. HD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p at Output, Bypass Mode
Figure 32. HD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p at Output, Bypass Mode
Rev. 0 | Page 12 of 29
Data Sheet
ADRF6520
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
Figure 33. HD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p at Output, Bypass Mode
Figure 36. HD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p at Output, Bypass Mode
–50
–50
–55
–60
–65
–70
–75
–55
LOWER TONE
–60
–65
–70
–75
–80
–80
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–85
–85
–90
–95
–90
UPPER TONE
–95
–100
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
Figure 34. IMD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p Composite at Output, 36 MHz Filter Corner
Figure 37. IMD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p Composite at Output, 36 MHz Filter Corner
–50
–50
–55
–60
–65
–70
–75
–40°C, 3.15V
–40°C, 3.3V
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
UPPER TONE
–80
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–85
LOWER TONE
–90
–95
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
Figure 35. IMD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p Composite at Output, 144 MHz Filter Corner
Figure 38. IMD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p Composite at Output, 144 MHz Filter Corner
Rev. 0 | Page 13 of 29
ADRF6520
Data Sheet
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
UPPER TONE
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
LOWER TONE
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
Figure 39. IMD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p Composite at Output, 720 MHz Filter Corner
Figure 42. IMD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p Composite at Output, 720 MHz Filter Corner
–50
–50
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–55
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
LOWER TONE
–60
–65
–70
–75
–80
–85
–90
UPPER TONE
–95
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
Figure 40. IMD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p Composite at Output, 36 MHz Filter Corner
Figure 43. IMD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p Composite at Output, 36 MHz Filter Corner
–50
–50
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
–55
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–60
UPPER TONE
–65
+85°C, 3.45V
–70
–75
–80
–85
–90
–95
LOWER TONE
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
Figure 41. IMD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p Composite at Output, 144 MHz Filter Corner
Figure 44. IMD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p Composite at Output, 144 MHz Filter Corner
Rev. 0 | Page 14 of 29
Data Sheet
ADRF6520
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
UPPER TONE
LOWER TONE
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
Figure 45. IMD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p Composite at Output, 720 MHz Filter Corner
Figure 48. IMD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p Composite at Output, 720 MHz Filter Corner
–50
–50
–55
–60
–65
–70
–75
UPPER TONE
–55
–60
–65
–70
–75
–80
–80
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–85
–85
–90
–95
–90
LOWER TONE
–95
–100
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
Figure 46. IMD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p Composite at Output, Bypass Mode, 500 MHz Tones
Figure 49. IMD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p Composite at Output, Bypass Mode, 500 MHz Tones
–50
–55
–60
–65
–70
–75
–50
–55
–60
–65
–70
–75
–80
–80
–40°C, 3.15V
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
–40°C, 3.3V
–40°C, 3.45V
–85
–85
+25°C, 3.15V
+25°C, 3.15V
–90
–95
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–90
–95
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–100
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
Figure 47. IMD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p Composite at Output, Bypass Mode, 1 GHz Tones,
Low Tone Measured
Figure 50. IMD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V,
1.5 V p-p Composite at Output, Bypass Mode, 1 GHz Tones
Rev. 0 | Page 15 of 29
ADRF6520
Data Sheet
–50
–55
–60
–65
–70
–75
–80
–85
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
UPPER TONE
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
LOWER TONE
–90
–95
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
Figure 51. IMD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p Composite at Output, Bypass Mode, 500 MHz Tones
Figure 54. IMD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p Composite at Output, Bypass Mode, 500 MHz Tones
–50
–55
–60
–65
–70
–75
–50
–55
–60
–65
–70
–75
–80
–80
–40°C, 3.15V
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
–40°C, 3.3V
–40°C, 3.45V
–85
–85
+25°C, 3.15V
+25°C, 3.15V
–90
–95
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–90
–95
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–100
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN2 (V)
Figure 52. IMD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p Composite at Output, Bypass Mode, 1 GHz Tones,
Low Tone Measured
Figure 55. IMD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V,
1.5 V p-p Composite at Output, Bypass Mode, 1 GHz Tones
75
75
–40°C, 3.15V
–40°C, 3.15V
IIP2
70
65
60
55
50
45
40
35
30
25
20
15
10
5
70
65
60
55
50
45
40
35
30
25
20
15
10
5
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
–40°C, 3.3V
–40°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
IIP2
IIP3
IIP3
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN1 (V)
VGN1 (V)
Figure 53. Input IP2 (IIP2), Input IP3 (IIP3) vs. VGN1, VGN2 = 0 V, Bypass Mode,
500 MHz Tones
Figure 56. IIP2, IIP3 vs. VGN1, VGN2 = 0 V, Bypass Mode, 1 GHz Tones
Rev. 0 | Page 16 of 29
Data Sheet
ADRF6520
100
90
80
70
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
5
36MHz FILTER IIP2
720MHz FILTER IIP2
36MHz FILTER IIP3
720MHz FILTER IIP3
0
–10
–5
0
5
10
15
20
25
30
35
40
–10
–5
0
5
10
15
20
25
30
35
40
ABSOLUTE GAIN (dB)
ABSOLUTE GAIN (dB)
Figure 57. Out of Band IIP2, IMD2 for 36 MHz and 720 MHz
Figure 60. Out of Band IIP3, IMD3 for 36 MHz and 720 MHz
0
70
–10
60
50
40
30
20
10
0
–20
–30
–40
–50
–60
–70
–80
–90
–100
GAIN = +53dB
GAIN = +40dB
GAIN = +25dB
GAIN = +10dB
GAIN = –7dB
VGN1 = 1.5V, VGN2 = 0V
VGN1 = 0V, VGN2 = 0V
VGN1 = 1.5V, VGN2 = 1.5V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
100 200 300 400 500 600 700 800 900 1000 1100
FREQUENCY (MHz)
DIFFERENITAL OUTPUT (V p-p COMPOSITE)
Figure 58. In Band IMD3 vs. Differential Output Voltage (V p-p Composite)
over Gain, Bypass Mode at 500 MHz
Figure 61. Common-Mode Rejection Ratio (CMRR) vs. Frequency,
Bypass Mode
1
1
CH2 500mV
CH4 500mV
M2.00µs
CH2 500mV
CH4 500mV
M2.00µs
Figure 59. VGA1 Gain Step Response
Figure 62. VGA2 Gain Step Response; C9 and C16 = Open
Rev. 0 | Page 17 of 29
ADRF6520
Data Sheet
10
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
+85°C
+25°C
–40°C
+85°C, 3.15V
+85°C, 3.3V
+85°C, 3.45V
+25°C, 3.15V
+25°C, 3.3V
+25°C, 3.45V
–40°C, 3.15V
–40°C, 3.3V
–40°C, 3.45V
1
0.1
0.01
–50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
5
0
0.5
1.0
1.5
2.0
2.5
INPUT POWER (dBm)
OUTPUT SIGNAL LEVEL (V p-p)
Figure 63. Detector Output vs. Input Power (PIN) over Temperature,
VGN1 = 1.5 V, VGN2 = 0 V, Both Inputs Driven to Same Amplitude
Figure 64. Detector Output Voltage vs. Output Signal Level (V p-p) over Supply
and Temperature, VGN1 = 1.5 V, VGN2 = 0 V, Both Inputs Driven to Same
Amplitude
Rev. 0 | Page 18 of 29
Data Sheet
ADRF6520
THEORY OF OPERATION
36MHz TO 720MHz
PROGRAMMABLE
FILTERS
30dB
VVA
30dB
VVA
BASEBAND
INPUTS
BASEBAND
OUTPUTS
6dB
12dB
18dB
18dB
ANALOG
GAIN CONTROL
30mV/dB
SPI
INTERFACE
FILTER, CHIP ENABLE,
AND DC OFFSET LOOP
PROGRAMMING
SPI BUS
Figure 65. Signal Path Block Diagram for a Single Channel of the ADRF6520
The ADRF6520 consists of a matched pair of input VGAs
RMS DETECTOR
followed by programmable filters, 6 dB fixed gain amplifiers,
and finally another matched pair of variable gain amplifiers and
output ADC drivers. The filters can be bypassed and powered
down through the SPI interface for operation beyond the
maximum filter bandwidth. The block diagram of a single
channel is shown in Figure 65.
To measure the signal level at the critical interface of the VGA1
output and the programmable filter input, an rms detector was
implemented. The rms detector simultaneously measures both
channels at the VGA1 output and reports the sum of the two at
the VRMS pin. On-chip averaging capacitors set the minimum
settling time for the VRMS voltage to roughly 50 ns for most of
the signal measurement range. The on-chip capacitors can be
augmented by placing capacitors between the CFLT1 and CFLT2
pins and VPS. Off-chip capacitors are needed in most cases to
obtain an accurate rms measurement of the input signal, as well
as to reduce the modulation ripple in the VRMS output voltage.
The programmability of the filter bandwidth through the SPI
offers great flexibility when coping with signals in the presence
of noise and large, undesired signals near the desired band. The
entire differential signal chain is dc-coupled. The bandwidth
and gain setting controls for the two channels are shared,
ensuring close matching of their magnitude and phase
responses. The ADRF6520 can be fully disabled through the
ENBL pin or the enable bit in the SPI register.
The rms detector responds in a linear in volts manner, with the
VRMS voltage representing the rms value of the input signal
with the following relationship at maximum VGA1 gain:
Filtering and amplification are fundamental operations in
any signal processing system. Filtering is necessary to select
the intended signal while rejecting out of band noise and
interferers. Amplification increases the level of the desired
signal to overcome noise added by the system. When used
together, filtering and amplification can extract a low level
signal of interest in the presence of noise and out of band
interferers. Such analog signal processing alleviates the
requirements on the analog, mixed signal, and digital
components that follow.
VRMS = k × [RMS(ch1 input) + RMS(ch2 input)]
where RMS(x) is the root mean square value, and it is assumed
that sufficiently large filtering capacitors are chosen to allow
averaging of the modulation content.
The previous relationship applies at maximum VGA1 gain only.
When VGA1 gain is reduced, the VRMS output voltage also
decreases proportionately. Relating VRMS, the gain of VGA1
and the summation of the rms values of the channel inputs is
VRMS =
1(V/VRMS)(VGA1 Linear Voltage Gain)(RMS(ch1 input) +
RMS(ch2 input))
INPUT VGAs
The input VGAs are designed to have low noise and high
linearity. The VGAs have a differential input impedance of
100 Ω, maximum gain of 18 dB, and minimum gain of −12 dB,
providing a 30 dB gain range. They are designed to drive the
filters with up to 1.5 V p-p of undesired signal or 0.75 V p-p of
desired signal, or a combination of both. The input to the
ADRF6520 must be ac-coupled. The topology of the input VGA
is such that its noise figure (NF) degrades dB for dB as its gain
is reduced, although its high linearity is maintained across its
full input range. The input VGA can drive up to 3 V p-p at its
output; however, it is recommended that the VGA be kept to the
aforementioned limits to avoid overdriving the filter or 6 dB
fixed gain amplifier.
For example, if VGA1 is at its maximum gain of 18 dB, the
equation reduces down to
VRMS =
8(V/VRMS)(RMS(ch1 input) + RMS(ch2 input))
And at the VGA1 minimum gain of −12 dB, the equation
reduces down to
VRMS =
0.25(V/VRMS) × (RMS(ch1 input) + RMS(ch2 input))
Rev. 0 | Page 19 of 29
ADRF6520
Data Sheet
20
0
The RC time constant that, to a first order, dictates the rise and
fall times of the rms output is expressed with the following
equation:
36MHz
72MHz
144MHz
288MHz
432MHz
576MHz
720MHz
–20
τ (sec) = 500 Ω × (100 pF + CFLTx)
–40
where CFLTx is either the external CFLT1 value or CFLT2 value.
–60
Therefore, for the example of CFLTx = 0 (no external capacitor),
the settling time is 50 ns; and if CFLTx = 1 nF, the settling time is
550 ns. Note that this is the 90% settling time of the rms detector.
–80
–100
–120
–140
–160
There is a slight dependency on input power level, wherein larger
input signals to the rms detector cause it to settle more quickly.
Also, the settling time varies with temperature. The simple
equation, shown previously, is given for guidance so that the
user can set the settling times within an order of magnitude of
where they want it to be. If settling time is important, some
experimentation by the user is necessary to optimize the CFLTx
value for their system.
1M
10M
100M
1G
10G
100G
FREQUENCY (Hz)
Figure 66. Ideal Fourth-Order Butterworth Magnitude Response for All 1 dB
Bandwidths Programmed
18
36MHz
72MHz
16
144MHz
288MHz
PROGRAMMABLE FILTERS
14
12
10
8
432MHz
576MHz
720MHz
The integrated programmable filter is the key signal processing
function in the ADRF6520. The filters follow a four-pole
Butterworth type response that provides minimum in-band
ripple and group delay variation, and good out of band rejection.
The −1 dB bandwidth is programmed from 36 MHz to 720 MHz
in six steps via the SPI, as described in the Programming the
ADRF6520 section. The quoted corner frequency is the −1 dB
point; the ADRF6520 has filter corners at 36 MHz, 72 MHz, 144
MHz, 288 MHz, 432 MHz, 576 MHz, and 720 MHz.
6
4
2
0
1M
10M
100M
1G
10G
100G
The filters are designed so that the gain and phase responses vs.
frequency are retained for any bandwidth setting. Figure 66 and
Figure 67 illustrate the ideal four-pole Butterworth response.
The group delay, τG, is defined as
FREQUENCY (Hz)
Figure 67. Ideal Fourth-Order Butterworth Group Delay Response for All 1 dB
Bandwidths Programmed
Bypassing the Filters
τG = −∂φ/∂ω
For bandwidth applications greater than 720 MHz, the filters of
the ADRF6520 can be bypassed via the SPI. In filter bypass mode,
filters are disabled and power consumption is significantly
reduced. The bandwidth of cascaded VGAs is fully realized in
the filter bypass mode.
where:
φ is the phase in radians.
ω = 2πf is the frequency in radians per second.
Note that for a frequency scaled filter prototype, the absolute
magnitude of the group delay scales inversely with the
bandwidth; however, the shape is retained. For example, the
peak group delay for a 36 MHz bandwidth setting is 20× more
than for a 720 MHz setting.
VARIABLE GAIN AMPLIFIERS
The second VGA, VGA2, is based on the same architecture as the
input VGA, with 12 dB maximum gain and minimum gain of
−18 dB, providing a 30 dB gain range controlled with a separate
high impedance gain control input, the VGN2 pin. The basic
VGA structure of the second VGA is identical to that of the first
VGA. However, the VGA2 details vary slightly from VGA1 to
produce a higher noise figure.
The corner frequency of the filters is defined by the on-chip
RC product, which can vary by 20% over manufacturing
variations. Therefore, all the devices are factory calibrated for
corner frequency, resulting in a residual 8% corner frequency
variation over the −40°C to +85°C temperature range. Although
absolute accuracy requires calibration, the matching of RC
products between the pair of channels is better than 1% by
observing careful design and layout practices. Calibration and
excellent matching ensure that the magnitude and group delay
responses of both channels track together, a critical requirement
for digital IQ-based communication systems.
OUTPUT BUFFERS/ADC DRIVERS
The low impedance (<20 Ω) output buffers of the ADRF6520
have 18 dB of gain and are designed to drive either ADC inputs or
subsequent amplifier stages. They are capable of delivering up to
3.5 V p-p composite two-tone signals into 100 Ω differential
loads with >50 dBc IMD3. The output common-mode of the
ADC driver is set internally to mid supply and cannot be
Rev. 0 | Page 20 of 29
Data Sheet
ADRF6520
adjusted. If the circuit must be dc-coupled, it must be coupled
to a subsequent stage with matching common mode. However,
if common-mode matching is not possible, take care to limit the
dc common-mode current that is used to shift the common
mode, or else poor linearity results are observed.
In general, the expression for fHP is given by
HP (Hz) = 16.1 × VGA2 Linear Voltage Gain/COFS (µF)
f
where VGA2 Linear Voltage Gain is expressed in linear terms,
not in decibels (dB), and is the gain following the offset
correction amplifier, which excludes the all prior gain.
DC OFFSET COMPENSATION LOOP
For example, the high-pass corner at maximum VGA2 gain,
30 dB, and with COFS = 1 µF, is calculated as follows:
In many signal processing applications, no information is
carried in the dc level. In fact, dc voltages and other low
frequency disturbances can often dominate the intended signal
and consume precious dynamic range in the analog path and
bits in the data converters. These dc voltages can be present
with the desired input signal or can be generated inside the
signal path by inherent dc offsets or other unintended signal-
dependent processes such as self mixing or rectification.
30
1
10
20
fHP (Hz) =16.1
= 509.1Hz
Note that fHP increases in proportion to the gain. For this reason,
choose COFS at the highest operating gain to guarantee that fHP is
always below the maximum limit required by the system.
PROGRAMMING THE ADRF6520
It is recommended to use ac coupling capacitors at the input and
output terminals of the ADRF6520. The ac coupling capacitors
at the input block any dc offset from the input getting into the
device. The coupling capacitors must be sufficiently large,
because they form a high pass filter with the100 Ω differential
input impedance plus any source impedance of the driving circuit.
The high-pass corners may need to be <1 kHz in some cases.
The filter frequency, filter bypass mode, chip enable, and dc offset
correction loop enable are programmed simultaneously through
the SPI port. A 24-bit register stores 8 data bits, 15 bits for
addressing, and 1 bit for a read/write instruction (see Table 5).
The SPI protocol allows these selections to be written into and
read out of the SDIO pin (see the timing diagrams in Figure 69).
CS
The chip select bar ( ) pin must first go to a Logic 0 for a read
To address the issue of dc offsets generated inside the device, the
ADRF6520 provides a dc offset correction loop that nulls the
output differential dc level, as shown in Figure 68. The correction
loop can be disabled through the SPI port; however, when the
correction loop is disabled, the dc offsets can consume nearly
all of the output dynamic range, especially near maximum gain
settings, because of the large gain of the ADRF6520.
or write cycle to begin. On the next rising edge of the clock (SCLK),
a Logic 0 on the SDIO pin initiates a write cycle, whereas a Logic 1
on the SDIO pin initiates a read cycle. In a write cycle, the next
15 SCLK rising edges latch the desired 15-bit address, followed
by the 8-bit data word. The result is a 24-bit code, including the
CS
first Logic 0 to initiate a write cycle. When
goes high, the write
cycle is completed, and different codes are presented to the filter,
chip enable, and dc offset correction loop enable blocks that
require programming. In a read cycle, after writing in a Logic 1
for the read/write bit and the 15 address bits, the SDIO changes
from an input to an output in the ½ cycle of SCLK between the
last rising edge of SCLK of the instruction (read/write bit and
address bits) and the following falling edge. The next 8 SCLK
rising edges present the stored 8-bit word of data, MSB first on
ENABLE
BIT 5
C
HP
CHPx
FROM
6dB AMP
BASEBAND
OUTPUTS
30dB
VGA
OUTPUT ADC
DRIVER
CS
the SDIO pin. When
goes high, the read cycle is completed.
Detailed timing diagrams are shown in Figure 69.
VGN2
Figure 68. DC Offset Compensation Loop Operates Around the Second VGA
and ADC Driver
NOISE CHARACTERISTICS
The output noise behavior of the ADRF6520 primarily depends
on the gain. Filter corner switching in ADRF6520 is achieved by
changing the on-chip capacitors and keeping the resistors constant,
which results in constant contribution from the filter to the total
noise, irrespective of the filter corner. In filter bypass mode, noise
contribution of the bypass switches is significantly lower than
the active filter, which results in roughly 1 dB lower NF in the
filter bypass mode than the filter mode, at maximum gain.
The offset control loop creates a high-pass corner, fHP, that is
superimposed on the normal Butterworth filter response when
filters are enabled. Typically, fHP is many orders of magnitude
lower than the lower programmed filter bandwidth so that there
is no interaction between them. Setting fHP is accomplished with
capacitors, from the CHP1 and CHP2 pins to ground, as shown
in Figure 68. Because the correction loop works around the
VGA sections, fHP is also dependent on the total gain of the
cascaded VGAs.
Each of the VGA sections used in the ADRF6520 contributes a
fixed noise spectral density to its respective output, independent
of the analog gain setting. When cascaded, the total noise
contributed by the VGAs at the output of the ADRF6520
Rev. 0 | Page 21 of 29
ADRF6520
Data Sheet
increases gradually with higher gain. This behavior is apparent
in the noise floor variation at different VGA gain settings.
To distinguish and quantify the distortion performance of the
input section, two different IP2 and IP3 specifications are
presented. The first is called in-band IP2/IP3 and refers to a
two-tone test where the signals are inside the filter bandwidth.
This specification is exactly the same figure of merit familiar
to communications engineers in which the second-order and
third-order intermodulation levels, IMD2 and IMD3
respectively, are measured.
At low values of the VGA2 gain, the noise at the output is the
flat spectral density contributed by VGA2. As the VGA2 gain
increases, more of the filter and VGA1 noise is gained up by
VGA2, and the noise of the filter and VGA1 appears at the
output.
Because the noise spectral density outside the filter bandwidth
is limited by the VGA output noise, it may be necessary to use
an external, fixed frequency, passive filter prior to analog-to-
digital conversion to prevent noise aliasing from degrading the
signal-to-noise ratio (SNR). A higher sampling rate, relative to
the maximum required ADRF6520 corner frequency setting,
reduces the order and complexity of this external filter.
To quantify the effect of out of band signals, an out of band IIP2
and IIP3 figure of merits are introduced. These tests also involve
two-tone stimulus; however, the two tones are placed out of
band so that the lower IMD product falls in the middle of the
filter pass band. At the output, only the IMD product is visible
because the original two tones are filtered out. To calculate the
out of band IIP2/IIP3 at the input, the IMD2/IMD3 level is
referred to the input by the overall gain. The out of band
IIP2/IIP3 allows the user to predict the impact of out of band
blockers or interferers at an arbitrary signal level on the in-band
performance. The ratio of the desired input signal level to the
input referred IMD2/IMD3 at a given blocker level represents a
signal-to-distortion limit imposed by the out of band signals.
DISTORTION CHARACTERISTICS
To maintain low distortion through the cascaded VGAs and
filter of the ADRF6520, consider the distortion limits of each
stage. The first VGA has higher signal handling capability and
slightly more bandwidth than the 6 dB amplifier and VGA2,
because it must cope with out of band signals that can be larger
than the in-band signals. In filter mode, these out of band
signals are filtered before reaching the 6 dB amplifier and
VGA2. It is important to understand the signals presented to
the ADRF6520 and to match these signals with the input and
output characteristics of the device. It is useful to partition the
ADRF6520 into the front end (composed of VGA1 and the filter)
and the back end (composed of the 6 dB amplifier and VGA2).
MAXIMIZING THE DYNAMIC RANGE
When used in filter mode, the role of the ADRF6520 is to increase
the level of a variable in-band signal while minimizing out of
band signals. Ideally, this increase is achieved without degrading
the SNR of the incoming signal or introducing distortion to the
incoming signal.
The first goal is to maximize the output signal swing, which can
be defined by the ADC input range or the input signal capacity
of the next analog stage. For the complex waveforms often
encountered in communication systems, the peak to average
ratio, or crest factor, must be considered when choosing the
peak-to-peak output. From the chosen output signal and the
maximum gain of the ADRF6520, the minimum input level can
be defined.
VGA1 can handle a 4 V p-p signal at a maximum analog
attenuation setting (VGN1 = 0 V) without experiencing
appreciable distortion at the input. In most applications, VGA1
gain must be adjusted such that the maximum signal presented
at the filter inputs (or the input of the 6 dB amplifier in filter
bypass mode) is <1.5 V p-p. At this level, the front end does not
limit the distortion performance. The rms detector output,
VRMS, can be used as an indicator of the signal level present at
this critical interface. Choose the second VGA gain such that its
output levels do not exceed 1.5 V p-p if the user wants to
achieve better than 55 dBc HD2/HD3 linearity.
As the input signal level increases, the VGA2 gain is reduced
from its maximum gain point to maintain the desired fixed
output level. VGA1 can then be adjusted as the input signal
level keeps increasing. This sequencing of the gain maintains
the best NF for the cascaded chain. The output noise, initially
dominated by the filter and VGA1 combination, follows the
gain reduction, yielding a progressively better SNR. At some
point, the VGA2 gains drop sufficiently so that their noise
becomes dominant, resulting in a slower reduction in SNR from
that point. From the perspective of SNR alone, the maximum
input level is reached when the VGA1 reaches its minimum gain.
For these signal level considerations, it is recommended that the
out of band signal, if larger than the desired in-band signal, be
addressed. In filter mode, such an out of band signal only
affects the VGA1 operation, because it is filtered out by the
filter and does not affect the following stages. In this case, a
high VGA2 gain may be needed to raise the small desired signal
to a higher level at the output. In filter bypass mode, such out of
band signals may need to be filtered prior to the ADRF6520.
Distortion must also be considered when maximizing the
dynamic range. At low and moderate signal levels, the output
distortion is constant and assumed to be adequate for the
selected output level. At some point, the input signal becomes
large enough that distortion at the input limits the system. This
distortion can be kept in check by monitoring the rms detector
voltage, VRMS.
The overall distortion introduced by the device depends on the
input drive level, including the out of band signals, and the desired
output signal level. To achieve best distortion performance and
the desired overall gain, keep in mind the maximum signal levels
indicated previously in this section when selecting different
VGA gains.
Rev. 0 | Page 22 of 29
Data Sheet
ADRF6520
The most challenging scenario in terms of dynamic range is the
presence of a large out of band blocker accompanying a weaker
in-band wanted signal. In this case, the maximum input level is
dictated by the blocker and its inclination to cause distortion.
After filtering, the weak wanted signal must be amplified to the
desired output level, possibly requiring the maximum gain on
VGA2. In such a case, both the distortion limits associated with
the blocker at the input and the SNR limits created by the
weaker signal and higher gains are present simultaneously.
Furthermore, not only does the blocker scenario degrade the
dynamic range, it also reduces the range of input signals that
can be handled because a larger part of the gain range is used
to extract the weak desired signal from the stronger blocker.
and valleys. In a typical receiver, the goal is to recover the pair
of quadrature baseband signals in the presence of noise and
interfering signals after quadrature demodulation. In the process
of filtering out of band noise and unwanted interferers and
restoring the levels of the wanted I and Q baseband signals, it
is critical to retain their gain and phase integrity over the
bandwidth.
In filter mode, the ADRF6520 delivers flat, in band gain and
group delay, consistent with a four-pole Butterworth prototype
filter, as described in the Programmable Filters section.
Furthermore, careful design ensures excellent matching of these
parameters between the I and Q channels. Although absolute
gain flatness and group delay can be corrected with digital
equalization, mismatch introduces quadrature errors and
intersymbol interference that degrade bit error rates in digital
communication systems.
KEY PARAMETERS FOR QUADRATURE-BASED
RECEIVERS
The majority of digital communication receivers use quadrature
signaling, in which bits of information are encoded onto pairs of
baseband signals that then modulate in-phase (I) and quadrature
(Q) sinusoidal carriers. Both the baseband and modulated signals
appear quite complex in the time domain with dramatic peaks
For signals greater than 720 MHz of bandwidth, the filters can
be bypassed, and the ADRF6520 then becomes a dual cascaded
chain of two VGAs, offering a large gain range while maintaining
gain and group delay match between the two channels.
Rev. 0 | Page 23 of 29
ADRF6520
Data Sheet
SPI REGISTER AND TIMING
The filter frequency, filter bypass mode and offset correction loops can be programmed using the SPI interface. Table 5 provides the bit
map for the internal 24-bit register of the ADRF6520.
Table 5. Bit Map
MSB
LSB
B24
[B23:B9]
Address bits
B8
[B7:B6]
Don’t care
Don’t care
B5
B4
[B3:B1]
Filter frequency code
1 dB corner in MHz
000: 36 MHz
Read/write bit
0: write operation
1: read operation
Enable
0: disable
1: enable
DC offset disable
0: disable
1: enable
Don’t care
Don’t care
Set to 000000000010000
001: 72 MHz
010: 144 MHz
011: 288 MHz
100: 432 MHz
101: 576 MHz
110: 720 MHz
111: bypass
Table 6. Bit Map Default on Power-Up
MSB
LSB
B24
[B23:B9]
Address bits
B8
[B7:B6]
B5
B4
[B3:B1]
Filter frequency code
111
Read/write bit
0
Enable
1
Don’t care DC offset disable
Don’t care
Don’t care
Don’t care
000000000010000
1
Rev. 0 | Page 24 of 29
Data Sheet
ADRF6520
REGISTER READ/WRITE TIMING
tDS
tHI
tCLK
tH
tS
tACCESS
tDH
tLO
CS
SCLK
SDIO
DON’T CARE
DON’T CARE
DON’T CARE
tZ
R/W A14 A13 A12 A11 A10
A9
D7
D6
D5
D4
D3
D2
D1
D0
DON’T CARE
tDS
tHI
tCLK
tH
tS
tACCESS
tDH
tLO
CS
SCLK DON’T CARE
DON’T CARE
tZ
SDIO
DON’T CARE
R/W A14 A13 A12 A11 A10
A9
D7
D6
D5
D4
D3
D2
D1
D0
DON’T CARE
SETUP AND HOLD TIMEING MEASUREMENTS.
LEVEL MUST BE AT THE SAME HEAD AND TAIL.
Figure 69. SPI Port Read and Write Timing Diagrams
The interface is capable of reading and writing at speeds of at
least 25 MHz (tCLK = 40 ns). The hold time (tDH) is less than 25%
of the clock period. The setup time (tDS) is less than 25% of the
clock period. There is no minimum interface speed.
Table 7. SPI Port Timing Specifications
Symbol Description
tDS
tDH
tCLK
tS
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CS and SCLK
Hold time between CS and SCLK
Write Cycle
The instruction word, followed by the register data, is written
serially into the device through the SDIO pin on the rising
edges of the interface clock, SCLK. The device is configured in
MSB first mode and descending addressing.
tH
tHI
tLO
tZ
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Maximum time delay between CS deactivation and
SDIO or SDO bus return to high impedance
Read Cycle
The instruction word is written to the device MSB first,
followed by the data. Chip readback is sent via the SDIO. The
SDIO pin becomes an output pin after receiving the instruction
header with a readback request. In read mode, the SDIO line
must be changed from an input to an output in the half cycle of
SCLK between the last rising edge of SCLK of the instruction
tACCESS
Maximum time delay between falling edge of SCLK
and output data valid for a read operation
B24 = 0 initiates a write, and B24 = 1 initiates a read. The
instruction word (B24 followed by the 15 address bits) is written
to the device, MSB first (as shown in Figure 69), followed by the
data. The SDIO pin becomes an output pin after receiving the
instruction header with a readback request. In read mode, the
SDIO line must be changed from an input to an output in the
half cycle of SCLK between the last rising edge of SCLK of the
CS
and the following falling edge. When
is deasserted, SDIO
returns to high impedance until the next read transaction.
CS
instruction and the following falling edge. When is deasserted,
SDIO returns to high impedance until the next read transaction.
Rev. 0 | Page 25 of 29
ADRF6520
Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS
OUTPUT SIGNAL PATH
Figure 70 shows the basic connections for a typical ADRF6520
application.
The low impedance (20 Ω) output buffers are designed to drive
a 100 Ω impedance load, but can drive larger resistive loads.
The output pins (OPP1, OPM1, OPP2, and OPM2) sit at a
nominal output common-mode voltage of 1.65 V. The outputs
can be dc-coupled or ac-coupled; however, ac coupling is
preferred. There is no mechanism to change the output
common-mode voltage; therefore, if the user wants to dc-
couple, the common-mode voltage of the following stage must
match the ADRF6520 output common-mode voltage of 1.65 V.
SUPPLY DECOUPLING
Apply a nominal supply voltage of 3.3 V to the supply pins, VPS
and VPSD. The supply voltage must not exceed 3.45 V or drop
below 3.15 V for VPS and VPSD. Decouple each supply pin to
ground with at least one low inductance, surface-mount
ceramic capacitor of 0.1 μF placed as close as possible to the
ADRF6520 device.
DC OFFSET COMPENSATION LOOP ENABLED
The ADRF6520 has two separate supplies: one analog supply
and one digital supply. Take care to separate the analog and
digital supplies with a large surface-mount inductor of 33 μH.
Then decouple each supply separately to its respective ground
through a 10 μF capacitor.
When the dc offset compensation loop is enabled via Bit B5 of
the SPI register, the ADRF6520 can null the output differential
dc level. The loop is enabled by setting Bit B5 to 1. The offset
compensation loop creates a high-pass corner frequency, which
is proportional to the value of the capacitors that are connected
from the CHP1 and CHP2 pins to ground. For more
INPUT SIGNAL PATH
information about setting the high-pass corner frequency, see
the DC Offset Compensation Loop section.
Each signal path has an input VGA, accessed through the INP1,
INM1, INP2, and INM2 pins, which sets a differential input
impedance of 100 Ω.
SERIAL PORT CONNECTIONS
The inputs can be dc-coupled or ac-coupled, but ac coupling is
preferred. There is no mechanism to change the common-mode
voltage; therefore, if the user wants to dc-couple, the common-
mode voltage of the previous stage must match the ADRF6520
input common-mode voltage of 1.375 V.
The ADRF6520 has a SPI port to control the filter bandwidth,
chip enable, and dc offset compensation loop. Data can be
written to the internal 24-bit register and read from the register.
It is recommended that low-pass RC filtering be placed on the
SPI lines to filter out any high frequency glitches. See the
evaluation board schematic in the ADRF6520-EVALZ user
guide for an example of a low-pass RC filter.
0.1µF
VPS
VPSD
0.1µF
1µF
SERIAL
CONTROL
INTERFACE
VPS
OUTPUT1 (+)
INPUT1 (+)
INP1
OPP1
OPM1
COM
INPUT1 (–)
INPUT2 (–)
INM1
VPS
COM
CFLT1
CFLT2
COM
INM2
INP2
OUTPUT1 (–)
OUTPUT2 (–)
0.01µF
VGN1
VGN2
COM
ADRF6520
1nF
0.1µF
0.1µF
1nF
0.01µF
OPM2
OPP2
VPS
INPUT2 (+)
33µH
OUTPUT2 (+)
VPSD
10µF
VPS
SERIAL
CONTROL
INTERFACE
1µF
10µF
33µH
VPS
0.1µF
COMD
COM
Figure 70. Basic Connections
Rev. 0 | Page 26 of 29
Data Sheet
ADRF6520
section shows the VGA2 gain step response without the CHPx
capacitor installed. Settling time is approximately 3 µs, and there
are no transient events of any kind while the output settles. This
is not the case when there is a large capacitor placed on CHPx.
Figure 72 shows the VGA2 gain step response with a 1 µF capacitor
placed on CHPx. Settling time is increased to approximately
750 µs, and there is a large transient shift on the output. The user
wants to keep fHP as low as possible to minimize the corruption
of the low frequency spectral information. Care must be taken
when choosing the CHPx capacitor values, to find the correct
balance of the high-pass corner (fHP) imposed on the signal
paths vs. the VGA2 gain step response time. The larger the
CHPx capacitor, the lower fHP corner. The trade-off for lowering
ENABLE/DISABLE FUNCTION
To enable the ADRF6520, pull the ENBL pin high and set the
enable bit in the SPI register (B8) to a logic 1 (by default, the
ADRF6520 powers up with B8 = 1). Either driving the ENBL pin
low or setting B8 = 0 disables the device, reducing current
consumption to approximately 1 mA at room temperature.
GAIN PIN DECOUPLING
The ADRF6520 has two analog gain control pins: VGN1 and
VGN2. Use at least one low inductance, surface-mount ceramic
capacitor with a value of 0.1 µF and one 1000 pF in parallel to
ground on each gain pin to decouple. An example of this can be
seen in the evaluation board schematic in the ADRF6520-
EVALZ user guide.
fHP is longer VGA2 gain step response settling times and larger
transient values on the output.
RMS DETECTOR CONNECTIONS
The user must determine what their needs and priorities are for
their application and decide what specifications (fHP vs. VGA2
step response time) to trade-off to satisfy their total system
requirements.
The ADRF6520 has an rms detector output on the VRMS pin,
with a scaling of 1 V/V rms differential at filter inputs. VRMS
output reports a scaled summation of the differential rms voltage
of both channels: 1 V/V rms × (CH1_RMS + CH2_RMS).
CFLT1 and CFLT2 control the averaging of the Channel 1 and
Channel 2 rms detectors, respectively. The user can leave these
pins open for the fastest response time. The equation relating
the VRMS output video bandwidth and the CFLT1 (or CFLT2)
capacitor is given by
1
Video BWRMS (Hz) = 0.0007/(130 pF + CFLTx)
where CFLTx is the value of either CFLT1 or CFLT2.
The VRMS pin can source up to 3 mA of current. The output
structure is an NPN emitter follower type, with a 9.5 kΩ resistor
placed from VRMS to ground, internally (see Figure 71). Do
not to load the VRMS output with any load less than 1 kΩ.
CH2 500mV
CH4 500mV
M500µs
Figure 72. VGA2 Gain Step Response; C9 or C16 = 1 µF
3mA
MAXIMUM
VRMS
LINEAR OPERATION OF THE ADRF6520
1kΩ
MINIMUM
9.5kΩ
The ADRF6520 has multiple stages per channel. Each stage can
independently be driven into compression depending on the
gain settings and input signal level. There is only access to the
input stages (INP1/INM1 and INP2/INM2) and the output
stages (OPP1/OPM2 and OPP2/OPM2); therefore, the user
must infer the signal level at the input and output of each stage
from the device under test (DUT) input signal level and the
analog gain settings. The maximum recommended signal levels
are shown in Figure 73. Signal levels are presented in units of
V p-p differential, and their equivalent power in dBm re:100 Ω.
Figure 71. Simplified Schematic of VRMS Output
VGA2 GAIN STEP RESPONSE
VGA2 gain step response is affected by the dc offset correction
loop. The bandwidth of the loop is set by the value of the CHP1
and CHP2 capacitors. Changing the value of the CHPx capacitors
changes the signature and settling time of VGA2 gain step
response. Figure 62 in the Typical Performance Characteristics
POWER (dBm re: 100Ω)
+13
4.0
+12
+12
+8
+10.8
3.1
+12
VOLTAGE (V p-p)
3.56
3.56
2.25
3.56
INP1/INP2
INM1/INM2
VGN1
OPP1/OPP2
OPM1/OPM2
VGN2
Figure 73. Maximum Signal Levels—Single Channel Shown
Rev. 0 | Page 27 of 29
ADRF6520
Data Sheet
EVALUATION BOARD
An evaluation board is available for testing the ADRF6520.
Information on control software and board setup is available in
the ADRF6520-EVALZ user guide. Also available in the user
guide are the schematic, bill of materials, top level layout drawing,
and bottom level layout drawing.
Software, schematics, the bill of materials, and Gerber files are
available to download from the ADRF6520 product page.
Rev. 0 | Page 28 of 29
Data Sheet
ADRF6520
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
Figure 74. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-32-12
CP-32-12
ADRF6520ACPZ
ADRF6520ACPZ-R7
ADRF6520-EVALZ
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP], 7”Tape and Reel
Evaluation Board
1 Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14830-0-4/17(0)
Rev. 0 | Page 29 of 29
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