ADRF6521-EVALZ [ADI]
Low Frequency to 3 GHz, Dual VGA with Output Common-Mode and DC Offset Control;
| 型号： | ADRF6521-EVALZ |
| 厂家： | 
ADI |
| 描述： | Low Frequency to 3 GHz, Dual VGA with Output Common-Mode and DC Offset Control |
| 文件： | 总33页 (文件大小：1020K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Frequency to 3 GHz, Dual VGA with
Output Common-Mode and DC Offset Control
ADRF6521
Data Sheet
FEATURES
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
VPOS VGN
VNEG FLT1
OFS1
Dual, matched VGAs
Maximum voltage gain: 18 dB
+ –
INM1
INP1
OPM1
OPP1
Gain control attenuation range: 21 dB typical for TA = 25°C
1 dB gain flatness bandwidth: 2.5 GHz typical
IMD2 and IMD3 (1.5 V p-p output level)
−56.8 dBc typical and −75 dBc typical, respectively, at VGN =
1.5 V, 980 MHz and 1000 MHz tones
18dB
– +
COMM
VOCM
ADRF6521
HD2 and HD3 (1.5 V p-p output level)
−75 dBc typical and −73.7 dBc typical, respectively, atVGN =
1.5 V, fundamental at 500 MHz
−55.9 dBc typical and −57.5 dBc typical, respectively, at
VGN = 1.5 V, fundamental at 1 GHz
+ –
– +
INP2
INM2
OPP2
OPM2
18dB
Noise figure
10.5 dB typical at maximum gain and at 500 MHz
14.8 dB at maximum gain and at 2 GHz
Noise figure decreases dB for dB with gain backoff
100 Ω differential input impedance
VPOS PWD
VNEG FLT2
OFS2
Figure 1.
≤16 Ω differential output impedance
Programmable
Output DC offset nominal range: 400 mV
Output common-mode control: > 200 mV for VOCM = 0.2 V
Single- or dual-supply operation with power-down feature
Single supply: VPOS = 5 V, VNEG = 0 V (nominal)
Dual supply: VPOS = 3 V, VNEG =−2 V (nominal)
APPLICATIONS
Point-to-point and point-to-multipoint radios
Baseband IQ receivers
Diversity receivers
ADC drivers
Instrumentation
Medical
GENERAL DESCRIPTION
The ADRF6521 is a dual, fully differential, low noise and low
distortion variable gain amplifier (VGA). The high spurious-
free dynamic range over the gain range makes the ADRF6521
ideal for communication systems with dense constellations,
multiple carriers, and nearby interferers.
for second and third harmonic distortion (HD2 and HD3) from
low frequency to 1 GHz. Variable output dc offset control is
accomplished with the OFS1 and OFS2 pins, and the output
common-mode can be controlled with the VOCM pin.
The ADRF6521 flexibly operates from a single +5 V supply or
from a range of dual supplies and consumes a total supply
current of 200 mA. When fully disabled, it consumes 25 mA
typical. The ADRF6521 is fabricated in an advanced silicon-
germanium BiCMOS process and is available in a 20-lead,
exposed pad, 3 mm × 3 mm LFCSP. Performance is specified
over the −40°C to +85°C temperature range.
The VGA has a 21 dB attenuation range with a typical voltage
gain of 18 dB. The differential input impedance is 100 Ω, while the
differential output impedance is 16 Ω. The 1 dB gain flatness
bandwidth is 2.5 GHz. The output buffers are capable of swinging
1.5 V p-p into 100 ꢀ loads at >55 dBc for second-order and
third-order intermodulation distortion (IMD2 and IMD3), and
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADRF6521
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Output DC Offset Circuit ......................................................... 29
Gain Control Interface............................................................... 30
Power-Down Function .............................................................. 30
Applications Information.............................................................. 31
Basic Connections...................................................................... 31
Supply Decoupling ..................................................................... 31
Input Signal Path ........................................................................ 31
Output Signal Path ..................................................................... 31
Enable and Disable Function.................................................... 32
Gain Pin (VGN) Decoupling.................................................... 32
Output Impedance Matching ................................................... 32
Single-Supply Operation ........................................................... 32
Dual-Supply Operation ............................................................. 32
Avoiding Latch-Up..................................................................... 32
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 33
Applications....................................................................................... 1
Simplified Functional Block Diagram ........................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Electrostatic Discharge (ESD) Ratings ...................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Single-Supply Operation ............................................................. 9
Dual-Supply Operation ............................................................. 19
Theory of Operation ...................................................................... 29
Input VVAs .................................................................................. 29
Amplifiers.................................................................................... 29
Output Common-Mode Voltage .............................................. 29
REVISION HISTORY
11/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 33
Data Sheet
ADRF6521
SPECIFICATIONS
For single-supply operation, VPOS = 5 V, VNEG = 0 V nominal, and VOCM = 2.5 V, and for dual-supply operation, VPOS = 3 V, VNEG =
−2 V nominal, and VOCM = 0 V, unless otherwise noted. TA = 25°C and load impedance (ZLOAD) = 186 Ω, unless otherwise noted. Voltages
on VOCM, OFS1, and OFS2 are with respect to COMM (analog ground).
Table 1.
Parameter
Test Conditions/Comments
Single-supply operation
Channel 1 or 2, maximum gain
Maximum gain
Defined as difference between value at 100 kHz and
1 GHz
Min Typ
Max Unit
FREQUENCY RESPONSE
1 dB Gain Flatness Bandwidth
−3 dB Bandwidth
2.5
3.25
0.5
GHz
GHz
dB
Pass-Band Flatness
Gain Matching
Channel A and Channel B at same gain
Less than 1 GHz
0.2
0.4
dB
dB
Less than 3 GHz
Group Delay
Variation
Matching
From 500 MHz to 1 GHz
Frequency = 1 GHz
Frequency = 3 GHz
0.1
25
40
ns
ps
ps
INPUT STAGE
INP1, INM1, INP2, INM2
At minimum gain, VGN = 0 V
Maximum Input Swing
Differential Input Impedance
Input Common-Mode
8
100
V p-p
Ω
(VPOS + VNEG)/2, ac coupling recommended
VOCM undriven, single-supply operation
VOCM undriven, dual-supply operation
VGN (ground referenced)
Minimum
2.5
0.5
V
V
GAIN CONTROL
Voltage Range1, 2
0
V
Maximum
1.5
18
−3
21
>20
45
0.2
V
Voltage Gain
VGN = 1.5 V, maximum gain
VGN = 0 V, minimum gain
TA = 25°C
dB
dB
dB
dB
mV/dB
dB
Attenuation Range
−40°C ≤ TA ≤ +85°C
Gain Slope
Gain Error
VGA Step Response Time
Rise Time
Fall Time
COMMON-MODE CONTROL3
Default Value
Voltage Range1
VGN voltage (VVGN) range = 500 mV to 1000 mV
Through full attenuator range
From 10% to 90% of output
From 90% to 10% of output
VOCM (VPOS and VNEG supply referenced)
VOCM floating (nominal)
240
250
ns
ns
(VVPOS + VVNEG)/2
(VVPOS + VVNEG)/2
– 1
V
V
Minimum
Maximum
(VVPOS + VVNEG)/2
+ 1
V
Output Common Mode4
(VOPP1 + VOPM1)/2 or (VOPP2 + VOPM2)/2
VOCM = 0 V
0
V
VOCM = 0.2 V
VOCM = −0.2 V
VOCM = 0.3 V, functional maximum
OFS1 and OFS2 (ground referenced)
Minimum
200
−200
300
mV
mV
mV
DC OFFSET CONTROL
Voltage Range1, 2
0
1.5
V
V
Maximum
Rev. 0 | Page 3 of 33
ADRF6521
Data Sheet
Parameter
Test Conditions/Comments
Min Typ
Max Unit
Output DC Offset
(VOPP1 − VOPM1) or (VOPP2 − VOPM2)
OFS1 and OFS2 = 0.75 V (nominal)
OFS1 and OFS2 = 1.2 V
OFS1 and OFS2 = 0.3 V
OFS1 and OFS2 = 0 V
OFS1 and OFS2 = 1.5 V
OFS1 and OFS2 = 0.75 V
<20
400
−400
−600
600
mV
mV
mV
mV
mV
mV
DC Offset Channel to Channel
Mismatch
6.2
OUTPUT STAGE
OPP1, OPM1, OPP2, and OPM2
Maximum Output Swing
At maximum gain, load resistance (RLOAD) = 186 Ω
IMD2, IMD3, HD2, and HD3 are > 55 dBc at a 100 Ω
interface5
5.64
1.5
V p-p
V p-p
Output 1 dB Compression Point
(OP1dB)
Frequency = 1 GHz, gain = 18 dB, RLOAD = 186 Ω
>6
dBV6
At 100 Ω interface5
> 0.6
≤16
dBV6
Ω
Differential Output Impedance
NOISE AND DISTORTION
Single-Supply Operation
Output Noise Density
Input impedance (ZIN) = 100 Ω at 100 Ω interface5
VGN = 1.5 V at 500 MHz
VGN = 0.75 V at 500 MHz
VGN = 0 V at 500 MHz
VGN = 1.5 V at 2 GHz
VGN = 0.75 V at 2 GHz
−159.9
−161
−161.5
−155
−157
−157.4
dBV/Hz
dBV/Hz
dBV/Hz
dBV/Hz
dBV/Hz
dBV/Hz
VGN = 0 V at 2 GHz
Noise Figure
VGN = 1.5 V at 500 MHz
VGN = 0.75 V at 500 MHz
VGN = 0 V at 500 MHz
VGN = 1.5 V at 2 GHz
VGN = 0.75 V at 2 GHz
VGN = 0 V at 2 GHz
12.3
21.5
31.5
16.3
24.5
34.3
dB
dB
dB
dB
dB
dB
Second Harmonic Distortion, HD2
Third Harmonic Distortion, HD3
IMD2
1.5 V p-p output level
VGN = 1.5 V, fundamental at 500 MHz
VGN = 0.75 V, fundamental at 500 MHz
VGN = 0 V, fundamental at 500 MHz
VGN = 1.5 V, fundamental at 1 GHz
VGN = 0.75 V, fundamental at 1 GHz
VGN = 0 V, fundamental at 1 GHz
1.5 V p-p output level
VGN = 1.5 V, fundamental at 500 MHz
VGN = 0.75 V, fundamental at 500 MHz
VGN = 0 V, fundamental at 500 MHz
VGN = 1.5 V, fundamental at 1 GHz
VGN = 0.75 V, fundamental at 1 GHz
VGN = 0 V, fundamental at 1 GHz
1.5 V p-p output level
−75
−76
−77
−55.9
−54
−41
dBc
dBc
dBc
dBc
dBc
dBc
−73.7
−72
−72.6
−57.5
−68
dBc
dBc
dBc
dBc
dBc
dBc
−62
VGN = 1.5 V, 480 MHz and 500 MHz tones
VGN = 0.75 V, 480 MHz and 500 MHz tones
VGN = 0 V, 480 MHz and 500 MHz tones
VGN = 1.5 V, 980 MHz and 1000 MHz tones
VGN = 0.75 V, 980 MHz and 1000 MHz tones
VGN = 0 V, 980 MHz and 1000 MHz tones
−74
−62
−53
−56.8
−54
−45
dBc
dBc
dBc
dBc
dBc
dBc
Rev. 0 | Page 4 of 33
Data Sheet
ADRF6521
Parameter
Test Conditions/Comments
Min Typ
Max Unit
IMD3
1.5 V p-p output level
VGN = 1.5 V, 480 MHz and 500 MHz tones
VGN = 0.75 V, 480 MHz and 500 MHz tones
VGN = 0 V, 480 MHz and 500 MHz tones
VGN = 1.5 V, 980 MHz and 1000 MHz tones
VGN = 0.75 V, 980 MHz and 1000 MHz tones
VGN = 0 V, 980 MHz and 1000 MHz tones
−74
−77
−73
−75
−82
−76
dBc
dBc
dBc
dBc
dBc
dBc
Input Second-Order Intercept
Point (IIP2)
VGN = 1.5 V, 480 MHz and 500 MHz tones
VGN = 0.75 V, 480 MHz and 500 MHz tones
VGN = 0 V, 480 MHz and 500 MHz tones
VGN = 1.5 V, 980 MHz and 1000 MHz tones
VGN = 0.75 V, 980 MHz and 1000 MHz tones
VGN = 0 V, 980 MHz and 1000 MHz tones
44.9
44.5
45
27.5
36.3
36.7
dBV
dBV
dBV
dBV
dBV
dBV
Input Third-Order Intercept Point
(IIP3)
VGN = 1.5 V, 480 MHz and 500 MHz tones
VGN = 0.75 V, 480 MHz and 500 MHz tones
VGN = 0 V, 480 MHz and 500 MHz tones
VGN = 1.5 V, 980 MHz and 1000 MHz tones
VGN = 0.75 V, 980 MHz and 1000 MHz tones
VGN = 0 V, 980 MHz and 1000 MHz tones
7.9
dBV
dBV
dBV
dBV
dBV
dBV
20.1
28.5
8.2
23.3
29.7
Dual-Supply Operation
Output Noise Density
ZIN = 100 Ω at 100 Ω interface5
VGN = 1.5 V at 500 MHz
VGN = 0.75 V at 500 MHz
VGN = 0 V at 500 MHz
VGN = 1.5 V at 2 GHz
−161.7
dBV/Hz
dBV/Hz
dBV/Hz
dBV/Hz
dBV/Hz
dBV/Hz
−162.2
−162.1
−158.2
−158.4
−158.7
VGN = 0.75 V at 2 GHz
VGN = 0 V at 2 GHz
Noise Figure
VGN = 1.5 V at 500 MHz
VGN = 0.75 V at 500 MHz
VGN = 0 V at 500 MHz
VGN = 1.5 V at 2 GHz
VGN = 0.75 V at 2 GHz
VGN = 0 V at 2 GHz
10.5
20
31.3
14.8
24.5
34.4
dB
dB
dB
dB
dB
dB
HD2
1.5 V p-p output level
VGN = 1.5 V, fundamental at 500 MHz
VGN = 0.75 V, fundamental at 500 MHz
VGN = 0 V, fundamental at 500 MHz
VGN = 1.5 V, fundamental at 1 GHz
VGN = 0.75 V, fundamental at 1 GHz
VGN = 0 V, fundamental at 1 GHz
1.5V p-p output level
−79
−93
−79
−59
−53
−40.5
dBc
dBc
dBc
dBc
dBc
dBc
HD3
VGN = 1.5 V, fundamental at 500 MHz
VGN = 0.75 V, fundamental at 500 MHz
VGN = 0 V, fundamental at 500 MHz
VGN = 1.5 V, fundamental at 1 GHz
VGN = 0.75 V, fundamental at 1 GHz
VGN = 0 V, fundamental at 1 GHz
−72
−75
−72
−57
−70
−62.5
dBc
dBc
dBc
dBc
dBc
dBc
Rev. 0 | Page 5 of 33
ADRF6521
Data Sheet
Parameter
Test Conditions/Comments
Min Typ
Max Unit
IMD2
1.5 V p-p output level
VGN = 1.5 V, 480 MHz and 500 MHz tones
VGN = 0.75 V, 480 MHz and 500 MHz tones
VGN = 0 V, 480 MHz and 500 MHz tones
VGN = 1.5 V, 980 MHz and 1000 MHz tones
VGN = 0.75 V, 980 MHz and 1000 MHz tones
VGN = 0 V, 980 MHz and 1000 MHz tones
1.5 V p-p output level
−74
−60.9
−53
−58
−55
−46
dBc
dBc
dBc
dBc
dBc
dBc
IMD3
VGN = 1.5 V, 480 MHz and 500 MHz tones
VGN = 0.75 V, 480 MHz and 500 MHz tones
VGN = 0 V, 480 MHz and 500 MHz tones
VGN = 1.5 V, 980 MHz and 1000 MHz tones
VGN = 0.75 V, 980 MHz and 1000 MHz tones
VGN = 0 V, 980 MHz and 1000 MHz tones
−80
−86
−73.5
−71.6
−87
dBc
dBc
dBc
dBc
dBc
dBc
−76
IIP2
VGN = 1.5 V, 480 MHz and 500 MHz tones
VGN = 0.75 V, 480 MHz and 500 MHz tones
VGN = 0 V, 480 MHz and 500 MHz tones
VGN = 1.5 V, 980 MHz and 1000 MHz tones
VGN = 0.75 V, 980 MHz and 1000 MHz tones
VGN = 0 V, 980 MHz and 1000 MHz tones
44.9
43.4
45
28.7
37.3
37.7
dBV
dBV
dBV
dBV
dBV
dBV
IIP3
VGN = 1.5 V, 480 MHz and 500 MHz tones
VGN = 0.75 V, 480 MHz and 500 MHz tones
VGN = 0 V, 480 MHz and 500 MHz tones
VGN = 1.5 V, 980 MHz and 1000 MHz tones
VGN = 0.75 V, 980 MHz and 1000 MHz tones
VGN = 0 V, 980 MHz and 1000 MHz tones
VPOS, VNEG, COMM, and PWD
VPOS > COMM ≥ VNEG
Minimum
10.9
25.5
28.7
6.5
25.8
29.7
dBV
dBV
dBV
dBV
dBV
dBV
POWER AND ENABLE
Supply Voltage Range
VPOS − VNEG
4
V
Maximum
5
V
VPOS
VNEG
Minimum
Maximum
Minimum
2.5
5
−2.5
V
V
V
Maximum
0
V
Total Supply Current
Disable Current
PWD high voltage
200
mA
mA
V
PWD = VNEG
25
PWD Voltage Range
Minimum
VNEG
VNEG + 3.3
VNEG + 2.7
VNEG + 0.3
<20
Maximum
V
V
V
ns
ns
Enable Threshold
Disable Threshold
Enable Response Time
Disable Response Time
Delay following PWD low to high transition
Delay following PWD high to low transition
<8
1 Voltages beyond this range, but below the absolute maximum ratings, may cause latch-up problems.
2 The voltage range is the functional range of the pin.
3 VVPOS is the VPOS voltage, and VVNEG is the VNEG voltage.
4 VOPP1 is the OPP1 voltage, VOPM1 is the OPM1 voltage, VOPP2 is the OPP2 voltage, and VOPM2 is the OPM2 voltage.
5 Voltage levels at the interface are between the 43 Ω back termination resistors and 100 Ω differential load. This interface is −5.4 dB lower in voltage level than the
output of the ADRF6521.
6 X dBV = 20 × log10(x V rms/1 V rms). 0 dBV is equivalent to 1 V rms.
Rev. 0 | Page 6 of 33
Data Sheet
ADRF6521
ABSOLUTE MAXIMUM RATINGS
Table 2.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Parameter
Rating
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Supply Voltages: VPOS − VNEG
PWD
5.25 V
VNEG + 3.3 V
VPOS + 0.5 V
VPOS + 0.5 V
VPOS + 0.5 V
VPOS + 0.5 V
VPOS + 0.5 V
1.53 W
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
INP1, INM1, INP2, and INM2
OPP1, OPM1, OPP2, and OPM2
OFS1, OFS2
VOCM
VGN
Internal Power Dissipation
Temperature
Maximum Junction
Operating Range
Storage Range
Field induced charged device model (FICDM) per
ANSI/ESDA/JEDEC JS-002.
ESD Ratings for ADRF6521
Table 4. ADRF6521, 20-Lead LFCSP
ESD Model Withstand Threshold (V)
Class
1B
4
HBM
1000
1250
125°C
FICDM
−40°C to +85°C
−65°C to +150°C
300°C
Lead (Soldering 60 sec)
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 3. Thermal Resistance
1
2
Package Type
θJA
θJC
52.8
Unit
CP-20-19
62.25
°C/W
1 Based on simulation with JEDEC Standard JESD-51, using a 2S2P board.
2 Based on simulation with JEDEC Standard JESD-51, using a 1S0P board.
Rev. 0 | Page 7 of 33
ADRF6521
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
20 19 18 17 16
INM1
INP1
1
2
3
4
5
15 OPM1
14
13
12
11
OPP1
VOCM
OPP2
OPM2
ADRF6521
COMM
INP2
TOP VIEW
(Not to Scale)
INM2
6
7 8 9 10
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS INTERNALLY
CONNECTED TO VNEG AND MUST BE SOLDERED
TO THE NEGATIVE SUPPLY RAIL.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2
3
INM1, INP1
COMM
Channel 1 Differential Inputs, 100 Ω Differential Input Impedance. (VPOS + VNEG)/2 nominal common mode.
Analog Ground.
4, 5
6
INP2, INM2
OFS2
Channel 2 Differential Inputs, 100 Ω Differential Input Impedance. (VPOS + VNEG)/2 nominal common mode.
Channel 2 Output DC Offset Control. Nominal control range from 0.3 V to 1.2 V relative to analog ground. A 0.75 V
on OFSx produces a 0 V output offset voltage. OFS2 is not self biased. OFS2 must be driven. Left unconnected,
OFS2 is pulled to ground via an on-chip 5 kΩ resistor, which forces the output dc offset to be −700 mV. Voltages
greater than 1.5 V but less than the absolute maximum ratings may cause latch-up.
7
FLT2
Channel 2 Filter Pin. Connect FLT2 to the negative supply via a 1 µF capacitor.
8, 18
VNEG
Analog Negative Supply Voltage. For single-supply operation, set VNEG to 0 V nominal, and for dual-supply
operation, set VNEG to −2 V nominal. Keep (VPOS − VNEG) ≤ 5 V, VNEG ≤ COMM ≤ VPOS, and −2.5 V ≤ VNEG ≤ 0 V
to keep the voltage at the allowable pin voltage related to the voltage on the VPOS pin. Pins are electrically connected
on chip and to the exposed pad. Connect both VNEG pins and the exposed pad to the negative supply voltage.
9
PWD
Chip Power Down. Pull to VNEG supply to disable both channels. Leave unconnected to enable. Keep VPWD
(VNEG + 3.3 V).
≤
10, 16
VPOS
Analog Positive Supply Voltage. For single-supply operation, set VPOS to 5 V nominal, and for dual-supply
operation, set VPOS to 3 V nominal. Keep (VPOS − VNEG) ≤ 5 V, VNEG ≤ COMM ≤ VPOS, and VPOS ≥ 2.3 V to keep
the voltage at the allowable pin voltage related to the voltage on the VNEG pin. Pins are electrically connected
on chip. Connect both VPOS pins to the positive supply voltage.
11, 12
13
OPM2, OPP2
VOCM
Channel 2 Differential Outputs. These outputs have a 16 Ω differential output impedance.
Output Common-Mode Voltage Control. The nominal control range is (VPOS + VNEG)/2 − 200 mV to (VPOS +
VNEG)/2 + 200 mV. A 0 V on VOCM is a 0 V output common-mode voltage. Self biased to (VPOS + VNEG)/2.
Voltages greater than (VVPOS + VVNEG)/2 1 V but less than the absolute maximum ratings may cause latch-up.
14, 15
17
OPP1, OPM1
VGN
Channel 2 Differential Outputs. These outputs have a 16 Ω differential output impedance.
VGA Analog Gain Control. The VGN pins operate from 0 V to 1.5 V with 45 mV/dB gain scaling. Voltages greater
than 1.5 V but less than the absolute maximum ratings may cause latch-up.
19
20
FLT1
OFS1
Channel 1 Filter Pin. Connect FLT1 to a negative supply via a 1 µF capacitor.
Channel 1 Output DC Offset Control. Nominal control range from 0.3 V to 1.2 V relative to analog ground. A 0.75 V
on OFSx produces a 0 V output offset voltage. OFS1 is not self biased. OFS1 must be driven. Left unconnected,
OFS1 is pulled to ground via an on-chip 5 kΩ resistor, which forces the output dc offset to be −700 mV.
EP
Exposed Pad. The exposed pad is internally connected to VNEG and must be soldered to the negative supply rail.
Rev. 0 | Page 8 of 33
Data Sheet
ADRF6521
TYPICAL PERFORMANCE CHARACTERISTICS
SINGLE-SUPPLY OPERATION
VPOS = 5 V, VNEG = 0 V, TA = 25°C, ZLOAD = 186 Ω, VGN = 1.5 V, VOCM = 2.5 V, OFS1 = OFS2 = 0.75 V, output level = 1.5 V p-p, and
43 Ω back termination resistors de-embedded, unless otherwise noted. Noise figure measured with 100 Ω differential input termination.
Worst case IMD2 and IMD3 tone reported. VOFSx sweeps = 0 V, 0.4 V, 0.75 V, or 1.2 V. VOCM sweeps = 2.4 V, 2.5 V, or 2.6 V.
5
20
18
16
14
12
10
8
5
20
18
16
14
12
10
8
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
4
4
3
3
2
2
1
1
0
0
6
6
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
4
4
2
2
0
0
–2
–4
–2
–4
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 3. Voltage Gain and Error vs. VGN Voltage over Temperature at 500 MHz
Figure 6. Voltage Gain and Error vs. VGN Voltage over Temperature at 1 GHz
20
18
16
14
12
10
8
5
5
20
18
16
14
12
10
8
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
4
4
3
3
2
2
1
1
0
0
6
6
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
4
4
2
2
0
0
–2
–4
–2
–4
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 4. Voltage Gain and Error vs. VGN Voltage over Temperature at 2 GHz
Figure 7. Voltage Gain and Error vs. VGN Voltage over Temperature at 3 GHz
20
15
10
5
15
10
5
0
0
–5
–10
–5
–10
VGN = 1.5V, –40°C
VGN = 0.75V, –40°C
VGN = 0V, –40°C
–15
–20
–25
VGN = 1.5V, +25°C
VGN = 0.75V, +25°C
VGN = 0V, +25°C
VGN = 1.5V, +85°C
VGN = 0.75V, +85°C
VGN = 0V, +85°C
VGN = 1.5V
VGN = 1.4V
VGN = 1.2V
VGN = 1.0V
VGN = 0.8V
VGN = 0.6V
VGN = 0.4V
VGN = 0.2V
VGN = 0V
–15
1M
10M
100M
1G
0.1
1
10
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 5. Voltage Gain vs. Frequency over Temperature and VGN, 43 Ω Back
Terminations not De-Embedded
Figure 8. Voltage Gain vs. Frequency over 200 mV VGN Steps, 43 Ω Back
Terminations not De-Embedded
Rev. 0 | Page 9 of 33
ADRF6521
Data Sheet
0
0
–5
VGN = 1.5V, –40°C
VGN = 0.75V, –40°C
VGN = 0V, –40°C
VGN = 1.5V, +85°C
VGN = 0.75V, +85°C
VGN = 0V, +85°C
VGN = 1.5V, –40°C
VGN = 0.75V, –40°C
VGN = 0V, –40°C
VGN = 1.5V, +85°C
VGN = 0.75V, +85°C
VGN = 0V, +85°C
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
VGN = 1.5V, +25°C
VGN = 0.75V, +25°C
VGN = 0V, +25°C
VGN = 1.5V, +25°C
VGN = 0.75V, +25°C
VGN = 0V, +25°C
–10
–15
–20
–25
–30
–35
–40
–45
0.1
1
0.1
1
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Differential Input Return Loss (S11) vs. Frequency over Temperature
and VGN
Figure 12. Differential Output Return Loss (S22) vs. Frequency over
Temperature and VGN
40
35
30
25
20
–150
VGN = 1.5V, = –40°C
VGN = 0.75V, –40°C
VGN = 0V, –40°C
VGN = 1.5V, +85°C
VGN = 0.75V, +85°C
VGN = 0V, +85°C
–151
–152
–153
–154
–155
–156
–157
–158
–159
–160
–161
–162
–163
–164
–165
VGN = 1.5V, +25°C
VGN = 0.75V, +25°C
VGN = 0V, +25°C
15
VGN = 1.5V, +25°C
10
VGN = 0.75V, +25°C
VGN = 0V, +25°C
VGN = 1.5V, +85°C
VGN = 0.75V, +85°C
VGN = 0V, +85°C
VGN = 1.5V, –40°C
VGN = 0.75V, –40°C
VGN = 0V, –40°C
5
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
FREQUENCY (GHz)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
FREQUENCY (GHz)
Figure 10. Noise Figure vs. Frequency over Temperature and VGN
Figure 13. Output Noise Density vs. Frequency over Temperature and VGN
40
–150
–40°C
–40°C
–151
+25°C
+25°C
35
30
+85°C
–152
–153
–154
–155
–156
–157
–158
–159
–160
–161
–162
–163
–164
–165
+85°C
25
20
15
10
5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 11. Noise Figure vs. VGN Voltage over Temperature at 500 MHz
Figure 14. Output Noise Density vs. VGN over Temperature at 500 MHz
Rev. 0 | Page 10 of 33
Data Sheet
ADRF6521
40
35
30
25
20
15
10
5
–150
–151
–152
–153
–154
–155
–156
–157
–158
–159
–160
–161
–162
–163
–164
–165
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN (V)
Figure 15. Noise Figure vs. VGN Voltage over Temperature, at 1 GHz
Figure 18. Output Noise Density vs. VGN over Temperature at 1 GHz
40
–150
–40°C
–40°C
+25°C
–151
–152
–153
–154
–155
–156
–157
–158
–159
–160
–161
–162
–163
–164
–165
+25°C
+85°C
35
30
25
20
15
10
5
+85°C
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 16. Noise Figure vs. VGN Voltage over Temperature, at 2 GHz
Figure 19. Output Noise Density vs. VGN over Temperature at 2 GHz
40
–150
–40°C
–40°C
–151
+25°C
+25°C
35
30
+85°C
–152
–153
–154
–155
–156
–157
–158
–159
–160
–161
–162
–163
–164
–165
+85°C
25
20
15
10
5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 17. Noise Figure vs. VGN Voltage over Temperature at 3 GHz
Figure 20. Output Noise Density vs. VGN over Temperature at 3 GHz
Rev. 0 | Page 11 of 33
ADRF6521
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–100
500M
1G
3G
500M
1G
3G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. IMD3 vs. Frequency over VGN and OFSx
Figure 21. IMD2 vs. Frequency over VGN and OFSx
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
–10
500M
1G
3G
500M
1G
3G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. IIP3 vs. Frequency over VGN
Figure 22. IIP2 vs. Frequency over VGN
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 23. IMD2 vs. VGN Voltage over Temperature and OFSx at 500 MHz
Figure 26. IMD3 vs. VGN Voltage over Temperature and OFSx at 500 MHz
Rev. 0 | Page 12 of 33
Data Sheet
ADRF6521
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 27. IMD2 vs. VGN Voltage over Temperature and OFSx at 1 GHz
Figure 30. IMD3 vs. VGN Voltage over Temperature and OFSx at 1 GHz
0
0
–40°C
–40°C
+25°C
+85°C
+25°C
–10
–20
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+85°C
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 28. IMD2 vs. VGN Voltage, over Temperature and OFSx at 2 GHz
Figure 31. IMD3 vs. VGN Voltage over Temperature and OFSx at 2 GHz
0
0
–40°C
+25°C
+85°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40°C
+25°C
+85°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 29. IMD2 vs. VGN Voltage over Temperature and OFSx at 3 GHz
Figure 32. IMD3 vs. VGN Voltage over Temperature and OFSx at 3 GHz
Rev. 0 | Page 13 of 33
ADRF6521
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 33. HD2 vs. VGN Voltage over Temperature and OFSx at 500 MHz
Figure 36. HD3 vs. VGN Voltage over Temperature and OFSx at 500 MHz
0
0
–40°C
–40°C
+25°C
+85°C
+25°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
+85°C
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 34. HD2 vs. VGN Voltage over Temperature and OFSx at 1 GHz
Figure 37. HD3 vs. VGN Voltage over Temperature and VOCM at 1 GHz
0
0
–40°C
–40°C
+25°C
–10
–20
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+25°C
+85°C
+85°C
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 35. HD2 vs. VGN Voltage over Temperature and OFSx at 2 GHz
Figure 38. HD3 vs. VGN Voltage over Temperature and OFSx at 2 GHz
Rev. 0 | Page 14 of 33
Data Sheet
ADRF6521
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 39. HD2 vs. VGN Voltage over Temperature and OFSx at 3 GHz
Figure 42. HD3 vs. VGN Voltage over Temperature and OFSx at 3 GHz
0
0
–40°C
–40°C
+25°C
+25°C
+85°C
–10
–20
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+85°C
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 40. HD2 vs. VGN Voltage over Temperature and VOCM at 500 MHz
Figure 43. HD3 vs. VGN Voltage over Temperature and VOCM at 500 MHz
0
0
–40°C
–40°C
+25°C
+85°C
+25°C
+85°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 41. HD2 vs. VGN Voltage over Temperature and VOCM at 1 GHz
Figure 44. HD3 vs. VGN Voltage over Temperature and VOCM at 1 GHz
Rev. 0 | Page 15 of 33
ADRF6521
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 48. HD3 vs. VGN Voltage over Temperature and VOCM at 2 GHz
Figure 45. HD2 vs. VGN Voltage over Temperature and VOCM at 2 GHz
0
0
–40°C
–40°C
+25°C
+25°C
–10
–20
–10
–20
+85°C
+85°C
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 49. HD3 vs. VGN Voltage over Temperature and VOCM at 3 GHz
Figure 46. HD2 vs. VGN Voltage over Temperature and VOCM at 3 GHz
20
20
–40°C
–40°C
+25°C
+85°C
+25°C
18
16
14
12
10
8
18
16
+85°C
14
12
10
8
6
6
4
4
2
2
0
0
500M
1G
3G
500M
1G
3G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 47. OP1dB vs. Frequency over Temperature and OFSx
Figure 50. OP1dB vs. Frequency over Temperature and VOCM
Rev. 0 | Page 16 of 33
Data Sheet
ADRF6521
600
8
7
6
5
4
3
2
1
0
VOCM VARIED FROM –0.3V TO +0.3V IN 0.1V STEPS
VOCM = –0.3V
VOCM = –0.2V
VOCM = –0.1V
VOCM = 0V
VOCM = 0.1V
VOCM = 0.2V
VOCM = 0.3V
400
200
0
–200
–400
–600
+85°C
+25°C
–40°C
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
V
VOLTAGE (V)
V
OFSx
VOLTAGE (V)
OFSx
Figure 51. Differential DC Offset Voltage vs. VOFSx Voltage over Temperature
and VOCM
Figure 54. Differential Offset Voltage Mismatch (Channel to Channel) vs.
V
OFSx Voltage over VOCM
5
1.2
1.0
0.8
0.6
0.4
0.2
0
VGN = 1.50V
VGN = 0.75V
4
VGN = 0V
3
2
1
0
–1
–2
–3
–4
–5
VGN = 1.5V
VGN = 0.7V
VGN = 0V
0.1
1.0
FREQUENCY (GHz)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
FREQUENCY (GHz)
Figure 52. Channel to Channel Phase Mismatch vs. Frequency over VGN
Figure 55. Group Delay vs. Frequency over VGN
208
206
204
202
200
198
196
194
192
190
0.25
0.20
0.15
0.10
0.05
0
1.8
CHANNEL 1
VGN
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.05
–0.10
–0.15
–0.20
–0.25
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–0.2
600
–200 –100
0
100
200
300
400
500
TIME (ns)
Figure 53. Supply Current vs. Temperature for Multiple Devices
Figure 56. VGA Step Response Rise Time, Minimum to Maximum Gain
Rev. 0 | Page 17 of 33
ADRF6521
Data Sheet
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
6
CHANNEL 1
VGN
CHANNEL 1
PWD
5
0.15
0.10
0.05
0
4
3
2
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
–0.15
–0.20
–0.25
1
0
–1
–2
–0.25
–200
–100
0
100
200
300
400
500
600
–15
–10
–5
0
5
10
15
20
25
30
TIME (ns)
TIME (ns)
Figure 57. VGA Step Response Fall Time, Maximum to Minimum Gain
Figure 59. Enable Response Time
0.25
0.20
0.15
0.10
0.05
0
6
CHANNEL 1
PWD
5
4
3
2
–0.05
–0.10
–0.15
–0.20
–0.25
1
0
–1
–10
–5
0
5
10
15
20
25
30
TIME (ns)
Figure 58. Disable Response Time
Rev. 0 | Page 18 of 33
Data Sheet
ADRF6521
DUAL-SUPPLY OPERATION
VPOS = 3 V and VNEG = −2 V, T A = 25°C, ZLOAD = 186 Ω, VGN = 1.5 V, VOCM = 0 V, OFS1 = OFS2 = 0.75 V, output level = 1.5 V p-p,
and 43 Ω back termination de-embedded, unless otherwise noted. Noise figure measured with 100 Ω differential input termination.
Worst case IMD2 and IMD3 tone reported. VOFSx sweeps = 0 V, 0.4 V, 0.75 V, or 1.2 V. VOCM sweeps = −0.1 V, 0 V, or +0.1 V.
20
18
16
14
12
10
8
5
20
18
16
14
12
10
8
5
4
4
3
3
2
2
1
1
0
0
6
6
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
4
4
2
2
+85°C
+25°C
–40°C
0
+85°C
+25°C
–40°C
0
–2
–4
–2
–4
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
VGN VOLTAGE (V)
Figure 60. Voltage Gain and Error vs. VGN Voltage over Temperature at 500 MHz
Figure 63. Voltage Gain and Error vs. VGN Voltage over Temperature at 1 GHz
20
18
16
14
12
10
8
5
20
18
16
14
12
10
8
5
4
4
3
3
2
2
1
1
0
0
6
6
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
4
4
2
2
+85°C
+25°C
–40°C
0
+85°C
+25°C
–40°C
0
–2
–4
–2
–4
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
VGN VOLTAGE (V)
Figure 61. Voltage Gain and Error vs. VGN Voltage over Temperature at 2 GHz
Figure 64. Voltage Gain and Error vs. VGN Voltage over Temperature at 3 GHz
15
10
5
0
–5
–10
–40°C, VGN = 1.5V
–40°C, VGN = 0.75V
–40°C, VGN = 0V
+85°C, VGN = 1.5V
+85°C, VGN = 0.75V
+85°C, VGN = 0V
+25°C, VGN = 1.5V
+25°C, VGN = 0.75V
+25°C, VGN = 0V
VGN = 1.5V
VGN = 1.4V
VGN = 1.2V
VGN = 1.0V
VGN = 0.8V
VGN = 0.6V
VGN = 0.4V
VGN = 0.2V
VGN = 0V
–15
0.1
1
1
10
100
1000
FREQUENCY (GHz)
FREQUENCY (MHz)
Figure 62. Voltage Gain vs. Frequency, over Temperature and VGN, 43 Ω Back
Terminations not De-Embedded
Figure 65. Voltage Gain vs. Frequency over 200 mV VGN Steps, 43 Ω Back
Terminations not De-Embedded
Rev. 0 | Page 19 of 33
ADRF6521
Data Sheet
0
0
–5
–40°C, VGN = 1.5V
–40°C, VGN = 0.75V
–40°C, VGN = 0V
+25°C, VGN = 1.5V
+25°C, VGN = 0.75V
+25°C, VGN = 0V
+85°C, VGN = 1.5V
+85°C, VGN = 0.75V
+85°C, VGN = 0V
–10
–15
–20
–25
–30
–35
–40
–45
+85°C, VGN = 1.50V
+25°C, VGN = 1.50V
–40°C, VGN = 1.50V
+85°C, VGN = 0.75V
+25°C, VGN = 0.75V
–40°C, VGN = 0.75V
+85°C, VGN = 0V
+25°C, VGN = 0V
–40°C, VGN = 0V
–50
0.1
0.1
1
1
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 66. Differential S11 vs. Frequency over Temperature and VGN
Figure 69. Differential S22 vs. Frequency over Temperature and VGN with 43 Ω
Back Terminations
40
–150
+85°C, VGN = 1.50V
+25°C, VGN = 1.50V
+85°C, VGN = 1.50V
–151
+25°C, VGN = 1.50V
35
–152
–153
–154
–155
–156
–157
–158
–159
–160
–161
–162
–163
–164
–165
–40°C, VGN = 1.50V
–40°C, VGN = 1.50V
+85°C, VGN = 0.70V
+25°C, VGN = 0.70V
–40°C, VGN = 0.70V
30
25
+85°C, VGN = 0V
+25°C, VGN = 0V
–40°C, VGN = 0V
20
+85°C, VGN = 0.70V
+25°C, VGN = 0.70V
–40°C, VGN = 0.70V
15
10
5
+85°C, VGN = 0V
+25°C, VGN = 0V
–40°C, VGN = 0V
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
FREQUENCY (GHz)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
FREQUENCY (GHz)
Figure 67. Noise Figure vs. Frequency over Temperature and VGN
Figure 70. Output Noise Density vs. Frequency over Temperature and VGN
40
–150
–151
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
35
30
25
20
15
10
5
–152
–153
–154
–155
–156
–157
–158
–159
–160
–161
–162
–163
–164
–165
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 68. Noise Figure vs. VGN Voltage over Temperature at 500 MHz
Figure 71. Output Noise Density vs. VGN Voltage over Temperature at 500 MHz
Rev. 0 | Page 20 of 33
Data Sheet
ADRF6521
40
35
30
25
20
15
10
5
–150
–151
–152
–153
–154
–155
–156
–157
–158
–159
–160
–161
–162
–163
–164
–165
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 72. Noise Figure vs. VGN Voltage over Temperature at 1 GHz
Figure 75. Output Noise Density vs. VGN Voltage over Temperature at 1 GHz
40
–150
–151
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
35
30
25
20
15
10
5
–152
–153
–154
–155
–156
–157
–158
–159
–160
–161
–162
–163
–164
–165
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 73. Noise Figure vs. VGN Voltage over Temperature at 2 GHz
Figure 76. Output Noise Density vs. VGN Voltage over Temperature at 2 GHz
40
–150
+85°C
+25°C
–40°C
–151
–152
–153
–154
–155
–156
–157
–158
–159
–160
–161
–162
–163
–164
–165
+85°C
35
30
25
20
15
10
5
+25°C
–40°C
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 74. Noise Figure vs. VGN Voltage over Temperature at 3 GHz
Figure 77. Output Noise Density vs. VGN Voltage over Temperature at 3 GHz
Rev. 0 | Page 21 of 33
ADRF6521
Data Sheet
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
500M
1G
3G
500M
1G
3G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 78. IMD2 vs. Frequency over Temperature and VGN
Figure 81. IMD3 vs. Frequency over Temperature and VGN
60
60
50
40
30
20
10
0
50
40
30
20
10
0
–10
500M
1G
3G
500M
1G
3G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 79. IIP2 vs. Frequency over VGN in 200 mV Steps
Figure 82. IIP3 vs. Frequency over VGN in 200 mV Steps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 80. IMD2 vs. VGN Voltage over Temperature and OFSx at 500 MHz
Figure 83. IMD3 vs. VGN Voltage over Temperature and OFSx at 500 MHz
Rev. 0 | Page 22 of 33
Data Sheet
ADRF6521
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 84. IMD2 vs. VGN Voltage over Temperature and OFSx at 1 GHz
Figure 87. IMD3 vs. VGN Voltage over Temperature and OFSx at 1 GHz
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 85. IMD2 vs. VGN Voltage over Temperature and OFSx at 2 GHz
Figure 88. IMD3 vs. VGN Voltage over Temperature and OFSx at 2 GHz
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 86. IMD2 vs. VGN Voltage over Temperature and OFSx at 3 GHz
Figure 89. IMD3 vs. VGN Voltage over Temperature and OFSx at 3 GHz
Rev. 0 | Page 23 of 33
ADRF6521
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 90. HD2 vs. VGN Voltage over Temperature and OFSx at 500 MHz
Figure 93. HD3 vs. VGN Voltage over Temperature and OFSx at 500 MHz
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 91. HD2 vs. VGN Voltage over Temperature and OFSx at 1 GHz
Figure 94. HD3 vs. VGN Voltage over Temperature and OFSx at 1 GHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
+85°C
–10
–20
+25°C
–40°C
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 92. HD2 vs. VGN Voltage over Temperature and OFSx at 2 GHz
Figure 95. HD3 vs. VGN Voltage over Temperature and OFSx at 2 GHz
Rev. 0 | Page 24 of 33
Data Sheet
ADRF6521
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40°C
+25°C
+85°C
+85°C
+25°C
–40°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 96. HD2 vs. VGN Voltage over Temperature and OFSx at 3 GHz
Figure 99. HD3 vs. VGN Voltage over Temperature and OFSx at 3 GHz
0
0
–40°C
–40°C
+25°C
+85°C
+25°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–10
–20
+85°C
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 97. HD2 vs. VGN Voltage over Temperature and VOCM at 500 MHz
Figure 100. HD3 vs. VGN Voltage over Temperature and VOCM at 500 MHz
0
0
–40°C
–40°C
+25°C
+85°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
+25°C
+85°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 98. HD2 vs. VGN Voltage over Temperature and VOCM at 1 GHz
Figure 101. HD3 vs. VGN Voltage over Temperature and VOCM at 1 GHz
Rev. 0 | Page 25 of 33
ADRF6521
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
Figure 102. HD2 vs. VGN Voltage over Temperature and VOCM at 2 GHz
Figure 105. HD3 vs. VGN Voltage over Temperature and VOCM at 2 GHz
0
0
–40°C
–40°C
+25°C
–10
–10
–20
+25°C
+85°C
+85°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VGN VOLTAGE (V)
`Figure 103. HD2 vs. VGN Voltage over Temperature and VOCM at 3 GHz
Figure 106. HD3 vs. VGN Voltage over Temperature and VOCM at 3 GHz
20
20
–40°C
–40°C
+25°C
+85°C
+25°C
18
18
16
14
12
10
8
+85°C
16
14
12
10
8
6
6
4
4
2
2
0
0
500M
1G
3G
500M
1G
3G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 104. OP1dB vs. Frequency over Temperature and OFSx at Maximum
Gain
Figure 107. OP1dB vs. Frequency over Temperature and VOCM at Maximum
Gain
Rev. 0 | Page 26 of 33
Data Sheet
ADRF6521
14
12
10
8
500
VOCM VARIED FROM –0.3V TO +0.3V IN 0.1V STEPS
400
300
200
100
0
6
–100
–200
–300
–400
–500
VOCM = –0.3V
VOCM = –0.2V
VOCM = –0.1V
VOCM = 0V
VOCM = 0.1V
VOCM = 0.2V
VOCM = 0.3V
4
–40°C
+25°C
+85°C
2
0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
V
VOLTAGE (V)
V
VOLTAGE (V)
OFSx
OFSx
Figure 108. Output Differential DC Offset Voltage vs. VOFSx Voltage over
Temperature and VOCM
Figure 111. Output Differential DC Offset Channel to Channel Mismatch vs.
OFSx Voltage over VOCM
V
1.20
1.00
0.80
0.60
0.40
0.20
0
0.5
VGN = 0V
VGN = 0V
VGN = 0.7V
0.4
VGN = 1.5V
0.3
VGN = 0.7V
VGN = 1.5V
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 112. Group Delay vs. Frequency over VGN
Figure 109. Channel to Channel Amplitude Mismatch vs. Frequency over VGN
40
30
20
10
0
5
VGN = 0V
VGN = 0V
VGN = 0.7V
VGN = 1.5V
VGN = 0.7V
4
VGN = 1.5V
3
2
1
0
–10
–1
–2
–3
–4
–5
–20
–30
–40
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
FREQUENCY (GHz)
0.1
1
FREQUENCY (GHz)
Figure 110. Channel to Channel Phase Mismatch vs. Frequency over VGN
Figure 113. Group Delay Mismatch (Channel to Channel) vs. Frequency over
VGN
Rev. 0 | Page 27 of 33
ADRF6521
Data Sheet
90
80
70
60
50
40
30
20
208
206
204
202
200
198
196
194
192
190
188
VGN = 0V
10
0
VGN = 0.7V
VGN = 1.5V
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
FREQUENCY (GHz)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 117. Supply Current vs. Temperature over Multiple Devices
Figure 114. Channel to Channel Isolation vs. Frequency over VGN
1.8
1.8
0.25
0.25
CHANNEL 1
VGN
1.6
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.20
0.15
0.10
05
0.20
1.4
0.15
1.2
0.10
1.0
0.05
0.8
0
0
0.6
–05
–0.05
0.4
–0.10
–0.15
–0.20
–0.25
–0.10
0.2
–0.15
0
–0.20
CHANNEL 1
VGN
–0.2
600
–0.2
600
–0.25
–200
–100
0
100
200
300
400
500
–200
–100
0
100
200
300
400
500
TIME (ns)
TIME (ns)
Figure 115. VGA Step Response Time, Minimum to Maximum Gain
Figure 118. VGA Step Response Time, Maximum to Minimum Gain
0.5
0.15
0.10
05
0.5
0.15
0.10
05
CHANNEL 1
PWD
CHANNEL 1
PWD
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–0.5
–1.0
–1.5
–2.0
–2.5
0
0
–05
–05
–0.10
–0.10
–0.15
–0.15
–10
–5
0
5
10
15
20
25
30
–10
–5
0
5
10
15
20
25
30
TIME (ns)
TIME (ns)
Figure 116. Enable Response Time
Figure 119. Disable Response Time
Rev. 0 | Page 28 of 33
Data Sheet
ADRF6521
THEORY OF OPERATION
The ADRF6521 is a highly linear, dual channel VGA with a
−3 dB frequency response of 3.25 GHz. The ADRF6521 consists
of a matched pair of VGAs, each consisting of a voltage variable
attenuator (VVA) designed to have 21 dB of attenuation range
at room temperature (TA = 25°C), followed by an 18 dB
amplifier, producing a gain range from +18 dB to −3 dB.
OUTPUT COMMON-MODE VOLTAGE
The output common-mode voltage is set internally to (VPOS +
VNEG)/2, with an on-chip resister divider (see Figure 122). This
voltage can be adjusted 200 mV via the VOCM pin and the
ADRF6521 still maintains IMD2, IMD3, HD2, and HD3 of
−55 dBc or better. There is a 1 to 1 mapping between the control
voltage applied to VOCM and the output common-mode voltage.
VPOS
The output stage has the ability to change its common-mode
voltage and have a purposeful dc offset voltage. The output
common-mode voltage range and output dc offset voltage range
are adjustable up to 200 mV and 400 mV, respectively, while
still maintaining the high linearity outlined in Table 1. Larger
ranges are possible, but linearity degrades. Figure 120 shows the
simplified block diagram of a single channel.
2.5kΩ
OUTPUT
VOCM
COMMON-MODE
CONTROL CIRCUITRY
2.5kΩ
20dB
VVA
– +
VNEG
Figure 122. VOCM Simplified Circuit
18dB
OUTPUTS
INPUTS
VGN
– +
OUTPUT DC OFFSET CIRCUIT
The output dc offset on each channel of the ADRF6521 can be
independently nulled out to account for the small inherent dc
offsets of the VVA and amplifier. For applications such as
predistortion, the output dc offset voltage of each channel can
intentionally be increased up to 400 mV in addition to the
200 mV output common-mode range, while still maintaining
high linearity. Adjusting the output common-mode and the
output dc offset voltage more than a combined 400 mV from
the nominal voltage on any output pin causes the linearity to
degrade, possibly to IMDx and/or HDx levels worse than −55 dBc.
ANALOG
VOCM OFSx
GAIN CONTROL
45mV/dB
Figure 120. Simplified Functional Block Diagram for a Single Channel
The entire differential signal chain is dc-coupled. However it is
recommended to ac-couple the input signal paths. The gain setting
control for the two channels is a shared pin (VGN), ensuring close
matching of their magnitude and phase responses. The ADRF6521
PWD
is fully disabled by pulling
to the VNEG supply.
INPUT VVAs
The input VVAs are designed to have high linearity and excellent
log conformance. The VVAs have a differential input impedance
of 100 Ω and an attenuation range of 21 dB, which decreases
slightly over temperature. If the input must be dc-coupled, the
output common mode of the previous stage must match the
voltage on the VOCM pin. The topology of an input VGA, for
example, the VVA located at the input of the device, is such that
the noise figure degrades dB for dB as attenuation increases. The
VVA maintains its high linearity across its full range of attenuation.
The output dc offset voltage is defined as follows:
V
OFS_DC = VOPPx − VOPMx
where VOPPx and VOPMx are the dc voltages on the OPP1 and
OPM1 or the OPP2 and OPM2 output pins.
The output dc offset voltage is controlled via the OFS1 pin and
OFS2 pin, shown in Figure 120 and Figure 124 as a generic
OFSx pin. The output dc offset voltage is fundamentally caused
by injecting a differential current into the input of the amplifier.
The differential current consists of the following:
AMPLIFIERS
•
A reference current (IREF), which is added to both the
positive and negative legs of the differential path
The ADRF6521 amplifiers use the same core as the ADL5569.
The amplifiers have a low output impedance (<20 Ω), and the
RF to RG on-chip resistor ratio is approximately 8×, which creates
the 18 dB of differential voltage gain. The amplifiers are designed to
drive subsequent amplifier stages and are capable of high linearity
with 1.5 V p-p two-tone signals into 100 Ω differential loads.
•
A bipolar offset current (IOFS), which is added on one leg of
the differential path and subtracted from the other leg
The reference current is a static current, but the bipolar offset
current is controlled via the respective OFSx pins. Both currents
are injected between the 18 dB amplifier and VVA. Because the
offset current is bipolar, the output dc offset voltage goes up to
+400 mV or down to −400 m V. The nominal closed form
equation between the control voltage on the FLTx pins and the
output dc offset voltage is
R
F
A
=
= 8
R
V
F
R
G
R
G
ADL5569
CORE
FROM
VVA
OUTPUTS
R
G
V
DC_OFFSET_DIFF = 0.89 × VOFSx − 0.668 V
R
F
Figure 121. 18 dB Amplifier for a Single Channel
Rev. 0 | Page 29 of 33
ADRF6521
Data Sheet
DC Offset Loop High-Pass Corner
The output dc offset circuits are filtered on each channel via the
FLT1 and FLT2 pins, for Channel 1 and Channel 2, respectively.
Connect both pins to the negative supply via a 1 µF capacitor.
There is an on-chip capacitance of 35 pF on each FLTx node.
The ADRF6521 has dc offset loops that null any signal below
their low-pass frequency corner, which is set by a combination
of the internal 35 pF capacitor plus any external capacitor
decoupled to VNEG from OFSx.
GAIN CONTROL INTERFACE
Although the dc offset loops have a low-pass response, the signal
paths show a high-pass response because the loops null any low
frequency signal below their low-pass corner. The following
equation shows the relationship between the high-pass corner
observed on the signal paths and the value of the external
The ADRF6521 has a linear-in-dB gain control interface. The
gain control slope is maintained at 22.2 dB/V over temperature,
supply, and process as gain varies from 250 mV to 1200 mV.
The gain function is given by
Gain (dB) = 22.2 × VVGN – 8.5
capacitor decoupled to VNEG, which is called COFS
HP (Hz) = 60/(COFS (µF) + 35 × 10−6)
With COFS = 1 µF, the high-pass corner in Hz is calculated as:
HP (Hz) = 60/(1 + 35 × 10−6) = 60 Hz
:
where VVGN is the voltage on the VGN gain pin in volts.
f
The gain control voltage range is from 0 V to 1.5 V, with respect
to analog ground.
f
POWER-DOWN FUNCTION
The feedback loop shown in Figure 124 creates the output dc
offset voltage. The differential to single-ended amplifier samples
the differential output, converts the signal into single-ended mode,
and averages the signal with a capacitor connected to VNEG.
This averaged version of the output is compared to the dc voltage
applied to the OFSx pin(s) with the transconductance amplifier
(gm). The output differential current of the gm stage is injected
between the RF and RG resistors of the 18 dB amplifier. The
feedback loop forces the differential current of the gm amplifier to
increase or decrease until the averaged voltage from the differential
to single-ended amplifier is equal to the applied OFSx voltage.
This differential current injected at the input of the amplifier
creates an intentional dc offset voltage at the input, which is
then amplified and seen on the output pins, OPPx and OPMx.
PWD
The power-down function is accomplished via the
default, the device is enabled via the resistive divider shown in
PWD
pin. By
Figure 123. Assert the
pin to the same potential as VNEG
to reduce the current consumption to roughly 25 mA. Do not
PWD
apply a voltage more than VNEG + 3.3 V on the
Higher voltages may cause damage to the device.
VPOS
pin.
20kΩ
POWER-DOWN
PWD
CONTROL CIRCUITRY
30kΩ
VNEG
Figure 123. Simplified Power Down Interface
FLTx VNEG
DIFFERENTIAL TO
SINGLE-ENDED
AMPLIFIER
35pF
OFSx
5kΩ
gm
I
± I
I
± (–I
)
R
REF
OFS
REF
OFS
F
R
R
G
FROM
VVA
ADL5569
CORE
OUTPUTS
G
R
F
Figure 124. Output DC Offset Circuit for a Single Channel
Rev. 0 | Page 30 of 33
Data Sheet
ADRF6521
APPLICATIONS INFORMATION
BASIC CONNECTIONS
OUTPUT SIGNAL PATH
Figure 125 shows the basic connections for a typical ADRF6521
application.
The low impedance (20 Ω) output buffers are designed to drive
a 100 Ω impedance load. However, the buffers can drive larger
resistive loads. The output pins (OPP1, OPM1, OPP2, and OPM2)
sit at a nominal output common-mode voltage of (VPOS +
VNEG)/2 V. The outputs can be dc-coupled or ac-coupled.
However, dc coupling is required to take advantage of the output
dc offset voltage functionality. To change the output common-
mode voltage, the user must apply a dc voltage to the VOCM
pin different than (VPOS + VNEG)/2 V. Left open, VOCM
defaults to (VPOS + VNEG)/2 V. To change the output dc offset
voltage, the user must apply a voltage to the OFS1 and OFS2
pins different than 0.75 V. Left open, these pins are pulled to
ground via an on-chip 5 kΩ resistor, which creates an
SUPPLY DECOUPLING
Decouple each supply pin, VPOS and VNEG, to ground with at
least one low inductance, surface-mount ceramic capacitor of
0.1 µF placed as close as possible to the ADRF6521 device.
INPUT SIGNAL PATH
Each signal path has an input VGA, accessed through the INP1,
INM1, INP2, and INM2 pins, which sets a differential input
impedance of 100 Ω.
The inputs can be dc-coupled or ac-coupled, but ac coupling is
strongly recommended. There is no mechanism to change the
common-mode voltage. Therefore, if the user wants to use dc
coupling, the common-mode voltage of the previous stage must
match the ADRF6521 input common-mode voltage of (VPOS +
VNEG)/2 V.
approximately −670 mV dc output offset.
100pF
VNEG
0.1µF
GAIN
0.1µF
0.1µF
100pF
100pF
0.1µF
VPOS
OFS1
100pF
0.1µF
20
19
18
17
16
INPUT1 (–)
INPUT1 (+)
OUTPUT1 (–)
OUTPUT1 (+)
1
2
3
4
5
OPM1 15
INM1
INP1
14
13
OPP1
VOCM
VOCM
COMM
INP2
ADRF6521
0.1µF
100pF
INPUT2 (+)
INPUT2 (–)
OPP2 12
11
OUTPUT2 (+)
OUTPUT2 (–)
OPM2
INM2
6
7
8
9
10
VPOS
PWD
OFS2
0.1µF
100pF
100pF
100pF
0.1µF
0.1µF
0.1µF
VNEG
100pF
0.1µF
Figure 125. Basic Connections
Rev. 0 | Page 31 of 33
ADRF6521
Data Sheet
ENABLE AND DISABLE FUNCTION
SINGLE-SUPPLY OPERATION
PWD
The ADRF6521 can operate on a 5 V single supply. Connect
VNEG to analog ground. The output common-mode voltage
defaults to 2.5 V in this configuration. The nominal range of
200 mV still applies. A larger range is possible, however,
linearity performance degrades.
To enable the ADRF6521, leave the
PWD
pin open or pull this
pin to VNEG + 3.0 V. Driving the
pin to VNEG disables
the device, reducing the current consumption to approximately
25 mA at room temperature.
GAIN PIN (VGN) DECOUPLING
DUAL-SUPPLY OPERATION
The ADRF6521 has one analog gain control pin, VGN. The gain
changes when an applied VGN voltage is between 0 V and 1.5 V.
Maximum voltage on the VGN pin is equal to the voltage applied
to VPOS. Use at least one low inductance, surface-mount
ceramic capacitor with a value of 0.1 µF and one 1000 pF in
parallel to ground on the gain pin (VGN) to decouple to ground.
Apply a nominal supply voltage of +2.5 V to the VPOS supply
pin, and −2.5 V to the VNEG supply pin. This setup yields a
nominal output common-mode voltage of 0 V, and the output
dc offset voltage moves above and below ground according to
what voltage is applied to the OFSx pins.
When using a dual supply, ensure the following supply
constraints:
OUTPUT IMPEDANCE MATCHING
The ADRF6521 natively has a low differential output impedance
of ≤16 Ω. Depending on the PCB design of the user and the S22
requirements, matching the output impedance to 100 Ω differential
may be desirable. To achieve a match looking towards the output
pins, place a pair of 43 Ω series resistors as close as possible to
the output pins (OPP1, OPM1, OPP2, and OPM2).
•
•
•
4 V ≤ (VPOS − VNEG) ≤ 5 V.
VNEG ≤ COMM ≤ VPOS
VPOS ≥ 2.5 V
AVOIDING LATCH-UP
To avoid latch-up when the device is operational or when the
device is powering up, do not apply a voltage greater than the
following:
The installation of these 43 Ω resistors decreases the voltage level
of the signal by roughly 6 dB, and thus decreases the maximum
gain of the VGA to 12 dB. This loss of signal level is usually
acceptable because of the high linearity of the ADRF6521. That
is, the ADRF6521 can operate at twice the output signal level
(with respect to no matching resistors), and still maintain
−55 dBc IMD2 and IMD3 and HD2 and HD3 levels or better.
•
1.5 V (relative to ground) to the control pins (VGN, OFS1,
and OFS2).
•
(VVPOS + VVNEG)/2 1 V to the control pin VOCM
If the RF input must be dc coupled, the common-mode voltage
must be the same as the VOCM pin voltage, which must be
limited to (VPOS + VNEG)/2 0.2 V. If while powered down
and dc coupled a dc voltage with a magnitude greater than
(VPOS + VNEG)/2 0.2 V is applied, this dc voltage must
return within the common-mode limit before powering up the
ADRF6521.
Note that when using series matching resistors, the output dc
offset voltage is also reduced by the same amount as the RF
signal level.
If a full 100 Ω match is not required and a greater than 12 dB
gain value is more important, the user can decrease the series
resistor value until an optimum trade-off between the gain and
the output match is found.
Rev. 0 | Page 32 of 33
Data Sheet
ADRF6521
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.25
0.20
0.15
3.10
3.00 SQ
2.90
0.876
0.776
0.676
20
PIN 1
IN DICATOR AR EA
(SEE DETAIL A)
PIN 1
INDICATOR
AREA
OP TIO NS
16
1
15
0.40
BSC
1.175
1.075
0.975
EXPOSED
PAD
11
5
10
6
0.40
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.35
0.30
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.050 MAX
0.035 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.152 REF
SEATING
PLANE
Figure 126. 20-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 Package Height
(CP-20-19)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF6521ACPZ
ADRF6521ACPZ-R7
ADRF6521-EVALZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-20-19
CP-20-19
20-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Lead Frame Chip Scale Package [LFCSP], 7”Tape and Reel
Evaluation Board
1 Z = RoHS Compliant Parts.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D24784-11/20(0)
Rev. 0 | Page 33 of 33
相关型号：
©2020 ICPDF网 联系我们和版权申明