ADRF6601-EVALZ_技术文档

750 MHz to 1160 MHz Rx Mixer with

Integrated Fractional-N PLL and VCO

ADRF6601

The PLL reference input can support input frequencies from

12 MHz to 160 MHz. The PFD output controls a charge pump

whose output drives an off-chip loop filter.

FEATURES

Rx mixer with integrated fractional-N PLL

RF input frequency range: 300 MHz to 2500 MHz

Internal LO frequency range: 750 MHz to 1160 MHz

Input P1dB: 14.2 dBm

Input IP3: 30.0 dBm

IIP3 optimization via external pin

SSB noise figure

The loop filter output is then applied to an integrated VCO. The

VCO output at 2 × f_LOis applied to an LO divider, as well as to a

programmable PLL divider. The programmable PLL divider is

controlled by a Σ-Δ modulator (SDM). The modulus of the SDM

can be programmed from 1 to 2047.

IP3SET pin open: 13.0 dB

IP3SET pin at 3.3 V: 13.8 dB

The active mixer converts the single-ended 50 Ω RF input to

a 200 ꢀ differential IF output. The IF output can operate up

to 500 MHz.

Voltage conversion gain: 6.7 dB

Matched 200 Ω IF output impedance

IF 3 dB bandwidth: 500 MHz

Programmable via 3-wire SPI interface

40-lead, 6 mm × 6 mm LFCSP

The ADRF6601 is fabricated using an advanced silicon-germanium

BiCMOS process. It is available in a 40-lead, RoHS-compliant,

6 mm × 6 mm LFCSP with an exposed paddle. Performance is

specified over the −40°C to +85°C temperature range.

APPLICATIONS

Table 1.

Cellular base stations

Internal

LO Range

3 dB RF Input

Balun Range

1 dB RF Input

Balun Range

GENERAL DESCRIPTION

Part No.

ADRF6601

750 MHz to

1160 MHz

1550 MHz to 1000 MHz to

2150 MHz 3100 MHz

2100 MHz to 1100 MHz to

300 MHz to

2500 MHz

450 MHz to

1600 MHz

1350 MHz to

2750 MHz

1450 MHz to

2850 MHz

The ADRF6601 is a high dynamic range active mixer with an

integrated fractional-N phase-locked loop (PLL) and a voltage-

controlled oscillator (VCO) for internal mixer LO generation.

ADRF6602

ADRF6603

Along with the ADRF6602 and the ADRF6603, the ADRF6601

forms a family of integrated PLL/mixers. The ADRF6601 covers

the frequency range of 750 MHz to 1160 MHz.

2600 MHz

3200 MHz

FUNCTIONAL BLOCK DIAGRAM

VCC1

1

VCC2 VCC_LO VCC_MIX VCC_V2I VCC_LO

NC NC

10

17

22

27

34

32

33

36

LODRV_EN

LON 37

38

ADRF6601

3.3V

LDO

2

9

DECL3P3

INTERNAL LO RANGE

750MHz TO 1160MHz

BUFFER

2.5V

LDO

DECL2P5

DECLVCO

LOP

VCO

LDO

PLL_EN 16

DIV

2:1

40

BY

4, 2, 1

INTEGER

REG

FRACTION

REG

MUX

12

DATA

MODULUS

SPI

13

14

CLK

LE

INTERFACE

26

29

RF

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

IN

VCO

CORE

IP3SET

×2

N COUNTER

21 TO 123

PRESCALER

÷2

6

8

REF_IN

MUX

÷2

CHARGE PUMP

250µA,

500µA (DEFAULT),

–

+

PHASE

FREQUENCY

DETECTOR

TEMP

SENSOR

÷4

750µA,

1000µA

5

MUXOUT

4

7

11 15 20 21 23 24 25 28 30 31 35

39

18 19

3

R

CP VTUNE IFP IFN

SET

GND

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADRF6601

TABLE OF CONTENTS

Features .............................................................................................. 1

Register 4—PLL Charge Pump, PFD, and Reference Path

Control (Default: 0x0AA7E4)................................................... 13

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

RF Specifications .......................................................................... 3

Synthesizer/PLL Specifications................................................... 4

Logic Input and Power Specifications ....................................... 5

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Register Structure ........................................................................... 11

Register 0—Integer Divide Control (Default: 0x0001C0)..... 11

Register 1—Modulus Divide Control (Default: 0x003001).. 11

Register 2—Fractional Divide Control (Default: 0x001802) 12

Register 5—PLL Enable and LO Path Control (Default:

0x0000E5).................................................................................... 14

Register 6—VCO Control and VCO Enable (Default:

0x1E2106).................................................................................... 14

Register 7—Mixer Bias Enable and External VCO Enable

(Default: 0x000007).................................................................... 14

Theory of Operation ...................................................................... 15

Programming the ADRF6601................................................... 15

Initialization Sequence .............................................................. 15

LO Selection Logic ..................................................................... 16

Applications Information.............................................................. 17

Basic Connections for Operation............................................. 17

Evaluation Board ............................................................................ 18

Evaluation Board Control Software......................................... 18

Schematics and Artwork ........................................................... 20

Evaluation Board Configuration Options............................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Register 3—Σ-Δ Modulator Dither Control (Default:

0x10000B).................................................................................... 12

REVISION HISTORY

4/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADRF6601

SPECIFICATIONS

RF SPECIFICATIONS

VCCx = 5 V; ambient temperature (T_A) = 25°C; f_REF= 38.4 MHz; f_PFD= 38.4 MHz; high-side LO injection; f_IF= 140 MHz; IIP3 optimized

using CDAC = 0x1 and IP3SET = 3.3 V, unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

750

300

Typ

Max

1160

2500

Unit

MHz

INTERNAL LO FREQUENCY RANGE

RF INPUT FREQUENCY RANGE

RF INPUT AT 610 MHz

Iinpt Retpꢂi Loss

3 ꢀd RF ꢁinpt ꢂaige

Relatꢁve to 50 Ω (cai be ꢁmnꢂoveꢀ wꢁth exteꢂial match)

−14

14.3

62

32.5

13.0

12.2

−51

ꢀd

Iinpt P1ꢀd

ꢀdm

ꢀd

ꢀdm

Secoiꢀ-Oꢂꢀeꢂ Iiteꢂcent (IIP2)

Thꢁꢂꢀ-Oꢂꢀeꢂ Iiteꢂcent (IIP3)

Sꢁigle-Sꢁꢀe daiꢀ Noꢁse Fꢁgpꢂe

−5 ꢀdm each toie (10 MHz snacꢁig betweei toies)

IP3SET = 3.3 V

IP3SET = onei

At 1× LO fꢂeqpeicy, 50 Ω teꢂmꢁiatꢁoi at the RF noꢂt

LO-to-IF Leakage

RF INPUT AT 910 MHz

Iinpt Retpꢂi Loss

Iinpt P1ꢀd

Secoiꢀ-Oꢂꢀeꢂ Iiteꢂcent (IIP2)

Thꢁꢂꢀ-Oꢂꢀeꢂ Iiteꢂcent (IIP3)

Sꢁigle-Sꢁꢀe daiꢀ Noꢁse Fꢁgpꢂe

Relatꢁve to 50 Ω (cai be ꢁmnꢂoveꢀ wꢁth exteꢂial match)

−18

14.3

59

31.0

14.0

13.1

−51

ꢀd

ꢀdm

ꢀd

ꢀdm

−5 ꢀdm each toie (10 MHz snacꢁig betweei toies)

IP3SET = 3.3 V

IP3SET = onei

At 1× LO fꢂeqpeicy, 50 Ω teꢂmꢁiatꢁoi at the RF noꢂt

Low-sꢁꢀe ꢁijectꢁoi

LO-to-IF Leakage

RF INPUT AT 1020 MHz

Iinpt Retpꢂi Loss

Iinpt P1ꢀd

Secoiꢀ-Oꢂꢀeꢂ Iiteꢂcent (IIP2)

Thꢁꢂꢀ-Oꢂꢀeꢂ Iiteꢂcent (IIP3)

Sꢁigle-Sꢁꢀe daiꢀ Noꢁse Fꢁgpꢂe

Relatꢁve to 50 Ω (cai be ꢁmnꢂoveꢀ wꢁth exteꢂial match)

−16

14.3

64

31.5

14.5

13.5

−45

ꢀd

ꢀdm

ꢀd

ꢀdm

−5 ꢀdm each toie (10 MHz snacꢁig betweei toies)

IP3SET = 3.3 V

IP3SET = onei

At 1× LO fꢂeqpeicy, 50 Ω teꢂmꢁiatꢁoi at the RF noꢂt

LO-to-IF Leakage

IF OUTPUT

Voltage Coiveꢂsꢁoi Gaꢁi

IF daiꢀwꢁꢀth

Optnpt Commoi-Moꢀe Voltage

Gaꢁi Flatiess

Gaꢁi Vaꢂꢁatꢁoi

Optnpt Swꢁig

Optnpt Retpꢂi Loss

LO INPUT/OUTPUT (LOP, LON)

Fꢂeqpeicy Raige

Optnpt Level (LO as Optnpt)

Iinpt Level (LO as Iinpt)

Iinpt Imneꢀaice

Dꢁffeꢂeitꢁal 200 Ω loaꢀ

Small-sꢁgial 3 ꢀd baiꢀwꢁꢀth

Exteꢂial npll-pn balpi oꢂ ꢁiꢀpctoꢂs ꢂeqpꢁꢂeꢀ

Oveꢂ fꢂeqpeicy ꢂaige, aiy 5 MHz/50 MHz

Oveꢂ fpll temneꢂatpꢂe ꢂaige

6.7

500

5

0.2/1.0

1.0

2

ꢀd

MHz

V

ꢀd

Dꢁffeꢂeitꢁal 200 Ω loaꢀ

Relatꢁve to 200 Ω

V n-n

ꢀd

−15

Exteꢂially annlꢁeꢀ 1× LO ꢁinpt, ꢁiteꢂial PLL ꢀꢁsableꢀ

250

6000

MHz

ꢀdm

Ω

1× LO ꢁito a 50 Ω loaꢀ, LO optnpt bpffeꢂ eiableꢀ

−5.5

6

50

Rev. 0 | Page 3 of 24

ADRF6601

SYNTHESIZER/PLL SPECIFICATIONS

VCCx = 5 V; ambient temperature (T_A) = 25°C; f_REF= 153.6 MHz; f_REFpower = 4 dBm; f_PFD= 38.4 MHz; high-side LO injection;

f_IF= 140 MHz; IIP3 optimized using CDAC = 0x1 and IP3SET = 3.3 V, unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SYNTHESIZER SPECIFICATIONS

Fꢂeqpeicy Raige

Fꢁgpꢂe of Meꢂꢁt¹

Syithesꢁzeꢂ snecꢁfꢁcatꢁois ꢂefeꢂeiceꢀ to 1× LO

Iiteꢂially geieꢂateꢀ LO

f_REFnoweꢂ = 0 ꢀdm

750

1160

MHz

ꢀdc/Hz

−221.4

Refeꢂeice Snpꢂs

f_REF= 153.6 MHz

f_REF/4

f_REF/2

f_REF

> f_REF

−107

−84

ꢀdc

−88

PHASE NOISE

f_LO= 750 MHz to 1160 MHz, f_PFD= 38.4 MHz

1 kHz to 10 kHz offset

100 kHz offset

−102

−108.6

−127

−135

−147

−151

−153

0.13

ꢀdc/Hz

°ꢂms

500 kHz offset

1 MHz offset

5 MHz offset

10 MHz offset

20 MHz offset

1 kHz to 40 MHz ꢁitegꢂatꢁoi baiꢀwꢁꢀth

Iitegꢂateꢀ Phase Noꢁse

PFD Fꢂeqpeicy

20

12

40

MHz

REFERENCE CHARACTERISTICS

REF_IN Iinpt Fꢂeqpeicy

REF_IN Iinpt Canacꢁtaice

MUXOUT Optnpt Level

REF_IN, MUXOUT nꢁis

160

0.25

MHz

nF

V

4

V_OL(lock ꢀetect optnpt selecteꢀ)

V_OH(lock ꢀetect optnpt selecteꢀ)

2.7

V

MUXOUT Dpty Cycle

CHARGE PUMP

50

%

Ppmn Cpꢂꢂeit

Optnpt Comnlꢁaice Raige

Pꢂogꢂammable to 250 μA, 500 μA, 750 μA, 1 mA

500

ꢃA

V

1

2.8

¹The fꢁgpꢂe of meꢂꢁt (FOM) ꢁs comnpteꢀ as nhase ioꢁse (ꢀdc/Hz) – 10log10(f_PFD) – 20log10(f_LO/f_PFD). The FOM was measpꢂeꢀ acꢂoss the fpll LO ꢂaige, wꢁth f_REF= 80 MHz,

_REFnoweꢂ = 10 ꢀdm (500 V/ꢃs slew ꢂate) wꢁth a 40 MHz f_PFD. The FOM was comnpteꢀ at 50 kHz offset.

f

Rev. 0 | Page 4 of 24

ADRF6601

LOGIC INPUT AND POWER SPECIFICATIONS

VCCx = 5 V; ambient temperature (T_A) = 25°C; f_REF= 38.4 MHz; f_PFD= 38.4 MHz; high-side LO injection; f_IF= 140 MHz; IIP3 optimized

using CDAC = 0x1 and IP3SET = 3.3 V, unless otherwise noted.

Table 4.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC INPUTS

CLK, DATA, LE

Iinpt Hꢁgh Voltage, V_INH

Iinpt Low Voltage, V_INL

Iinpt Cpꢂꢂeit, I_INH/I_INL

Iinpt Canacꢁtaice, C_IN

POWER SUPPLIES

Voltage Raige

1.4

0

3.3

0.7

V

ꢃA

nF

0.1

5

VCC1, VCC2, VCC_LO, VCC_MIX, aiꢀ VCC_V2I nꢁis

PLL oily

Exteꢂial LO moꢀe (ꢁiteꢂial PLL ꢀꢁsableꢀ,

IP3SET nꢁi = 3.3 V)

4.75

5

101

179

5.25

V

mA

Spnnly Cpꢂꢂeit

Iiteꢂial LO moꢀe (ꢁiteꢂial PLL eiableꢀ,

IP3SET nꢁi = 3.3 V)

Poweꢂ-ꢀowi moꢀe

280

30

mA

TIMING CHARACTERISTICS

VCC2 = 5 V 5ꢁ.

Table 5.

Parameter

Limit

20

10

25

10

20

Unit

Description

t₁

t₂

t₃

t₄

t₅

t₆

t₇

is mꢁi

LE setpn tꢁme

DATA to CLK setpn tꢁme

DATA to CLK holꢀ tꢁme

CLK hꢁgh ꢀpꢂatꢁoi

CLK low ꢀpꢂatꢁoi

CLK to LE setpn tꢁme

LE nplse wꢁꢀth

Timing Diagram

t₄

t₅

CLK

t₂

t₃

DB2

(CONTROL BIT C3)

DB1

DB0 (LSB)

(CONTROL BIT C1)

DB23 (MSB)

t₁

DB22

DATA

LE

(CONTROL BIT C2)

t₇

t₆

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 24

ADRF6601

ABSOLUTE MAXIMUM RATINGS

Table 6.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

Spnnly Voltage, VCC1, VCC2, VCC_LO, −0.5 V to +5.5 V

VCC_MIX, VCC_V2I

Dꢁgꢁtal I/O, CLK, DATA, LE

IFP, IFN

RF_IN

−0.3 V to +3.6 V

−0.3 V to VCC_V2I + 0.3 V

18 ꢀdm

θ_JA(Exnoseꢀ Paꢀꢀle Solꢀeꢂeꢀ Dowi) 35°C/W

ESD CAUTION

Maxꢁmpm Jpictꢁoi Temneꢂatpꢂe

Oneꢂatꢁig Temneꢂatpꢂe Raige

Stoꢂage Temneꢂatpꢂe Raige

150°C

−40°C to +85°C

−65°C to +150°C

Rev. 0 | Page 6 of 24

ADRF6601

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

VCC1

DECL3P3

CP

1

2

30 GND

INDICATOR

29 IP3SET

28 GND

3

GND

27 VCC_V2I

4

ADRF6601

R

RF

5

26

25

SET

IN

REF_IN

6

GND

TOP VIEW

7

24 GND

GND

MUXOUT

DECL2P5

VCC2

(Not to Scale)

8

23 GND

9

22 VCC_MIX

21

10

GND

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A

LOW IMPEDANCE GROUND PLANE.

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic Description

1

VCC1

Poweꢂ Spnnly foꢂ the 3.3 V LDO. Poweꢂ spnnly voltage ꢂaige ꢁs 4.75 V to 5.25 V. Each noweꢂ spnnly nꢁi

shoplꢀ be ꢀecopnleꢀ wꢁth a 100 nF canacꢁtoꢂ aiꢀ a 0.1 ꢃF canacꢁtoꢂ locateꢀ close to the nꢁi.

2

3

DECL3P3

CP

Decopnlꢁig Noꢀe foꢂ the 3.3 V LDO. Coiiect a 0.1 ꢃF canacꢁtoꢂ betweei thꢁs nꢁi aiꢀ gꢂopiꢀ.

Chaꢂge Ppmn Optnpt Pꢁi. Coiiect to VTUNE thꢂopgh the loon fꢁlteꢂ.

Gꢂopiꢀ. Coiiect these nꢁis to a low ꢁmneꢀaice gꢂopiꢀ nlaie.

4, 7, 11, 15, 20, GND

21, 23, 24, 25,

28, 30, 31, 35

5

R_SET

Chaꢂge Ppmn Cpꢂꢂeit. The iomꢁial chaꢂge npmn cpꢂꢂeit cai be set to 250 ꢃA, 500 ꢃA, 750 ꢃA, oꢂ 1 mA

psꢁig dꢁts[Dd11:Dd10] ꢁi Regꢁsteꢂ 4 aiꢀ by settꢁig dꢁt Dd18 to 0 (ꢁiteꢂial ꢂefeꢂeice cpꢂꢂeit). Ii thꢁs moꢀe,

io exteꢂial R_SETꢁs ꢂeqpꢁꢂeꢀ. If dꢁt Dd18 ꢁs set to 1, the fopꢂ iomꢁial chaꢂge npmn cpꢂꢂeits (I_NOMINAL) cai be

exteꢂially aꢀjpsteꢀ accoꢂꢀꢁig to the followꢁig eqpatꢁoi:

217.4 × I

⎛

⎜

⎝

⎞

⎟

⎠

CP

R_SET

=

− 37.8Ω

I_NOMINAL

6

8

REF_IN

MUXOUT

Refeꢂeice Iinpt. Nomꢁial ꢁinpt level ꢁs 1 V n-n. Iinpt ꢂaige ꢁs 12 MHz to 160 MHz.

Mpltꢁnlexeꢂ Optnpt. Thꢁs optnpt cai be nꢂogꢂammeꢀ to nꢂovꢁꢀe the ꢂefeꢂeice optnpt sꢁgial oꢂ the lock ꢀetect

sꢁgial. The optnpt ꢁs selecteꢀ by nꢂogꢂammꢁig dꢁts[Dd23:Dd21] ꢁi Regꢁsteꢂ 4.

9

10

DECL2P5

VCC2

Decopnlꢁig Noꢀe foꢂ the 2.5 V LDO. Coiiect a 0.1 ꢃF canacꢁtoꢂ betweei thꢁs nꢁi aiꢀ gꢂopiꢀ.

Poweꢂ Spnnly foꢂ the 2.5 V LDO. Poweꢂ spnnly voltage ꢂaige ꢁs 4.75 V to 5.25 V. Each noweꢂ spnnly nꢁi

shoplꢀ be ꢀecopnleꢀ wꢁth a 100 nF canacꢁtoꢂ aiꢀ a 0.1 ꢃF canacꢁtoꢂ locateꢀ close to the nꢁi.

12

13

DATA

CLK

Seꢂꢁal Data Iinpt. The seꢂꢁal ꢀata ꢁinpt ꢁs loaꢀeꢀ MSd fꢁꢂst; the thꢂee LSds aꢂe the coitꢂol bꢁts.

Seꢂꢁal Clock Iinpt. The seꢂꢁal clock ꢁinpt ꢁs pseꢀ to clock ꢁi the seꢂꢁal ꢀata to the ꢂegꢁsteꢂs. The ꢀata ꢁs latcheꢀ

ꢁito the 24-bꢁt shꢁft ꢂegꢁsteꢂ oi the CLK ꢂꢁsꢁig eꢀge. Maxꢁmpm clock fꢂeqpeicy ꢁs 20 MHz.

14

16

LE

Loaꢀ Eiable. Whei the LE ꢁinpt nꢁi goes hꢁgh, the ꢀata stoꢂeꢀ ꢁi the shꢁft ꢂegꢁsteꢂs ꢁs loaꢀeꢀ ꢁito oie of the

eꢁght ꢂegꢁsteꢂs. The ꢂelevait latch ꢁs selecteꢀ by the thꢂee coitꢂol bꢁts of the 24-bꢁt woꢂꢀ.

PLL Eiable. Swꢁtch betweei ꢁiteꢂial PLL aiꢀ exteꢂial LO ꢁinpt. Whei thꢁs nꢁi ꢁs logꢁc hꢁgh, the mꢁxeꢂ LO ꢁs

aptomatꢁcally swꢁtcheꢀ to the ꢁiteꢂial PLL aiꢀ the ꢁiteꢂial PLL ꢁs noweꢂeꢀ pn. Whei thꢁs nꢁi ꢁs logꢁc low, the

ꢁiteꢂial PLL ꢁs noweꢂeꢀ ꢀowi aiꢀ the exteꢂial LO ꢁinpt ꢁs ꢂopteꢀ to the mꢁxeꢂ LO ꢁinpts. The SPI cai also be

pseꢀ to swꢁtch moꢀes.

PLL_EN

17, 34

VCC_LO

Poweꢂ Spnnly. Poweꢂ spnnly voltage ꢂaige ꢁs 4.75 V to 5.25 V. Each noweꢂ spnnly nꢁi shoplꢀ be ꢀecopnleꢀ

wꢁth a 100 nF canacꢁtoꢂ aiꢀ a 0.1 ꢃF canacꢁtoꢂ locateꢀ close to the nꢁi.

18, 19

22

IFP, IFN

VCC_MIX

Mꢁxeꢂ IF Optnpts. These optnpts shoplꢀ be nplleꢀ to VCC wꢁth RF chokes.

Poweꢂ Spnnly. Poweꢂ spnnly voltage ꢂaige ꢁs 4.75 V to 5.25 V. Each noweꢂ spnnly nꢁi shoplꢀ be ꢀecopnleꢀ

wꢁth a 100 nF canacꢁtoꢂ aiꢀ a 0.1 ꢃF canacꢁtoꢂ locateꢀ close to the nꢁi.

26

RF_IN

RF Iinpt (Sꢁigle-Eiꢀeꢀ, 50 Ω).

Rev. 0 | Page 7 of 24

ADRF6601

Pin No.

Mnemonic Description

27

VCC_V2I

Poweꢂ Spnnly. Poweꢂ spnnly voltage ꢂaige ꢁs 4.75 V to 5.25 V. Each noweꢂ spnnly nꢁi shoplꢀ be ꢀecopnleꢀ

wꢁth a 100 nF canacꢁtoꢂ aiꢀ a 0.1 ꢃF canacꢁtoꢂ locateꢀ close to the nꢁi.

Coiiect a ꢂesꢁstoꢂ fꢂom thꢁs nꢁi to a +5 V spnnly to aꢀjpst IIP3. Noꢂmally leave onei.

No Coiiectꢁoi.

29

32, 33

36

IP3SET

NC

LODRV_EN LO Dꢂꢁveꢂ Eiable. Togetheꢂ wꢁth Pꢁi 16 (PLL_EN), thꢁs ꢀꢁgꢁtal ꢁinpt nꢁi ꢀeteꢂmꢁies whetheꢂ the LOP aiꢀ LON

nꢁis oneꢂate as ꢁinpts oꢂ optnpts. LOP aiꢀ LON become ꢁinpts ꢁf the PLL_EN nꢁi ꢁs low oꢂ ꢁf the PLL_EN nꢁi ꢁs

set hꢁgh wꢁth the PLEN bꢁt (Dd6 ꢁi Regꢁsteꢂ 5) set to 0. LOP aiꢀ LON become optnpts ꢁf eꢁtheꢂ the LODRV_EN nꢁi

oꢂ the LDRV bꢁt (Dd3 ꢁi Regꢁsteꢂ 5) ꢁs set to 1 whꢁle the PLL_EN nꢁi ꢁs set hꢁgh. The exteꢂial LO ꢀꢂꢁve fꢂeqpeicy

mpst be 1× LO. Thꢁs nꢁi shoplꢀ iot be left floatꢁig.

37, 38

39

LON, LOP

Local Oscꢁllatoꢂ Iinpt/Optnpt. The ꢁiteꢂially geieꢂateꢀ 1× LO ꢁs avaꢁlable oi these nꢁis. Whei ꢁiteꢂial LO

geieꢂatꢁoi ꢁs ꢀꢁsableꢀ, ai exteꢂial 1× LO cai be annlꢁeꢀ to these nꢁis.

VCO Coitꢂol Voltage Iinpt. Thꢁs nꢁi ꢁs ꢀꢂꢁvei by the optnpt of the loon fꢁlteꢂ. The iomꢁial ꢁinpt voltage ꢂaige

oi thꢁs nꢁi ꢁs 1.5 V to 2.5 V.

VTUNE

40

DECLVCO

EPAD

Decopnlꢁig Noꢀe foꢂ the VCO LDO. Coiiect a 100 nF canacꢁtoꢂ aiꢀ a 10 ꢃF canacꢁtoꢂ betweei thꢁs nꢁi aiꢀ

gꢂopiꢀ.

Exnoseꢀ Paꢀꢀle. The exnoseꢀ naꢀꢀle shoplꢀ be solꢀeꢂeꢀ to a low ꢁmneꢀaice gꢂopiꢀ nlaie.

EP

Rev. 0 | Page 8 of 24

ADRF6601

TYPICAL PERFORMANCE CHARACTERISTICS

CDAC = 0x1, IP3SET = 3.3 V, internally generated LO, RF_IN= −10 dBm, f_IF= 140 MHz, unless otherwise noted.

45

40

35

30

25

20

15

10

5

4

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

3

2

1

0

–1

–2

–3

–4

–5

750

800

850

900

950

1000 1050 1100 1150

750

800

850

900

950

1000 1050 1100 1150

LO FREQUENCY (MHz)

Figure 4. Gain vs. LO Frequency

Figure 7. IIP3 vs. LO Frequency, RF_IN= −5 dBm

90

80

70

20

18

16

14

12

10

8

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

60

50

40

30

6

4

2

0

750

800

850

900

950

1000 1050 1100 1150

800

850

900

950

1000 1050 1100 1150

LO FREQUENCY (MHz)

Figure 8. IP1dB vs. LO Frequency

Figure 5. IIP2 vs. LO Frequency, RF_IN= −5 dBm

0

–10

–20

–30

–40

–50

–60

20

19

18

17

16

15

14

13

12

11

10

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

750

800

850

900

950

1000 1050 1100 1150

750

800

850

900

950

1000 1050 1100 1150

LO FREQUENCY (MHz)

Figure 6. Noise Figure vs. LO Frequency

Figure 9. LO-to-IF Leakage vs. LO Frequency, LO Output Turned Off,

50 Ω Termination at RF Port

Rev. 0 | Page 9 of 24

ADRF6601

Phase noise measurements made at IF output, unless otherwise noted.

–80

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

–80

–90

LO = 752MHz

LO = 848MHz

LO = 953.6MHz

LO = 1049.6MHz

LO = 1155.2MHz

1kHz OFFSET

–90

100kHz OFFSET

–100

–110

–120

–130

–140

–150

–160

–170

–100

–110

–120

–130

–140

–150

–160

10kHz OFFSET

1MHz OFFSET

10MHz OFFSET

INTERGRATED PHASE NOISE

750

800

850

900

950

1000 1050 1100 1150

1k

10k

100k

1M

10M

100M

LO FREQUENCY (MHz)

OFFSET FREQUENCY (Hz)

Figure 10. PLL Spot Phase Noise at Various Offsets

and Integrated Phase Noise vs. LO Frequency

Figure 12. Phase Noise vs. Offset Frequency and LO Frequency

(LO Frequency Varies from 750 MHz to 1160 MHz)

–80

–85

–90

–95

1× PFD OFFSET

2× PFD

OFFSET

–100

–105

–110

4× PFD OFFSET

0.25× AND

0.5× PFD

OFFSET

750

800

850

900

950

1000 1050 1100 1150

LO FREQUENCY (MHz)

Figure 11. PLL Reference Spurs vs. LO Frequency

Rev. 0 | Page 10 of 24

ADRF6601

REGISTER STRUCTURE

This section provides the register maps for the ADRF6601. The three LSBs determine the register that is programmed.

REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)

DIVIDE

MODE

RESERVED

INTEGER DIVIDE RATIO

CONTROL BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0)

0

DM

0

DIVIDE MODE

FRACTIONAL (DEFAULT)

INTEGER

1

INTEGER DIVIDE RATIO

ID6

0

ID5

0

ID4

1

ID3

0

ID2

1

ID1

0

ID0

21 (INTEGER MODE ONLY)

1

0

22 (INTEGER MODE ONLY)

0

1

0

1

23 (INTEGER MODE ONLY)

0

1

0

1

24

0

1

0

...

0

...

1

...

1

...

1

...

0

...

0

...

0

...

56 (DEFAULT)

...

1

...

1

...

1

...

0

...

1

...

1

...

1

...

119

120 (INTEGER MODE ONLY)

121 (INTEGER MODE ONLY)

122 (INTEGER MODE ONLY)

123 (INTEGER MODE ONLY)

1

0

1

0

1

0

1

0

1

0

1

Figure 13. Register 0—Integer Divide Control Register Map

REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)

RESERVED

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)

MODULUS VALUE

CONTROL BITS

0

MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0

MODULUS VALUE

1

0

1

2

0

1

0

...

1

...

1

...

0

...

0

...

0

...

0

...

0

...

0

...

0

...

0

...

0

...

1536 (DEFAULT)

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

2047

Figure 14. Register 1—Modulus Divide Control Register Map

Rev. 0 | Page 11 of 24

ADRF6601

REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)

CONTROL BITS

RESERVED

FRACTIONAL VALUE

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2 DB1 DB0

0

FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0)

FRACTIONAL VALUE

FD10

0

FD9

0

FD8

0

FD7

0

FD6

0

FD5

0

FD4

0

FD3

0

FD2

0

FD1

0

FD0

0

1

0

1

...

0

...

1

...

1

...

0

...

0

...

0

...

0

...

0

...

0

...

0

...

0

...

768 (DEFAULT)

...

FRACTIONAL VALUE MUST BE LESS THAN MODULUS

<MDR

Figure 15. Register 2—Fractional Divide Control Register Map

REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)

DITHER

MAGNITUDE

DITHER

ENABLE

DITHER RESTART VALUE

CONTROL BITS

RES

DB23 DB22

DITH1

DB21

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

DITH0

DEN

DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)

DITH1

DITH0 DITHER MAGNITUDE

0

1

15 (DEFAULT)

7

1

0

1

3

1 (RECOMMENDED)

DEN DITHER ENABLE

0

1

DISABLE

ENABLE (DEFAULT, RECOMMENDED)

DITHER RESTART

VALUE

DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0

0x00001 (DEFAULT)

0

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

0x1FFFF

Figure 16. Register 3—Σ-Δ Modulator Dither Control Register Map

Rev. 0 | Page 12 of 24

ADRF6601

REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)

CP

PFD ANTI-

REF OUTPUT

MUX SELECT

INPUT REF

PATH

PFD

POL

PFD PHASE OFFSET

MULTIPLIER

CP

CURRENT

REF

PFD EDGE BACKLASH

CONTROL BITS

CURRENT SRC CONTROL

DELAY

SOURCE

DB23 DB22 DB21 DB20 DB19

RMS2 RMS1 RMS0 RS1 RS0

DB18

CPM

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)

PFD ANTIBACKLASH

PAB0 PAB1

DELAY

0

1

0

1

0

1

0ns (DEFAULT)

0.5ns

0.75ns

0.9ns

REFERENCE PATH EDGE

SENSITIVITY

PE0

0

1

FALLING EDGE

RISING EDGE (DEFAULT)

DIVIDER PATH EDGE

SENSITIVITY

PE1

0

1

FALLING EDGE

RISING EDGE (DEFAULT)

CHARGE PUMP CONTROL

CPC1 CPC0

BOTH ON

PUMP DOWN

PUMP UP

0

1

0

1

0

1

TRISTATE (DEFAULT)

CPS CHARGE PUMP CONTROL SOURCE

0

1

CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL)

CONTROL FROM PFD (DEFAULT)

CPP1 CPP0 CHARGE PUMP CURRENT

250µA

500µA (DEFAULT)

750µA

0

1

0

1

0

1

1000µA

PFD PHASE OFFSET MULTIPLIER

CPB4 CPB3 CPB2 CPB1 CPB0

0 × 22.5°/I

CPMULT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 × 22.5°/I

CPMULT

6 × 22.5°/I

CPMULT

(RECOMMENDED)

(DEFAULT)

10 × 22.5°/I

16 × 22.5°/I

31 × 22.5°/I

CPMULT

CPBD PFD PHASE OFFSET POLARITY

0

1

NEGATIVE

POSITIVE (DEFAULT)

CHARGE PUMP CURRENT

REFERENCE SOURCE

CPM

INTERNAL (DEFAULT)

EXTERNAL

0

1

INPUT REFERENCE

PATH SOURCE

RS1 RS0

2 × REF_IN

REF_IN (DEFAULT)

0.5 × REF_IN

0

1

0

1

0

1

0.25 × REF_IN

RMS2 RMS1 RMS0 REF OUTPUT MUX SELECT

LOCK DETECT (DEFAULT)

VPTAT

REF_IN (BUFFERED)

0.5 × REF_IN (BUFFERED)

2 × REF_IN (BUFFERED)

TRISTATE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

RESERVED

Figure 17. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map

Rev. 0 | Page 13 of 24

ADRF6601

REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)

PLL

EN

LO

DIV1

LO

EXT

LO

DRV

CAP DAC

RES

CONTROL BITS

RESERVED

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7

DB6

DB5

DB4

LXL

DB3 DB2 DB1 DB0

LDRV C3(1) C2(0) C1(1)

0

CD3 CD2 CD1 CD0

CAPACITOR DAC

0

PLEN LDV1

LO OUTPUT DRIVER

LDRV

CD3

CD2

CD1

CD0 CONTROL FOR IIP3

OPTIMIZATION

ENABLE

DRIVER OFF (DEFAULT)

DRIVER ON

0

1

MIN

MAX

0

1

0

1

0

1

0

1

EXTERNAL LO DRIVE

ENABLE (PIN 37, PIN 38)

LXL

INTERNAL LO OUTPUT (DEFAULT)

EXTERNAL LO INPUT

0

1

LDV1 DIVIDE-BY-2 IN LO CHAIN ENABLE

DIVIDE BY 1

DIVIDE BY 2 (DEFAULT)

0

1

PLEN PLL ENABLE

DISABLE

ENABLE (DEFAULT)

0

1

Figure 18. Register 5—PLL Enable and LO Path Control Register Map

REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)

CHARGE

PUMP

3.3V

LDO

VCO

BW SW

CTRL

VCO LDO VCO

VCO

CONTROL BITS

DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VCO BAND SELECT FROM SPI

RESERVED

VCO AMPLITUDE

ENABLE ENABLE SWITCH

ENABLE ENABLE

DB23 DB22 DB21 DB20

DB19

L3EN

DB18

DB17

DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

0

CPEN

LVEN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)

CHARGE PUMP ENABLE

CPEN

VC[5:0] VCO AMPLITUDE

VBS[5:0] VCO BAND SELECT FROM SPI

DISABLE

ENABLE (DEFAULT)

0x00

….

0

0x00

0x01

0

1

….

DEFAULT 0x20

….

0x18

….

0x2B

….

24 (DEFAULT)

….

43

….

0x3F

L3EN 3.3V LDO ENABLE

VBSRC VCO BW CAL AND SW SOURCE CONTROL

0

1

DISABLE

ENABLE (DEFAULT)

0x3F

63 (RECOMMENDED)

0

1

BAND CAL (DEFAULT)

SPI

VCO SW VCO SWITCH CONTROL FROM SPI

LVEN VCO LDO ENABLE

REGULAR (DEFAULT)

BAND CAL

0

1

0

1

DISABLE

ENABLE (DEFAULT)

VCO EN VCO ENABLE

0

1

DISABLE

ENABLE (DEFAULT)

Figure 19. Register 6—VCO Control and VCO Enable Register Map

REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)

MIXER

B_EN

RESERVED

CONTROL BITS

RES XVCO

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

XVCO MBE C3(1) C2(1) C1(1)

0

MBE MIXER BIAS ENABLE

DISABLE

ENABLE (DEFAULT)

0

1

EXTERNAL VCO

XVCO

INTERNAL VCO (DEFAULT)

EXTERNAL VCO

0

1

Figure 20. Register 7—Mixer Bias Enable and External VCO Enable Register Map

Rev. 0 | Page 14 of 24

ADRF6601

THEORY OF OPERATION

The ADRF6601 integrates a high performance downconverting

mixer with a state-of-the-art fractional-N PLL. The PLL also inte-

grates a low noise VCO. The SPI port allows the user to control the

fractional-N PLL functions and the mixer optimization functions,

as well as allowing for an externally applied LO or VCO.

PROGRAMMING THE ADRF6601

The ADRF6601 is programmed via a 3-pin SPI port. The timing

requirements for the SPI port are shown in Figure 2. Eight pro-

grammable registers, each with 24 bits, control the operation of

the device. The register functions are listed in Table 8.

The mixer core within the ADRF6601 is the next generation of

an industry leading family of mixers from Analog Devices, Inc.

The RF input is converted to a current and then mixed down to

IF using high performance NPN transistors. The mixer output

currents are transformed to a differential output voltage.

Table 8. ADRF6601 Register Functions

Register

Function

Regꢁsteꢂ 0

Regꢁsteꢂ 1

Regꢁsteꢂ 2

Regꢁsteꢂ 3

Regꢁsteꢂ 4

Regꢁsteꢂ 5

Regꢁsteꢂ 6

Regꢁsteꢂ 7

Iitegeꢂ ꢀꢁvꢁꢀe coitꢂol foꢂ the PLL

Moꢀplps ꢀꢁvꢁꢀe coitꢂol foꢂ the PLL

Fꢂactꢁoial ꢀꢁvꢁꢀe coitꢂol foꢂ the PLL

Σ-Δ moꢀplatoꢂ ꢀꢁtheꢂ coitꢂol

PLL chaꢂge npmn, PFD, ꢂefeꢂeice nath coitꢂol

PLL eiable aiꢀ LO nath coitꢂol

VCO coitꢂol aiꢀ VCO eiable

The high performance active mixer core results in an excep-

tional IIP3 and IP1dB, with a very low output noise floor for

excellent dynamic range. Over the specified frequency range,

the ADRF6601 typically provides an IF input P1dB of 14.3 dBm

and an IIP3 of 31 dBm.

Mꢁxeꢂ bꢁas eiable aiꢀ exteꢂial VCO eiable

Improved performance at specific frequencies can be achieved

with the use of the internal capacitor DAC (CDAC), which is

programmable via the SPI port, and through the use of a resistor

to a 5 V supply from the IP3SET pin (Pin 29). Adjustment of

the capacitor DAC allows increments in phase shift at internal

nodes in the ADRF6601, thus allowing cancellation of third-

order distortion with no change in supply current. Connecting

a resistor to a 5 V supply from the IP3SET pin increases the

internal mixer core current, thereby improving overall IIP2 and

IIP3, as well as IP1dB. Using the IP3SET pin for this purpose

increases the overall supply current.

Note that internal calibration for the PLL must be run when the

ADRF6601 is initialized at a given frequency. This calibration is

run automatically whenever Register 0, Register 1, or Register 2 is

programmed. Because the other registers affect PLL performance,

Register 0, Register 1, and Register 2 should always be programmed

in the order specified in the Initialization Sequence section.

To program the frequency of the ADRF6601, the user typically

programs only Register 0, Register 1, and Register 2. However,

if registers other than these are programmed first, a short delay

should be inserted before programming Register 0. This delay

ensures that the VCO band calibration has sufficient time to com-

plete before the final band calibration for Register 0 is initiated.

The fractional divide function of the PLL allows the frequency

multiplication value from REF_IN to LO output to be a frac-

tional value rather than be restricted to an integer value as

in traditional PLLs. In operation, this multiplication value is

Software is available on the ADRF6601 product page of the

Analog Devices website (www.analog.com) that allows easy

programming from a PC running Windows XP or Vista.

INT + (FRAC/MOD)

INITIALIZATION SEQUENCE

where:

INT is the integer value.

FRAC is the fractional value.

MOD is the modulus value.

To ensure proper power-up of the ADRF6601, it is important to

reset the PLL circuitry after the VCC supply rail settles to 5 V

0.25 V. Resetting the PLL ensures that the internal bias cells are

properly configured, even under poor supply start-up conditions.

The INT, FRAC, and MOD values are all programmable via

the SPI port.

To ensure that the PLL is reset after power-up, follow these steps:

In other fractional-N PLL designs, fractional multiplication

is achieved by periodically changing the fractional value in a

deterministic way. The disadvantage of this approach is often

spurious components close to the fundamental signal. In the

ADRF6601, a Σ-Δ modulator is used to distribute the fractional

value randomly, thus significantly reducing the spurious content

due to the fractional function.

1. Disable the PLL by setting the PLEN bit to 0 (Register 5,

Bit DB6).

2. After a delay of >100 ms, set the PLEN bit to 1.

After this procedure is followed, the other registers should be

programmed in this order: Register 7, Register 6, Register 4,

Register 3, Register 2, Register 1. Then, after a delay of >100 ms,

Register 0 should be programmed.

Rev. 0 | Page 15 of 24

ADRF6601

The operation of the LO generation and whether LOP and LON

are inputs or outputs are determined by the logic levels applied

at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3

(LDRV) and Bit DB6 (PLEN) in Register 5. The combination of

externally applied logic and internal bits required for particular

LO functions is given in Table 9.

LO SELECTION LOGIC

The downconverting mixer in the ADRF6601 can be used

without the internal PLL by applying an external differential

LO to Pin 37 and Pin 38 (LON and LOP). In addition, when

using an LO generated by the internal PLL, the LO signal can

be accessed directly at these same pins. This function can be

used for debugging purposes, or the internally generated LO

can be used as the LO for a separate mixer.

Table 9. LO Selection Logic

Pins¹

Register 5 Bits¹

Outputs

LO

Pin 16 (PLL_EN)

Pin 36 (LODRV_EN) Bit DB6 (PLEN)

Bit DB3 (LDRV)

Output Buffer

Dꢁsableꢀ

Eiableꢀ

0

1

X

0

X

1

0

1

0

1

X

0

1

X

Exteꢂial

Iiteꢂial

Eiableꢀ

¹X = ꢀoi’t caꢂe.

Rev. 0 | Page 16 of 24

ADRF6601

APPLICATIONS INFORMATION

shown in Figure 21. The reference signal, or a divided-down

version of the reference signal, can be brought back off chip at

the multiplexer output pin (MUXOUT). A lock detect signal

and a voltage proportional to the ambient temperature can also

be selected on the multiplexer output pin.

BASIC CONNECTIONS FOR OPERATION

Figure 21 shows the basic connections for the ADRF6601. The

six power supply pins should be individually decoupled using

100 pF and 0.1 μF capacitors located as close as possible to the

device. In addition, the internal decoupling nodes (DECL3P3,

DECL2P5, and DECLVCO) should be decoupled with the

capacitor values shown in Figure 21.

The loop filter is connected between the CP and VTUNE pins.

When connected in this way, the internal VCO is operational.

For information about the loop filter components, see the

Evaluation Board Configuration Options section.

The RF input is internally ac-coupled and needs no external

bias. The IF outputs are open collector, and a bias inductor

is required from these outputs to VCC.

Operation with an external VCO is also possible. In this case,

the loop filter components should be referred to ground. The

output of the loop filter is connected to the input voltage pin of

the external VCO. The output of the VCO is brought back into

the device on the LOP and LON pins, using a balun if necessary.

A peak-to-peak differential swing on RF_INof 1 V (0.353 V rms

for a sine wave input) results in an IF output power of 4.7 dBm.

The reference frequency for the PLL should be from 12 MHz

to 160 MHz and should be applied to the REF_IN pin, which

should be ac-coupled and terminated with a 50 ꢀ resistor, as

P1

9-PIN

DSUB

1

2

3

4

5

6

7

8

9

VCC

R36

R19

0Ω

(0402)

R35

R30

0Ω

R54

0Ω

(0402)

R20

10kΩ

(0402) (0402)

R57

0Ω

(0402)

0Ω

(0402)

S2

R53

10kΩ

(0402)

C34

OPEN

(0402)

R52

OPEN

(0402)

VCC

RED

+5V

C33

OPEN

(0402)

R51

OPEN

(0402)

C7

0.1µF

(0402)

C25

0.1µF

(0402)

C23

0.1µF

(0402)

C20

0.1µF

(0402)

C19

0.1µF

(0402)

C9

0.1µF

(0402)

R6

R26

R25

R24

R17

R7

VCC1

RED

R55

OPEN

(0402)

C32

OPEN

(0402)

R50

OPEN

(0402)

0Ω

(0402)

C8

(0402)

C24

C22

C21

C18

C10

100pF

(0402)

100pF

(0402)

100pF

(0402)

S1

OPEN

VCC_LO

VCC_V2I

VCC_MIX

VCC_LO

VCC2

VCC1

34

27

22

17

10

1

16 13 12 14

DECL2P5

C16

R56

9

2

0Ω

LODRV_EN

C17

C42

R18

(0402)

36

SPI

INTERFACE

100pF

(0402)

0.1µF

(0402)

10µF

(0603)

0Ω

LON

C5

(0402)

37

38

LO IN/OUT

DIVIDER

÷2

4

5

3

1

BUFFER

DECL3P3

C12

LOP

1nF

(0402)

C11

0.1µF

(0402)

C41

OPEN

(0603)

R8

0Ω

(0402)

100pF

(0402)

DIV

BY

4, 2, 1

2:1

MUX

T8

TC1-1-13+

INTEGER

REG

FRACTION

REG

C6

1nF

(0402)

MODULUS

ADRF6601

RF

IN

26

29

RFIN

THIRD-ORDER

R28

FRACTIONAL

C31

1nF

0Ω

VCO

CORE

INTERPOLATOR

(0402)

×2

N COUNTER

21 TO 123

PRESCALER

÷2

REFIN

(0402)

REF_IN

6

8

R70

MUX

÷2

IP3SET

CHARGE PUMP

250µA,

49.9Ω

–

+

C27

0.1µF

(0402)

PHASE

FREQUENCY

DETECTOR

R27

0Ω

(0402)

500µA (DEFAULT),

750µA,

TEMP

SENSOR

÷4

REFOUT

(0402)

MUXOUT

1000µA

R16

4

7

11 15 20 21 23 24 25 28 30 31 35

5

3

39

40

18

19

0Ω

R

SET

VTUNE DECLVCO IFP

IFN

CP

(0402)

1

2

4

R2

RFOUT

OPEN

(0402)

R37

R43

R62

VCC

+5V

0Ω

R59

3

(0402)

5

(0402)

0Ω

R38

0Ω

(0402)

R9 10kΩ R65 10kΩ

CP

TEST

VTUNE

(0402)

C29

0.1µF

(0402)

POINT

R10

3.0kΩ

(0603)

R63

(ORANGE)

OPEN

(0402)

C14

22pF

(0603)

C13

6.8pF

(0603)

C40

22pF

(0603)

C15

2.7nF

(1206)

R12

R11

OPEN

(0402)

R1

0Ω

(0402)

C43

10µF

(0603)

C2

OPEN

(0402)

C1

100pF

(0402)

Figure 21. Basic Connections for Operation of the ADRF6601

Rev. 0 | Page 17 of 24

ADRF6601

EVALUATION BOARD

Figure 24 shows the schematic of the RoHS-compliant evalua-

tion board for the ADRF6601. This board has four layers and

was designed using Rogers 4350 hybrid material to minimize

high frequency losses. FR4 material is also adequate if the design

can accept the slightly higher trace loss of this material.

To connect the evaluation board to a USB port, a USB adapter

board (Part No. EVAL-ADF4XXXZ-USB) must be purchased

from www.analog.com. This board connects to the PC using a

standard USB cable with USB mini-connector at one end. An

additional 25-pin male to 9-pin female adapter is required to

mate the EVAL-ADF4XXXZ-USB board to the 9-pin D-Sub

connector on the ADRF6601 evaluation board.

The evaluation board is designed to operate using the internal

VCO of the device (the default configuration) or with an

external VCO. To use an external VCO, R62 and R12 should

be removed. Place 0 ꢀ resistors in R63 and R11. The input of

the external VCO should be connected to the VTUNE SMA

connector, and the external VCO output should be connected

to the LO IN/OUT SMA connector. In addition to these hard-

ware changes, internal register settings must also be changed to

enable operation with an external VCO (see the Register 6—

VCO Control and VCO Enable (Default: 0x1E2106) section).

Additional configuration options for the evaluation board are

described in Table 10.

EVALUATION BOARD CONTROL SOFTWARE

Software to program the ADRF6601 is available for download

from the ADRF6601 product page at www.analog.com. To install

the software, download and extract the zip file. Then run the

following installation file:

Figure 22. Control Software Opening Menu

ADRF6x0x_3p0p0_XP_install.exe

The evaluation board can be connected to the PC using a PC

parallel port or a USB port. These options are selectable from

the opening menu of the software interface (see Figure 22). The

evaluation board is shipped with a 25-pin parallel port cable

for connection to the PC parallel port.

Figure 23 shows the main window of the control software with

the default settings displayed.

Rev. 0 | Page 18 of 24

ADRF6601

Figure 23. Main Window of the ADRF6601 Evaluation Board Software

Rev. 0 | Page 19 of 24

ADRF6601

SCHEMATICS AND ARTWORK

2 3 0 6 - 0 8 5 4

1 W 4 - C T

6

4

3

2

1

0

R 4 3

0

6

R 6

8

C 2

F U 1 0

0

d d _ V C C

O L _ V C C

F R _ V C C

R 3 2

R 3 1

R 2 9

D N G

N F I

D N G

C N

0

P F I

0

C N

3

R 3

O L _ C C V

N E _ L L P

D N G

E L

R 3 4

R 2 0

O L _ C C V

D N G

3

2

1

2

3

S2

1

N E _ V R D O L

N O L

S 1

0

K L C

1

P O L

R 3 5

A T A D

D N G

E N U T V

O C V L C E D

0

R 7 2

R 6 2

1

0

R 1 2

3 K

R 1 0

D

T d

R 7 1

I

D N

R 1 1

0

7

R 3

I

D N

R 1

4

Y 1

Figure 24. Evaluation Board Schematic

Rev. 0 | Page 20 of 24

ADRF6601

Figure 25. Evaluation Board Layout (Bottom)

Figure 26. Evaluation Board Layout (Top)

Rev. 0 | Page 21 of 24

ADRF6601

EVALUATION BOARD CONFIGURATION OPTIONS

Table 10.

Default Condition/

Option Settings

Component

Description

S1, R55, R56, R33

LO select. Swꢁtch aiꢀ ꢂesꢁstoꢂs to gꢂopiꢀ the LODRV_EN nꢁi. The LODRV_EN nꢁi settꢁig, ꢁi

combꢁiatꢁoi wꢁth ꢁiteꢂial ꢂegꢁsteꢂ settꢁigs, ꢀeteꢂmꢁies whetheꢂ the LOP aiꢀ LON nꢁis

fpictꢁoi as ꢁinpts oꢂ optnpts (see the LO Selectꢁoi Logꢁc sectꢁoi foꢂ moꢂe ꢁifoꢂmatꢁoi).

S1 = R55 = onei

(iot ꢁistalleꢀ)

R56 = R33 = 0 Ω

LODRV_EN = 0 V

LO IN/OUT

SMA coiiectoꢂ

LO ꢁinpt/optnpt. Ai exteꢂial 1× LO oꢂ 2× LO fꢂeqpeicy cai be annlꢁeꢀ to thꢁs sꢁigle-eiꢀeꢀ LO ꢁinpt

ꢁinpt coiiectoꢂ.

REFIN

SMA coiiectoꢂ

Refeꢂeice ꢁinpt. The ꢁinpt ꢂefeꢂeice fꢂeqpeicy foꢂ the PLL ꢁs annlꢁeꢀ to thꢁs coiiectoꢂ.

Iinpt ꢁmneꢀaice ꢁs 50 Ω.

REFOUT

SMA coiiectoꢂ

Mpltꢁnlexeꢂ optnpt. The REFOUT coiiectoꢂ coiiects ꢀꢁꢂectly to the MUXOUT nꢁi. The

oi-boaꢂꢀ mpltꢁnlexeꢂ cai be nꢂogꢂammeꢀ to bꢂꢁig opt the followꢁig sꢁgials:

REF_IN, 2 × REF_IN, 0.5 × REF_IN, 0.25 × REF_IN.

Lock ꢀetect

Temneꢂatpꢂe seisoꢂ optnpt voltage.

Lock ꢀetect ꢁiꢀꢁcatoꢂ.

CP test noꢁit

Chaꢂge npmn test noꢁit. The pifꢁlteꢂeꢀ chaꢂge npmn sꢁgial cai be nꢂobeꢀ at thꢁs test

noꢁit. Note that the CP nꢁi shoplꢀ iot be nꢂobeꢀ ꢀpꢂꢁig cꢂꢁtꢁcal measpꢂemeits spch as

nhase ioꢁse.

R37, C14, R9, R10,

C15, C13, R65, C40

Loon fꢁlteꢂ. Loon fꢁlteꢂ comnoieits.

R11, R12

Loon fꢁlteꢂ ꢂetpꢂi. Whei the ꢁiteꢂial VCO ꢁs pseꢀ, the loon fꢁlteꢂ comnoieits shoplꢀ be

ꢂetpꢂieꢀ to Pꢁi 40 (DECLVCO) by ꢁistallꢁig a 0 Ω ꢂesꢁstoꢂ ꢁi R12. Whei ai exteꢂial VCO ꢁs pseꢀ,

the loon fꢁlteꢂ comnoieits cai be ꢂetpꢂieꢀ to gꢂopiꢀ by ꢁistallꢁig a 0 Ω ꢂesꢁstoꢂ ꢁi R11.

R12 = 0 Ω (0402)

R11 = onei (0402)

R62, R63, VTUNE

SMA coiiectoꢂ

Iiteꢂial vs. exteꢂial VCO. Whei the ꢁiteꢂial VCO ꢁs eiableꢀ, the loon fꢁlteꢂ comnoieits aꢂe

coiiecteꢀ ꢀꢁꢂectly to the VTUNE nꢁi (Pꢁi 39) by ꢁistallꢁig a 0 Ω ꢂesꢁstoꢂ ꢁi R62.

To pse ai exteꢂial VCO, R62 shoplꢀ be left onei. A 0 Ω ꢂesꢁstoꢂ shoplꢀ be ꢁistalleꢀ ꢁi R63,

aiꢀ the voltage ꢁinpt of the VCO shoplꢀ be coiiecteꢀ to the VTUNE SMA coiiectoꢂ. The

optnpt of the VCO ꢁs bꢂopght back ꢁito the PLL vꢁa the LO IN/OUT SMA coiiectoꢂ.

R62 = 0 Ω (0402)

R63 = onei (0402)

R2

R_SETnꢁi. Thꢁs nꢁi ꢁs pipseꢀ aiꢀ shoplꢀ be left onei.

R2 = onei (0402)

RFIN SMA coiiectoꢂ RF ꢁinpt. The RF ꢁinpt sꢁgial shoplꢀ be annlꢁeꢀ to the RFIN SMA coiiectoꢂ. The RF ꢁinpt of

the ADRF6601 ꢁs ac-copnleꢀ; theꢂefoꢂe, io bꢁas ꢁs iecessaꢂy.

T3

IF optnpt. The ꢀꢁffeꢂeitꢁal IF optnpt sꢁgials fꢂom the ADRF6601 (IFP aiꢀ IFN) aꢂe coiveꢂteꢀ

to a sꢁigle-eiꢀeꢀ sꢁgial by T3.

Rev. 0 | Page 22 of 24

ADRF6601

OUTLINE DIMENSIONS

6.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

31

40

1

30

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

4.25

4.10 SQ

3.95

5.75

BSC SQ

EXPOSED

PAD

(BOT TOM VIEW)

0.50

0.40

0.30

21

10

20

11

0.25 MIN

4.50

REF

12° MAX

0.80 MAX

0.65 TYP

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SECTION OF THIS DATA SHEET.

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 27. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADRF6601ACPZ-R7

ADRF6601-EVALZ

Temperature Range

Package Description

Package Option

CP-40-1

−40°C to +85°C

40-Leaꢀ Leaꢀ Fꢂame Chꢁn Scale Package [LFCSP_VQ]

Evalpatꢁoi doaꢂꢀ

¹Z = RoHS Comnlꢁait Paꢂt.

Rev. 0 | Page 23 of 24

ADRF6601

NOTES

registered trademarks are the property of their respective owners.

D08546-0-4/10(0)

Rev. 0 | Page 24 of 24


型号：	ADRF6601-EVALZ
厂家：	ADI
描述：	750 MHz to 1160 MHz Rx Mixer with Integrated Fractional-N PLL and VCO 750 MHz至1160 MHz的接收混频器，集成小数N分频PLL和VCO
文件：	总24页 (文件大小：565K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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