ADRF6603ACPZ-R7_技术文档

2100 MHz to 2600 MHz Rx Mixer with

Integrated Fractional-N PLL and VCO

ADRF6603

FEATURES

Table 1.

Rx mixer with integrated fractional-N PLL

RF input frequency range: 1100 MHz to 3200 MHz

Internal LO frequency range: 2100 MHz to 2600 MHz

Input P1dB: 14.6 dBm

Input IP3: 27 dBm

Input IP3 optimization via external pin

SSB noise figure

Internal LO

Range

3 dB RF_IN

Balun Range

1 dB RF_IN

Balun Range

Part No.

ADRF6602 1550 MHz

2150 MHz

1000 MHz

3100 MHz

1100 MHz

3200 MHz

1350 MHz

2750 MHz

1450 MHz

2850 MHz

ADRF6603 2100 MHz

2600 MHz

The PLL reference input can support input frequencies from

12 MHz to 160 MHz. The PFD output controls a charge pump

whose output drives an off-chip loop filter.

IP3SET pin open: 14.2 dB

IP3SET pin at 3.3 V: 15.2 dB

Voltage conversion gain: 6.9 dB

Matched 200 Ω IF output impedance

IF 3 dB bandwidth: 500 MHz

Programmable via 3-wire SPI interface

40-lead, 6 mm × 6 mm LFCSP

The loop filter output is then applied to an integrated VCO. The

VCO output at 2× f_LOis applied to an LO divider, as well as to a

programmable PLL divider. The programmable PLL divider is

controlled by a sigma-delta modulator (SDM). The modulus of

the SDM can be programmed from 1 to 2047.

APPLICATIONS

The active mixer converts the single-ended 50 Ω RF input to

a 200 ꢀ differential IF output. The IF output can operate up

to 500 MHz.

Cellular base stations

GENERAL DESCRIPTION

The ADRF6603 is fabricated using an advanced silicon-germanium

BiCMOS process. It is available in a 40-lead, RoHS-compliant,

6 mm × 6 mm LFCSP with an exposed paddle. Performance is

specified over the −40°C to +85°C temperature range.

The ADRF6603 is a high dynamic range active mixer with

integrated fractional-N phase-locked loop (PLL) and voltage-

controlled oscillator (VCO) for internal mixer LO generation.

Along with the ADRF6602, the ADRF6603 forms a family of

integrated PLL/mixers that cover the frequency range of 2100 MHz

to 2600 MHz.

FUNCTIONAL BLOCK DIAGRAM

VCC1

1

VCC2 VCC_LO VCC_MIX VCC_V2I VCC_LO

NC NC

10

17

22

27

34

32

33

ADRF6603

36

INTERNAL LO RANGE

2100MHz TO 2600MHz

LODRV_EN

3.3V

LDO

2

9

DECL3P3

DECL2P5

DECLVCO

LON 37

BUFFER

2.5V

LDO

38

LOP

VCO

LDO

PLL_EN 16

DIV

2:1

40

BY

INTEGER

REG

FRACTION

REG

MUX

12

13

14

DATA

CLK

LE

MODULUS

2, 1

SPI

INTERFACE

26

29

RF

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

IN

VCO

CORE

IP3SET

×2

N COUNTER

21 TO 123

PRESCALER

÷2

6

8

REF_IN

MUX

÷2

CHARGE PUMP

250µA,

500µA (DEFAULT),

–

+

PHASE

FREQUENCY

DETECTOR

TEMP

SENSOR

÷4

750µA,

1000µA

5

MUXOUT

4

7

11 15 20 21 23 24 25 28 30 31 35

GND

39

18 19

3

R

CP VTUNE IFP IFN

SET

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADRF6603

TABLE OF CONTENTS

Features .............................................................................................. 1

Register 4—PLL Charge Pump, PFD, and Reference Path

Control (Default: 0x0AA7E4)................................................... 13

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

RF Specifications .......................................................................... 3

Synthesizer/PLL Specifications................................................... 4

Logic Input and Power Specifications ....................................... 5

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Register Structure ........................................................................... 11

Register 0—Integer Divide Control (Default: 0x0001C0)..... 11

Register 1—Modulus Divide Control (Default: 0x003001).. 11

Register 2—Fractional Divide Control (Default: 0x001802) 12

Register 5—PLL Enable and LO Path Control (Default:

0x0000E5).................................................................................... 14

Register 6—VCO Control and VCO Enable (Default:

0x1E2106).................................................................................... 14

Register 7—Mixer Bias Enable and External VCO Enable

(Default: 0x000007).................................................................... 14

Theory of Operation ...................................................................... 15

Programming the ADRF6603................................................... 15

Initialization Sequence .............................................................. 15

LO Selection Logic ..................................................................... 16

Applications Information.............................................................. 17

Basic Connections for Operation............................................. 17

Evaluation Board ............................................................................ 18

Evaluation Board Control Software......................................... 18

Schematics and Artwork ........................................................... 20

Evaluation Board Configuration Options............................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Register 3—Σ-Δ Modulator Dither Control (Default:

0x10000B).................................................................................... 12

REVISION HISTORY

3/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADRF6603

SPECIFICATIONS

RF SPECIFICATIONS

V_S= 5 V; ambient temperature (T_A) = 25°C; f_REF= 38.4 MHz; f_PFD= 38.4 MHz; high-side LO injection; f_IF= 140 MHz; IIP3 optimized

using capacitor DAC (0x1) and IP3SET (3.3 V), unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

2600

3200

Unit

MHz

INTERNAL LO FREQUENCY RANGE

RF INPUT FREQUENCY RANGE

RF INPUT AT 2140 MHz

Iinpu Reupꢂi Loss

2100

1100

3 ꢀd RF ꢁinpu ꢂaige

Relauꢁve uo 50 Ω (cai be ꢁmnꢂoveꢀ wꢁuh exueꢂial mauch)

−27

14.6

56

ꢀd

Iinpu P1ꢀd

ꢀdm

ꢀd

ꢀdm

Secoiꢀ-Oꢂꢀeꢂ Iiueꢂcenu (IIP2)

Thꢁꢂꢀ-Oꢂꢀeꢂ Iiueꢂcenu (IIP3)

Sꢁigle-Sꢁꢀe daiꢀ Noꢁse Fꢁgpꢂe

−5 ꢀdm each uoie (10 MHz snacꢁig beuweei uoies)

IP3SET = 3.3 V

IP3SET = onei

Au 1× LO fꢂeqpeicy, 50 Ω ueꢂmꢁiauꢁoi au uhe RF noꢂu

28

15.2

14.5

−42

LO uo IF Leakage

RF INPUT AT 2400 MHz

Iinpu Reupꢂi Loss

Iinpu P1ꢀd

Secoiꢀ-Oꢂꢀeꢂ Iiueꢂcenu (IIP2)

Thꢁꢂꢀ-Oꢂꢀeꢂ Iiueꢂcenu (IIP3)

Sꢁigle-Sꢁꢀe daiꢀ Noꢁse Fꢁgpꢂe

Relauꢁve uo 50 Ω (cai be ꢁmnꢂoveꢀ wꢁuh exueꢂial mauch)

−16

14.6

55

27.7

15.3

14.2

−43

ꢀd

ꢀdm

ꢀd

ꢀdm

−5 ꢀdm each uoie (10 MHz snacꢁig beuweei uoies)

IP3SET = 3.3 V

IP3SET = onei

Au 1× LO fꢂeqpeicy, 50 Ω ueꢂmꢁiauꢁoi au uhe RF noꢂu

Low sꢁꢀe Iijecuꢁoi

LO uo IF Leakage

RF INPUT AT 2650 MHz

Iinpu Reupꢂi Loss

Iinpu P1ꢀd

Secoiꢀ-Oꢂꢀeꢂ Iiueꢂcenu (IIP2)

Thꢁꢂꢀ-Oꢂꢀeꢂ Iiueꢂcenu (IIP3)

Sꢁigle-Sꢁꢀe daiꢀ Noꢁse Fꢁgpꢂe

Relauꢁve uo 50 Ω (cai be ꢁmnꢂoveꢀ wꢁuh exueꢂial mauch)

−11

14.6

54

28.0

15.3

14.2

−42.5

ꢀd

ꢀdm

ꢀd

ꢀdm

−5 ꢀdm each uoie (10 MHz snacꢁig beuweei uoies)

IP3SET = 3.3 V

IP3SET = onei

Au 1× LO fꢂeqpeicy, 50 Ω ueꢂmꢁiauꢁoi au uhe RF noꢂu

LO uo IF Leakage

IF OUTPUT

Voluage Coiveꢂsꢁoi Gaꢁi

IF daiꢀwꢁꢀuh

Opunpu Commoi-Moꢀe Voluage

Gaꢁi Flauiess

Gaꢁi Vaꢂꢁauꢁoi

Opunpu Swꢁig

Opunpu Reupꢂi Loss

LO INPUT/OUTPUT (LOP, LON)

Fꢂeqpeicy Raige

Opunpu Level (LO as Opunpu)

Iinpu Level (LO as Iinpu)

Iinpu Imneꢀaice

Dꢁffeꢂeiuꢁal 200 Ω loaꢀ

Small-sꢁgial 3 ꢀd baiꢀwꢁꢀuh

Exueꢂial npll-pn balpi oꢂ ꢁiꢀpcuoꢂs ꢂeqpꢁꢂeꢀ

Oveꢂ fꢂeqpeicy ꢂaige, aiy 5 MHz/50 MHz

Oveꢂ fpll uemneꢂaupꢂe ꢂaige

6.9

500

5

0.2/1.0

1.0

2

ꢀd

MHz

V

ꢀd

Dꢁffeꢂeiuꢁal 200 Ω loaꢀ

Relauꢁve uo 200 Ω

V n-n

ꢀd

−14

Exueꢂially annlꢁeꢀ 1× LO ꢁinpu, ꢁiueꢂial PLL ꢀꢁsableꢀ

250

6000

MHz

ꢀdm

Ω

1× LO ꢁiuo a 50 Ω loaꢀ, LO opunpu bpffeꢂ eiableꢀ

−7

6

50

Rev. 0 | Page 3 of 24

ADRF6603

SYNTHESIZER/PLL SPECIFICATIONS

V_S= 5 V; ambient temperature (T_A) = 25°C; f_REF= 153.6 MHz; f_PFD= 38.4 MHz; high-side LO injection; f_IF= 140 MHz; IIP3 optimized

using capacitor DAC (0x1) and IP3SET (3.3 V), unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SYNTHESIZER SPECIFICATIONS

Fꢂeqpeicy Raige

Fꢁgpꢂe of Meꢂꢁu

Syiuhesꢁzeꢂ snecꢁfꢁcauꢁois ꢂefeꢂeiceꢀ uo 1× LO

Iiueꢂially geieꢂaueꢀ LO

P_{REF_IN}= 0 ꢀdm

2100

2600

MHz

ꢀdc/Hz

−222

Refeꢂeice Snpꢂs

f_REF= 153.6 MHz

f_REF/4

f_REF/2

f_REF

> f_REF

−107

−86

ꢀdc

−83

PHASE NOISE

f_LO= 2100 MHz uo 2600 MHz, f_PFD= 38.4 MHz

1 kHz uo 10 kHz offseu

100 kHz offseu

−90

ꢀdc/Hz

°ꢂms

−99.5

−120

−128

−142

−148

−149

0.4

500 kHz offseu

1 MHz offseu

5 MHz offseu

10 MHz offseu

20 MHz offseu

Iiuegꢂaueꢀ Phase Noꢁse

PFD Fꢂeqpeicy

1 kHz uo 40 MHz ꢁiuegꢂauꢁoi baiꢀwꢁꢀuh

20

12

40

MHz

REFERENCE CHARACTERISTICS

REF_IN Iinpu Fꢂeqpeicy

REF_IN Iinpu Canacꢁuaice

MUXOUT Opunpu Level

REF_IN, MUXOUT nꢁis

160

0.25

MHz

nF

V

%

4

V_OL(lock ꢀeuecu opunpu selecueꢀ)

V_OH(lock ꢀeuecu opunpu selecueꢀ)

2.7

1

MUXOUT Dpuy Cycle

CHARGE PUMP

Ppmn Cpꢂꢂeiu

50

Pꢂogꢂammable uo 250 μA, 500 μA, 750 μA, 1 mA

500

ꢃA

V

Opunpu Comnlꢁaice Raige

2.8

Rev. 0 | Page 4 of 24

ADRF6603

LOGIC INPUT AND POWER SPECIFICATIONS

V_S= 5 V; ambient temperature (T_A) = 25°C; f_REF= 38.4 MHz; f_PFD= 38.4 MHz; high-side LO injection; f_IF= 140 MHz; IIP3 optimized

using capacitor DAC (0x1) and IP3SET (3.3 V), unless otherwise noted.

Table 4.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC INPUTS

CLK, DATA, LE

Iinpu Hꢁgh Voluage, V_INH

Iinpu Low Voluage, V_INL

Iinpu Cpꢂꢂeiu, I_INH/I_INL

Iinpu Canacꢁuaice, C_IN

POWER SUPPLIES

Voluage Raige

1.4

0

3.3

0.7

V

ꢃA

nF

0.1

5

VCC1, VCC2, VCC_LO, VCC_MIX, aiꢀ VCC_V2I nꢁis

PLL oily

Exueꢂial LO moꢀe (ꢁiueꢂial PLL ꢀꢁsableꢀ,

IP3SET nꢁi = 3.3 V)

4.75

5

98

163

5.25

V

mA

Spnnly Cpꢂꢂeiu

Iiueꢂial LO moꢀe (ꢁiueꢂial PLL eiableꢀ,

IP3SET nꢁi = 3.3 V)

Poweꢂ-ꢀowi moꢀe

261

30

mA

TIMING CHARACTERISTICS

VCC2 = 5 V 5ꢁ.

Table 5.

Parameter

Limit

20

10

25

10

20

Unit

Description

u₁

u₂

u₃

u₄

u₅

u₆

u₇

is mꢁi

LE seupn uꢁme

DATA uo CLK seupn uꢁme

DATA uo CLK holꢀ uꢁme

CLK hꢁgh ꢀpꢂauꢁoi

CLK low ꢀpꢂauꢁoi

CLK uo LE seupn uꢁme

LE nplse wꢁꢀuh

Timing Diagram

t₄

t₅

CLK

t₂

t₃

DB2

(CONTROL BIT C3)

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB23 (MSB)

t₁

DB22

DATA

LE

t₇

t₆

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 24

ADRF6603

ABSOLUTE MAXIMUM RATINGS

Table 6.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

Spnnly Voluage, VCC1, VCC2, VCC_LO,

VCC_MIX, VCC_V2I

−0.5 V uo +5.5 V

Dꢁgꢁual I/O, CLK, DATA, LE

IFP, IFN

RF_IN

−0.3 V uo +3.6 V

−0.3 V uo VCC + 0.3 V

18 ꢀdm

θ_JA(Exnoseꢀ Paꢀꢀle Solꢀeꢂeꢀ Dowi)

Maxꢁmpm Jpicuꢁoi Temneꢂaupꢂe

Oneꢂauꢁig Temneꢂaupꢂe Raige

Suoꢂage Temneꢂaupꢂe Raige

35°C/W

150°C

−40°C uo +85°C

−65°C uo +150°C

ESD CAUTION

Rev. 0 | Page 6 of 24

ADRF6603

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

VCC1

DECL3P3

CP

1

2

30 GND

INDICATOR

29 IP3SET

28 GND

3

GND

27 VCC_V2I

4

ADRF6603

R

RF

5

26

25

SET

IN

REF_IN

6

GND

TOP VIEW

7

24 GND

GND

MUXOUT

DECL2P5

VCC2

(Not to Scale)

8

23 GND

9

22 VCC_MIX

21

10

GND

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A

LOW IMPEDANCE GROUND PLANE.

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic Description

1

VCC1

Poweꢂ Spnnly foꢂ uhe 3.3 V LDO. Poweꢂ spnnly voluage ꢂaige ꢁs 4.75 V uo 5.25 V. Each noweꢂ spnnly nꢁi

shoplꢀ be ꢀecopnleꢀ wꢁuh a 100 nF canacꢁuoꢂ aiꢀ a 0.1 ꢃF canacꢁuoꢂ locaueꢀ close uo uhe nꢁi.

2

3

DECL3P3

CP

Decopnlꢁig Noꢀe foꢂ 3.3 V LDO. Coiiecu a 0.1 ꢃF canacꢁuoꢂ beuweei uhꢁs nꢁi aiꢀ gꢂopiꢀ.

Chaꢂge Ppmn Opunpu Pꢁi. Coiiecu uo VTUNE uhꢂopgh uhe loon fꢁlueꢂ.

Gꢂopiꢀ. Coiiecu uhese nꢁis uo a low ꢁmneꢀaice gꢂopiꢀ nlaie.

4, 7, 11, 15, 20, GND

21, 23, 24, 25,

28, 30, 31, 35

5

R_SET

Chaꢂge Ppmn Cpꢂꢂeiu. The iomꢁial chaꢂge npmn cpꢂꢂeiu cai be seu uo 250 ꢃA, 500 ꢃA, 750 ꢃA, oꢂ 1 mA psꢁig

dꢁu Dd11 aiꢀ dꢁu Dd10 ꢁi Regꢁsueꢂ 4 aiꢀ by seuuꢁig dꢁu Dd18 uo 0 (ꢁiueꢂial ꢂefeꢂeice cpꢂꢂeiu). Ii uhꢁs moꢀe,

io exueꢂial R_SETꢁs ꢂeqpꢁꢂeꢀ. If dꢁu Dd18 ꢁs seu uo 1, uhe fopꢂ iomꢁial chaꢂge npmn cpꢂꢂeius (I_NOMINAL) cai be

exueꢂially aꢀjpsueꢀ accoꢂꢀꢁig uo uhe followꢁig eqpauꢁoi:

217.4 × I

⎛

⎜

⎝

⎞

⎟

⎠

CP

R_SET

=

− 37.8 Ω

I_NOMINAL

6

8

REF_IN

MUXOUT

Refeꢂeice Iinpu. Nomꢁial ꢁinpu level ꢁs 1 V n-n. Iinpu ꢂaige ꢁs 12 MHz uo 160 MHz.

Mpluꢁnlexeꢂ Opunpu. Thꢁs opunpu cai be nꢂogꢂammeꢀ uo nꢂovꢁꢀe uhe ꢂefeꢂeice opunpu sꢁgial oꢂ uhe lock ꢀeuecu

sꢁgial. The opunpu ꢁs selecueꢀ by nꢂogꢂammꢁig uhe annꢂonꢂꢁaue ꢂegꢁsueꢂ.

9

10

DECL2P5

VCC2

Decopnlꢁig Noꢀe foꢂ 2.5 V LDO. Coiiecu a 0.1 ꢃF canacꢁuoꢂ beuweei uhꢁs nꢁi aiꢀ gꢂopiꢀ.

Poweꢂ Spnnly foꢂ uhe 2.5 V LDO. Poweꢂ spnnly voluage ꢂaige ꢁs 4.75 V uo 5.25 V. Each noweꢂ spnnly nꢁi

shoplꢀ be ꢀecopnleꢀ wꢁuh a 100 nF canacꢁuoꢂ aiꢀ a 0.1 ꢃF canacꢁuoꢂ locaueꢀ close uo uhe nꢁi.

12

13

DATA

CLK

Seꢂꢁal Daua Iinpu. The seꢂꢁal ꢀaua ꢁinpu ꢁs loaꢀeꢀ MSd fꢁꢂsu; uhe uhꢂee LSds aꢂe uhe coiuꢂol bꢁus.

Seꢂꢁal Clock Iinpu. The seꢂꢁal clock ꢁinpu ꢁs pseꢀ uo clock ꢁi uhe seꢂꢁal ꢀaua uo uhe ꢂegꢁsueꢂs. The ꢀaua ꢁs laucheꢀ

ꢁiuo uhe 24-bꢁu shꢁfu ꢂegꢁsueꢂ oi uhe CLK ꢂꢁsꢁig eꢀge. Maxꢁmpm clock fꢂeqpeicy ꢁs 20 MHz.

14

16

LE

Loaꢀ Eiable. Whei uhe LE ꢁinpu nꢁi goes hꢁgh, uhe ꢀaua suoꢂeꢀ ꢁi uhe shꢁfu ꢂegꢁsueꢂs ꢁs loaꢀeꢀ ꢁiuo oie of uhe

eꢁghu ꢂegꢁsueꢂs. The ꢂelevaiu lauch ꢁs selecueꢀ by uhe uhꢂee coiuꢂol bꢁus of uhe 24-bꢁu woꢂꢀ.

PLL Eiable. Swꢁuch beuweei ꢁiueꢂial PLL aiꢀ exueꢂial LO ꢁinpu. Whei uhꢁs nꢁi ꢁs logꢁc hꢁgh, uhe mꢁxeꢂ LO ꢁs

apuomauꢁcally swꢁucheꢀ uo uhe ꢁiueꢂial PLL aiꢀ uhe ꢁiueꢂial PLL ꢁs noweꢂeꢀ pn. Whei uhꢁs nꢁi ꢁs logꢁc low, uhe

ꢁiueꢂial PLL ꢁs noweꢂeꢀ ꢀowi aiꢀ uhe exueꢂial LO ꢁinpu ꢁs ꢂopueꢀ uo uhe mꢁxeꢂ LO ꢁinpus. The SPI cai also be

pseꢀ uo swꢁuch moꢀes.

PLL_EN

17, 34

VCC_LO

Poweꢂ Spnnly. Poweꢂ spnnly voluage ꢂaige ꢁs 4.75 V uo 5.25 V. Each noweꢂ spnnly nꢁi shoplꢀ be ꢀecopnleꢀ

wꢁuh a 100 nF canacꢁuoꢂ aiꢀ a 0.1 ꢃF canacꢁuoꢂ locaueꢀ close uo uhe nꢁi.

18, 19

22

IFP, IFN

VCC_MIX

Mꢁxeꢂ IF Opunpus. These opunpus shoplꢀ be nplleꢀ uo VCC wꢁuh RF chokes.

Poweꢂ Spnnly. Poweꢂ spnnly voluage ꢂaige ꢁs 4.75 V uo 5.25 V. Each noweꢂ spnnly nꢁi shoplꢀ be ꢀecopnleꢀ

wꢁuh a 100 nF canacꢁuoꢂ aiꢀ a 0.1 ꢃF canacꢁuoꢂ locaueꢀ close uo uhe nꢁi.

26

RF_IN

RF Iinpu (Sꢁigle-Eiꢀeꢀ, 50 Ω).

Rev. 0 | Page 7 of 24

ADRF6603

Pin No.

Mnemonic Description

27

VCC_V2I

Poweꢂ Spnnly. Poweꢂ spnnly voluage ꢂaige ꢁs 4.75 V uo 5.25 V. Each noweꢂ spnnly nꢁi shoplꢀ be ꢀecopnleꢀ

wꢁuh a 100 nF canacꢁuoꢂ aiꢀ a 0.1 ꢃF canacꢁuoꢂ locaueꢀ close uo uhe nꢁi.

Coiiecu a ꢂesꢁsuoꢂ fꢂom uhꢁs nꢁi uo a +5 V spnnly uo aꢀjpsu IIP3. Noꢂmally leave onei.

No Coiiecuꢁoi.

29

32, 33

36

IP3SET

NC

LODRV_EN LO Dꢂꢁveꢂ Eiable. Togeuheꢂ wꢁuh Pꢁi 16 (PLL_EN), uhꢁs ꢀꢁgꢁual ꢁinpu nꢁi ꢀeueꢂmꢁies wheuheꢂ uhe LOP aiꢀ LON

nꢁis oneꢂaue as ꢁinpus oꢂ opunpus. LOP aiꢀ LON become ꢁinpus ꢁf uhe PLL_EN nꢁi ꢁs low oꢂ ꢁf uhe PLL_EN nꢁi

ꢁs seu hꢁgh wꢁuh uhe PLEN bꢁu (Dd6 ꢁi Regꢁsueꢂ 5) seu uo 0. LOP aiꢀ LON become opunpus ꢁf eꢁuheꢂ uhe LODRV_EN

nꢁi oꢂ uhe LDRV bꢁu (Dd3 ꢁi Regꢁsueꢂ 5) ꢁs seu uo 1 whꢁle uhe PLL_EN nꢁi ꢁs seu hꢁgh. The exueꢂial LO ꢀꢂꢁve

fꢂeqpeicy mpsu be 1× LO. Thꢁs nꢁi shoplꢀ iou be lefu floauꢁig.

37, 38

39

LON, LOP

Local Oscꢁllauoꢂ Iinpu/Opunpu. The ꢁiueꢂially geieꢂaueꢀ 1× LO ꢁs avaꢁlable oi uhese nꢁis. Whei ꢁiueꢂial LO

geieꢂauꢁoi ꢁs ꢀꢁsableꢀ, ai exueꢂial 1× LO cai be annlꢁeꢀ uo uhese nꢁis.

VCO Coiuꢂol Voluage Iinpu. Thꢁs nꢁi ꢁs ꢀꢂꢁvei by uhe opunpu of uhe loon fꢁlueꢂ. The iomꢁial ꢁinpu voluage

ꢂaige oi uhꢁs nꢁi ꢁs 1.5 V uo 2.5 V.

VTUNE

40

EP

DECLVCO

EPAD

Decopnlꢁig Noꢀe foꢂ VCO LDO. Coiiecu a 100 nF canacꢁuoꢂ aiꢀ a 10 ꢃF canacꢁuoꢂ beuweei uhꢁs nꢁi aiꢀ gꢂopiꢀ.

Exnoseꢀ Paꢀꢀle. The exnoseꢀ naꢀꢀle shoplꢀ be solꢀeꢂeꢀ uo a low ꢁmneꢀaice gꢂopiꢀ nlaie.

Rev. 0 | Page 8 of 24

ADRF6603

TYPICAL PERFORMANCE CHARACTERISTICS

CDAC = 0x1, IP3SET = 3.3 V, internally generated LO, RF_IN= −10 dBm, f_IF= 140 MHz, unless otherwise noted.

45

40

35

30

25

20

15

10

5

4

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

3

2

1

0

–1

–2

–3

–4

–5

2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600

LO FREQUENCY (MHz)

Figure 4. Gain vs. LO Frequency

Figure 7. IIP3 vs. LO Frequency, RF_IN= −5 dBm

90

20

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

18

16

14

12

10

8

80

70

60

50

40

30

6

4

2

0

2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600

LO FREQUENCY (MHz)

Figure 5. IIP2 vs. LO Frequency, RF_IN= −5 dBm

Figure 8. IP1dB vs. LO Frequency

20

0

19

18

17

16

15

14

13

12

11

10

–40°C

+25°C

+85°C

–10

+25°C

+85°C

–20

–30

–40

–50

–60

2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600

LO FREQUENCY (MHz)

Figure 6. Noise Figure vs. LO Frequency

Figure 9. LO Feedthrough to IF vs. LO Frequency, LO Output Turned Off

Rev. 0 | Page 9 of 24

ADRF6603

Phase noise measurements made at IF output, unless otherwise noted.

–80

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

–80

–90

1kHz OFFSET

–90

–100

–110

–120

–130

–140

–150

–160

–100

–110

–120

–130

–140

–150

–160

100kHz OFFSET

10kHz OFFSET

LO = 2115.2MHz

LO = 2211.2MHz

LO = 2307.2MHz

LO = 2403.2MHz

LO = 2499.2MHz

LO = 2595.2MHz

1MHz OFFSET

INTERGRATED PHASE NOISE

10MHz OFFSET

2100

2200

2300

2400

2500

2600

1k

10k

100k

1M

10M

100M

LO FREQUENCY (MHz)

OFFSET FREQUENCY (Hz)

Figure 10. PLL Spot Phase Noise at Various Offsets

and Integrated Phase Noise vs. LO Frequency

Figure 12. Phase Noise vs. Offset Frequency and LO Frequency

(LO Frequency Varies from 2100 MHz to 2600 MHz)

–75

–80

2× PFD OFFSET

–85

–90

1× PFD OFFSET

4× PFD OFFSET

–95

–100

–105

–110

0.25× AND

0.5× PFD OFFSET

2100

2200

2300

2400

2500

2600

LO FREQUENCY (MHz)

Figure 11. PLL Reference Spurs vs. LO Frequency

Rev. 0 | Page 10 of 24

ADRF6603

REGISTER STRUCTURE

This section provides the register maps for the ADRF6603. The three LSBs determine the register that is programmed.

REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)

DIVIDE

MODE

RESERVED

INTEGER DIVIDE RATIO

CONTROL BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0)

0

DM

0

DIVIDE MODE

FRACTIONAL (DEFAULT)

INTEGER

1

INTEGER DIVIDE RATIO

ID6

0

ID5

0

ID4

1

ID3

0

ID2

1

ID1

0

ID0

21 (INTEGER MODE ONLY)

1

0

22 (INTEGER MODE ONLY)

0

1

0

1

23 (INTEGER MODE ONLY)

0

1

0

1

24

0

1

0

...

0

...

1

...

1

...

1

...

0

...

0

...

0

...

56 (DEFAULT)

...

1

...

1

...

1

...

0

...

1

...

1

...

1

...

119

120 (INTEGER MODE ONLY)

121 (INTEGER MODE ONLY)

122 (INTEGER MODE ONLY)

123 (INTEGER MODE ONLY)

1

0

1

0

1

0

1

0

1

0

1

Figure 13. Register 0—Integer Divide Control Register Map

REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)

RESERVED

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)

MODULUS VALUE

CONTROL BITS

0

MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0

MODULUS VALUE

1

0

1

2

0

1

0

...

1

...

1

...

0

...

0

...

0

...

0

...

0

...

0

...

0

...

0

...

0

...

1536 (DEFAULT)

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

2047

Figure 14. Register 1—Modulus Divide Control Register Map

Rev. 0 | Page 11 of 24

ADRF6603

REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)

CONTROL BITS

RESERVED

FRACTIONAL VALUE

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2 DB1 DB0

0

FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0)

FRACTIONAL VALUE

FD10

0

FD9

0

FD8

0

FD7

0

FD6

0

FD5

0

FD4

0

FD3

0

FD2

0

FD1

0

FD0

0

1

0

1

...

0

...

1

...

1

...

0

...

0

...

0

...

0

...

0

...

0

...

0

...

0

...

768 (DEFAULT)

...

FRACTIONAL VALUE MUST BE LESS THAN MODULUS

<MDR

Figure 15. Register 2—Fractional Divide Control Register Map

REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)

DITHER

MAGNITUDE

DITHER

ENABLE

DITHER RESTART VALUE

CONTROL BITS

DB23 DB22

DITH1

DB21

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

DITH0

DEN

DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)

DITH1

DITH0 DITHER MAGNITUDE

0

1

15 (DEFAULT)

7

1

0

1

3

1 (RECOMMENDED)

DEN DITHER ENABLE

0

1

DISABLE

ENABLE (DEFAULT, RECOMMENDED)

DITHER RESTART

VALUE

DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0

0x00001 (DEFAULT)

0

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

1

...

0x1FFFF

Figure 16. Register 3—Σ-Δ Modulator Dither Control Register Map

Rev. 0 | Page 12 of 24

ADRF6603

REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)

CP

PFD ANTI

REF OUPUT

MUX SELECT

INPUT REF

PATH

PFD

POL

PFD PHASE OFFSET

MULTIPLIER

CP

CURRENT

REF

PFD EDGE BACKLASH

CONTROL BITS

CURRENT SRC CONTROL

DELAY

SOURCE

DB23 DB22 DB21 DB20 DB19

RMS2 RMS1 RMS0 RS1 RS0

DB18

CPM

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)

PFD ANTI BACKLASH

PAB0 PAB1

DELAY

0

1

0

1

0

1

0ns (DEFAULT)

0.5ns

0.75ns

0.9ns

REFERENCE PATH EDGE

SENSITIVITY

PE0

0

1

FALLING EDGE

RISING EDGE (DEFAULT)

DIVIDER PATH EDGE

SENSITIVITY

PE1

0

1

FALLING EDGE

RISING EDGE (DEFAULT)

CHARGE PUMP CONTROL

CPC1 CPC0

BOTH ON

PUMP DOWN

PUMP UP

0

1

0

1

0

1

TRISTATE (DEFAULT)

CPS CHARGE PUMP CONTROL SOURCE

0

1

CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL)

CONTROL FROM PFD (DEFAULT)

CPP1 CPP0 CHARGE PUMP CURRENT

250µA

500µA (DEFAULT)

750µA

0

1

0

1

0

1

1000µA

PFD PHASE OFFSET MULTIPLIER

CPB4 CPB3 CPB2 CPB1 CPB0

0 × 22.5°/I

CPMULT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 × 22.5°/I

CPMULT

6 × 22.5°/I

CPMULT

(RECOMMENDED)

(DEFAULT)

10 × 22.5°/I

16 × 22.5°/I

31 × 22.5°/I

CPMULT

CPBD PFD PHASE OFFSET POLARITY

0

1

NEGATIVE

POSITIVE (DEFAULT)

CHARGE PUMP CURRENT

REFERENCE SOURCE

CPM

INTERNAL (DEFAULT)

EXTERNAL

0

1

INPUT REFERENCE

PATH SOURCE

RS0 RS1

2× REFIN

REFIN (DEFAULT)

0.5× REFIN

0

1

0

1

0

1

0.25× REFIN

RMS2 RMS1 RMS0 REF OUTPUT MUX SELECT

LOCK DETECT (DEFAULT)

VPTAT

REFIN (BUFFERED)

0.5× REFIN (BUFFERED)

2× REFIN (BUFFERED)

TRISTATE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

RESERVED

Figure 17. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map

Rev. 0 | Page 13 of 24

ADRF6603

REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)

PLL

EN

LO

DIV1

LO

EXT

LO

DRV

CAP DAC

RES

CONTROL BITS

RESERVED

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7

DB6

DB5

DB4

LXL

DB3 DB2 DB1 DB0

LDRV C3(1) C2(0) C1(1)

0

CD3 CD2 CD1 CD0

CAPACITOR DAC

0

PLEN LDV1

LO OUTPUT DRIVER

LDRV

CD3

CD2

CD1

CD0 CONTROL FOR IIP3

OPTIMIZATION

ENABLE

DRIVER OFF (DEFAULT)

DRIVER ON

0

1

MIN

MAX

0

1

0

1

0

1

0

1

EXTERNAL LO DRIVE

ENABLE (PIN 37, PIN 38)

LXL

INTERNAL LO OUTPUT (DEFAULT)

EXTERNAL LO INPUT

0

1

LDV1 DIVIDE-BY-2 IN LO CHAIN ENABLE

DIVIDE BY 1

DIVIDE BY 2 (DEFAULT)

0

1

PLEN PLL ENABLE

DISABLE

ENABLE (DEFAULT)

0

1

Figure 18. Register 5—PLL Enable and LO Path Control Register Map

REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)

CHARGE

PUMP

3.3V

LDO

VCO

BW SW

CTRL

VCO LDO VCO

VCO

CONTROL BITS

DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VCO BAND SELECT FROM SPI

RESERVED

VCO AMPLITUDE

ENABLE ENABLE SWITCH

ENABLE ENABLE

DB23 DB22 DB21 DB20

DB19

L3EN

DB18

DB17

DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

0

CPEN

LVEN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)

CHARGE PUMP ENABLE

CPEN

VC[5:0] VCO AMPLITUDE

VBS[5:0] VCO BAND SELECT FROM SPI

DISABLE

ENABLE (DEFAULT)

0x00

….

0

0x00

0x01

0

1

….

DEFAULT 0x20

….

0x18

….

0x2B

….

24 (DEFAULT)

….

43

….

0x3F

L3EN 3.3V LDO ENABLE

VBSRC VCO BW CAL AND SW SOURCE CONTROL

0

1

DISABLE

ENABLE (DEFAULT)

0x3F

63 (RECOMMENDED)

0

1

BAND CAL (DEFAULT)

SPI

VCO SW VCO SWITCH CONTROL FROM SPI

LVEN VCO LDO ENABLE

REGULAR (DEFAULT)

BAND CAL

0

1

0

1

DISABLE

ENABLE (DEFAULT)

VCO EN VCO ENABLE

0

1

DISABLE

ENABLE (DEFAULT)

Figure 19. Register 6—VCO Control and VCO Enable Register Map

REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)

MIXER

B_EN

RESERVED

CONTROL BITS

RES XVCO

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

XVCO MBE C3(1) C2(1) C1(1)

0

MBE MIXER BIAS ENABLE

DISABLE

ENABLE (DEFAULT)

0

1

EXTERNAL VCO

XVCO

INTERNAL VCO (DEFAULT)

EXTERNAL VCO

0

1

Figure 20. Register 7—Mixer Bias Enable and External VCO Enable Register Map

Rev. 0 | Page 14 of 24

ADRF6603

THEORY OF OPERATION

The ADRF6603 integrates a high performance downconverting

mixer with a state-of-the-art fractional-N PLL. The PLL also inte-

grates a low noise VCO. The SPI port allows the user to control the

fractional-N PLL functions and the mixer optimization functions,

as well as allowing for an externally applied LO or VCO.

Table 8. ADRF6603 Register Functions

Register

Function

Regꢁsueꢂ 0

Regꢁsueꢂ 1

Regꢁsueꢂ 2

Regꢁsueꢂ 3

Regꢁsueꢂ 4

Regꢁsueꢂ 5

Regꢁsueꢂ 6

Regꢁsueꢂ 7

Iiuegeꢂ ꢀꢁvꢁꢀe coiuꢂol foꢂ uhe PLL

Moꢀplps ꢀꢁvꢁꢀe coiuꢂol foꢂ uhe PLL

Fꢂacuꢁoial ꢀꢁvꢁꢀe coiuꢂol foꢂ uhe PLL

Σ-Δ moꢀplauoꢂ ꢀꢁuheꢂ coiuꢂol

PLL chaꢂge npmn, PFD, ꢂefeꢂeice nauh coiuꢂol

PLL eiable aiꢀ LO nauh coiuꢂol

The mixer core within the ADRF6603 is the next generation of

an industry leading family of mixers from Analog Devices, Inc.

The RF input is converted to a current and then mixed down to

IF using high performance NPN transistors. The mixer output

currents are transformed to a differential output. The high perfor-

mance active mixer core results in an exceptional IIP3 and IP1dB,

with a very low output noise floor for excellent dynamic range.

Over the specified frequency range, the ADRF6603 typically

provides an IF input P1dB of 14.6 dBm and an IIP3 of 27 dBm.

VCO coiuꢂol aiꢀ VCO eiable

Mꢁxeꢂ bꢁas eiable aiꢀ exueꢂial VCO eiable

Note that internal calibration for the PLL must be run when the

ADRF6603 is initialized at a given frequency. This calibration is

run automatically whenever Register 0, Register 1, or Register 2 is

programmed. Because the other registers affect PLL performance,

Register 0, Register 1, and Register 2 should always be programmed

last and in this order: Register 0, Register 1, Register 2.

Improved performance at specific frequencies can be achieved

with the use of the internal capacitor DAC (CDAC), which is

programmable via the SPI port, and through the use of a resistor

to a +5 V supply from the IP3SET pin (Pin 29). Adjustment of

the capacitor DAC allows increments in phase shift at internal

nodes in the ADRF6603, thus allowing cancellation of third-

order distortion with no change in supply current. Connecting

a resistor to a +5 V supply from the IP3SET pin increases the

internal mixer core current, thereby improving overall IIP2 and

IIP3, as well as IP1dB. Using the IP3SET pin for this purpose

increases the overall supply current.

To program the frequency of the ADRF6603, the user typically

programs only Register 0, Register 1, and Register 2. However,

if registers other than these are programmed first, a short delay

should be inserted before programming Register 0. This delay

ensures that the VCO band calibration has sufficient time to com-

plete before the final band calibration for Register 0 is initiated.

Software is available on the product page of the Analog Devices

website (www.analog.com) that allows easy programming from

a PC running Windows XP or Vista.

The fractional divide function of the PLL allows the frequency

multiplication value from REF_IN to LO output to be a frac-

tional value rather than be restricted to an integer value as

in traditional PLLs. In operation, this multiplication value is

INT + (FRAC/MOD), where INT is the integer value, FRAC

is the fractional value, and MOD is the modulus value, all

programmable via the SPI port. In other fractional-N PLL

designs, fractional multiplication is achieved by periodically

changing the fractional value in a deterministic way. The

disadvantage of this approach is often spurious components

close to the fundamental signal. In the ADRF6603, a Σ-Δ

modulator is used to distribute the fractional value randomly,

thus significantly reducing the spurious content due to the

fractional function.

INITIALIZATION SEQUENCE

To ensure proper power-up of the ADRF6603, it is important to

reset the PLL circuitry after the VCC supply rail settles to 5 V

0.25 V. Resetting the PLL ensures that the internal bias cells are

properly configured, even under poor supply start-up conditions.

To ensure that the PLL is reset after power-up, follow this

procedure:

1. Disable the PLL by setting the PLEN bit to 0 (Register 5,

Bit DB6).

2. Disable the VCO LDO internal node by setting the LVEN

bit to 0 (Register 6, Bit DB18).

3. After a delay of >100 ms, set the PLEN and LVEN bits to 1.

PROGRAMMING THE ADRF6603

After this procedure, the other registers can be programmed, in

order, from Register 7 to Register 3, and then from Register 0 to

Register 2, as described in the Programming the ADRF6603

section.

The ADRF6603 is programmed via a 3-pin SPI port. The timing

requirements for the SPI port are shown in Figure 2. Eight pro-

grammable registers, each with 24 bits, control the operation of

the device. The register functions are listed in Table 8.

Rev. 0 | Page 15 of 24

ADRF6603

The operation of the LO generation and whether LOP and LON

are inputs or outputs are determined by the logic levels applied

at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3

(LDRV) and Bit DB6 (PLEN) in Register 5. The combination of

externally applied logic and internal bits required for particular

LO functions is given in Table 9.

LO SELECTION LOGIC

The downconverting mixer in the ADRF6603 can be used

without the internal PLL by applying an external differential

LO to Pin 37 and Pin 38 (LON and LOP). In addition, when

using an LO generated by the internal PLL, the LO signal can

be accessed directly at these same pins. This function can be

used for debugging purposes, or the internally generated LO

can be used as the LO for a separate mixer.

Table 9. LO Selection Logic

Pins¹

Register 5 Bits¹

Outputs

LO

Pin 16 (PLL_EN)

Pin 36 (LODRV_EN) Bit DB6 (PLEN)

Bit DB3 (LDRV)

Output Buffer

Dꢁsableꢀ

Eiableꢀ

0

1

X

0

X

1

0

1

0

1

X

0

1

X

Exueꢂial

Iiueꢂial

Eiableꢀ

¹X = ꢀoi’u caꢂe.

Rev. 0 | Page 16 of 24

ADRF6603

APPLICATIONS INFORMATION

shown in Figure 21. The reference signal, or a divided-down

version of the reference signal, can be brought back off chip at

the multiplexer output pin (MUXOUT). A lock detect signal

and a voltage proportional to the ambient temperature can also

be selected on the multiplexer output pin.

BASIC CONNECTIONS FOR OPERATION

Figure 21 shows the schematic for the ADRF6603 evaluation

board. The six power supply pins should be individually

decoupled using 100 pF and 0.1 μF capacitors located as

close as possible to the device. In addition, the internal decou-

pling nodes (DECL3P3, DECL2P5, and DECLVCO) should

be decoupled with the capacitor values shown in Figure 21.

The loop filter is connected between the CP and VTUNE pins.

When connected in this way, the internal VCO is operational.

For information about the loop filter components, see the

Evaluation Board Configuration Options section.

The RF input is internally ac-coupled and needs no external

bias. The IF outputs are open collector, and a bias inductor

is required from these outputs to VCC.

Operation with an external VCO is also possible. In this case,

the loop filter components should be referred to ground. The

output of the loop filter is connected to the input voltage pin of

the external VCO. The output of the VCO is brought back into

the device on the LOP and LON pins, using a balun if necessary.

A peak-to-peak differential swing on RF_INof 1 V (0.353 V rms

for a sine wave input) results in an IF output power of 4.7 dBm.

The reference frequency for the PLL should be from 12 MHz

to 160 MHz and should be applied to the REF_IN pin, which

should be ac-coupled and terminated with a 50 ꢀ resistor as

P1

9-PIN

DSUB

1

2

3

4

5

6

7

8

9

VCC

R36

R19

0Ω

R35

R30

0Ω

R43

0Ω

(0402)

R20

0Ω

10kΩ

(0402)

(0402) (0402)

R48

(0402)

0Ω

(0402)

S2

R47

10kΩ

(0402)

C31

OPEN

(0402)

R44

OPEN

(0402)

VCC

RED

+5V

C32

OPEN

(0402)

R45

OPEN

(0402)

C7

0.1µF

(0402)

C27

0.1µF

(0402)

C25

0.1µF

(0402)

C23

0.1µF

(0402)

C20

0.1µF

(0402)

C19

0.1µF

(0402)

R6

R27

R26

R25

R24

R17

VCC1

RED

R39

OPEN

(0402)

C30

OPEN

(0402)

R42

OPEN

(0402)

0Ω

(0402)

C8

(0402)

C26

C24

C22

C21

C18

100pF

(0402)

100pF

(0402)

S1

OPEN

VCC_LO

VCC_V2I

VCC_MIX

VCC_LO

VCC2

VCC1

34

27

22

17

10

1

16 13 12 14

DECL2P5

C16

R40

9

2

R41

0Ω

(0402)

0Ω

LODRV_EN

C17

C42

R18

(0402)

36

SPI

INTERFACE

100pF

(0402)

0.1µF

(0402)

10µF

(0603)

0Ω

LON

C5

(0402)

37

38

LO IN/OUT

DIVIDER

÷2

4

3

BUFFER

DECL3P3

C12

LOP

1nF

(0402)

C11

0.1µF

(0402)

C41

OPEN

(0603)

5

1

R8

0Ω

(0402)

100pF

(0402)

DIV

BY

2, 1

2:1

MUX

T8

TC1-1-13+

INTEGER

REG

FRACTION

REG

C6

1nF

(0402)

MODULUS

ADRF6603

RF

IN

26

29

RFIN

THIRD-ORDER

R22

FRACTIONAL

C13

1nF

0Ω

VCO

CORE

INTERPOLATOR

(0402)

×2

N COUNTER

21 TO 123

PRESCALER

÷2

REF_IN

(0402)

REF_IN

6

8

R73

MUX

÷2

IP3SET

CHARGE PUMP

250µA,

49.9Ω

(0402)

–

+

C27

PHASE

FREQUENCY

DETECTOR

R27

0Ω

0.1µF

(0402)

500µA (DEFAULT),

750µA,

TEMP

SENSOR

÷4

REFOUT

(0402)

MUXOUT

1000µA

R16

4

7

11 15 20 21 23 24 25 38 30 31 35

5

3

39

40

18

19

0Ω

R

SET

R2

VTUNE DECLVCO IFP

IFN

CP

(0402)

1

2

4

RFOUT

OPEN

(0402)

R37

R43

R62

VCC

+5V

0Ω

R27

3

(0402)

5

(0402)

0Ω

R38

0Ω

(0402)

R9 18kΩ R65 0Ω

CP

TEST

VTUNE

(0402)

C29

0.1µF

(0402)

POINT

R10

1.6kΩ

(0603)

R63

(ORANGE)

OPEN

(0402)

C14

270pF

(0603)

C13

27pF

(0603)

C40

OPEN

(0603)

C15

5.6nF

(1206)

R12

R11

OPEN

(0402)

R1

0Ω

(0402)

C43

10µF

(0603)

C2

OPEN

(0402)

C1

100pF

(0402)

Figure 21. Basic Connections for Operation of the ADRF6603

Rev. 0 | Page 17 of 24

ADRF6603

EVALUATION BOARD

Figure 24 shows the schematic of the RoHS-compliant evalua-

tion board for the ADRF6603. This board has four layers and

was designed using Rogers 4350 hybrid material to minimize

high frequency losses. FR4 material is also adequate if the design

can accept the slightly higher trace loss of this material.

The evaluation board is designed to operate using the internal

VCO of the device (the default configuration) or with an

external VCO. To use an external VCO, R62 and R12 should

be removed. Place 0 ꢀ resistors in R63 and R11. The input of

the external VCO should be connected to the VTUNE SMA

connector, and the external VCO output should be connected

to the LO IN/OUT SMA connector. In addition to these hard-

ware changes, internal register settings must also be changed to

enable operation with an external VCO (see the Register 6—

VCO Control and VCO Enable (Default: 0x1E2106) section).

Additional configuration options for the evaluation board are

described in Table 10.

EVALUATION BOARD CONTROL SOFTWARE

Software to program the ADRF6603 is available for download

from www.analog.com. To install the software, download and

extract the zip file. Then run the following installation file:

ADRF6x0x_3p0p0_XP_install.exe

The evaluation board can be connected to the PC using a PC

parallel port or a USB port. These options are selectable from

the opening menu of the software interface (see Figure 22). The

evaluation board is shipped with a 25-pin parallel port cable

for connection to the PC parallel port.

Figure 22. Control Software Opening Menu

To connect the evaluation board to a USB port, a USB adapter

board (Part No. EVAL-ADF4XXXZ-USB) must be purchased

from www.analog.com. This board connects to the PC using a

standard USB cable with USB mini-connector at one end. An

additional 25-pin male to 9-pin female adapter is required to

mate the ADF4XXXZ-USB board to the 9-pin D-Sub connector

on the ADRF6603 evaluation board.

Figure 23 shows the main menu of the control software with the

default settings displayed.

Rev. 0 | Page 18 of 24

ADRF6603

Figure 23. Main Window of the ADRF6603 Evaluation Board Software

Rev. 0 | Page 19 of 24

ADRF6603

SCHEMATICS AND ARTWORK

2 0 3 7 - 5 4 0 8

W 1 - 4 T C

6

4

3

2

1

0

3

R 4

0

6

R 6

G N D

N I F

D

G N

N C

_ L C O C V

G N

0

P I F

0

3

R 3

O L _ C V C

4

0

R 3

0

3

2

N

L L P _ E

G N D

L E

1

D

R 2

2

3

S2

1

N E _ V R D L O

L O N

S 1

0

K

C L

1

P

E

L O

5

R 3

A T D A

U N V T

G N D

C V O C L D E

0

2

R 6

2

R 7

1

0

2

R 1

6

8 0

D

1

T B

R 7

0

R 1

D N I

R 1

1

8

C 2

0

F U 1 0

7

R 3

0

B B _ C V C

O L _ C V C

F R _ C V C

2

1

9

R 3

D N I

R 1

0

4

Y 1

R 3

0

R 2

Figure 24. Evaluation Board Schematic

Rev. 0 | Page 20 of 24

ADRF6603

Figure 25. Evaluation Board Layout (Bottom)

Figure 26. Evaluation Board Layout (Top)

Rev. 0 | Page 21 of 24

ADRF6603

EVALUATION BOARD CONFIGURATION OPTIONS

Table 10.

Default Condition/

Option Settings

Component

Description

S1, R55, R56, R33

LO selecu. Swꢁuch aiꢀ ꢂesꢁsuoꢂs uo gꢂopiꢀ uhe LODRV_EN nꢁi. The LODRV_EN nꢁi seuuꢁig, ꢁi

combꢁiauꢁoi wꢁuh ꢁiueꢂial ꢂegꢁsueꢂ seuuꢁigs, ꢀeueꢂmꢁies wheuheꢂ uhe LOP aiꢀ LON nꢁis

fpicuꢁoi as ꢁinpus oꢂ opunpus (see uhe LO Selecuꢁoi Logꢁc secuꢁoi foꢂ moꢂe ꢁifoꢂmauꢁoi).

S1 = R55 = onei

(iou ꢁisualleꢀ)

R56 = R33 = 0 Ω

LODRV_EN = 0 V

LO IN/OUT

SMA Coiiecuoꢂ

LO ꢁinpu/opunpu. Ai exueꢂial 1× LO oꢂ 2× LO cai be annlꢁeꢀ uo uhꢁs sꢁigle-eiꢀeꢀ ꢁinpu

coiiecuoꢂ.

LO ꢁinpu

REFIN

SMA Coiiecuoꢂ

Refeꢂeice ꢁinpu. The ꢁinpu ꢂefeꢂeice fꢂeqpeicy foꢂ uhe PLL ꢁs annlꢁeꢀ uo uhꢁs coiiecuoꢂ.

Iinpu ꢁmneꢀaice ꢁs 50 Ω.

REFOUT

SMA Coiiecuoꢂ

Mpluꢁnlexeꢂ opunpu. The REFOUT coiiecuoꢂ coiiecus ꢀꢁꢂeculy uo uhe MUXOUT nꢁi. The

oi-boaꢂꢀ mpluꢁnlexeꢂ cai be nꢂogꢂammeꢀ uo bꢂꢁig opu uhe followꢁig sꢁgials:

REFIN, 2× REFIN, REFIN/2, REFIN/4.

Lock ꢀeuecu

Temneꢂaupꢂe seisoꢂ opunpu voluage.

Lock ꢀeuecu ꢁiꢀꢁcauoꢂ.

CP Tesu Poꢁiu

Chaꢂge npmn uesu noꢁiu. The pifꢁlueꢂeꢀ chaꢂge npmn sꢁgial cai be nꢂobeꢀ au uhꢁs uesu

noꢁiu. Noue uhau uhe CP nꢁi shoplꢀ iou be nꢂobeꢀ ꢀpꢂꢁig cꢂꢁuꢁcal measpꢂemeius spch as

nhase ioꢁse.

R37, C14, R9, R10,

C15, C13, R65, C40

Loon fꢁlueꢂ. Loon fꢁlueꢂ comnoieius.

R11, R12

Loon fꢁlueꢂ ꢂeupꢂi. Whei uhe ꢁiueꢂial VCO ꢁs pseꢀ, uhe loon fꢁlueꢂ comnoieius shoplꢀ be

ꢂeupꢂieꢀ uo Pꢁi 40 (DECLVCO) by ꢁisuallꢁig a 0 Ω ꢂesꢁsuoꢂ ꢁi R12. Whei ai exueꢂial VCO ꢁs pseꢀ,

uhe loon fꢁlueꢂ comnoieius cai be ꢂeupꢂieꢀ uo gꢂopiꢀ by ꢁisuallꢁig a 0 Ω ꢂesꢁsuoꢂ ꢁi R11.

R12 = 0 Ω (0402)

R11 = onei (0402)

R62, R63, VTUNE

SMA Coiiecuoꢂ

Iiueꢂial vs. exueꢂial VCO. Whei uhe ꢁiueꢂial VCO ꢁs eiableꢀ, uhe loon fꢁlueꢂ comnoieius aꢂe

coiiecueꢀ ꢀꢁꢂeculy uo uhe VTUNE nꢁi (Pꢁi 39) by ꢁisuallꢁig a 0 Ω ꢂesꢁsuoꢂ ꢁi R62.

To pse ai exueꢂial VCO, R62 shoplꢀ be lefu onei. A 0 Ω ꢂesꢁsuoꢂ shoplꢀ be ꢁisualleꢀ ꢁi R63,

aiꢀ uhe voluage ꢁinpu of uhe VCO shoplꢀ be coiiecueꢀ uo uhe VTUNE SMA coiiecuoꢂ. The

opunpu of uhe VCO ꢁs bꢂopghu back ꢁiuo uhe PLL vꢁa uhe LO IN/OUT SMA coiiecuoꢂ.

R62 = 0 Ω (0402)

R63 = onei (0402)

R2

R_SETnꢁi. Thꢁs nꢁi ꢁs pipseꢀ aiꢀ shoplꢀ be lefu onei.

R2 = onei (0402)

RFIN SMA Coiiecuoꢂ RF ꢁinpu. The RF ꢁinpu sꢁgial shoplꢀ be annlꢁeꢀ uo uhe RFIN SMA coiiecuoꢂ. The RF ꢁinpu of R3 = R23 = onei (0402)

uhe ADRF6603 ꢁs ac-copnleꢀ, uheꢂefoꢂe, io bꢁas ꢁs iecessaꢂy.

T3

IF opunpu. The ꢀꢁffeꢂeiuꢁal IF opunpu sꢁgials fꢂom uhe ADRF6603 (IFP aiꢀ IFN) aꢂe coiveꢂueꢀ

uo a sꢁigle-eiꢀeꢀ sꢁgial by T3.

Rev. 0 | Page 22 of 24

ADRF6603

OUTLINE DIMENSIONS

6.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

31

40

1

30

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

4.25

4.10 SQ

3.95

5.75

BSC SQ

EXPOSED

PAD

(BOT TOM VIEW)

0.50

0.40

0.30

21

10

20

11

0.25 MIN

4.50

REF

12° MAX

0.80 MAX

0.65 TYP

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SECTION OF THIS DATA SHEET.

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 27. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADRF6603ACPZ-R7

ADRF6603-EVALZ

Temperature Range

Package Description

Package Option

CP-40-1

−40°C uo +85°C

40-Leaꢀ Leaꢀ Fꢂame Chꢁn Scale Package [LFCSP_VQ]

Evalpauꢁoi doaꢂꢀ

¹Z = RoHS Comnlꢁaiu Paꢂu.

Rev. 0 | Page 23 of 24

ADRF6603

NOTES

registered trademarks are the property of their respective owners.

D08547-0-3/10(0)

Rev. 0 | Page 24 of 24


型号：	ADRF6603ACPZ-R7
厂家：	ADI
描述：	2100 MHz to 2600 MHz Rx Mixer with Integrated Fractional-N PLL and VCO 2100 MHz至2600 MHz的接收混频器，集成小数N分频PLL和VCO
文件：	总24页 (文件大小：490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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