ADRF6604 [ADI]
1200 MHz to 3600 MHz Rx Mixer with Integrated Fractional-N PLL and VCO;
| 型号： | ADRF6604 |
| 厂家： | 
ADI |
| 描述： | 1200 MHz to 3600 MHz Rx Mixer with Integrated Fractional-N PLL and VCO |
| 文件： | 总32页 (文件大小：834K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1200 MHz to 3600 MHz Rx Mixer with
Integrated Fractional-N PLL and VCO
ADRF6604
Data Sheet
The PLL can support input reference frequencies from 12 MHz
to 160 MHz. The PFD output controls a charge pump whose
output drives an off-chip loop filter.
FEATURES
Rx mixer with integrated fractional-N PLL
RF input frequency range: 1200 MHz to 3600 MHz
Internal LO frequency range: 2500 MHz to 2900 MHz
Input P1dB: 14.5 dBm
Input IP3: 27.5 dBm
IIP3 optimization via external pin
SSB noise figure
The loop filter output is then applied to an integrated VCO. The
VCO output at 2 × fLO is applied to an LO divider, as well as to a
programmable PLL divider. The programmable PLL divider is
controlled by a sigma-delta (Σ-Δ) modulator (SDM). The modulus
of the SDM can be programmed from 1 to 2047.
IP3SET pin open: 14.3 dB
IP3SET pin at 3.3 V: 15.5 dB
The active mixer converts the single-ended, 50 Ω RF input to
a differential, 200 Ω IF output. The IF output can operate up
to 500 MHz.
Voltage conversion gain: 6.8 dB
Matched 200 Ω IF output impedance
IF 3 dB bandwidth: 500 MHz
Programmable via 3-wire SPI interface
40-lead, 6 mm × 6 mm LFCSP
The ADRF6604 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP with an exposed paddle. Performance is
specified over the −40°C to +85°C temperature range.
APPLICATIONS
Table 1.
Cellular base stations
Internal LO
Range
3 dB RFIN
Balun Range
1 dB RFIN
Balun Range
Part No.
GENERAL DESCRIPTION
ADRF6601 750 MHz
1160 MHz
300 MHz
450 MHz
The ADRF6604 is a high dynamic range active mixer with
integrated phase-locked loop (PLL) and voltage controlled
oscillator (VCO). The PLL/synthesizer uses a fractional-N
PLL to generate a fLO input to the mixer. The reference input
can be divided or multiplied and then applied to the PLL phase
frequency detector (PFD).
2500 MHz
1000 MHz
3100 MHz
1100 MHz
3200 MHz
1200 MHz
3600 MHz
1600 MHz
1350 MHz
2750 MHz
1450 MHz
2850 MHz
1600 MHz
3200 MHz
ADRF6602 1550 MHz
2150 MHz
ADRF6603 2100 MHz
2600 MHz
ADRF6604 2500 MHz
2900 MHz
FUNCTIONAL BLOCK DIAGRAM
VCC1
1
VCC2 VCC_LO VCC_MIX VCC_V2I VCC_LO
NC NC
10
17
22
27
34
32
33
36
LODRV_EN
LON 37
38
ADRF6604
3.3V
LDO
2
9
DECL3P3
INTERNAL LO RANGE
2500MHz TO 2900MHz
BUFFER
BUFFER
2.5V
LDO
DECL2P5
DECLVCO
LOP
VCO
LDO
PLL_EN 16
DIV
2:1
40
BY
2, 1
INTEGER
REG
FRACTION
REG
MUX
12
DATA
MODULUS
SPI
13
14
CLK
LE
INTERFACE
26
29
RF
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
IN
VCO
CORE
IP3SET
×2
N COUNTER
21 TO 123
PRESCALER
÷2
6
8
REF_IN
MUX
÷2
CHARGE PUMP
250µA,
500µA (DEFAULT),
–
+
PHASE
FREQUENCY
DETECTOR
TEMP
SENSOR
÷4
750µA,
1000µA
5
MUXOUT
4
7
11 15 20 21 23 24 25 28 30 31 35
GND
39
18 19
3
R
CP VTUNE IFP IFN
SET
Figure 1.
Rev. B
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ADRF6604
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 3—Σ-Δ Modulator Dither Control
(Default: 0x10000B)................................................................... 17
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
RF Specifications .......................................................................... 3
Synthesizer/PLL Specifications................................................... 4
Logic Input and Power Specifications ....................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
RF Frequency Sweep .................................................................... 9
IF Frequency Sweep ................................................................... 10
Spurious Performance................................................................ 15
Register Structure ........................................................................... 16
Register 0—Integer Divide Control (Default: 0x0001C0)..... 16
Register 1—Modulus Divide Control (Default: 0x003001) ........16
Register 2—Fractional Divide Control (Default: 0x001802) ......17
Register 4—PLL Charge Pump, PFD, and Reference Path
Control (Default: 0x0AA7E4)................................................... 18
Register 5—PLL Enable and LO Path Control
(Default: 0x0000E5) ................................................................... 19
Register 6—VCO Control and VCO Enable
(Default: 0x1E2106) ................................................................... 19
Register 7—Mixer Bias Enable and External VCO Enable
(Default: 0x000007).................................................................... 19
Theory of Operation ...................................................................... 20
Programming the ADRF6604................................................... 20
Initialization Sequence .............................................................. 20
LO Selection Logic ..................................................................... 21
Applications Information.............................................................. 22
Basic Connections for Operation............................................. 22
AC Test Fixture ............................................................................... 23
Evaluation Board ............................................................................ 24
Evaluation Board Control Software......................................... 24
Schematic and Artwork............................................................. 26
Evaluation Board Configuration Options............................... 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
1/14—Rev. A to Rev. B
6/10—Revision 0: Initial Version
Change to Product Title................................................................... 1
Updated Outline Dimensions (Lead-to-Pad Dimension)......... 29
5/11—Rev. 0 to Rev. A
Changes to Features and General Description Sections.............. 1
Changes to Table 2............................................................................ 3
Changes to Synthesizer Specifications Parameter and to Phase
Noise Parameter, Table 3 ............................................................. 4
Changes to Power Supplies Parameter, Table 4 ............................ 4
Replaced Typical Performance Characteristics Section;
Renumbered Sequentially ........................................................... 9
Added Spurious Performance Section......................................... 15
Change to Figure 41 ....................................................................... 17
Changes to Figure 42...................................................................... 18
Changes to Theory of Operation Section.................................... 20
Changes to Figure 46...................................................................... 22
Added AC Test Fixture Section and Figure 47 ........................... 23
Changes to Evaluation Board Control Software Section and
Figure 48 ...................................................................................... 24
Changes to Figure 49...................................................................... 25
Rev. B | Page 2 of 32
Data Sheet
ADRF6604
SPECIFICATIONS
RF SPECIFICATIONS
VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fPFD = 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized
using CDAC = 0xC and IP3SET = 3.3 V, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
2900
3600
Unit
MHz
MHz
INTERNAL LO FREQUENCY RANGE
RF INPUT FREQUENCY RANGE
RF INPUT AT 2360 MHz
Input Return Loss
2500
1200
3 dB RF input range
Relative to 50 Ω (can be improved with external match)
−16.2
14.6
54.5
28
14.8
13.9
−43
dB
Input P1dB
dBm
dBm
dBm
dB
dB
dBm
Second-Order Intercept (IIP2)
Third-Order Intercept (IIP3)
Single-Sideband Noise Figure
−5 dBm each tone (10 MHz spacing between tones)
−5 dBm each tone (10 MHz spacing between tones)
IP3SET = 3.3 V
IP3SET = open
At 1× LO frequency, 50 Ω termination at the RF port
LO-to-IF Leakage
RF INPUT AT 2560 MHz
Input Return Loss
Input P1dB
Second-Order Intercept (IIP2)
Third-Order Intercept (IIP3)
Single-Sideband Noise Figure
Relative to 50 Ω (can be improved with external match)
−21
14.5
58.2
27.6
14.9
14.2
−42
dB
dBm
dBm
dBm
dB
dB
dBm
−5 dBm each tone (10 MHz spacing between tones)
−5 dBm each tone (10 MHz spacing between tones)
IP3SET = 3.3 V
IP3SET = open
At 1× LO frequency, 50 Ω termination at the RF port
LO-to-IF Leakage
RF INPUT AT 2760 MHz
Input Return Loss
Input P1dB
Second-Order Intercept (IIP2)
Third-Order Intercept (IIP3)
Single-Sideband Noise Figure
Relative to 50 Ω (can be improved with external match)
−20
14.4
64.4
27
15.5
14.6
−44
dB
dBm
dBm
dBm
dB
dB
dBm
−5 dBm each tone (10 MHz spacing between tones)
−5 dBm each tone (10 MHz spacing between tones)
IP3SET = 3.3 V
IP3SET = open
At 1× LO frequency, 50 Ω termination at the RF port
LO-to-IF Leakage
IF OUTPUT
Voltage Conversion Gain
IF Bandwidth
Output Common-Mode Voltage
Gain Flatness
Gain Variation
Output Swing
Output Return Loss
LO INPUT/OUTPUT (LOP, LON)
Frequency Range
Output Level (LO as Output)
Input Level (LO as Input)
Input Impedance
Differential 200 Ω load
Small signal 3 dB bandwidth
External pull-up balun or inductors required
Over frequency range, any 5 MHz/50 MHz
Over full temperature range
6.8
500
5
0.2/0.5
1.3
2
dB
MHz
V
dB
dB
Differential 200 Ω load
Relative to 200 Ω
V p-p
dB
−15
Externally applied 1× LO input, internal PLL disabled
250
−6
6000
+6
MHz
dBm
dBm
Ω
1× LO into a 50 Ω load, LO output buffer enabled
−9
0
50
Rev. B | Page 3 of 32
ADRF6604
Data Sheet
SYNTHESIZER/PLL SPECIFICATIONS
VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fREF power = 4 dBm, fPFD = 38.4 MHz, high-side LO injection,
fIF = 140 MHz, IIP3 optimized using CDAC = 0xC and IP3SET = 3.3 V, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SYNTHESIZER SPECIFICATIONS
Frequency Range
Figure of Merit1
Synthesizer specifications referenced to 1× LO
Internally generated LO
PREF_IN = 0 dBm
2500
2900
MHz
dBc/Hz/Hz
−221.4
Reference Spurs
fPFD = 38.4 MHz
fPFD/4
fPFD
>fPFD
−107
−82
−80
dBc
dBc
dBc
PHASE NOISE
fLO = 2500 MHz to 2900 MHz, fPFD = 38.4 MHz
1 kHz to 10 kHz offset
100 kHz offset
−87.7
−96
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
500 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
−117
−126
−142
−148
−150
0.69
20 MHz offset
Integrated Phase Noise
PFD Frequency
1 kHz to 40 MHz integration bandwidth
20
12
40
MHz
REFERENCE CHARACTERISTICS
REF_IN Input Frequency
REF_IN Input Capacitance
MUXOUT Output Level
REF_IN, MUXOUT pins
160
0.25
MHz
pF
V
4
VOL (lock detect output selected)
VOH (lock detect output selected)
2.7
V
MUXOUT Duty Cycle
CHARGE PUMP
50
%
Pump Current
Output Compliance Range
Programmable to 250 µA, 500 µA, 750 µA, 1 mA
500
µA
V
1
2.8
1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10 log 10(fPFD) – 20 log 10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz,
and fREF power = 10 dBm (500 V/µs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset.
LOGIC INPUT AND POWER SPECIFICATIONS
VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fPFD = 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized
using CDAC = 0xC and IP3SET = 3.3 V, unless otherwise noted.
Table 4.
Parameter
Test Conditions/Comments
Min
Typ Max Unit
LOGIC INPUTS
CLK, DATA, LE
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
POWER SUPPLIES
Voltage Range
1.4
0
3.3
0.7
V
V
µA
pF
0.1
5
VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins
4.75
5
5.25
V
Supply Current
PLL only
96
mA
mA
mA
mA
mA
External LO mode (internal PLL disabled, IP3SET pin = 3.3 V, LO output buffer off)
Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on)
Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off)
Power-down mode
164
274
260
30
Rev. B | Page 4 of 32
Data Sheet
ADRF6604
TIMING CHARACTERISTICS
VCC2 = 5 V 5%.
Table 5.
Parameter
Limit
20
10
10
25
25
10
20
Unit
Description
t1
t2
t3
t4
t5
t6
t7
ns min
ns min
ns min
ns min
ns min
ns min
ns min
LE setup time
DATA-to-CLK setup time
DATA-to-CLK hold time
CLK high duration
CLK low duration
CLK-to-LE setup time
LE pulse width
Timing Diagram
t4
t5
CLK
t2
t3
DB2
(CONTROL BIT C3)
DB1
DB0 (LSB)
(CONTROL BIT C1)
DB23 (MSB)
t1
DB22
DATA
LE
(CONTROL BIT C2)
t6
t7
Figure 2. Timing Diagram
Rev. B | Page 5 of 32
ADRF6604
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage, VCC1, VCC2, VCC_LO,
VCC_MIX, VCC_V2I
−0.5 V to +5.5 V
Digital I/O, CLK, DATA, LE, LODRV_EN,
PLL_EN
−0.3 V to +3.6 V
VTUNE
IFP, IFN
RFIN
0 V to 3.3 V
−0.3 V to VCC_V2I + 0.3 V
16 dBm
ESD CAUTION
LOP, LON, REF_IN
13 dBm
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
35°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Rev. B | Page 6 of 32
Data Sheet
ADRF6604
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
VCC1
DECL3P3
CP
1
2
30 GND
INDICATOR
29 IP3SET
28 GND
3
GND
27 VCC_V2I
4
ADRF6604
R
RF
5
26
25
SET
IN
REF_IN
6
GND
TOP VIEW
7
24 GND
GND
MUXOUT
DECL2P5
VCC2
(Not to Scale)
8
23 GND
9
22 VCC_MIX
21
10
GND
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A
LOW IMPEDANCE GROUND PLANE.
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description
1
VCC1
Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
2
3
DECL3P3
CP
Decoupling Node for 3.3 V LDO. Connect a 0.1 µF capacitor between this pin and ground.
Charge Pump Output Pin. Connect to VTUNE through the loop filter.
Ground. Connect these pins to a low impedance ground plane.
4, 7, 11, 15, 20, GND
21, 23, 24, 25,
28, 30, 31, 35
5
RSET
Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA, 750 µA, or 1 mA using
Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In
this mode, no external RSET is required. If Bit DB18 is set to 1, the four nominal charge pump currents (INOMINAL
)
can be externally adjusted according to the following equation:
217.4 × I
CP
RSET
=
− 37.8 Ω
INOMINAL
6
8
REF_IN
Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin is internally dc-
biased and should be ac-coupled.
Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect
signal. The output is selected by programming the appropriate register.
MUXOUT
9
10
DECL2P5
VCC2
Decoupling Node for 2.5 V LDO. Connect a 0.1 µF capacitor between this pin and ground.
Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
12
13
DATA
CLK
Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits.
Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. The maximum clock frequency is 20 MHz.
14
16
LE
Load Enable. When the LE input pin goes high, the data stored in the shift register is loaded into one of the
eight registers. The relevant latch is selected by the three control bits of the 24-bit word.
PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is
automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the
internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be
used to switch modes.
PLL_EN
17, 34
18, 19
VCC_LO
IFP, IFN
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
Mixer IF Outputs. These outputs should be pulled to VCC_MIX with RF chokes.
Rev. B | Page 7 of 32
ADRF6604
Data Sheet
Pin No.
Mnemonic Description
22
VCC_MIX
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
26
27
RFIN
VCC_V2I
RF Input. Single-ended, 50 Ω.
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
29
32, 33
36
IP3SET
NC
Connect a resistor from this pin to a 5 V supply to adjust IIP3. Normally leave open.
NC = No Connect. Do not connect to this pin.
LODRV_EN LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON pins
operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set
high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN pin
or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. The external LO drive frequency
must be 1× LO. This pin has an internal 100 kΩ pull-down resistor.
37, 38
39
LON, LOP
Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO
generation is disabled, an external 1× LO can be applied to these pins.
VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage
range on this pin is 1.5 V to 2.5 V.
VTUNE
40
DECLVCO
EPAD
Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 µF capacitor between this pin and ground.
Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Rev. B | Page 8 of 32
Data Sheet
ADRF6604
TYPICAL PERFORMANCE CHARACTERISTICS
RF FREQUENCY SWEEP
CDAC = 0xC, internally generated high-side LO, RFIN = −5 dBm, fIF = 140 MHz, unless otherwise noted.
5
35
T
T
T
= +85°C
= +25°C
= –40°C
IP3SET = OPEN
IP3SET = 3.3V
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
34
33
32
31
30
29
28
27
26
25
24
23
22
IP3SET = OPEN
IP3SET = 3.3V
4
3
2
1
0
–1
–2
–3
–4
–5
21
20
2360
2410
2460
2510
2560
2610
2660
2710 2760
2360
2410
2460
2510
2560
2610
2660
2710 2760
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 7. Input IP3 vs. RF Frequency
Figure 4. Gain vs. RF Frequency
18
17
16
15
14
13
12
11
10
9
90
80
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
IP3SET = OPEN
IP3SET = 3.3V
T
T
T
= +85°C
= +25°C
= –40°C
IP3SET = OPEN
IP3SET = 3.3V
A
A
A
70
60
50
40
30
8
2360
2410
2460
2510
2560
2610
2660
2710 2760
2360
2410
2460
2510
2560
2610
2660
2710 2760
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 5. Input IP2 vs. RF Frequency
Figure 8. Input P1dB vs. RF Frequency
20
18
16
14
12
10
8
6
4
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
IP3SET = OPEN
IP3SET = 3.3V
2
0
2360
2410
2460
2510
2560
2610
2660
2710 2760
RF FREQUENCY (MHz)
Figure 6. Noise Figure vs. RF Frequency
Rev. B | Page 9 of 32
ADRF6604
Data Sheet
IF FREQUENCY SWEEP
CDAC = 0xC, internally generated swept low-side LO, fRF = 2490 MHz, RFIN = −5 dBm, unless otherwise noted.
5
45
40
35
30
25
20
15
10
5
T
T
T
= +85°C
= +25°C
= –40°C
IP3SET = OPEN
IP3SET = 3.3V
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
IP3SET = OPEN
IP3SET = 3.3V
4
3
2
1
0
–1
–2
–3
–4
–5
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 9. Gain vs. IF Frequency
Figure 12. Input IP3 vs. IF Frequency, RFIN = −5 dBm
90
80
70
20
T
T
T
= +85°C
= +25°C
= –40°C
IP3SET = OPEN
IP3SET = 3.3V
A
A
A
18
16
14
12
10
8
60
50
6
4
40
30
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
IP3SET = OPEN
IP3SET = 3.3V
2
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 10. Input IP2 vs. IF Frequency, RFIN = −5 dBm
Figure 13. Input P1dB vs. IF Frequency
20
18
16
14
12
10
8
6
4
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
IP3SET = OPEN
IP3SET = 3.3V
2
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
IF FREQUENCY (MHz)
Figure 11. Noise Figure vs. IF Frequency
Rev. B | Page 10 of 32
Data Sheet
ADRF6604
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
T
T
T
= +85°C
= +25°C
= –40°C
IP3SET = OPEN
IP3SET = 3.3V
A
A
A
–5
–10
–15
–20
–25
–30
–35
–40
–45
–10
–11
–12
–13
–50
–55
–60
–14
–15
2500
2550
2600
2650
2700
2750
2800
2850 2900
2300
2400
2500
2600
2700
2800
2900
3000 3100
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 14. LO-to-IF Feedthrough vs. LO Frequency,
LO Output Turned Off, CDAC = 0xC
Figure 17. LO Input Return Loss vs. LO Frequency (Including TC1-1-13 Balun)
–20
–25
–30
350
300
250
200
150
100
50
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
IP3SET = OPEN
IP3SET = 3.3V
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
RESISTANCE
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
CAPACITANCE
–85
–90
0
2500
2550
2600
2650
2700
2750
2800
2850 2900
50
100
150
200
250
300
350
400
450
500
LO FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 18. IF Differential Output Impedance (R Parallel, C Equivalent)
Figure 15. LO-to-RF Leakage vs. LO Frequency, LO Output Turned Off
0
–5
35
IP3SET = OPEN
IP3SET = 3.3V
–10
–15
–20
–25
–30
–35
–40
–45
–50
30
25
20
15
10
2300
2400
2500
2600
2700
2800
2900
3000 3100
–60
–50
–40
–30
–20
–10
0
RF FREQUENCY (MHz)
CW BLOCKER LEVEL (dBm)
Figure 16. RF Input Return Loss vs. RF Frequency
Figure 19. SSB Noise Figure vs. 5 MHz Offset CW Blocker Level,
LO Frequency = 2500 MHz, RF Frequency = 2358 MHz
Rev. B | Page 11 of 32
ADRF6604
Data Sheet
0
–5
5.0
4.5
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–10
–15
–20
–25
–30
–35
–40
–45
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
T
T
T
= +85°C
= +25°C
= –40°C
IP3SET = OPEN
IP3SET = 3.3V
A
A
A
–50
–55
–60
0
2500
2160
2260
2360
2460
2560
2660
2760
2860 2960
2550
2600
2650
2700
2750
2800
2850 2900
RF FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 20. RF-to-IF Isolation vs. RF Frequency, High-Side LO, IF = 140 MHz,
LO Output Turned Off
Figure 23. VTUNE vs. LO Frequency
0
350
IP3SET = OPEN
IP3SET = 3.3V
T
T
T
= +85°C
= +25°C
= –40°C
IP3SET = OPEN
IP3SET = 3.3V
A
T
T
T
= +85°C
= +25°C
= –40°C
–1
–2
–3
–4
–5
–6
–7
–8
–9
A
A
A
A
A
300
250
200
150
–10
–11
–12
–13
–14
–15
2500
100
2500
2550
2600
2650
2700
2750
2800
2850 2900
2550
2600
2650
2700
2750
2800
2850 2900
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 21. LO Output Amplitude vs. LO Frequency
Figure 24. Supply Current vs. LO Frequency
25
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
IP3SET = OPEN
IP3SET = 3.3V
20
15
10
5
0
–5
1.5
1.4
–10
–15
–20
–25
1.3
1.2
1.1
1.0
–55
0
50
100
150
200
250
–35
–15
5
25
45
65
85
105
TIME (µs)
TEMPERATURE (°C)
Figure 22. Frequency Deviation from 2500 MHz vs. Time
(Demonstrates LO Frequency Settling Time from 2490 MHz to 2500 MHz)
Figure 25. VPTAT Voltage vs. Temperature (IP3SET = Optimized, Open)
Rev. B | Page 12 of 32
Data Sheet
ADRF6604
Complementary cumulative distribution function (CCDF), fRF = 2360 MHz, fIF = 140 MHz.
100
100
90
80
70
60
50
40
30
20
10
0
IP3SET =
OPEN
IP3SET =
3.3V
IP3SET =
OPEN
IP3SET =
3.3V
90
80
70
60
50
40
30
20
10
0
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–0.5
0
0.5
1.0
1.5
2.0
22
23
24
25
26
27
28
29
30
GAIN (dB)
INPUT IP3 (dBm)
Figure 26. Gain
Figure 29. Input IP3
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
IP3SET =
OPEN
IP3SET =
3.3V
IP3SET =
OPEN
IP3SET =
3.3V
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0
45
50
55
60
65
70
75
INPUT P1dB (dBm)
INPUT IP2 (dBm)
Figure 27. Input IP2
Figure 30. Input P1dB
100
90
80
70
60
50
40
30
20
10
0
100
IP3SET = OPEN
IP3SET = 3.3V
T
T
T
= +85°C
= +25°C
= –40°C
IP3SET = OPEN
A
A
A
90
80
70
60
50
40
30
20
10
0
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
10
11
12
13
14
15
16
17
18
19
20
–50
–48
–46
–44
–42
–40
–38
–36
NOISE FIGURE (dB)
LO FEEDTHROUGH TO IF (dBm)
Figure 31. LO Feedthrough to IF, LO Output Turned Off
Figure 28. Noise Figure
Rev. B | Page 13 of 32
ADRF6604
Data Sheet
Measured at IF output, CDAC = 0xC, IP3SET = open, internally generated high-side LO, fREF = 153.6 MHz, fPFD = 38.4 MHz,
RFIN = −5 dBm, fIF = 140 MHz, unless otherwise noted. Phase noise measurements made at LO output, unless otherwise noted.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–70
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
LO FREQUENCY = 2883.2MHz
–80
–90
–100
–110
–120
–130
–140
–150
–160
LO FREQUENCY = 2537.6MHz
2500
2550
2600
2650
2700
2750
2800
2850 2900
1k
1M
10M
100M
1G
LO FREQUENCY (MHz)
OFFSET FREQUENCY (Hz)
Figure 32. Phase Noise vs. Offset Frequency
Figure 35. Integrated Phase Noise vs. LO Frequency
–70
–80
OFFSET = 1kHz
–75
–80
–85
–90
–100
–110
–120
–130
–140
–150
OFFSET = 100kHz
–90
–95
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
OFFSET AT 2× PFD
OFFSET AT 4× PFD
–100
–105
–110
OFFSET = 5MHz
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
2500
2550
2600
2650
2700
2750
2800
2850 2900
2500
2550
2600
2650
2700
2750
2800
2850 2900
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 33. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD)
Figure 36. Phase Noise vs. LO Frequency (1 kHz, 100 kHz, and 5 MHz Steps)
–70
–80
–85
T
T
T
= +85°C
= +25°C
= –40°C
OFFSET AT 3× PFD
OFFSET AT 1× PFD
A
A
A
–75
–80
–85
–90
OFFSET = 10kHz
–95
–100
–105
–90
–95
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–110
–115
–120
–125
–130
–100
–105
–110
OFFSET AT 0.25× PFD
OFFSET = 1MHz
2500
2550
2600
2650
2700
2750
2800
2850 2900
2500
2550
2600
2650
2700
2750
2800
2850 2900
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 34. PLL Reference Spurs vs. LO Frequency (0.25× PFD, 1× PFD, and 3× PFD)
Figure 37. Phase Noise vs. LO Frequency (10 kHz, 1 MHz Steps)
Rev. B | Page 14 of 32
Data Sheet
ADRF6604
SPURIOUS PERFORMANCE
(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board (see the Evaluation Board section). Mixer spurious
products were measured in decibels relative to the carrier (dBc) from the IF output power level. All spurious components greater than
−125 dBc are shown.
LO = 2500 MHz, RF = 2360 MHz (horizontal axis is M, vertical axis is N), and RFIN power = 0 dBm.
M
0
1
2
3
4
-115.19
−23.6708
−63.4281
−43.0184
0.0
−33.3455
−67.1671
−61.1065
−86.8944
−108.708
0
1
2
3
4
5
6
7
−47.1921
−79.8957
−58.5001
−104.041
−110.825
−65.1191
−83.6746
−80.0324
−105.514
−108.518
−113.19
N
−108.548
LO = 2700 MHz, RF = 2560 MHz (horizontal axis is M, vertical axis is N), and RFIN power = 0 dBm.
M
0
1
2
3
4
0
1
2
3
4
5
6
7
−114.804
−22.6289
−61.2522
−42.7987
0.0
−31.9174
−65.0063
−57.5224
−82.5056
−108.087
−48.5279
−77.0905
−56.9437
−98.5103
−110.572
−66.5602
−84.4436
−76.8305
−98.8811
−99.2295
−113.601
−109.829
N
LO = 2900 MHz, RF = 2760 MHz (horizontal axis is M, vertical axis is N), and RFIN power = 0 dBm.
M
0
1
2
3
4
0
1
2
3
4
5
6
7
−114.956
−22.092
−60.2824
−44.0336
0.0
−31.2423
−62.6978
−56.7826
−80.7407
−108.949
−48.9358
−73.218
−69.8043
−85.957
N
−56.7503
−100.938
−110.193
−105.061
−100.159
−111.146
−111.428
Rev. B | Page 15 of 32
ADRF6604
Data Sheet
REGISTER STRUCTURE
This section provides the register maps for the ADRF6604. The three LSBs determine the register that is programmed.
REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)
DIVIDE
MODE
RESERVED
INTEGER DIVIDE RATIO
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
DM
DM
0
DIVIDE MODE
FRACTIONAL (DEFAULT)
INTEGER
1
INTEGER DIVIDE RATIO
ID6
0
ID5
0
ID4
1
ID3
0
ID2
1
ID1
0
ID0
21 (INTEGER MODE ONLY)
1
0
22 (INTEGER MODE ONLY)
0
0
1
0
1
1
23 (INTEGER MODE ONLY)
0
0
1
0
1
1
1
24
0
0
1
1
0
0
0
...
...
...
0
...
...
1
...
...
1
...
...
1
...
...
0
...
...
0
...
...
0
...
56 (DEFAULT)
...
...
...
1
...
...
1
...
...
1
...
...
0
...
...
1
...
...
1
...
...
1
...
119
120 (INTEGER MODE ONLY)
121 (INTEGER MODE ONLY)
122 (INTEGER MODE ONLY)
123 (INTEGER MODE ONLY)
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
0
1
1
1
1
0
1
1
Figure 38. Register 0—Integer Divide Control Register Map
REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)
MODULUS VALUE
CONTROL BITS
0
0
0
0
0
0
0
0
0
0
MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
MODULUS VALUE
1
0
0
0
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
0
0
0
1
0
...
...
...
1
...
...
1
...
...
0
...
...
0
...
...
0
...
...
0
...
...
0
...
...
0
...
...
0
...
...
0
...
...
0
...
1536 (DEFAULT)
...
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
2047
Figure 39. Register 1—Modulus Divide Control Register Map
Rev. B | Page 16 of 32
Data Sheet
ADRF6604
REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)
CONTROL BITS
DB2 DB1 DB0
RESERVED
FRACTIONAL VALUE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0)
FRACTIONAL VALUE
FD10
0
FD9
0
FD8
0
FD7
0
FD6
0
FD5
0
FD4
0
FD3
0
FD2
0
FD1
0
FD0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
...
...
...
0
...
...
1
...
...
1
...
...
0
...
...
0
...
...
0
...
...
0
...
...
0
...
...
0
...
...
0
...
...
0
...
768 (DEFAULT)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
<MDR
Figure 40. Register 2—Fractional Divide Control Register Map
REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)
DITHER
MAGNITUDE
DITHER
ENABLE
DITHER RESTART VALUE
CONTROL BITS
DB23 DB22
DITH1
DB21
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
DITH0
DEN
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)
DITH1
DITH0 DITHER MAGNITUDE
0
0
0
1
15 (DEFAULT)
7
1
1
0
1
3
1 (RECOMMENDED)
DEN DITHER ENABLE
0
1
DISABLE
ENABLE (DEFAULT, RECOMMENDED)
DITHER RESTART
VALUE
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
0x00001 (DEFAULT)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
1
...
...
0x1FFFF
Figure 41. Register 3—Σ-Δ Modulator Dither Control Register Map
Rev. B | Page 17 of 32
ADRF6604
Data Sheet
REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)
CP
PFD ANTI-
REF OUTPUT
MUX SELECT
INPUT REF
PATH
PFD
POL
PFD PHASE OFFSET
MULTIPLIER
CP
CP
CP
CURRENT
REF
PFD EDGE BACKLASH
CONTROL BITS
CURRENT SRC CONTROL
DELAY
SOURCE
DB23 DB22 DB21 DB20 DB19
RMS2 RMS1 RMS0 RS1 RS0
DB18
CPM
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)
PFD ANTIBACKLASH
PAB1 PAB0
DELAY
0
0
1
1
0
1
0
1
0ns (DEFAULT)
0.5ns
0.75ns
0.9ns
REFERENCE PATH EDGE
SENSITIVITY
PE0
0
1
FALLING EDGE
RISING EDGE (DEFAULT)
DIVIDER PATH EDGE
SENSITIVITY
PE1
0
1
FALLING EDGE
RISING EDGE (DEFAULT)
CHARGE PUMP CONTROL
CPC1 CPC0
BOTH ON
PUMP DOWN
PUMP UP
0
0
1
1
0
1
0
1
TRISTATE (DEFAULT)
CPS CHARGE PUMP CONTROL SOURCE
0
1
CONTROL BASED ON STATE OF DB7 AND DB8 (CP CONTROL)
CONTROL FROM PFD (DEFAULT)
CPP1 CPP0 CHARGE PUMP CURRENT
250µA
500µA (DEFAULT)
750µA
0
0
1
1
0
1
0
1
1000µA
PFD PHASE OFFSET MULTIPLIER
CPB4 CPB3 CPB2 CPB1 CPB0
0 × 22.5°/I
CPMULT
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
0
1
1 × 22.5°/I
CPMULT
6 × 22.5°/I
CPMULT
(RECOMMENDED)
(DEFAULT)
10 × 22.5°/I
16 × 22.5°/I
31 × 22.5°/I
CPMULT
CPMULT
CPMULT
CPBD PFD PHASE OFFSET POLARITY
0
1
NEGATIVE
POSITIVE (DEFAULT)
CHARGE PUMP CURRENT
REFERENCE SOURCE
CPM
INTERNAL (DEFAULT)
EXTERNAL
0
1
INPUT REFERENCE
PATH SOURCE
RS1 RS0
2 × REFIN
REFIN (DEFAULT)
0.5 × REFIN
0
0
1
1
0
1
0
1
0.25 × REFIN
RMS2 RMS1 RMS0 REF OUTPUT MUX SELECT
LOCK DETECT (DEFAULT)
VPTAT
REF_IN (BUFFERED)
0.5 × REFIN (BUFFERED)
2 × REFIN (BUFFERED)
TRISTATE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RESERVED
RESERVED
Figure 42. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map
Rev. B | Page 18 of 32
Data Sheet
ADRF6604
REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)
LO
DIV1
PLL
EN
LO
DIV1
LO
EXT
LO
DRV
CAP DAC
CONTROL BITS
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
DB6
DB5
DB4
LXL
DB3 DB2 DB1 DB0
LDRV C3(1) C2(0) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0
CD3 CD2 CD1 CD0 LDV2 PLEN LDV1
CAPACITOR DAC
LO OUTPUT DRIVER
LDRV
CD3
0
...
1
CD2
CD1
CD0 CONTROL FOR IIP3
OPTIMIZATION
ENABLE
DRIVER OFF (DEFAULT)
DRIVER ON
0
1
MIN
...
MAX
0
...
1
0
...
1
0
...
1
EXTERNAL LO DRIVE
ENABLE (PIN 37, PIN 38)
LXL
INTERNAL LO OUTPUT (DEFAULT)
EXTERNAL LO INPUT
0
1
LDV2 DIVIDE-BY-2 OR 1
LDV1 DIVIDE-BY-2 IN LO CHAIN ENABLE
DIVIDE BY 1
DIVIDE BY 2 (DEFAULT)
DIVIDE BY 1
DIVIDE BY 2 (DEFAULT)
0
1
0
1
PLEN PLL ENABLE
DISABLE
ENABLE (DEFAULT)
0
1
Figure 43. Register 5—PLL Enable and LO Path Control Register Map
REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)
CHARGE
3.3V
VCO
BW SW
CTRL
VCO LDO VCO
VCO
CONTROL BITS
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PUMP
LDO
VCO BAND SELECT FROM SPI
RESERVED
VCO AMPLITUDE
ENABLE ENABLE SWITCH
ENABLE ENABLE
DB23 DB22 DB21 DB20
DB19
L3EN
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
0
0
0
CPEN
LVEN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
CHARGE PUMP ENABLE
CPEN
VC[5:0] VCO AMPLITUDE
VBS[5:0] VCO BAND SELECT FROM SPI
0x00
0x01
….
0x00
….
0
DISABLE
ENABLE (DEFAULT)
0
1
….
0x18
….
24 (DEFAULT)
….
0x20
….
DEFAULT
L3EN 3.3V LDO ENABLE
0x2B
….
43
….
0x3F
0
1
DISABLE
ENABLE (DEFAULT)
0x3F
63 (RECOMMENDED)
VBSRC VCO BW CAL AND SW SOURCE CONTROL
VCO SW VCO SWITCH CONTROL FROM SPI
0
1
BAND CAL (DEFAULT)
SPI
LVEN VCO LDO ENABLE
REGULAR (DEFAULT)
BAND CAL
0
1
0
1
DISABLE
ENABLE (DEFAULT)
VCO EN VCO ENABLE
0
1
DISABLE
ENABLE (DEFAULT)
Figure 44. Register 6—VCO Control and VCO Enable Register Map
REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)
MIXER
B_EN
RESERVED
CONTROL BITS
RES XVCO
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
XVCO MBE C3(1) C2(1) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MBE MIXER BIAS ENABLE
ENABLE (DEFAULT)
DISABLE
0
1
EXTERNAL VCO
XVCO
INTERNAL VCO (DEFAULT)
EXTERNAL VCO
0
1
Figure 45. Register 7—Mixer Bias Enable and External VCO Enable Register Map
Rev. B | Page 19 of 32
ADRF6604
Data Sheet
THEORY OF OPERATION
The ADRF6604 integrates a high performance downconverting
mixer with a state-of-the-art fractional-N PLL. The PLL also
integrates a low noise VCO. The SPI port allows the user to control
the fractional-N PLL functions and the mixer optimization
functions, as well as allowing for an externally applied LO or VCO.
Table 8. ADRF6604 Register Functions
Register
Function
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Integer divide control for the PLL
Modulus divide control for the PLL
Fractional divide control for the PLL
Σ-Δ modulator dither control
PLL charge pump, PFD, reference path control
PLL enable and LO path control
The mixer core within the ADRF6604 is the next generation of
an industry-leading family of mixers from Analog Devices, Inc.
The RF input is converted to a current and then mixed down to IF
using high performance NPN transistors. The mixer output currents
are transformed to a differential output. The high performance active
mixer core results in an exceptional IIP3 and IP1dB with a very
low output noise floor for excellent dynamic range. Over the
specified frequency range, the ADRF6604 typically provides IF
input P1dB of 14.5 dBm and IIP3 of 27.5 dBm.
VCO control and VCO enable
Mixer bias enable and external VCO enable
Note that internal calibration for the PLL must be run when the
ADRF6604 is initialized at a given frequency. This calibration is
run automatically whenever Register 0, Register 1, or Register 2 is
programmed. Because the other registers affect PLL performance,
Register 0, Register 1, and Register 2 should always be programmed
last and in the following order: Register 0, Register 1, Register 2.
Improved performance at specific frequencies can be achieved
with the use of the internal capacitor DAC (CDAC), which is
programmable via the SPI port, and by using a resistor to a 5 V
supply from the IP3SET pin (Pin 29). Adjustment of the capacitor
DAC allows increments in phase shift at internal nodes in the
ADRF6604, thus allowing cancellation of third-order distortion
with no change in supply current. Connecting a resistor to a 5 V
supply from the IP3SET pin increases the internal mixer core current,
thereby improving overall IIP2 and IIP3, as well as IP1dB. Using
the IP3SET pin for this purpose increases the overall supply current.
To program the frequency of the ADRF6604, the user typically
programs only Register 0, Register 1, and Register 2. However,
if registers other than these are programmed first, a short delay
should be inserted before programming Register 0. This delay
ensures that the VCO band calibration has sufficient time to
complete before the final band calibration for Register 0 is initiated.
Software is available on the ADRF6604 product page under the
Evaluation Boards & Kits section that allows easy programming
from a PC running Windows® XP or Vista.
The fractional divide function of the PLL allows the frequency
multiplication value from REF_IN to LO output to be a fractional
value rather than to be restricted to an integer value as in tradi-
tional PLLs. In operation, this multiplication value is
INITIALIZATION SEQUENCE
To ensure proper power-up of the ADRF6604, it is important to
reset the PLL circuitry after the VCC supply rail settles to 5 V
0.25 V. Resetting the PLL ensures that the internal bias cells are
properly configured, even under poor supply start-up conditions.
INT + (FRAC/MOD)
where:
INT is the integer value.
FRAC is the fractional value.
MOD is the modulus value.
To ensure that the PLL is reset after power-up, use the following
procedure:
The INT, FRAC, and MOD values are all programmable via the
SPI port. In other fractional-N PLL designs, fractional multi-
plication is achieved by periodically changing the fractional value
in a deterministic way. The disadvantage of this approach is that
there are often spurious components close to the fundamental
signal. In the ADRF6604, a Σ-Δ modulator is used to distribute
the fractional value randomly, thus significantly reducing the
spurious content due to the fractional function.
1. Disable the PLL by setting the PLEN bit to 0 (Register 5,
Bit DB6).
2. After a delay of >100 ms, set the PLEN bit to 1 (Register 5,
Bit DB6).
After this procedure is completed, the other registers should
be programmed in the following order: Register 7, Register 6,
Register 4, Register 3, Register 2, Register 1. Then, after a delay
of >100 ms, Register 0 should be programmed.
PROGRAMMING THE ADRF6604
The ADRF6604 is programmed via a 3-pin SPI port. The timing
requirements for the SPI port are shown in Figure 2. Eight pro-
grammable registers, each with 24 bits, control the operation of
the device. The register functions are listed in Table 8.
Rev. B | Page 20 of 32
Data Sheet
ADRF6604
The operation of the LO generation and whether LOP and LON
are inputs or outputs are determined by the logic levels applied
at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3
(LDRV) and Bit DB6 (PLEN) in Register 5. The combination of
externally applied logic and internal bits required for particular
LO functions is given in Table 9.
LO SELECTION LOGIC
The downconverting mixer in the ADRF6604 can be used
without the internal PLL by applying an external differential LO
to Pin 37 (LON) and Pin 38 (LOP). In addition, when using an
LO generated by the internal PLL, the LO signal can be accessed
directly at these pins. This function can be used for debugging
purposes, or the internally generated LO can be used as the LO
for a separate mixer.
Table 9. LO Selection Logic
Pins1
Register 5 Bits1
Outputs
Pin 16 (PLL_EN)
Pin 36 (LODRV_EN) Bit DB6 (PLEN)
Bit DB3 (LDRV)
Output Buffer
Disabled
Disabled
Disabled
Disabled
Enabled
LO
0
0
1
1
1
1
X
X
X
0
X
1
0
1
0
1
1
1
X
X
X
0
1
X
External
External
External
Internal
Internal
Internal
Enabled
1 X = don’t care.
Rev. B | Page 21 of 32
ADRF6604
Data Sheet
APPLICATIONS INFORMATION
be ac-coupled and terminated with a 50 Ω resistor as shown in
Figure 46. The reference signal, or a divided-down version of
the reference signal, can be brought back off chip at the multiplexer
output pin (MUXOUT). A lock detect signal and a voltage
proportional to the ambient temperature can also be selected
on the multiplexer output pin.
BASIC CONNECTIONS FOR OPERATION
Figure 46 shows the basic connections for the ADRF6604 evalu-
ation board. The six power supply pins should be individually
decoupled using 100 pF and 0.1 µF capacitors located as close as
possible to the device. In addition, the internal decoupling nodes
(DECL3P3, DECL2P5, and DECLVCO) should be decoupled
with the capacitor values shown in Figure 46.
The loop filter is connected between the CP and VTUNE pins.
When connected in this way, the internal VCO is operational.
For information about the loop filter components, see the
Evaluation Board Configuration Options section.
The RF input is internally ac-coupled and needs no external
bias. The IF outputs are open collector, and a bias inductor is
required from these outputs to VCC.
Operation with an external VCO is also possible. In this case,
the loop filter components should be referred to ground. The
output of the loop filter is connected to the input voltage pin of
the external VCO. The output of the VCO is brought back into
the device on the LOP and LON pins, using a balun if necessary.
A peak-to-peak differential swing on RFIN of 1 V (0.353 V rms
for a sine wave input) results in an IF output power of 4.7 dBm.
The reference frequency for the PLL should be from 12 MHz to
160 MHz and should be applied to the REF_IN pin, which should
P1
9-PIN
DSUB
1
2
3
4
5
6
7
8
9
VCC
R36
R19
0Ω
(0402)
R35
R30
0Ω
R54
0Ω
0Ω
(0402)
R20
10kΩ
(0402) (0402)
R57
0Ω
(0402)
0Ω
(0402)
(0402)
S2
R53
10kΩ
(0402)
C34
OPEN
(0402)
R52
OPEN
(0402)
VCC
RED
+5V
C33
OPEN
(0402)
R51
OPEN
(0402)
C7
0.1µF
(0402)
C25
0.1µF
(0402)
C23
0.1µF
(0402)
C20
0.1µF
(0402)
C19
0.1µF
(0402)
C9
0.1µF
(0402)
R6
R26
R25
R24
R17
R7
VCC1
RED
R55
OPEN
(0402)
C32
OPEN
(0402)
R50
OPEN
(0402)
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
(0402)
C8
(0402)
(0402)
(0402)
(0402)
(0402)
C24
C22
C21
C18
C10
100pF
(0402)
100pF
(0402)
100pF
100pF
100pF
100pF
(0402)
(0402)
(0402)
(0402)
S1
OPEN
VCC_LO
VCC_V2I
VCC_MIX
VCC_LO
VCC2
VCC1
34
27
22
17
10
1
16 13 12 14
DECL2P5
C16
R56
9
2
0Ω
LODRV_EN
C17
C42
R18
(0402)
36
SPI
INTERFACE
100pF
(0402)
0.1µF
(0402)
10µF
(0603)
0Ω
LON
C5
(0402)
37
38
LO IN/OUT
4
5
3
1
DIVIDER
÷2
BUFFER
BUFFER
DECL3P3
C12
LOP
1nF
(0402)
C11
0.1µF
(0402)
C41
OPEN
(0603)
R8
0Ω
(0402)
100pF
(0402)
DIV
BY
2, 1
2:1
MUX
T8
TC1-1-13+
INTEGER
REG
FRACTION
REG
C6
1nF
(0402)
MODULUS
ADRF6604
RF
IN
26
29
RFIN
THIRD-ORDER
R28
FRACTIONAL
C31
1nF
0Ω
VCO
CORE
INTERPOLATOR
(0402)
×2
REF_IN
N COUNTER
21 TO 123
PRESCALER
÷2
(0402)
REF_IN
6
8
R70
MUX
÷2
IP3SET
CHARGE PUMP
250µA,
49.9Ω
–
+
C27
0.1µF
(0402)
PHASE
FREQUENCY
DETECTOR
R27
0Ω
(0402)
500µA (DEFAULT),
750µA,
TEMP
SENSOR
÷4
REFOUT
(0402)
MUXOUT
1000µA
R16
4
7
11 15 20 21 23 24 25 28 30 31 35
5
3
39
40
18
19
0Ω
R
SET
R2
VTUNE DECLVCO IFP
IFN
CP
(0402)
1
2
4
RFOUT
OPEN
(0402)
R37
R43
R62
VCC
+5V
0Ω
0Ω
0Ω
R59
3
(0402)
(0402)
5
(0402)
0Ω
R38
0Ω
(0402)
(0402)
R9 10kΩ R65 10kΩ
CP
TEST
VTUNE
(0402)
(0402)
C29
0.1µF
(0402)
POINT
R10
R63
(ORANGE)
3kΩ
OPEN
(0402)
C14
22pF
(0603)
C13
6.8pF
(0603)
C40
22pF
(0603)
(0603)
C15
2.7nF
(1206)
R12
R11
OPEN
(0402)
R1
0Ω
0Ω
(0402)
(0402)
C43
10µF
(0603)
C2
OPEN
(0402)
C1
100pF
(0402)
Figure 46. Basic Connections for Operation of the ADRF6604
Rev. B | Page 22 of 32
Data Sheet
ADRF6604
AC TEST FIXTURE
Characterization data for the ADRF6604 was taken under very
strict test conditions. All possible techniques were used to
achieve optimum accuracy and to remove degrading effects of
the signal generation and measurement equipment. Figure 47
shows the typical AC test setup used in the characterization of
the ADRF6604.
ADRF6604 CHARACTERIZATION RACK DIAGRAM.
ALL INSTRUMENTS ARE CONTROLLED BY A LAB
COMPUTER VIA A USB TO GPIB CONTROLLER, DAISY
CHAINED TO EACH INDIVIDUAL INSTRUMENT.
RF1 AGILENT N5181A
HP 11636A
POWER DIVIDER
RF2 AGILENT N5181A
REF_IN AGILENT N5181A
RF
IN
REF_IN
ADRF6604
EVALUATION BOARD
IF_OUT
ROHDE & SCHWARZ
FSEA30
AGILENT 34401A SET TO IDC
(SET FOR SUPPLY CURRENT)
GND VIA
10-PIN DC HEADER
5V dc VIA
10-PIN DC HEADER
3.3V dc VIA
10-PIN DC HEADER
AGILENT 34980A WITH THREE 34921 MODULES
AND ONE 34950 MODULE
5V dc MEASURED FOR SUPPLY CURRENT
AGILENT E3631A 25V SET TO
3.3V, 6V SET TO 5V.
RETURNS ARE
JUMPERED TOGETHER
Figure 47. ADRF6604 AC Test Setup
Rev. B | Page 23 of 32
ADRF6604
Data Sheet
EVALUATION BOARD
Figure 50 shows the schematic of the RoHS-compliant evaluation
board for the ADRF6604. This board has four layers and was
designed using Rogers 4350 hybrid material to minimize high
frequency losses. FR4 material is also adequate if the design can
accept the slightly higher trace loss of this material.
To connect the evaluation board to a USB port, a USB adapter board
(EVAL-ADF4XXXZ-USB) must be purchased from Analog Devices.
This board connects to the PC using a standard USB cable with
a USB mini-connector at one end. An additional 25-pin male to
9-pin female adapter is required to mate the EVAL-ADF4XXXZ-
USB board to the 9-pin D-Sub connector on the ADRF6604
evaluation board.
The evaluation board is designed to operate using the internal
VCO of the device (the default configuration) or using an external
VCO. To use an external VCO, R62 and R12 should be removed.
Place 0 Ω resistors in R63 and R11. The input of the external
VCO should be connected to the VTUNE SMA connector, and
the external VCO output should be connected to the LO IN/OUT
SMA connector. In addition to these hardware changes, internal
register settings must be changed to enable operation with an
external VCO (see the Register 6—VCO Control and VCO
Enable (Default: 0x1E2106) section).
Additional configuration options for the evaluation board are
described in Table 10.
EVALUATION BOARD CONTROL SOFTWARE
Software to program the ADRF6604 is available for download
from the ADRF6604 product page under the Evaluation Boards
& Kits section. To install the software
1. Download and extract the zip file:
ADRF6x0x_customer_6p0p0_install.zip file.
2. Follow the instructions in the read me file.
The evaluation board can be connected to the PC using a PC
parallel port or a USB port. These options are selectable from the
opening menu of the software interface (see Figure 48). The
evaluation board is shipped with a 25-pin parallel port cable
for connection to the PC parallel port.
Figure 48. Control Software Opening Menu
Figure 49 shows the main window of the control software with
the default settings displayed.
Rev. B | Page 24 of 32
Data Sheet
ADRF6604
Figure 49. Main Window of the ADRF6604 Evaluation Board Software
Rev. B | Page 25 of 32
ADRF6604
Data Sheet
SCHEMATIC AND ARTWORK
W 1 - 4 C T
6
4
3
2
1
0
3 4 R
0
6 6 R
8 2 C
F U 1 0
0
2 3 R
B B _ C V C
0
O L _ C V C
1 3 R
0
F R _ C V C
9 2 R
D
G N
I F N
I F P
D
G N
N C
0
0
N C
3 3 R
O L C V C _
N E _ L L P
4 3 R
0
O L C V C _
3
1
D
G N
2
0 2 R
2
3
S2
D
G N
E L
K L C
D A T
G N
1
E N V _ R D O L
L O N
1 S
0
1
L O P
5 3 R
A
U T N V E
D
C V O C L D E
0
0
2 7 R
2 6 R
1
0
2 1 R
K 3
0 1 R
D B T
1 7 R
I
N D
1 1 R
0
7 3 R
I
N D
4 1 R
1 Y
Figure 50. Evaluation Board Schematic
Rev. B | Page 26 of 32
Data Sheet
ADRF6604
Figure 52. Evaluation Board Layout (Top)
Figure 51. Evaluation Board Layout (Bottom)
Rev. B | Page 27 of 32
ADRF6604
Data Sheet
EVALUATION BOARD CONFIGURATION OPTIONS
Table 10.
Default Condition/
Option Settings
Component
Description
S1, R55, R56, R33
LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in
combination with internal register settings, determines whether the LOP and LON pins
function as inputs or outputs (see the LO Selection Logic section for more information).
S1 = R55 = open
(not installed),
R56 = R33 = 0 Ω,
LODRV_EN = 0 V
LO IN/OUT
SMA Connector
LO input/output. An external 1× LO or 2× LO can be applied to this single-ended input
connector.
LO input
REFIN
SMA Connector
Reference input. The input reference frequency for the PLL is applied to this connector.
Input impedance is 50 Ω.
REFOUT
SMA Connector
Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The
on-board multiplexer can be programmed to bring out the following signals: REFIN, 2×
REFIN, REFIN/2, and REFIN/4; temperature sensor output voltage; and lock detect indicator.
Lock detect
CP Test Point
Charge pump test point. The unfiltered charge pump signal can be probed at this test
point. Note that the CP pin should not be probed during critical measurements, such as
phase noise.
R37, C14, R9, R10,
C15, C13, R65, C40
Loop filter. Loop filter components.
R11, R12
Loop filter return. When the internal VCO is used, the loop filter components should be
returned to the DECLVCO pin (Pin 40) by installing a 0 Ω resistor in R12. When an external
VCO is used, the loop filter components can be returned to ground by installing a 0 Ω
resistor in R11.
R12 = 0 Ω (0402),
R11 = open (0402)
R62, R63, VTUNE
SMA Connector
Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are
connected directly to the VTUNE pin (Pin 39) by installing a 0 Ω resistor in R62. To use an
external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the
voltage input of the VCO should be connected to the VTUNE SMA connector. The output of
the VCO is brought back into the PLL via the LO IN/OUT SMA connector.
R62 = 0 Ω (0402),
R63 = open (0402)
R2
RSET pin. This pin is unused and should be left open.
R2 = open (0402)
RFIN SMA Connector RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of R3 = R23 = open (0402)
the ADRF6604 is ac-coupled; therefore, no bias is necessary.
T3
IF output. The differential IF output signals from the ADRF6604 (IFP and IFN) are converted
to a single-ended signal by T3.
Rev. B | Page 28 of 32
Data Sheet
ADRF6604
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
30
40
1
5.85
5.75 SQ
5.65
0.50
BSC
PIN 1
INDICATOR
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOTTOM VIEW)
10
11
21
20
0.50
0.40
0.30
0.20 MIN
TOP VIEW
4.50 REF
0.80 MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF6604ACPZ-R7
ADRF6604-EVALZ
Temperature Range
Package Description
Package Option
CP-40-1
−40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. B | Page 29 of 32
ADRF6604
NOTES
Data Sheet
Rev. B | Page 30 of 32
Data Sheet
NOTES
ADRF6604
Rev. B | Page 31 of 32
ADRF6604
NOTES
Data Sheet
©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08553-0-1/14(B)
Rev. B | Page 32 of 32
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