ADRF6614-EVALZ [ADI]
700 MHz to 3000 MHz, Dual Passive Receive Mixer with Integrated PLL and VCO;
| 型号： | ADRF6614-EVALZ |
| 厂家： | 
ADI |
| 描述： | 700 MHz to 3000 MHz, Dual Passive Receive Mixer with Integrated PLL and VCO |
| 文件： | 总61页 (文件大小：2965K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
700 MHz to 3000 MHz, Dual Passive
Receive Mixer with Integrated PLL and VCO
Data Sheet
ADRF6614
FEATURES
FUNCTIONAL BLOCK DIAGRAM
RF frequency: 700 MHz to 3000 MHz, continuous
LO input frequency: 200 MHz to 2700 MHz, high-side or low-
side injection
IF range: 40 MHz to 500 MHz
Power conversion gain of 9.0 dB
Phase noise performance of −144 dBc/Hz at 800 kHz offset
supporting stringent GSM standards in both 800 MHz to
900 MHz and 1800 MHz to 1900 MHz bands
Single-sideband (SSB) noise figure of 11.3 dB
Input IP3 of 30 dBm
2
46
45 44
48 47 43 42
39 38
41 40 37
1
3
6
7
34
33
32
GND
GND
GND
VCC1
VCC10
VCC9
VCC8
PLL REF BUFFER
PFD/CP
FRACTIONAL DIVIDER
VCO
VCO
VCO
36
35
RFBCT1
RFIN1
31 VCC7
30 LDO2
÷1 TO
32
4
5
EXTVCOIN+
EXTVCOIN–
26
RFIN2
ADRF6614
8
25
DECL1
DECL2
DECL3
DECL4
DECL5
RFBCT2
PLL
3.3V
LDO
VCO
LDO
9
Input P1dB of 10.6 dBm
Typical LO input drive of 0 dBm
Single-ended, 50 Ω RF port
29
28
27
VCC6
VCC5
VCC4
SPI
CONTROL
10
11
12
SPI
2.5V 3.3V
LDO LDO
DIV
13 14
15 16 17 18 19
22 23
20 21 24
Single-ended or balanced LO input port
Serial port interface (SPI) control on all functions
Exposed pad, 7 mm × 7 mm, 48-lead LFCSP
Figure 1.
APPLICATIONS
Multiband/multistandard cellular base station diversity receivers
Wideband radio link diversity downconverters
Multimode cellular extenders and picocells
IF buffer amplifiers follow the passive mixer cores, yielding
typical power conversion gains of 9.0 dB, and can be matched
to a wide range of output impedances.
GENERAL DESCRIPTION
The ADRF6614 is a dual radio frequency (RF) mixer and
intermediate frequency (IF) amplifier with an integrated phase-
locked loop (PLL) and voltage controlled oscillators (VCOs). The
ADRF6614 uses revolutionary broadband square wave limiting
local oscillator (LO) amplifiers to achieve a wideband RF bandwidth
of 700 MHz to 3000 MHz. Unlike narrow-band sine wave LO
amplifier solutions, the LO can be applied above or below the RF
input over a wide bandwidth. Energy storage elements are not
utilized in the LO amplifier, thus dc current consumption also
decreases with decreasing LO frequency.
The PLL architecture supports both integer-N and fractional-N
operation and can generate the entire LO frequency range of
200 MHz to 2700 MHz using an external reference input frequency
anywhere in the range of 12 MHz to 320 MHz. An external loop
filter provides flexibility in trading off phase noise vs. acquisition
time. To reduce fractional spurs in fractional-N mode, a Σ-Δ
modulator controls the post VCO-programmable divider. The
device integrates six VCO cores, four of which provide complete
frequency coverage between 200 MHz and 2700 MHz, and meet
the GSM phase noise requirements in the 800 MHz and 900 MHz
bands. Two additional GSM only cores enable the ADRF6614 to
meet the GSM phase noise requirements in the digital cellular
system 1800 MHz (DCS1800) and personal communications
service 1900 MHz (PCS1900) bands.
The ADRF6614 utilizes highly linear, doubly balanced passive
mixer cores with integrated RF and LO balancing circuits to
allow single-ended operation. Integrated RF baluns allow optimal
performance over the 700 MHz to 3000 MHz RF input frequency.
The balanced passive mixer arrangement provides outstanding LO
to RF and LO to IF leakages, excellent RF to IF isolation, and
excellent intermodulation performance over the full RF bandwidth.
All features of the ADRF6614 are controlled via a 3-wire SPI,
resulting in optimum performance and minimum external
components.
The balanced mixer cores provide extremely high input linearity,
allowing the device to be used in demanding wideband applications
where in-band blocking signals may otherwise result in the degra-
dation of dynamic range. Noise performance under blocking is
comparable to narrow-band passive mixer designs. High linearity
The ADRF6614 is fabricated using a BiCMOS, high performance
IC process. The device is available in a 7 mm × 7 mm, 48-lead
LFCSP package and operates over a −40°C to +85°C temperature
range. An evaluation board is available.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADRF6614
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Spurious Performance ............................................................... 32
Theory of Operation ...................................................................... 34
RF Subsystem.............................................................................. 34
External LO Generation ............................................................ 34
Internal LO Generation............................................................. 34
Applications Information .............................................................. 38
Basic Connections by Pin Description ........................................ 39
Mixer Optimization ....................................................................... 40
RF Input Balun Insertion Loss Optimization......................... 40
IIP3 Optimization ...................................................................... 40
VGS Programming..................................................................... 41
Low-Pass Filter Programming.................................................. 41
GSM Mode of Operation........................................................... 43
Register Summary .......................................................................... 44
Register Details ............................................................................... 45
Evaluation Board ............................................................................ 55
Outline Dimensions....................................................................... 61
Ordering Guide .......................................................................... 61
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
RF Specifications .......................................................................... 3
Synthesizer/PLL Specifications................................................... 4
VCO Specifications, Open-Loop................................................ 7
Logic Input and Power Specifications ....................................... 8
Digital Logic Specifications......................................................... 9
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Mixer, High Performance Mode............................................... 13
Mixer, High Efficiency Mode.................................................... 22
Synthesizer................................................................................... 23
REVISION HISTORY
3/16—Revision 0: Initial Version
Rev. 0 | Page 2 of 61
Data Sheet
ADRF6614
SPECIFICATIONS
RF SPECIFICATIONS
TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, frequency of the reference (fREF) = 122.88 MHz, fREF power = 4 dBm, fPFD
1.536 MHz, low-side LO injection, optimum RF balun (RFB) and low-pass filter (LPF) settings, unless otherwise noted.
=
Table 1. High Performance Mode
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF INTERFACE
Return Loss
Input Impedance
Tunable to >20 dB broadband via serial port
17.9
50
dB
Ω
RF Frequency Range (fRF)
IF OUTPUT INTERFACE
Output Impedance
IF Frequency Range (fIF)
DC Bias Voltage1
700
40
3000
500
+5
MHz
Differential impedance, f = 200 MHz
Externally generated
300||1.5
IFOUTx
Ω||pF
MHz
V
EXTERNAL LO INPUT
External LO Power Input
Return Loss
−5
0
−11
50
dBm
dB
Ω
Input Impedance
External VCO Input Frequency
LO Frequency Range
External VCO input supports divide by 1, 2, 4, 8, 16, and 32
Low-side or high-side LO, internally or externally
generated
250
250
5700
2850
MHz
MHz
DYNAMIC PERFORMANCE
Power Conversion Gain
4:1 IF port transformer and printed circuit board (PCB) loss
removed
9.0
dB
Voltage Conversion Gain
SSB Noise Figure
IF Output Phase Noise Under Blocking
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω
15.0
11.3
−153
dB
dB
dBc/Hz
10 dBm blocker present 10 MHz above desired the RF input,
fRF = 1900 MHz, fBLOCK = 1910 MHz, fLO = 1697 MHz, fIF =
203 MHz, IFBLOCKER = 213 MHz
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz, each RF
tone at −10 dBm
fRF1 = 1900 MHz, fRF2 = 1950 MHz, fLO = 1697 MHz, each RF
tone at −10 dBm
30
60
dBm
dBm
Input 1 dB Compression Point (P1dB)
LO to IF Output Leakage
LO to RF Input Leakage
RF to IF Output Isolation
IF/2 Spurious
10.6
−35
−45
−22
−72
−69
dBm
dBm
dBm
dB
dBc
dBc
Unfiltered IF output
−10 dBm input power
−10 dBm input power
IF/3 Spurious
POWER INTERFACE
VCC1, VCC2, VCC7, VCC12
Supply Voltage
Quiescent Current
VCC3, VCC4, VCC5, VCC6, VCC8, VCC9,
VCC10, VCC11, IFOUT1+, IFOUT1−,
IFOUT2+, IFOUT2−
Supply Voltage
Quiescent Current
3.55
3.55
3.7
260
3.85
5.25
V
mA
5
214
V
mA
LO OUTPUT (LOOUT+, LOOUT−)
Frequency Range (fLO)
Output Level
200
−5
2700
+7
MHz
dBm
Ω
Adjustable via SPI in four steps, in 50 Ω balanced load
Balanced
Output Impedance
50
1 Supply voltage must be applied from the external circuit through choke inductors.
Rev. 0 | Page 3 of 61
ADRF6614
Data Sheet
TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection,
optimum RFB and LPF settings, unless otherwise noted.
Table 2. High Efficiency Mode
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Power Conversion Gain
Voltage Conversion Gain
SSB Noise Figure
IIP3
4:1 IF port transformer and PCB loss removed
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω
8.7
dB
dB
dB
dBm
14.7
10.7
20.5
fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz,
each RF tone at −10 dBm
IIP2
fRF1 = 1900 MHz, fRF2 = 1950 MHz, fLO = 1697 MHz,
each RF tone at −10 dBm
53
dBm
Input P1dB
8.2
dBm
dBm
dBm
dB
dBc
dBc
LO to IF Output Leakage
LO to RF Input Leakage
RF to IF Output Isolation
IF/2 Spurious
Unfiltered IF output
−45.0
−52.0
−22.8
−58
−10 dBm input power
−10 dBm input power
IF/3 Spurious
−58
POWER INTERFACE
VCC1, VCC2, VCC7, VCC12
Supply Voltage
Quiescent Current
VCC3, VCC4, VCC5, VCC6, VCC8, VCC9, VCC10,
VCC11, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2−
3.55
3.55
3.7
260
3.85
5.25
V
mA
Supply Voltage
3.7
V
Quiescent Current
210
mA
SYNTHESIZER/PLL SPECIFICATIONS
High performance mode, TA = 25°C, measured on LO output, fLO = 1700 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fPFD = 1.536 MHz,
REF power (PREFIN) = 4 dBm, CSCALE = 8 mA, bleed = 0 µA, ABLDLY = 0.9 ns, integer mode loop filter, unless otherwise noted.
f
Table 3. Integer Mode
Parameter
SYNTHESIZER SPECIFICATIONS
Frequency Range (fLO
Figure of Merit (FOM)1
Test Conditions/Comments
Synthesizer specifications referenced to 1 × LO
Internally generated LO
Min
200
0.8
Typ
Max
2700
70
Unit
)
MHz
dBc/Hz/Hz
MHz
PREFIN = 6.5 dBm
−223
Phase and Frequency Detector (PFD)
Frequency (fPFD
)
Reference Spurs
fPFD = 1.536 MHz
1 × fPFD
−105
−105
−90
dBc
dBc
dBc
4 × fPFD
>4 × fPFD
CHARGE PUMP
Pump Current
Output Compliance Range
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Capacitance
Reference Divider Value
MUXOUT Output Level
Programmable to 250 µA, 500 µA, …, 8 mA
REFIN, MUXOUT pins
8
8.75
2.5
mA
V
0.7
12
320
MHz
pF
4
Programmable to 0.5, 1, 2, 3, …, 2047
VOL (lock detect output selected)
VOH (lock detect output selected)
Reference output selected
0.5
2.7
2047
0.25
V
V
%
MUXOUT Duty Cycle
50
Rev. 0 | Page 4 of 61
Data Sheet
ADRF6614
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VCO_0
Phase Noise, Locked
fLO = 2.55 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
1 kHz to 40 MHz integration bandwidth
−87
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−94.9
−103.3
−132.9
−154.1
−155.2
0.87
Integrated Phase Noise
VCO_1
Phase Noise, Locked
fLO = 2.22 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
1 kHz to 40 MHz integration bandwidth
−90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−98.4
−106.5
−136.1
−154.8
−155.5
0.63
Integrated Phase Noise
VCO_2
Phase Noise, Locked
fLO = 1.9 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
1 kHz to 40 MHz integration bandwidth
−90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−98.1
−109.8
−137.1
−155.7
−156.2
0.61
Integrated Phase Noise
VCO_3
Phase Noise, Locked
fLO = 1.6 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
1 kHz to 40 MHz integration bandwidth
−89
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−97.2
−107
−136.2
−155.7
−157.3
0.64
Integrated Phase Noise
VCO_4
Phase Noise, Locked
fLO = 1.57 GHz
1 kHz offset
50 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
1 kHz to 40 MHz integration bandwidth
−90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−109
−119
−144
−145
−156
−156
0.26
Integrated Phase Noise
VCO_5
Phase Noise, Locked
fLO = 1.68 GHz
1 kHz offset
−93
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
50 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
−107
−118
−144
−145
Rev. 0 | Page 5 of 61
ADRF6614
Data Sheet
Parameter
Test Conditions/Comments
10 MHz offset
40 MHz offset
Min
Typ
Max
Unit
−157
−157.5
0.27
dBc/Hz
dBc/Hz
°rms
Integrated Phase Noise
1 kHz to 40 MHz integration bandwidth
1 The FOM is computed as phase noise (dBc/Hz) –10log10(fPFD) – 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 122.88 MHz and fREF power =
6.5 dBm with a 1.536 MHz fPFD. The FOM was computed at 50 kHz offset.
High performance mode, TA = 25°C, measured on LO output, fLO = 1700 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fPFD = 30.72 MHz, fREF power =
4 dBm, CSCALE = 250 µA, bleed = 93.75 µA, ABLDLY = 0 ns, fractional mode loop filter, unless otherwise noted.
Table 4. Fractional Mode
Parameter
Test Conditions/Comments
Synthesizer specifications referenced to 1 × LO
PREFIN = 6.5 dBm
Min Typ
Max
Unit
SYNTHESIZER SPECIFICATIONS
FOM1
219
dBc/Hz/Hz
REFERENCE CHARACTERISTICS
VCO_0
REFIN, MUXOUT pins
Phase Noise, Locked
fLO = 2.55 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
1 kHz to 40 MHz integration bandwidth
−92.5
−97.4
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−109.7
−137.6
−153.6
−155.5
0.36
Integrated Phase Noise
VCO_1
Phase Noise, Locked
fLO = 2.22 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
1 kHz to 40 MHz integration bandwidth
−93.6
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−101.8
−112.5
−140.5
−154.3
−155.3
0.32
Integrated Phase Noise
VCO_2
Phase Noise, Locked
fLO = 1.9 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
1 kHz to 40 MHz integration bandwidth
−94.2
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−101.7
−112.4
−141.3
−155.8
−156.8
0.32
Integrated Phase Noise
VCO_3
Phase Noise, Locked
fLO = 1.6 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
1 kHz to 40 MHz integration bandwidth
−93.1
−99.8
−110.9
−140.2
−155.7
−157.2
0.33
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
Integrated Phase Noise
1 The FOM is computed as phase noise (dBc/Hz) − 10log10(fPFD) – 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 122.88 MHz and fREF power =
6.5 dBm with a 30.72 MHz fPFD. The FOM was computed at 45 kHz offset.
Rev. 0 | Page 6 of 61
Data Sheet
ADRF6614
VCO SPECIFICATIONS, OPEN-LOOP
High performance mode, TA = 25°C, measured on LO output, unless otherwise noted.
Table 5.
Parameter
Test Conditions/Comments
fLO = 2.55 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
fLO = 2.15 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
fLO = 1.9 GHz
1 kHz offset
50 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
fLO = 1.6 GHz
1 kHz offset
50 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
fVCO = 3.14 GHz
1 kHz offset
50 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
fVCO = 3.36 GHz
1 kHz offset
Min
Typ
Max
Unit
VCO_0 PHASE NOISE
−50
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−104.4
−112.6
−137.7
−154
−155.1
VCO_1 PHASE NOISE
VCO_2 PHASE NOISE
VCO_3 PHASE NOISE
−54
−106.1
−115
−138.9
−155.8
−155.2
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−53.6
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−106.6
−114.6
−140.8
−155.4
−156.3
−48.5
−106
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−115.3
−139.2
−140.2
−157.7
−156.3
VCO_4 PHASE NOISE
−53.8
−110.3
−118
−139.5
−140.6
−155.4
−157.4
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
VCO_5 PHASE NOISE
−54
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
50 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
−108.3
−116.3
−138.5
−140
−156.3
−157.8
Rev. 0 | Page 7 of 61
ADRF6614
Data Sheet
LOGIC INPUT/OUTPUT AND POWER SPECIFICATIONS
TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection,
optimum RFB and LPF settings, unless otherwise noted.
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
LOGIC INPUT/OUTPUTS
Input Voltage
SCLK, SDIO, CS
High, VIH
Low, VIL
1.4
0
3.3
0.7
V
V
Output Voltage
High, VOH
Low, VOL
IOH = −100 µA
IOL = 100 µA
2.3
V
V
0.2
Input Current, IINH/IINL
POWER SUPPLIES
High Performance Mode
Voltage Range
VCC1, VCC2, VCC7, VCC12
0.1
µA
3.55
4.75
3.7
5
5.25
5.25
V
V
VCC3, VCC4, VCC5, VCC6, VCC8, VCC9, VCC10,
VCC11, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2−
Power Dissipation
Internal LO mode (internal PLL)
External LO output enabled
External LO output disabled
2.7
2.5
W
W
High Efficiency Mode
Voltage Range
VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8,
VCC9, VCC10, VCC11, VCC12, IFOUT1+, IFOUT1−,
IFOUT2+, IFOUT2−
3.55
3.7
3.85
V
Power Dissipation
Internal LO mode (internal PLL)
External LO output enabled
External LO output disabled
2.0
1.8
W
W
Rev. 0 | Page 8 of 61
Data Sheet
ADRF6614
DIGITAL LOGIC SPECIFICATIONS
Table 7.
Symbol
Description
Min Typ Max Unit
tCLK
tDS
tDH
tS
Serial clock period
38
8
8
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Setup time between falling edge of CS and SCLK
Hold time between rising edge of CS and SCLK
Minimum period for SCLK to be in a logic high state
Minimum period for SCLK to be in a logic low state
Maximum delay between falling edge of SCLK and output data Valid for a read operation
Maximum delay between CS deactivation and SDIO bus return to high impedance
tH
tHIGH
tLOW
tACCESS
tZ
231
5
tHIGH
tH
tDS
tCLK
tS
tDH
tLOW
tACCESS
CS
DON'T CARE
tZ
DON'T CARE
DON'T CARE
SCLK
SDIO
A6
A5
A4
A3
A2
A1
A0
R/W
D15
D14
D13
D3
D2
D1
D0
DON'T CARE
Figure 2. Setup and Hold Timing Measurements
Rev. 0 | Page 9 of 61
ADRF6614
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 8.
THERMAL RESISTANCE
θJC is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Supply Voltage (VCC1, VCC2, VCC3,
VCC4, VCC5, VCC6, VCC7, VCC8, VCC9,
VCC10, VCC11, VCC12, IFOUT1+,
IFOUT1−, IFOUT2+, IFOUT2−)
−0.5 V to +5.5 V
Table 9. Thermal Resistance
Package Type
θJC
Unit
48-Lead LFCSP
1.62
°C/W
Digital Input/Output (SCLK, SDIO, CS)
RFINx
−0.3 V to +3.6 V
20 dBm
EXTVCOIN+, EXTVCOIN−
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
13 dBm
150°C
−40°C to +85°C
−65°C to +150°C
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 10 of 61
Data Sheet
ADRF6614
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
VCOVTUNE
GND
1
2
3
4
5
6
7
8
9
36
RFBCT1
35 RFIN1
34 VCC10
33 VCC9
EXTVCOIN+
EXTVCOIN–
GND
VCC8
VCC7
32
31
ADRF6614
TOP VIEW
(Not to Scale)
VCC1
30 LDO2
29 VCC6
28 VCC5
27 VCC4
26 RFIN2
25 RFBCT2
DECL1
DECL2
DECL3 10
DECL4 11
DECL5 12
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND
PLANE WITH LOW THERMAL IMPEDANCE.
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3, 6
GND
VCOVTUNE
GND
Common Ground Connection for External Loop Filter.
Control Voltage for Internal VCO.
Common Ground for External VCO.
4, 5
EXTVCOIN+, EXTVCOIN− Inputs from External VCO to Internal Divider.
7
VCC1
3.7 V VCO Supply.
8, 9
10, 11
12
13, 14
15
16
DECL1, DECL2
DECL3, DECL4
DECL5
LOOUT+, LOOUT−
LDO1
VCC2
SDIO
SCLK
LDO Output Decouplers for VCO.
External Decouplers for VCO Buffer.
External Decoupler for VCO Circuitry.
Differential Outputs of Internally Generated LO.
External Decoupling for Internal 2.5 V SPI Port LDO.
3.7 V Supply for Programmable SPI Port.
Serial Data Input/Output for Programmable SPI Port.
Clock for Programmable SPI Port.
17
18
19
CS
SPI Chip Select, Active Low.
20, 41
21, 40
22, 23
24, 37
25
VCC3, VCC11
DNC
IFOUT2+, IFOUT2−
GND
RFBCT2
RFIN2
5 V Biases for Channel 1 and Channel 2 IF.
Do Not Connect. Do not connect these pins externally.
Channel 2 Differential IF Outputs.
Ground Connections for Channel 1 and Channel 2 IF Stage.
Balun Center Tap Connection for Channel 2 RF Input.
Channel 2 RF Input.
26
27, 28, 29
30
31
32, 33, 34
35
VCC4, VCC5, VCC6
LDO2
VCC7
VCC8, VCC9, VCC10
RFIN1
5 V Supplies for Mixer LO Amplifiers.
External Decoupling for Internal 3.3 V PLL/Divider LDO.
3.7 V Supply for Mixer LO Divider Chain.
5 V Supplies for Mixer LO Amplifiers.
Channel 1 RF Input.
36
38, 39
42
RFBCT1
IFOUT1−, IFOUT1+
MUXOUT
Balun Center Tap Connection for Channel 1 RF Input.
Channel 1 Differential IF Outputs.
Internal Multiplexer Output.
Rev. 0 | Page 11 of 61
ADRF6614
Data Sheet
Pin No.
43
44
45
46
Mnemonic
Description
REFIN
LDO3
LDO4
VCC12
CPOUT
GND
Reference Input for Internal PLL (Single-Ended, CMOS).
External Decoupling for Internal 2.5 V PLL LDO.
External Decoupling for Internal 3.3 V PLL LDO.
3.7 V Supply for Internal PLL.
Charge Pump Output.
Common Ground for External Charge Pump.
47
48
EPAD
Exposed Pad. The exposed pad must be connected to a ground plane with low thermal impedance.
Rev. 0 | Page 12 of 61
Data Sheet
ADRF6614
TYPICAL PERFORMANCE CHARACTERISTICS
MIXER, HIGH PERFORMANCE MODE
TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, low-side LO injection, optimum RFB and
LPF settings, unless otherwise noted. For integer mode: fPFD = 1.536 MHz, CSCALE = 8 mA, bleed = 0 µA, ABLDLY = 0.9 ns. For fractional
mode: fPFD = 30.72 MHz, CSCALE = 250 µA, bleed = 93.75 µA, ABLDLY = 0.0 ns.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
90
85
80
75
70
65
60
55
50
45
40
35
30
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
A
A
A
A
A
A
A
A
A
A
A
A
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 4. Power Dissipation vs. RF Frequency over Three Temperatures
Figure 7. Input IP2 vs. RF Frequency over Three Temperatures
11.0
10.5
10.0
9.5
15
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
A
A
A
A
A
A
13
11
9
9.0
8.5
8.0
7.5
7.0
6.5
6.0
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
A
A
A
A
A
A
5.5
5.0
4.5
4.0
7
5
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 5. Power Conversion Gain vs. RF Frequency over Three Temperatures,
IF Balun and Board Loss Removed
Figure 8. Input P1dB vs. RF Frequency over Three Temperatures
40
38
36
34
32
30
28
26
24
22
20
18
–40°C LOCKED
–40°C EXTERNAL LO
17
16
15
14
13
12
11
10
9
+25°C LOCKED
+25°C EXTERNAL LO
+85°C LOCKED
+85°C EXTERNAL LO
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
18
16
14
12
10
A
A
A
A
A
A
8
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 6. Input IP3 vs. RF Frequency over Three Temperatures
Figure 9. SSB Noise Figure vs. RF Frequency over Three Temperatures
Rev. 0 | Page 13 of 61
ADRF6614
Data Sheet
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
2.7
2.5
2.3
2.1
1.9
RF = 900MHz, LOW-SIDE LO
RF = 900MHz, LOW-SIDE LO
RF = 1900MHz, LOW-SIDE LO
RF = 2500MHz, LOW-SIDE LO
RF = 900MHz, HIGH-SIDE LO
RF = 1900MHz, HIGH-SIDE LO
RF = 2500MHz, HIGH-SIDE LO
RF = 1900MHz, LOW-SIDE LO
RF = 2500MHz, LOW-SIDE LO
RF = 900MHz, HIGH-SIDE LO
RF = 1900MHz, HIGH-SIDE LO
RF = 2500MHz, HIGH-SIDE LO
1.7
1.5
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 10. Power Dissipation vs. Temperature for Three RF Frequencies
Figure 13. Input IP2 vs. Temperature for Three RF Frequencies
10.0
15
RF = 900MHz, LOW-SIDE LO
RF = 900MHz, LOW-SIDE LO
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
RF = 1900MHz, LOW-SIDE LO
RF = 2500MHz, LOW-SIDE LO
RF = 900MHz, HIGH-SIDE LO
RF = 1900MHz, HIGH-SIDE LO
RF = 2500MHz, HIGH-SIDE LO
RF = 1900MHz, LOW-SIDE LO
14
RF = 2700MHz, LOW-SIDE LO
RF = 900MHz, HIGH-SIDE LO
13
12
11
10
9
RF = 1900MHz, HIGH-SIDE LO
RF = 2700MHz, HIGH-SIDE LO
8
7
6
5
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 11. Power Conversion Gain vs. Temperature for Three RF Frequencies
Figure 14. Input P1dB vs. Temperature for Three RF Frequencies
35
34
33
32
31
30
29
28
27
26
25
18
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
17
16
15
14
13
12
11
10
9
24
RF = 900MHz, LOW-SIDE LO
23
RF = 1900MHz, LOW-SIDE LO
RF = 2500MHz, LOW-SIDE LO
22
RF = 900MHz, HIGH-SIDE LO
RF = 1900MHz, HIGH-SIDE LO
RF = 2500MHz, HIGH-SIDE LO
21
20
8
–40
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 12. Input IP3 vs. Temperature for Three RF Frequencies
Figure 15. SSB Noise Figure vs. Temperature for Three RF Frequencies
Rev. 0 | Page 14 of 61
Data Sheet
ADRF6614
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
85
80
75
70
65
60
55
50
45
40
35
30
RF = 2500MHz, HIGH-SIDE LO
RF = 2500MHz, LOW-SIDE LO
RF = 1900MHz, HIGH-SIDE LO
RF = 1900MHz, LOW-SIDE LO
RF = 900MHz, HIGH-SIDE LO
RF = 900MHz, LOW-SIDE LO
RF = 900MHz, LOW-SIDE LO
RF = 1900MHz, LOW-SIDE LO
RF = 2500MHz, LOW-SIDE LO
RF = 900MHz, HIGH-SIDE LO
RF = 1900MHz, HIGH-SIDE LO
RF = 2500MHz, HIGH-SIDE LO
40
80 120 160 200 240 280 320 360 400 440 480
IF FREQUENCY (MHz)
40 80 120 160 200 240 280 320 360 400 440 480
IF FREQUENCY (MHz)
Figure 16. Power Dissipation vs. IF Frequency for Three RF Frequencies
Figure 19. Input IP2 vs. IF Frequency for Three RF Frequencies
10.0
15
RF = 900MHz, LOW-SIDE LO
RF = 900MHz, LOW-SIDE LO
9.5
RF = 1900MHz, LOW-SIDE LO
RF = 1900MHz, LOW-SIDE LO
14
RF = 2500MHz, LOW-SIDE LO
RF = 2500MHz, LOW-SIDE LO
RF = 900MHz, HIGH-SIDE LO
RF = 1900MHz, HIGH-SIDE LO
RF = 2500MHz, HIGH-SIDE LO
9.0
RF = 900MHz, HIGH-SIDE LO
RF = 1900MHz, HIGH-SIDE LO
RF = 2500MHz, HIGH-SIDE LO
13
12
11
10
9
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
8
7
6
5
40
40 80 120 160 200 240 280 320 360 400 440 480
80 120 160 200 240 280 320 360 400 440 480
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 17. Power Conversion Gain vs. IF Frequency for Three RF Frequencies
Figure 20. Input P1dB vs. IF Frequency for Three RF Frequencies
18
36
34
32
30
28
26
24
22
20
–40°C, LOW-SIDE LO
+25°C, LOW-SIDE LO
17
+85°C, LOW-SIDE LO
–40°C, HIGH-SIDE LO
+25°C, HIGH-SIDE LO
+85°C, HIGH-SIDE LO
16
15
14
13
12
11
10
9
18
RF = 900MHz, LOW-SIDE LO
16
14
12
10
RF = 1900MHz, LOW-SIDE LO
RF = 2500MHz, LOW-SIDE LO
RF = 900MHz, HIGH-SIDE LO
RF = 1900MHz, HIGH-SIDE LO
RF = 2500MHz, HIGH-SIDE LO
8
50
100
150
200
250
300
350
400
450
40
80 120 160 200 240 280 320 360 400 440 480
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 18. Input IP3 vs. IF Frequency for Three RF Frequencies
Figure 21. SSB Noise Figure vs. IF Frequency for Three Temperatures
Rev. 0 | Page 15 of 61
ADRF6614
Data Sheet
–50
0
–4
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
A
A
A
–52
–54
–56
–58
–60
–62
–64
–66
–68
–70
–72
–74
–76
–78
–80
–82
–84
–86
–88
–90
–8
–12
–16
–20
–24
–28
–32
–36
–40
–44
–48
–52
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 22. IF/2 Spurious vs. RF Frequency over Three Temperatures
Figure 25. LO to IF Leakage vs. LO Frequency over Three Temperatures
–50
0
–4
–8
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
A
A
A
A
A
A
A
A
A
–52
–54
–56
–58
–60
–62
–64
–66
–68
–70
–72
–74
–76
–78
–80
–82
–84
–86
–88
–90
–12
–16
–20
–24
–28
–32
–36
–40
–44
–48
–52
–56
–60
–64
–68
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 23. IF/3 Spurious vs. RF Frequency over Three Temperatures
Figure 26. LO to RF Leakage vs. LO Frequency over Three Temperatures
0
–2
–4
–6
–8
0
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
A
A
A
A
A
A
A
A
A
–4
–8
–12
–16
–20
–24
–28
–32
–36
–40
–44
–48
–52
–56
–60
–64
2 × LO TO RF
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
–32
–34
–36
–38
–40
–42
–44
–46
2 × LO TO IF
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 24. RF to IF Isolation vs. RF Frequency over Three Temperatures
Figure 27. 2 × LO Leakage vs. LO Frequency over Three Temperatures (2 × LO
to RF and 2 × LO to IF)
Rev. 0 | Page 16 of 61
Data Sheet
ADRF6614
100
80
60
40
20
0
0
T
T
T
= –40°C
= +25°C
= +85°C
MEAN: 7.94
SD: 0.07%
A
A
A
–4
–8
–12
–16
–20
–24
–28
–32
–36
–40
–44
–48
–52
–56
–60
–64
3 × LO TO RF
3 × LO TO IF
7.70
7.75
7.80
7.85
7.90
7.95
8.00
8.05
8.10
300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO FREQUENCY (MHz)
CONVERSION GAIN (dB)
Figure 28. 3 × LO Leakage vs. LO Frequency over Three Temperatures
(3 × LO to RF and 3 × LO to IF)
Figure 31. Conversion Gain Distribution
0
100
80
60
40
20
0
MEAN: 31.23
SD: 0.34%
HIGH-SIDE LO
LOW-SIDE LO
–5
–10
–15
–20
–25
–30
–35
500
1000
1500
2000
2500
3000
27
28
29
30
31
32
33
34
35
RF FREQUENCY (MHz)
INPUT IP3 (dBm)
Figure 29. RF Port Return Loss, Fixed IF LO Return Loss
Figure 32. Input IP3 Distribution
100
80
60
40
20
0
0
–5
MEAN: 10.59
SD: 0.39%
–10
–15
–20
–25
–30
10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11.0
100
600
1100
1600
2100
2600
INPUT P1dB (dBm)
LO FREQUENCY (MHz)
Figure 30. LO Return Loss
Figure 33. Input P1dB Distribution
Rev. 0 | Page 17 of 61
ADRF6614
Data Sheet
80
75
70
65
60
55
50
45
40
35
30
25
20
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
10
8
6
4
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
A
A
A
A
A
A
2
0
0
50
100 150 200 250 300 350 400 450 500
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 34. IF Output Impedance (R Parallel C Equivalent)
Figure 37. IF Channel to Channel Isolation vs. RF Frequency
over Three Temperatures
10
9
8
7
6
5
4
3
2
1
0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
BAL_COUT = 0
BAL_COUT = 2
BAL_COUT = 4
BAL_COUT = 6
BAL_COUT = 8
BAL_COUT = 10
BAL_COUT = 12
BAL_COUT = 14
BAL_COUT = 0
BAL_COUT = 2
BAL_COUT = 4
BAL_COUT = 6
BAL_COUT = 8
BAL_COUT = 10
BAL_COUT = 12
BAL_COUT = 14
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
Figure 35. Conversion Gain vs. RF Frequency for All RFB Settings,
VGS Bit and LPF Use Optimum Settings
Figure 38. Input IP3 vs. RF Frequency for All RFB Settings,
VGS Bit and LPF Use Optimum Settings
20
18
BAL_COUT = 0
BAL_COUT = 0
BAL_COUT = 2
BAL_COUT = 4
BAL_COUT = 6
BAL_COUT = 8
BAL_COUT = 10
BAL_COUT = 12
BAL_COUT = 14
19
18
17
16
15
14
13
12
11
10
9
BAL_COUT = 2
BAL_COUT = 4
BAL_COUT = 6
BAL_COUT = 8
BAL_COUT = 10
BAL_COUT = 12
BAL_COUT = 14
17
16
15
14
13
12
11
10
9
8
7
6
5
8
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 36. Input P1dB vs. RF Frequency for All RFB Settings,
VGS Bit and LPF Use Optimum Settings
Figure 39. SSB Noise Figure vs. RF Frequency for All RFB Settings,
VGS Bit and LPF Use Optimum Settings
Rev. 0 | Page 18 of 61
Data Sheet
ADRF6614
10
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
VGS = 0
VGS = 1
VGS = 2
VGS = 3
VGS = 4
VGS = 5
VGS = 6
VGS = 7
9
8
7
6
5
4
VGS = 0
3
VGS = 1
VGS = 2
VGS = 3
VGS = 4
VGS = 5
VGS = 6
VGS = 7
2
1
0
9.0
8.5
8.0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
Figure 40. Conversion Gain vs. RF Frequency
for All VGS Bit Settings, RFB and LPF Use Optimum Settings
Figure 43. Input P1dB vs. RF Frequency for All VGS Bit Settings,
RFB and LPF Use Optimum Settings
38
14.0
VGS = 0
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
VGS = 1
13.5
VGS = 2
VGS = 3
VGS = 4
VGS = 5
VGS = 6
VGS = 7
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
VGS = 0
VGS = 1
VGS = 2
VGS = 3
VGS = 4
VGS = 5
VGS = 6
VGS = 7
9.0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 41. Input IP3 vs. RF Frequency for All VGS Bit Settings,
RFB and LPF Use Optimum Settings
Figure 44. SSB Noise Figure vs. RF Frequency for All VGS Bit Settings,
RFB and LPF Use Optimum Settings
10.0
15
LPF = 0
LPF = 2
LPF = 4
LPF = 6
LPF = 0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
LPF = 2
14
LPF = 4
LPF = 6
13
12
11
10
9
8
7
6
5
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 42. Conversion Gain vs. RF Frequency for All LPF Settings,
RFB and VGS Bit Use Optimum Settings
Figure 45. Input P1dB vs. RF Frequency for All LPF Settings,
RFB and VGS Bit Use Optimum Settings
Rev. 0 | Page 19 of 61
ADRF6614
Data Sheet
18
17
16
15
14
13
12
11
10
9
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LPF = 0
LPF = 2
LPF = 4
LPF = 6
14
LPF = 0
13
LPF = 2
12
LPF = 4
LPF = 6
11
8
10
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 46. Input IP3 vs. RF Frequency for All LPF Settings,
RFB and VGS Bit Use Optimum Settings
Figure 49. SSB Noise Figure vs. RF Frequency for All LPF Settings,
RFB and VGS Bit Use Optimum Settings
40
35
30
25
20
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
IFA_MAINBIAS = 8
IFA_MAINBIAS = 9
IFA_MAINBIAS = 10
IFA_MAINBIAS = 11
IFA_MAINBIAS = 12
IFA_MAINBIAS = 13
IFA_MAINBIAS = 14
IFA_MAINBIAS = 15
IFA_MAINBIAS = 3
IFA_MAINBIAS = 4
IFA_MAINBIAS = 5
IFA_MAINBIAS = 6
IFA_MAINBIAS = 7
IFA_MAINBIAS = 10
IFA_MAINBIAS = 11
IFA_MAINBIAS = 12
IFA_MAINBIAS = 13
IFA_MAINBIAS = 14
IFA_MAINBIAS = 15
IFA_MAINBIAS = 3
IFA_MAINBIAS = 4
IFA_MAINBIAS = 5
IFA_MAINBIAS = 6
IFA_MAINBIAS = 7
IFA_MAINBIAS = 8
IFA_MAINBIAS = 9
15
10
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 47. Power Dissipation vs. Temperature for Various IFA_MAINBIAS Settings
Figure 50. Input IP3 vs. Temperature for Various IFA_MAINBIAS Settings
2.38
36
34
32
30
28
IFA_LINBIAS = 0
IFA_LINBIAS = 1
IFA_LINBIAS = 2
IFA_LINBIAS = 3
IFA_LINBIAS = 4
IFA_LINBIAS = 5
IFA_LINBIAS = 6
IFA_LINBIAS = 7
IFA_LINBIAS = 8
IFA_LINBIAS = 9
IFA_LINBIAS = 10
IFA_LINBIAS = 11
IFA_LINBIAS = 12
IFA_LINBIAS = 13
IFA_LINBIAS = 14
IFA_LINBIAS = 15
2.36
2.34
2.32
2.30
2.28
2.26
2.24
2.22
2.20
2.18
2.16
26
24
22
IFA_LINBIAS = 0
IFA_LINBIAS = 1
IFA_LINBIAS = 2
IFA_LINBIAS = 3
IFA_LINBIAS = 4
IFA_LINBIAS = 5
IFA_LINBIAS = 6
IFA_LINBIAS = 7
IFA_LINBIAS = 8
IFA_LINBIAS = 9
IFA_LINBIAS = 10
IFA_LINBIAS = 11
IFA_LINBIAS = 12
IFA_LINBIAS = 13
IFA_LINBIAS = 14
IFA_LINBIAS = 15
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 48. Power Dissipation vs. Temperature for Various IFA_LINBIAS Settings
Figure 51. Input IP3 vs. Temperature for Various IFA_LINBIAS Settings
Rev. 0 | Page 20 of 61
Data Sheet
ADRF6614
–60
–60
–70
890MHz +10dBm
1910MHz +10dBm
2510MHz +10dBm
890MHz +10dBm
1910MHz +10dBm
2510MHz +10dBm
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
–160
–160
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
OFFSET FREQUENCY (MHz)
OFFSET FREQUENCY (MHz)
Figure 52. Phase Noise at IF Output vs. Offset Frequency with 10 dBm Blocker
in Integer Mode
Figure 53. Phase Noise at IF Output vs. Offset Frequency with 10 dBm Blocker
in Fractional Mode
Rev. 0 | Page 21 of 61
ADRF6614
Data Sheet
MIXER, HIGH EFFICIENCY MODE
TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection,
optimum RFB and LPF settings, unless otherwise noted.
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
70
65
60
55
50
45
40
35
30
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= 25°C, HIGH-SIDE LO
= 85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= 25°C, LOW-SIDE LO
= 85°C, LOW-SIDE LO
A
A
A
A
A
A
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
A
A
A
A
A
A
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 54. Power Dissipation vs. RF Frequency over Three Temperatures
Figure 57. Input IP2 vs. RF Frequency over Three Temperatures
12.0
13
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
A
A
A
A
A
A
A
A
A
A
A
A
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
12
11
10
9
8
7
6
5
4
3
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 55. Conversion Gain vs. RF Frequency over Three Temperatures
Figure 58. Input P1dB vs. RF Frequency over Three Temperatures
35
18
T
T
T
T
T
T
= –40°C, HIGH-SIDE LO
= +25°C, HIGH-SIDE LO
= +85°C, HIGH-SIDE LO
= –40°C, LOW-SIDE LO
= +25°C, LOW-SIDE LO
= +85°C, LOW-SIDE LO
–40°C LOCKED
–40°C EXTERNAL LO
A
A
A
A
A
A
33
31
29
27
25
23
21
19
17
15
13
11
9
17
16
15
14
13
12
11
10
9
+25°C LOCKED
+25°C EXTERNAL LO
+85°C LOCKED
+85°C EXTERNAL LO
7
5
8
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 56. Input IP3 vs. RF Frequency over Three Temperatures
Figure 59. SSB Noise Figure vs. RF Frequency over Three Temperatures
Rev. 0 | Page 22 of 61
Data Sheet
ADRF6614
SYNTHESIZER
VS = high performance mode, TA = 25°C, measured on LO output, fLO = 1700 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fPFD = 1.536 MHz, fREF
power = 4 dBm, integer mode loop filter, unless otherwise noted.
–40
–60
LO_DIV = ÷2
LO_DIV = ÷4
LO_DIV = ÷8
–70
–60
–80
–80
–90
–100
–110
–120
–130
–140
–150
–160
–100
–120
–140
–160
–180
1k
10k
100k
1M
10M
100M
0.001
0.01
0.1
1
10
100
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (MHz)
Figure 60. VCO_0 Open-Loop Phase Noise vs. Offset Frequency,
VCO_0 = 2.55 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V
Figure 63. VCO_0 Closed-Loop Phase Noise vs. Offset Frequency for Various
LO_DIV Dividers, fVCO_0 = 5.1 GHz
f
–40
–60
LO_DIV = ÷2
LO_DIV = ÷4
LO_DIV = ÷8
–70
–80
–60
–80
–90
–100
–110
–120
–130
–140
–150
–160
–100
–120
–140
–160
–180
1k
10k
100k
1M
10M
100M
0.001
0.01
0.1
1
10
100
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (MHz)
Figure 61. VCO_1 Open-Loop Phase Noise vs. Offset Frequency,
Figure 64. VCO_1 Closed-Loop Phase Noise vs. Offset Frequency for Various
LO_DIV Dividers, fVCO_1 = 4.5 GHz
f
VCO_1 = 2.2 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V
–40
–60
LO_DIV = ÷2
LO_DIV = ÷4
LO_DIV = ÷8
–70
–80
–60
–80
–90
–100
–110
–120
–130
–140
–150
–160
–100
–120
–140
–160
–180
1k
10k
100k
1M
10M
100M
0.001
0.01
0.1
1
10
100
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (MHz)
Figure 62. VCO_2 Open-Loop Phase Noise vs. Offset Frequency,
VCO_2 = 1.9 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V
Figure 65. VCO_2 Closed-Loop Phase Noise vs. Offset Frequency for Various
LO_DIV Dividers, fVCO_2 = 3.8 GHz
f
Rev. 0 | Page 23 of 61
ADRF6614
Data Sheet
–60
–70
–40
LO_DIV = ÷2
LO_DIV = ÷4
LO_DIV = ÷8
–60
–80
–90
–80
–100
–110
–120
–130
–140
–150
–160
–100
–120
–140
–160
1k
0.001
0.01
0.1
1
10
100
10k
100k
1M
10M
100M
OFFSET FREQUENCY (MHz)
OFFSET FREQUENCY (Hz)
Figure 66. VCO_3 Open-Loop Phase Noise vs. Offset Frequency,
Figure 69. VCO_3 Closed-Loop Phase Noise for Various LO_DIV Dividers vs.
Offset Frequency, fVCO_3 = 3.2 GHz
f
VCO_3 = 1.6 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V
–60
0
–40°C
–70
–80
+25°C
+85°C
–20
–40
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–60
–80
–100
–120
–140
–160
–180
1k
10k
100k
1M
10M
100M
0.001
0.01
0.1
1
10
100
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (MHz)
Figure 67. VCO_4 Open-Loop Phase Noise vs. Offset Frequency,
Figure 70. VCO_4 Closed-Loop Phase Noise for Various Temperatures vs.
Offset Frequency, fVCO_4 = 1.536 GHz, Divide by Two Selected
f
VCO_4 = 3.087 GHz, Divide by One Selected, VCOVTUNE = 1.5 V
0
–60
–40°C
–70
–80
+25°C
+85°C
–20
–40
–90
–60
–100
–110
–120
–130
–140
–150
–160
–170
–180
–80
–100
–120
–140
–160
–180
1k
10k
100k
1M
10M
100M
0.001
0.01
0.1
1
10
100
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (MHz)
Figure 68. VCO_5 Open-Loop Phase Noise vs. Offset Frequency,
VCO_5 = 3.375 GHz, Divide by One Selected, VCOVTUNE = 1.5 V
Figure 71. VCO_5 Closed-Loop Phase Noise for Various Temperatures vs.
Offset Frequency, fVCO_5 = 1.688 GHz, Divide by Two Selected
f
Rev. 0 | Page 24 of 61
Data Sheet
ADRF6614
–200
–90
–100
–110
–120
–130
–140
–150
–160
–170
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
50kHz OFFSET
200kHz OFFSET
–205
–210
–215
–220
–225
–230
1MHz OFFSET
40MHz OFFSET
1430
1630
1830
2030
2230
2430
2630
2830
1430
1630
1830
2030
2230
2430
2630
2830
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 72. PLL Figure of Merit (FOM) vs. LO Frequency, Integer Mode
Figure 75. Open-Loop Phase Noise vs. LO Frequency,
Divide by Two Selected
0
–70
–80
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–20
–40
1kHz OFFSET
–90
1kHz OFFSET
–100
–110
–120
–130
–140
–150
–160
–170
100kHz OFFSET
500kHz OFFSET
–60
–80
–100
–120
–140
–160
–180
100kHz OFFSET
500kHz OFFSET
10MHz OFFSET
10 MHz OFFSET
1430
1630
1830
2030
2230
2430
2630
2830
1430
1630
1830
2030
2230
2430
2630
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 73. Open-Loop Phase Noise vs. LO Frequency,
Divide by Two Selected
Figure 76. Integer Loop Filter Phase Noise vs. LO Frequency, Divide by Two
Selected, Offset = 1 kHz, 100 kHz, 500 kHz, and 10 MHz
–200
–205
–210
–215
–220
–225
–230
–60
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–80
1kHz OFFSET
–100
100kHz OFFSET
–120
500kHz OFFSET
–140
–160
10MHz OFFSET
–180
1525
1530
1535
1540
1545
1430
1630
1830
2030
2230
2430
2630
2830
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 74. PLL Figure of Merit (FOM) vs. LO Frequency, Fractional Mode,
Offset = 45 kHz, Bleed = 125 µA
Figure 77. VCO_4 GSM Loop Filter Phase Noise, Divide by Two Selected,
Offset = 1 kHz, 100 kHz, 500 kHz, and 10 MHz
Rev. 0 | Page 25 of 61
ADRF6614
Data Sheet
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–80
–40°C
+25°C
–40°C
+25°C
+85°C
+85°C
–90
50 kHz OFFSET
200 kHz OFFSET
–100
–110
–120
–130
–140
–150
–160
–170
LO_DIV = ÷2
1MHz OFFSET
40MHz OFFSET
LO_DIV = ÷4
4360
VCO FREQUENCY (MHz)
LO_DIV = ÷8
2860
3360
3860
4860 5360
1430
1630
1830
2030
2230
2430
2630
LO FREQUENCY (Hz)
Figure 78. Integer Loop Filter Phase Noise vs. LO Frequency, Divide by Two
Selected, Offset = 50 kHz, 200 kHz, 1 MHz, and 40 MHz
Figure 81. 10 kHz to 40 MHz Integrated Phase Noise vs. VCO Frequency,
Divide by Two, Four, and Eight, Including Spurs
–90
0.40
–40°C
–40°C
+25°C
+85°C
+25°C
+85°C
–100
0.35
50kHz OFFSET
–110
0.30
0.25
0.20
0.15
0.10
0.05
0
–120
200kHz OFFSET
–130
–140
1MHz OFFSET
–150
–160
40MHz OFFSET
–170
1525
1530
1535
1540
1545
1525
1530
1535
1540
1545
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 79. VCO_4 GSM Loop Filter Phase Noise, Divide by Two Selected,
Offset = 50 kHz, 200 kHz, 1 MHz, and 40 MHz
Figure 82. VCO_4 10 kHz to 40 MHz Integrated Phase Noise vs. VCO
Frequency, For Various Temperatures, Including Spurs
–60
–80
–40°C
–40°C
+25°C
+85°C
+25°C
+85°C
–90
–80
1kHz OFFSET
–100
50kHz OFFSET
–100
–110
100kHz OFFSET
–120
200kHz OFFSET
–120
–130
500kHz OFFSET
–140
–140
1MHz OFFSET
–150
–160
10MHz OFFSET
–160
40MHz OFFSET
–180
1668
–170
1668
1673
1678
1683
1688
1693
1698
1703
1708
1673
1678
1683
1688
1693
1698
1703
1708
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 80. VCO_5 GSM Loop Filter Phase Noise, Divide by Two Selected,
Offset = 1 kHz, 100 kHz, 500 kHz, and 10 MHz
Figure 83. VCO_5 GSM Loop Filter Phase Noise, Divide by Two Selected,
Offset = 50 kHz, 200 kHz, 1 MHz, and 40 MHz
Rev. 0 | Page 26 of 61
Data Sheet
ADRF6614
–75
–85
1.4
–40°C LO_DIV = ÷2
+25°C LO_DIV = ÷2
+85°C LO_DIV = ÷2
–40°C LO_DIV = ÷4
+25°C LO_DIV = ÷4
+85°C LO_DIV = ÷4
–40°C
+25°C
+85°C
1.2
–40°C LO_DIV = ÷8
+25°C LO_DIV = ÷8
+85°C LO_DIV = ÷8
LO_DIV = ÷2
1.0
0.8
0.6
0.4
0.2
0
–95
–105
–115
–125
–135
LO_DIV = ÷8
5360
LO_DIV = ÷4
4360
VCO FREQUENCY (MHz)
2860
3360
3860
4860
2860
3360
3860
4360
4860
5360
VCO FREQUENCY (MHz)
Figure 84. 10 kHz to 40 MHz Integrated Phase Noise vs. VCO Frequency,
Divide by Two, Four, and Eight, Excluding Spurs
Figure 87. fPFD Reference Spurs vs. VCO Frequency,
1 × PFD Offset, Measured at LO Output, Integer Mode
–75
–85
0.40
–40°C LO_DIV = ÷2
+25°C LO_DIV = ÷2
+85°C LO_DIV = ÷2
–40°C LO_DIV = ÷4
+25°C LO_DIV = ÷4
+85°C LO_DIV = ÷4
–40°C LO_DIV = ÷8
+25°C LO_DIV = ÷8
+85°C LO_DIV = ÷8
–40°C
+25°C
+85°C
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–95
–105
–115
–125
–135
2860
3360
3860
4360
4860
5360
1525
1530
1535
1540
1545
VCO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 85. VCO_4 10 kHz to 40 MHz Integrated Phase Noise vs. VCO
Frequency, For Various Temperatures, Excluding Spurs
Figure 88. fPFD Reference Spurs vs. VCO Frequency,
3 × PFD Offset, Measured at LO Output, Integer Mode
0.45
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
1668
1673
1678
1683
1688
1693
1698
1703
1708
1668
1673
1678
1683
1688
1693
1698
1703
1708
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 86. VCO_5 10 kHz to 40 MHz Integrated Phase Noise vs. VCO
Frequency, For Various Temperatures, Including Spurs
Figure 89. VCO_5 10 kHz to 40 MHz Integrated Phase Noise vs. VCO
Frequency, For Various Temperatures, Excluding Spurs
Rev. 0 | Page 27 of 61
ADRF6614
Data Sheet
–75
–60
–62
–64
–66
–68
–70
–72
–74
–76
–78
–80
–40°C LO_DIV = ÷2
–40°C LO_DIV = ÷8
+25°C LO_DIV = ÷8
+85°C LO_DIV = ÷8
–40°C
+25°C
+85°C
+25°C LO_DIV = ÷2
+85°C LO_DIV = ÷2
–40°C LO_DIV = ÷4
+25°C LO_DIV = ÷4
+85°C LO_DIV = ÷4
–85
–95
–105
–115
–125
–135
2860
3360
3860
4360
4860
5360
1430
1630
1830
2030
2230
2430
2630
2830
VCO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 90. fPFD Reference Spurs vs. VCO Frequency,
2 × PFD Offset, Measured at LO Output, Integer Mode
Figure 93. fPFD Reference Spurs vs. LO Frequency,
2 × PFD Offset, Measured at LO Output, Fractional Mode
–75
–85
–70
–72
–74
–76
–78
–80
–82
–84
–86
–88
–90
–40°C LO_DIV = /2
+25°C LO_DIV = /2
+85°C LO_DIV = /2
–40°C LO_DIV = /4
+25°C LO_DIV = /4
+85°C LO_DIV = /4
–40°C LO_DIV = /8
+25°C LO_DIV = /8
+85°C LO_DIV = /8
–40°C
+25°C
+85°C
–95
–105
–115
–125
–135
2860
3360
3860
4360
4860
5360
1430
1630
1830
2030
2230
2430
2630
2830
VCO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 91. fPFD Reference Spurs vs. VCO Frequency,
4 × PFD Offset, Measured at LO Output, Integer Mode
Figure 94. fPFD Reference Spurs vs. LO Frequency,
3 × PFD Offset, Measured at LO Output, Fractional Mode
–60
–65
–70
–75
–80
–85
–90
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–76
–78
–80
–82
–84
–86
–88
–90
1430
1630
1830
2030
2230
2430
2630
2830
1430
1630
1830
2030
2230
2430
2630
2830
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 92. fPFD Reference Spurs vs. LO Frequency,
1 × PFD Offset, Measured at LO Output, Fractional Mode
Figure 95. fPFD Reference Spurs vs. LO Frequency,
4 × PFD Offset, Measured at LO Output, Fractional Mode
Rev. 0 | Page 28 of 61
Data Sheet
ADRF6614
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
IF AT –40°C
IF AT +25°C
IF AT +85°C
LO AT –40°C
LO AT +25°C
LO AT +85°C
–20
–40
–60
–80
–100
–120
–140
1430
1630
1830
2030
2230
2430
2630
2830
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 96. fPFD Reference Spurs vs. LO Frequency, Divide by Two Selected, 1 ×
PFD Offset, Measured on LO Output and IF Output
Figure 99. RF to LO Output Feedthrough, LO_DRV_LVL = 0
10
1520
LO_DRV_LVL = 0 AT –40°C
LO_DRV_LVL = 0 AT +25°C
LO_DRV_LVL = 0 AT +85°C
LO_DRV_LVL = 1 AT –40°C
LO_DRV_LVL = 1 AT +25°C
LO_DRV_LVL = 1 AT +85°C
8
3
1515
1510
1505
1500
1495
1490
1485
1480
4
2
0
–2
–4
–6
–8
–10
–12
LO_DRV_LVL = 2 AT –40°C
LO_DRV_LVL = 2 AT +25°C
LO_DRV_LVL = 2 AT +85°C
LO_DRV_LVL = 3 AT –40°C
LO_DRV_LVL = 3 AT +25°C
LO_DRV_LVL = 3 AT +85°C
350
850
1350
1850
2350
2850
0
10
20
30
40
50
60
70
80
90
100
LO FREQUENCY (MHz)
LOCK TIME (ms)
Figure 97. LO Amplitude vs. LO Frequency, LO_DRV_LVL = 0, 1, 2, and 3
Figure 100. LO Frequency Settling Time, Integer Mode Loop Filter,
Integer Mode
225
1520
1515
1510
1505
1500
1495
1490
1485
1480
LO_DRV_LVL = 3 AT –40°C
LO_DRV_LVL = 3 AT +25°C
215
LO_DRV_LVL = 3 AT +85°C
LO_DRV_LVL = 2 AT –40°C
LO_DRV_LVL = 2 AT +25°C
LO_DRV_LVL = 2 AT +85°C
205
195
185
175
165
155
145
135
125
LO_DRV_LVL = 1 AT –40°C
LO_DRV_LVL = 1 AT +25°C
LO_DRV_LVL = 1 AT +85°C
LO_DRV_LVL = 0 AT –40°C
LO_DRV_LVL = 0 AT +25°C
LO_DRV_LVL = 0 AT +85°C
350
850
1350
1850
2350
2850
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LO FREQUENCY (MHz)
LOCK TIME (ms)
Figure 98. Supply Current for VCC7 vs. LO Frequency,
LO_DRV_LVL = 0, 1, 2, and 3
Figure 101. LO Frequency Settling Time, Fractional Loop Filter, Fractional
Mode
Rev. 0 | Page 29 of 61
ADRF6614
Data Sheet
–60
–70
2.5
3.18GHz
3.81GHz
4.45GHz
5.08GHz
+85°C
–40°C
2.0
–80
–90
1.5
1.0
0.5
0
–100
–110
–120
–130
–140
–100 –80 –60 –40 –20
0
20
40
60
80
100
1430
1630
1830
2030
2230
2430
2630
2830
OFFSET FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 102. VCO Tuning Voltage (VTUNE) vs. LO Frequency for Lock at Cold
Drift to Hot
Figure 104. PFD Spurs vs. Offset Frequency for Four VCOs, Integer Mode
3.5
2.5
+85°C
–40°C
+85°C
–40°C
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
1525
1530
1535
1540
1545
1430
1630
1830
2030
2230
2430
2630
2830
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 103. VTUNE vs. LO Frequency for Lock at Hot Drift to Cold
Figure 105. VCO_4 VTUNE vs. LO Frequency for Lock at Hot Drift to Cold
Rev. 0 | Page 30 of 61
Data Sheet
ADRF6614
3.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
+85°C
–40°C
+85°C
–40°C
3.0
2.5
2.0
1.5
1.0
0.5
0
1668
1673
1678
1683
1688
1693
1698
1703
1708
1668
1673
1678
1683
1688
1693
1698
1703
1708
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 106. VCO_5 VTUNE vs. LO Frequency for Lock at Hot Drift to Cold
Figure 108. VCO_5 VTUNE vs. LO Frequency for Lock at Cold Drift to Hot
3.5
+85°C
–40°C
3.0
2.5
2.0
1.5
1.0
0.5
0
1525
1530
1535
1540
1545
LO FREQUENCY (MHz)
Figure 107. VCO_4 VTUNE vs. LO Frequency for Lock at Cold Drift to Hot
Rev. 0 | Page 31 of 61
ADRF6614
Data Sheet
SPURIOUS PERFORMANCE
(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products are measured in dBc from the
IF output power level. Data was measured only for frequencies less than 6 GHz; blank cells indicate frequencies that were not measured. Typical
noise floor of the measurement system = −100 dBm.
High Performance Mode
VS = high performance mode, TA = 25°C, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection,
optimum RFB and LPF settings, unless otherwise noted.
Table 11. RF = 900 MHz, LO = 697 MHz
M
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
−27.1
0.0
−32.1
−52.5
−68.8
<−100
<−100
<−100
<−100
<−100
<−100
−39.1
−18.4
−73.4
−79.5
<−100
<−100
<−100
<−100
<−100
−27.0
−56.6
−64.9
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−54.2
−43.6
<−100
−94.1
<−100
<−100
<−100
<−100
<−100
<−100
−48.5
−66.7
−68.3
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−69.3
−53.5
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−65.6
−87.4
−80.6
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−35.5
−55.3
−88.2
<−100
<−100
<−100
−73.5
−68.9
−88.4
−56.6
−43.6
−66.7
−53.5
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
N
Table 12. RF = 1900 MHz, LO = 1697 MHz
M
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
−37.0
0.0
−31.2
−47.9
−81.6
−93.5
<−100
−64.2
−52.1
−81.2
−75.2
<−100
<−100
−30.2
−70.8
<−100
−74.4
−71.9
<−100
<−100
−67.2
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
N
<−100
<−100
<−100
<−100
<−100
Table 13. RF = 2500 MHz, LO = 2297 MHz
M
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
−40.7
0.0
−44.1
−49.4
−75.4
−91.9
<−100
−29.0
−81.0
−58.7
−79.0
−74.7
<−100
<−100
−87.3
<−100
−84.7
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
N
<−100
−92.5
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
Rev. 0 | Page 32 of 61
Data Sheet
ADRF6614
High Efficiency Mode
VS = high efficiency mode, TA = 25°C, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection,
optimum RFB and LPF settings, unless otherwise noted.
Table 14. RF = 900 MHz, LO = 697 MHz
M
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
−30.4
0.0
−34.1
−52.6
−68.8
−96.4
−97.9
<−100
<−100
<−100
<−100
−46.7
−19.2
−71.9
−74.7
<−100
<−100
<−100
<−100
<−100
−29.6
−61.6
−59.9
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−57.4
−44.3
−93.0
−85.0
<−100
<−100
<−100
<−100
<−100
<−100
−51.2
−64.0
−67.8
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−74.7
−53.6
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−62.7
−91.8
−79.0
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−37.7
−70.3
−86.4
<−100
<−100
<−100
−73.2
−66.4
−81.0
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
N
Table 15. RF = 1900 MHz, LO = 1697 MHz
M
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
−41.4
0.0
−35.1
−46.9
−74.6
−89.9
<−100
−69.0
−52.2
−71.3
−67.7
<−100
<−100
−30.5
−71.5
<−100
−74.4
−67.7
<−100
<−100
−63.6
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
N
<−100
<−100
<−100
<−100
<−100
Table 16. RF = 2500 MHz, LO = 2297 MHz
M
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
−42.3
0.0
−48.6
−48.6
−71.6
−86.2
−77.0
−29.1
−75.6
−59.4
−70.8
−66.9
<−100
<−100
−88.8
−59.4
−77.0
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
N
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
Rev. 0 | Page 33 of 61
ADRF6614
Data Sheet
THEORY OF OPERATION
The ADRF6614 consists of two primary components: the RF
subsystem and the LO subsystem. The combination of design,
process, and packaging technology allows the functions of these
subsystems to be integrated into a single die, using mature
packaging and interconnection technologies to provide a high
performance device with excellent electrical, mechanical, and
thermal properties. The wideband frequency response and flexible
frequency programming simplifies the receiver design, saves
on-board space, and minimizes the need for external components.
analog-to-digital converter (ADC) input while providing optimum
second-order intermodulation suppression. The differential output
impedance of the IF amplifier is approximately 200 Ω. If operation
in a 50 Ω system is desired, the output can be transformed to 50 Ω
by using a 4:1 transformer or an LC impedance matching network.
EXTERNAL LO GENERATION
The ADRF6614 LO can be generated by an externally applied
source or by using the internal PLL synthesizer. To select the
external LO mode, write 011 to Register 0x22, Bits[2:0] and apply
the differential LO signal to Pin 4 (EXTVCOIN+) and Pin 5
(EXTVCOIN−).
The RF subsystem consists of an integrated, tunable, low loss RF
balun, a double balanced, passive MOSFET mixer, a tunable sum
termination network, and an IF amplifier.
Internal dividers allow the externally applied LO signal to be
divided before this signal arrives at the mixer LO input. The
divider value is set by Register 0x22, Bits[5:3] and has possible
values of 1, 2, 4, and 8. With the divider set to 1, the externally
applied LO input frequency range is 250 MHz to 2850 MHz.
When using a divider value of other than 1, the maximum
externally applied LO frequency is 5700 MHz.
The LO subsystem consists of a multistage, limiting LO amplifier.
The purpose of the LO subsystem is to provide a large, fixed ampli-
tude, balanced signal to drive the mixer independent of the level of
the LO input. A schematic of the device is shown in Figure 110.
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a tunable, low loss, unbalanced to balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended to use a blocking capacitor
to avoid running excessive dc current through the device. The RF
balun can easily support an RF input frequency range of 700 MHz
to 3000 MHz. This balun is tuned over the frequency range by a SPI
controlled switched capacitor network at the output of the RF balun.
The external LO input pins present a broadband differential 50 Ω
input impedance. The EXTVCOIN+ and EXTVCOIN− input
pins must be ac-coupled. When not in use, EXTVCOIN+ and
EXTVCOIN− can be left unconnected.
INTERNAL LO GENERATION
Reference Input Circuitry
The ADRF6614 includes an on-chip PLL for LO synthesis. The
PLL, shown in Figure 109, consists of a reference input and input
dividers, a PFD, a charge pump, VCOs, and a programmable
fractional/integer divider with a 2× prescaler.
The resulting balanced RF signal is applied to a passive mixer that
commutates the RF input in accordance with the output of the LO
subsystem. The passive mixer is a balanced, low loss switch that adds
minimum noise to the frequency translation. The only noise con-
tribution from the mixer is due to the resistive loss of the switches,
which is in the order of a few ohms.
The reference path takes in a reference clock and divides it by a
factor of 1 to 8191 before passing it to the PFD. The PFD compares
this signal to the divided down signal from the VCO. Depending
on the PFD polarity selected, the PFD sends an up or down signal
to the charge pump if the VCO signal is slow or fast compared to
the reference frequency. The charge pump sends a current pulse
to the off-chip loop filter to increase or decrease the tuning
voltage (VCOVTUNE).
The IF amplifier is a balanced feedback design that simultaneously
provides the gain, noise figure, and input impedance required to
achieve the overall performance. The balanced open-collector
output of the IF amplifier, with an impedance modified by the
feedback within the amplifier, permits the output to be connected
directly to a high impedance filter, a differential amplifier, or an
CPOUT
VCOVTUNE
LOOP FILTER
R8
R10
1 TO 8191
(REG 0x21[11:0])
CHARGE
PUMP
REFIN
PFD
R7
C18
C20
C22
C23
GNDCP
FRAC
MOD
(REG 0x02, REG 0x03,
REG 0x04)
N = INT +
2×
PRESCALER
MIXER 1 LO
MIXER 2 LO
LO DIVIDER
(1, 2, 4, 8, 16, 32)
(REG 0x22[5:3])
EXTERNAL
LO INPUT
Figure 109. LO Generation Block Diagram
Rev. 0 | Page 34 of 61
Data Sheet
ADRF6614
In-band (within the band of the loop filter) phase noise perfor-
mance is typically limited by the reference source. Due to the
inherent phase noise reduction when performing frequency
division, improved in-band phase noise performance can be
achieved with higher reference divide values. However, the
divide chain adds its own small amount of phase noise; thus,
there is a limit on how much improvement can be gained by
increasing the divider value.
Table 18. Fractional Mode Loop Filter Components and PLL
Dynamic Settings
Loop Filter Components PLL Dynamic Settings
C18
R7
C20
1000 pF
700 Ω
33 nF
R8
C22
R10
C23
1.8 kΩ
560 pF
20 kΩ
39 pF
Loop Filters
Defining a loop filter for the ADRF6614 depends on several
dynamic: the PLL REFIN and PFD frequency and desired PFD
and fractional spur levels. Higher reference and PFD frequencies
spread the PFD spurs over a wider bandwidth (wider separation
between spurs), but also lead to higher levels of spurs coupling
through the reference divider chain. Lower reference and PFD
frequencies lower the spacing between PFD spurs, but the spur
levels can be significantly improved by using lower frequencies.
At lower PFD frequencies, it may also be possible to achieve the
desired synthesizer frequency step size using the integer divider
mode, therefore eliminating the risk of fractional spurs. Table 17
shows the recommended loop filter components and dynamic
loop settings when using integer mode and PFD frequencies at
less than 10 MHz.
CSCALE
Bleed Current
ABLDLY
500 µA
93.75 µA
0 ns
For GSM mode of operation at the PFD rate of 1.536 MHz, the
recommended loop filter components and dynamic loop
settings are shown in Table 19.
Table 19. GSM Mode Loop Filter Components and PLL
Dynamic Settings
Loop Filter Components PLL Dynamic Settings
C18
R7
2200 pF
1.2 kΩ
47 nF
C20
R8
C22
R10
C23
CSCALE
Bleed Current
ABLDLY
1 kΩ
Table 17. Integer Mode Loop Filter Components and PLL
Dynamic Settings
Loop Filter Components PLL Dynamic Settings
1200 pF
6.2 kΩ
330 pF
8 mA
0 µA
0.9 ns
C18
R7
C20
1500 pF
910 Ω
33 nF
R8
C22
R10
C23
1.8 kΩ
560 pF
20 kΩ
39 pF
VCOs and Dividers
The ADRF6614 has six internal VCOs. Considering the range of
these VCOs, the fixed 2× prescaler after the VCO, and the LO_DIV
(1, 2, 4, 8, 16, and 32) range, the total LO range allows an RF
generation of 200 MHz to 2700 MHz.
CSCALE
Bleed Current
ABLDLY
8000 µA
0 µA
0.9 ns
Table 20. VCO Range
VCO_SEL (Register 0x22, Bits[2:0]) Frequency Range (GHz)
If a smaller frequency step size is desired, the ADRF6614 can be
used in fractional mode. The 16-bit FRAC_DIV and MOD_DIV
values available in the ADRF6614 mean that small step sizes
can be achieved with high PFD frequencies. PFD spurs may be
higher in amplitude, but are spaced further apart. Fractional
spurs may be present as well.
000
001
010
011
100
101
4.6 to 5.7
4.02 to 4.6
3.5 to 4.02
2.85 to 3.5
3.050 to 3.094
3.336 to 3.416
Rev. 0 | Page 35 of 61
ADRF6614
Data Sheet
For the VCO_0, VCO_1, VCO_2, and VCO_3 selections, it is
required to set VTUNE_DAC_SLOPE (Register 0x49, Bits[13:9]) =
11d, VTUNE_DAC_OFFSET (Register 0x49, Bits[8:0]) = 184d,
VCO_LDO_R2 (Register 0x22, Bits[11:8]) = 0d, and VCO_
LDO_R4 (Register 0x22, Bits[15:12]) = 5d. For VCO_4 and
VC0_5 selections, the required settings are VTUNE_DAC_
SLOPE (Register 0x49, Bits[13:9]) = 9d, VTUNE_DAC_OFFSET
(Register 0x49, Bits[8:0]) = 171d, VCO_LDO_R2 (Register 0x22,
Bits[11:8]) = 2d, and VCO_LDO_R4 (Register 0x22, Bits[15:12]) =
10d. In transitioning from a GSM VCO (VCO_4 and VCO_5)
to an octave VCO, the LDO settings must be changed before
changing the VCO selection.
The lock detect signal is available as one of the selectable outputs
through the MUXOUT pin; a logic high indicates that the loop is
locked. The MUXOUT pin is controlled by the REF_MUX_SEL bits
(Register 0x21, Bits[14:13]); the PLL lock detect signal is the default
configuration.
To ensure that the PLL locks to the desired frequency, follow
the proper write sequence of the PLL registers. The PLL
registers must be configured accordingly to achieve the
desired frequency, and the last writes must be to Register 0x02
(INT_DIV in Table 26), Register 0x03 (FRAC_DIV in Table 26),
or Register 0x04 (MOD_DIV in Table 26). When one of these
registers is programmed, an internal VCO calibration is
initiated, which is the last step in locking the PLL.
The N-divider divides down the differential VCO signal to the PFD
frequency. The N-divider can be configured for fractional mode or
integer mode by addressing the DIV_MODE bit (Register 0x02,
Bit 15). The default configuration is set for fractional mode.
The time it takes to lock the PLL after the last register is written
can be broken down into two parts: VCO band calibration and
loop settling.
The following equations can be used to determine the N value and
the PLL frequency:
After the last register is written, the PLL automatically performs
a VCO band calibration to choose the correct VCO band. This
calibration takes approximately 5120 PFD cycles. For a 40 MHz
fVCO
fPFD
=
f
PFD, this corresponds to 128 µs. After calibration is complete, the
2 × N
feedback action of the PLL causes the VCO to lock eventually to
the correct frequency. The speed with which this locking occurs
depends on the nonlinear cycle slipping behavior, as well as the
small signal settling of the loop. For an accurate estimation of
the lock time, download the ADIsimPLL™ tool, which correctly
captures these effects. In general, higher bandwidth loops tend
to lock faster than lower bandwidth loops.
where:
f
f
PFD is the phase frequency detector frequency.
VCO is the voltage controlled oscillator frequency.
N is the fractional divide ratio.
FRAC
N = INT +
MOD
Additional LO Controls
where:
INT is the integer divide ratio programmed in Register 0x02.
FRAC is the fractional divide ratio programmed in Register 0x03.
MOD is the modulus divide ratio programmed in Register 0x04.
To access the LO signal going to the mixer core through the
LOOUT+ and LOOUT− pins (Pin 13 and Pin 14), enable the
LO_DRV_EN bit in Register 0x01, Bit 7. This setting offers direct
monitoring of the LO signal to the mixer for debug purposes; or the
LO signal can be used to daisy-chain many devices synchronously.
One ADRF6614 can serve as the master where the LO signal is
sourced, and the subsequent slave devices share the same LO signal
from the master. This flexibility substantially eases the LO
requirements of a system with multiple LOs.
f
PFD × 2 ×N
fLO
=
LO_DIVIDER
where:
LO is the LO frequency going to the mixer core when the loop is
f
locked.
LO_DIVIDER is the final divider block that divides the VCO
frequency down by 1, 2, 4, or 8 before it reaches the mixer
(see Table 21). This control is located in the LO_DIV bits
(Register 0x22, Bits[5:3]).
The LO output drive level is controlled by the LO_DRV_LVL bits
(Register 0x22, Bits[7:6]). Table 22 shows the available drive levels.
Table 22. LO Drive Levels
LO_DRV_LVL (Register 0x22, Bits[7:6])
Amplitude (dBm)
Table 21. LO Divider
LO_DIV (Register 0x22, Bits[5:3])
00
01
10
11
−4
0.5
3
LO_DIVIDER
00
01
10
11
1
2
4
8
4.5
Rev. 0 | Page 36 of 61
Data Sheet
ADRF6614
46
41
34
33
2
47
43
42
40
39 38
8
9
10
11
DECL3
DECL4
EXPOSED
PAD
VCO
VCO
LDO BUFFER
LDO
VCC1
VCC2
VCC3
7
REFIN
DIVIDER
16
20
VCO BAND
SWITCH LDO
12
DECL5
LDO4
LOCK
DETECT
VPTAT
SCAN
PLL
CHARGE PUMP 45
3.3V LDO
VCC4 27
VCC5 28
PFD
35
36
RFIN1
N-DIVIDER
VCO
29
VCC6
DIVIDE BY
1 TO 32
RFBCT1
VCO
VCO
VCC7 31
26
RFIN2
32
VCC8
25
RFBCT2
SPI
CONTROL
INT
N-DIVIDER
44
LDO3
2.5V
LDO
4
5
EXTVCOIN+
EXTVCOIN–
SPI
2.5V
LDO
LO DIV
3.3V
LDO
1
3
6
24
37
48
17
18
19
13
14
21
22 23
15
30
Figure 110. Simplified Schematic
Rev. 0 | Page 37 of 61
ADRF6614
Data Sheet
APPLICATIONS INFORMATION
recommended to ac couple the RF and LO input ports to
prevent nonzero dc voltages from damaging the RF balun or LO
input circuit. A RFIN capacitor value of 22 pF is recommended.
The ADRF6614 mixer is designed to downconvert radio
frequencies (RF) primarily between 700 MHz and 3000 MHz to
lower intermediate frequencies (IF) between 40 MHz to 500 MHz.
Figure 111 depicts the basic connections of the mixer. It is
+5V
330nH
330nH
150pF
(0402)
IFOUT1
22pF
(0402)
150pF
(0402)
10µF
(0603)
0.1µF
(0402)
10pF
(0402)
10kΩ
(0402)
6.8pF
(0402)
REFIN
10µF
(0603)
0.1µF
(0402)
10pF
(0402)
150pF
(0402)
10kΩ
(0402)
22pF
(0402)
50Ω
(0402)
10µF
0.1µF
(0402)
10pF
(0402)
(0603)
100pF
(0402)
10µF
(0603)
1000pF
(0402)
2700pF
(0402)
10µF
(0603)
0.1µF
(0402)
10pF
(0402)
3.16kΩ
(0402)
100pF
(0402)
10µF
(0603)
46
41
34
33
2
47
43
42
40
39 38
8
9
DECL3
10
11
EXPOSED
PAD
100pF
(0402)
10µF
(0603)
VCO
VCO
DECL4
LDO BUFFER
VCC1
LDO
100pF
(0402)
10µF
(0603)
7
REFIN
DIVIDER
10µF
(0603)
0.1µF
(0402)
10pF
(0402)
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
DECL5
LDO4
16
VCO BAND
12
10µF
0.1µF
10pF
LOCK
SWITCH LDO
100pF
(0402)
10µF
(0603)
(0402)
(0402)
DETECT
(0603)
20
27
28
29
31
32
VPTAT
SCAN
PLL
10µF
(0603)
0.1µF
(0402)
10pF
(0402)
CHARGE PUMP 45
3.3V LDO
100pF
(0402)
10µF
(0603)
PFD
10µF
(0603)
0.1µF
(0402)
10pF
(0402)
22pF
(0402)
10µF
(0603)
0.1µF
(0402)
10pF
(0402)
RFIN1
RFIN1
RFIN2
35
36
N-DIVIDER
VCO
DIVIDE BY
1 TO 32
RFBCT1
10µF
(0603)
0.1µF
(0402)
10pF
(0402)
10pF
(0402)
10nF
(0603)
VCO
VCO
22pF
(0402)
10µF
(0603)
0.1µF
(0402)
10pF
(0402)
RFIN2
26
25
RFBCT2
10µF
(0603)
0.1µF
(0402)
10pF
(0402)
10pF
(0402)
10nF
(0603)
SPI
CONTROL
INT
N-DIVIDER
2.5V
LDO3
100pF
(0402)
44
LDO
10pF
(0402)
10µF
(0603)
EXTVCOIN+
EXTVCOIN–
LOIN
4
5
SPI
2.5V
LDO
LO DIV
3.3V
LDO
100pF
(0402)
22 23
1
3
6
24
37
48
17
18
19
13
14
21
15
30
100pF
(0402)
10µF
(0603)
GND
100pF
(0402)
10µF
(0603)
100pF
(0402)
100pF
(0402)
150pF
(0402)
LOOUT
IFOUT2
150pF
(0402)
150pF
(0402)
330nH
330nH
+5V
Figure 111. Basic Connections Diagram
Rev. 0 | Page 38 of 61
Data Sheet
ADRF6614
BASIC CONNECTIONS BY PIN DESCRIPTION
Table 23. Basic Connections
Pin No.
Mnemonic
Description
Basic Connection
5 V Power
Decouple to GND with a 10 µF, a 0.1 µF, and a 10 pF
capacitor as close to the pin as possible.
7
VCC1
5 V VCO supply
16
VCC2
5 V supply for SPI port
20, 41
VCC3, VCC11
5 V biases for IF Channel 2 and IF Channel 1
5 V supplies for mixer LO amplifier
27, 28, 29, 32, 33, 34 VCC4, VCC5, VCC6,
VCC8, VCC9, VCC10
31
46
VCC7
VCC12
5 V supply for mixer LO divider chain
5 V supply for internal PLL
Internal LDO Nodes
Decouple to GND with a 10 µF and a 100 pF
capacitor, as close to the pin as possible.
8, 9
DECL1, DECL2
VCO LDO outputs
10, 11, 12
15
30
DECL3, DECL4, DECL5 External decoupling for VCO circuitry
LDO1
LDO2
External decoupling for internal 2.5 V SPI LDO
External decoupling for internal 3.3 V
PLL/divider LDO
44
45
LDO3
LDO4
External decoupling for internal 2.5 V PLL LDO
External decoupling for internal 3.3 V PLL LDO
GND
Connect directly to the PCB ground through a low
impedance connection.
1
3, 6
24, 37
48
GND
GND
GND
GND
External loop filter ground
Common ground for external loop filter
IF stage, Channel 2 and Channel 1 ground
External charge pump ground
SPI
17
18
SDIO
SCLK
CS
SPI port data input/output
SPI port clock
SPI port chip select
19
RF, Mixer, IF Path
4, 5
EXTVCOIN+,
EXTVCOIN−
LOOUT+, LOOUT−
IFOUT2+, IFOUT2−
External VCO or LO inputs
DC block with 100 pF capacitors.
DC block with 100 pF capacitors.
Bias to 5 V supply with 330 nH inductors and dc
block with 150 pF capacitors.
13, 14
22, 23
Differential LO outputs
Channel 2 differential IF outputs
25
RFBCT2
Internal mixer bias control for Channel 2 RF
input
Decouple to GND with a 10 pF and a 10 nF
capacitor, as close to the pin as possible.
26
36
RFIN2
RFBCT1
Channel 2 single-ended RF input
Internal mixer bias control for Channel 1 RF
input
DC block with a 22 pF capacitor.
Decouple to GND with a 10 pF and a 10 nF
capacitor, as close to the pin as possible.
35
38, 39
RFIN1
IFOUT1−, IFOUT1+
Channel 1 single-ended RF input
Channel 1 differential IF outputs
DC block with a 22 pF capacitor.
Bias to 5 V supply with 330 nH inductors and dc
block with 150 pF capacitors.
PLL/VCO
2
43
47
VCOVTUNE
REFIN
CPOUT
Control voltage for internal VCO
External reference for internal PLL
Charge pump output
Output from external loop filter.
Input to external loop filter.
Other
42
MUXOUT
DNC
Output for various internal analog signals,
including PLL lock detect and voltage
proportional to absolute temperature (VPTAT)
Can be read directly from the pin; the user must be
careful of loading effects; not a low impedance output.
21, 40
Do not connect
Rev. 0 | Page 39 of 61
ADRF6614
Data Sheet
MIXER OPTIMIZATION
figure. The contour plot is located directly underneath the surface
plot. The best approach for reading the figure is to localize the
peaks on the surface plot, which indicate maximum IIP3, and to
follow the same color pattern to the contour plot to determine the
optimized IFA main bias and linearity bias settings.
35
RF INPUT BALUN INSERTION LOSS OPTIMIZATION
At lower input frequencies, more capacitance is needed. This
increase is achieved by programming higher codes into
BAL_COUT. At high frequencies, less capacitance is required;
therefore, lower BAL_COUT codes are appropriate.
As shown in Figure 112 and Figure 113, this tuning range can
be further optimized by adding capacitance across the RF input
in conjunction with tuning BAL_COUT. This added capacitance
can help to increase the low frequency range of the device
significantly.
30
25
20
15
0
–2
–4
IFA_LINBIAS = 0
IFA_LINBIAS = 1
IFA_LINBIAS = 2
IFA_LINBIAS = 3
IFA_LINBIAS = 4
IFA_LINBIAS = 5
IFA_LINBIAS = 6
IFA_LINBIAS = 7
IFA_LINBIAS = 8
IFA_LINBIAS = 9
IFA_LINBIAS = 10
IFA_LINBIAS = 11
IFA_LINBIAS = 12
IFA_LINBIAS = 13
IFA_LINBIAS = 14
10
5
–6
–8
–10
–12
–14
–16
0
0
2
4
6
8
10
12
14
16
IFA_MAINBIAS
Figure 114. IIP3 vs. Main Bias (IFA_MAINBIAS) and Linearity Bias
(IFA_LINBIAS) Level at IF Frequency = 50 MHz
NO CAP
1pF
4pF
35
30
25
20
15
5.6pF
6.8pF
–18
2pF
3.3pF
–20
500
900
1300
1700
2100
2500
2900
RF FREQUENCY (MHz)
Figure 112. Return Loss; Optimum BAL_COUT vs. RF Frequency for Various
Tuning Capacitor Values on RFINx Using a High-Side LO
0
–2
IFA_LINBIAS = 0
IFA_LINBIAS = 1
IFA_LINBIAS = 2
IFA_LINBIAS = 3
IFA_LINBIAS = 4
IFA_LINBIAS = 5
IFA_LINBIAS = 6
IFA_LINBIAS = 7
IFA_LINBIAS = 8
IFA_LINBIAS = 9
IFA_LINBIAS = 10
IFA_LINBIAS = 11
IFA_LINBIAS = 12
IFA_LINBIAS = 13
IFA_LINBIAS = 14
–4
10
5
–6
–8
–10
–12
–14
–16
0
0
2
4
6
8
10
12
14
16
IFA_MAINBIAS
Figure 115. IIP3 vs. Main Bias (IFA_MAINBIAS) and Linearity Bias
(IFA_LINBIAS) Level at IF Frequency = 100 MHz
NO CAP
1pF
2pF
3.3pF
4pF
5.6pF
6.8pF
35
30
25
20
15
–18
–20
500
900
1300
1700
2100
2500
2900
RF FREQUENCY (MHz)
Figure 113. Return Loss; Optimum BAL_COUT vs. RF Frequency for Various
Tuning Capacitor Values on RFINx Using a Low-Side LO
IIP3 OPTIMIZATION
IFA_LINBIAS = 0
IFA_LINBIAS = 1
IFA_LINBIAS = 2
IFA_LINBIAS = 3
IFA_LINBIAS = 4
IFA_LINBIAS = 5
IFA_LINBIAS = 6
IFA_LINBIAS = 7
IFA_LINBIAS = 8
IFA_LINBIAS = 9
IFA_LINBIAS = 10
IFA_LINBIAS = 11
IFA_LINBIAS = 12
IFA_LINBIAS = 13
IFA_LINBIAS = 14
In applications in which performance is critical, the ADRF6614
offers IIP3 optimization. The IF amplifier bias current can be
reduced to trade performance vs. power consumption. This
tradeoff saves on the overall power at the expense of degraded
performance.
10
5
0
0
2
4
6
8
10
12
14
16
Figure 114 to Figure 117 show the IIP3 sweeps for all combinations
of IFA main bias and linearity bias. The IIP3 vs. main bias and
linearity bias figures show both a surface and a contour plot in one
IFA_MAIN
Figure 116. IIP3 vs. Main Bias (IFA_MAINBIAS) and Linearity Bias
(IFA_LINBIAS) Level at IF Frequency = 150 MHz
Rev. 0 | Page 40 of 61
Data Sheet
ADRF6614
35
30
25
20
15
VGS PROGRAMMING
The ADRF6614 allows programmability for internal gate-to-
source voltages (VGS) for optimizing mixer performance over
the desired frequency bands. The ADRF6614 default VGS
setting is 0. Both channels of the ADRF6614 are programmed
together using the same VGS setting. Power conversion gain,
input IP3, input P1dB, and SSB noise figure can be optimized,
as shown in Figure 40, Figure 41, Figure 43, and Figure 44,
respectively.
IFA_LINBIAS = 0
IFA_LINBIAS = 8
IFA_LINBIAS = 9
IFA_LINBIAS = 10
IFA_LINBIAS = 11
IFA_LINBIAS = 12
IFA_LINBIAS = 13
IFA_LINBIAS = 14
IFA_LINBIAS = 1
IFA_LINBIAS = 2
IFA_LINBIAS = 3
IFA_LINBIAS = 4
IFA_LINBIAS = 5
IFA_LINBIAS = 6
IFA_LINBIAS = 7
10
5
LOW-PASS FILTER PROGRAMMING
The ADRF6614 allows programmability for the low-pass filter
terminating the mixer output. This filter blocks sum term mixing
products at the expense of some noise figure and gain and can
significantly increase input IP3. The ADRF6614 default LPF setting
is 0. Both channels of the ADRF6614 are programmed together
using the same LPF settings. Power conversion gain, input P1dB,
input IP3, and SSB noise figure can be optimized as shown in
Figure 42, Figure 45, Figure 46, and Figure 49, respectively.
0
0
2
4
6
8
10
12
14
16
IFA_MAINBIAS
Figure 117. IIP3 vs. Main Bias (IFA_MAINBIAS) and Linearity Bias
(IFA_LINBIAS) Level at IF Frequency = 200 MHz
Rev. 0 | Page 41 of 61
ADRF6614
Data Sheet
Table 24. Recommended Optimum Settings for High Performance Mode (in Decimal)
RF Frequency (MHz)
LO Frequency (MHz)
IFA_MAINBIAS
IFA_LINBIAS
BAL_COUT
LPF
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
VGS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
497
597
697
797
897
997
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
11
11
11
11
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
14
10
10
10
10
10
6
6
4
4
4
4
4
4
4
2
2
2
2
1097
1197
1297
1397
1497
1597
1697
1797
1897
1997
2097
2197
2297
2397
2497
2597
2697
2797
2
2
0
0
Table 25. Recommended Optimum Settings for High Efficiency Mode (in Decimal)
RF Frequency (MHz)
LO Frequency (MHz)
IFA_MAINBIAS
IFA_LINBIAS
BAL_COUT
LPF
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
VGS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
497
597
697
797
897
997
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
13
13
13
13
13
13
13
13
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
14
10
10
10
10
10
6
6
4
4
4
4
4
4
4
2
2
2
2
1097
1197
1297
1397
1497
1597
1697
1797
1897
1997
2097
2197
2297
2397
2497
2597
2697
2797
2
2
0
0
Rev. 0 | Page 42 of 61
Data Sheet
ADRF6614
When using the VCO_4 or VCO_5 cores, it is required to
GSM MODE OF OPERATION
set VTUNE_DAC_SLOPE (Register 0x49, Bits[13:9]) = 9d,
VTUNE_DAC_OFFSET (Register 0x49, Bits[8:0]) = 171d,
VCO_LDO_R2 (Register 0x22, Bits[11:8]) = 2d, and VCO_
LDO_R4 (Register 0x22, Bits[15:12]) = 10d. In transitioning
from a GSM VCO (VCO_4 and VCO_5) to an octave VCO, the
LDO settings must be changed before changing the VCO
selection.
The ADRF6614 supports GSM phase noise specifications in
typical GSM bands such as the 800 MHz, 900 MHz, 1800 MHz,
and 1900 MHz. GSM phase noise performance in the 800 MHz
and 900 MHz bands is met by simply tuning the integrated
PLLVCO to the desired frequency.
Integrated VCO cores (VCO_4 and VCO_5) support GSM phase
noise performance in the 1800 MHz and 1900 MHz GSM bands.
To ensure that GSM phase noise performance is achieved when
using the ADRF6614 in 1800 MHz or 1900 MHz bands, select
the VCO_4 core by writing the VCO_SEL bits in the VCO_
CTRL1 register (Register 0x22, Bits[2:0]) for a frequency range
of 1.525 GHz to 1.547 GHz, and the VCO_5 core for a frequency
range of 1.668 GHz to 1.708 GHz.
–20
1: 1kHz
2: 10kHz
3: 50kHz
–88.8656dBc/Hz
–91.0102dBc/Hz
–111.8226dBc/Hz
–30
–40
4: 100kHz –121.2806dBc/Hz
5: 500kHz –141.0461dBc/Hz
6: 800kHz –145.2453dBc/Hz
–50
7: 1MHz
–148.3557dBc/Hz
–60
8: 10MHz –158.4950dBc/Hz
9: 40MHz –158.6742dBc/Hz
10: 100MHz –157.3591dBc/Hz
–70
–80
START: 500Hz
STOP: 20MHz
CENTER: 10.00025MHz
SPAN: 19.9995MHz
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
1
2
INTG NOISE: –47.5392dBc/19.7MHz
RMS NOISE: 5.93684 mrad
340.156mdeg
RMS JITTER: 615.168fs
RESIDUAL FM: 866.159Hz
The VCO_4 and VCO_5 cores operate at fundamental frequencies
of 3.050 GHz to 3.094 GHz and 3.336 GHz to 3.416 GHz, respec-
tively. To generate the desired LO frequency in the 1800 MHz
and 1900 MHz bands, enable divide by 2 by writing to LO_DIV
(Register 0x22, Bits[5:3]).
3
4
10
5
6
7
8
9
1k
10k
100k
1M
10M
100M
For the GSM mode of operation, the recommended loop filter
components and dynamic loop settings are shown in Table 19 at
the PFD rate of 1.536 MHz.
FREQUENCY (Hz)
Figure 118. GSM Phase Noise Performance at 1.535 GHz
See Figure 118 for the GSM mode phase noise performance
of −145 dBc/Hz at 800 kHz offset at the carrier frequency of
1.535 GHz.
Rev. 0 | Page 43 of 61
ADRF6614
Data Sheet
REGISTER SUMMARY
Table 26. Register Summary
Reg. Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x00 SOFT_RESET
[15:8]
[7:0]
SOFT_RESET[15:8]
SOFT_RESET[7:0]
0x0000
R
0x01 ENABLES
[15:8] LO_LDO_EN
[7:0] LO_DRV_EN
LO_PATH_EN
0x0000 RW
LDO_3P3_EN
0x02 INT_DIV
0x03 FRAC_DIV
0x04 MOD_DIV
0x10 IF_BIAS
[15:8] DIV_MODE
INT_DIV[14:8]
0x0058 RW
0x0250 RW
0x0600 RW
0x02B5 RW
[7:0]
INT_DIV[7:0]
[15:8]
[7:0]
FRAC_DIV[15:8]
FRAC_DIV[7:0]
MOD_DIV[15:8]
MOD_DIV[7:0]
[15:8]
[7:0]
[15:8] IFA_LIN_HIEFFP
IFA_LINBIAS_EN
IFA_LINBIAS[3:2]
IFA_MAINBIAS_EN
[7:0]
[15:8]
[7:0]
IFA_LINBIAS[1:0]
UNUSED
IFA_MAINBIAS
CSCALE
0x20 CP_CTRL
0x0026 RW
BLEED_
BLEED
POLARITY
0x21 PFD_CTRL1
0x22 VCO_CTRL1
0x30 BALUN_CTRL
0x40 PFD_CTRL2
0x42 DITH_CTRL1
0x43 DITH_CTRL2
[15:8] UNUSED
[7:0]
REF_MUX_SEL
PFD_POLARITY
REFSEL[7:0]
REFSEL[11:8]
0x0003 RW
0x000A RW
0x0000 RW
0x0010 RW
0x000E RW
0x0001 RW
0x0000 RW
[15:8]
[7:0]
VCO_LDO_R4
BAL_COUT
VCO_LDO_R2
VCO_SEL
LPF
LO_DRV_LVL
UNUSED
LO_DIV
[15:8]
[7:0]
VGS
RESERVED
[15:8]
[7:0]
UNUSED
ABLDLY[3]
CLKEDGE
ABLDLY[2:0]
UNUSED[3:0]
CPCTRL
UNUSED[11:4]
DITH_EN
[15:8]
[7:0]
DITH_MAG
DITH_VAL_H
[15:8]
[7:0]
DITH_VAL_L[15:8]
DITH_VAL_L[7:0]
UNUSED[9:2]
0x44 SYNTH_FCNTN_ [15:8]
CTRL
[7:0]
UNUSED[1:0]
BANDCAL_DIVD_
CLR
0x45 VCO_CTRL2
0x46 VCO_CTRL3
[15:8]
[7:0]
UNUSED
0x0020 RW
0x0000 RW
VCO_BAND_SRC
BAND
[15:8]
[7:0]
UNUSED
VCO_CNTR_
DONE
VCO_BAND
0x47 VCO_CNTR_
CTRL
[15:8]
[7:0]
UNUSED[11:4]
0x0000 RW
UNUSED[3:0]
VCO_CNTR_EN
0x48 VCO_CNTR_RB [15:8]
[7:0]
VCO_CNTR_RB[15:8]
VCO_CNTR_RB[7:0]
0x0000 R
0x49 VTUNE_DAC_
CTRL
[15:8]
UNUSED
VTUNE_DAC_SLOPE
VTUNE_DAC_
OFFSET[8]
0x0000 RW
0x0000 RW
[7:0]
VTUNE_DAC_OFFSET[7:0]
UNUSED
0x4A VCO_BUF_LDO [15:8]
[7:0]
VCOBUF_LDO_R4
VCOBUF_LDO_R2
Rev. 0 | Page 44 of 61
Data Sheet
ADRF6614
REGISTER DETAILS
Address: 0x00, Reset: 0x0000, Name: SOFT_RESET
Table 27. Bit Descriptions for SOFT_RESET
Bits
Bit Name
Settings
Description
Reset
0x0
0x0
Access
[15:0]
SOFT_RESET
Soft reset bit.
R
R
0
Any write to this register asserts a soft reset command.
Address: 0x01, Reset: 0x0000, Name: ENABLES
Table 28. Bit Descriptions for ENABLES
Bits
Bit Name
LO_LDO_EN
LO2_ENP
Settings
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
15
Power up LO LDO.
LO 2 enable.
14
RW
13
BALUN_EN
LO1_ENP
Input balun enable.
LO 1 enable.
RW
12
RW
11
DIV2P5_EN
PWRUPRX
Enable dividers 2.5 V LDO.
Power up Rx.
RW
[10:9]
RW
0x0 Power down both mixer channels.
0x1 Power up mixer Channel 1.
0x2 Power up mixer Channel 2.
0x3 Power up both mixer channels.
External LO path enable.
8
7
LO_PATH_EN
LO_DRV_EN
0x0
0x0
RW
RW
LO driver enable.
Rev. 0 | Page 45 of 61
ADRF6614
Data Sheet
Bits
6
Bit Name
Settings
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
VCOBUF_LDO_EN
REF_BUF_EN
VCO_EN
VCO buffer LDO enable.
Reference buffer enable.
Power up VCOs.
5
RW
4
RW
3
DIV_EN
Power up dividers.
Power up charge pump.
Power up VCO LDO.
Power up 3.3 V LDO.
RW
2
CP_EN
RW
1
VCO_LDO_EN
LDO_3P3_EN
RW
0
RW
Address: 0x02, Reset: 0x0058, Name: INT_DIV
Table 29. Bit Descriptions for INT_DIV
Bits
Bit Name
Settings
Description
Reset
Access
15
DIV_MODE
Set fractional/integer mode.
Fractional.
Integer.
0x0
RW
0
1
[14:0]
INT_DIV
Set divider INT value.
0x58
RW
Address: 0x03, Reset: 0x0250, Name: FRAC_DIV
Table 30. Bit Descriptions for FRAC_DIV
Bits
Bit Name
Settings
Description
Reset
Access
[15:0]
FRAC_DIV
Set divider FRAC value.
0x250
RW
Address: 0x04, Reset: 0x0600, Name: MOD_DIV
Table 31. Bit Descriptions for MOD_DIV
Bits
Bit Name
Settings
Description
Reset
Access
[15:0]
MOD_DIV
Set divider MOD value.
0x600
RW
Rev. 0 | Page 46 of 61
Data Sheet
ADRF6614
Address: 0x10, Reset: 0x02B5, Name: IF_BIAS
Table 32. Bit Descriptions for IF_BIAS
Bits
Bit Name
Settings
Description
Reset
Access
15
IFA_LIN_HIEFFP
Linearity RDAC.
0x0
RW
0
1
High performance mode.
High efficiency mode.
14
IFA_MAIN_HIEFFP
Main RDAC.
0x0
RW
0
1
High performance mode.
High efficiency mode.
[13:12] IFA_LINSLOPE
[11:10] IFA_MAINSLOPE
Linearity slope adjust for IF amps (IPMix).
Main slope adjust for IF amps (IPMix).
Linearity bias adjust for IF amps (IPMix).
Enable internal linearity bias adjust for IF amps (IPMix).
Main bias adjust for IF amps (IPMix).
Enable internal main bias adjust for IF amps (IPMix).
0x0
0x0
0xa
0x1
0xa
0x1
RW
RW
RW
RW
RW
RW
[9:6]
5
IFA_LINBIAS
IFA_LINBIAS_EN
IFA_MAINBIAS
IFA_MAINBIAS_EN
[4:1]
0
Address: 0x20, Reset: 0x0026, Name: CP_CTRL
Table 33. Bit Descriptions for CP_CTRL
Bits Bit Name Settings
[15:14] UNUSED
Description
Reset
0x0
Access
RW
Unused.
[13:8]
7
[6:0]
CSCALE
BLEED_POLARITY
BLEED
Charge pump current adjust.
Charge pump bleed current polarity.
Charge pump bleed.
0x0
0x0
0x26
RW
RW
RW
Rev. 0 | Page 47 of 61
ADRF6614
Data Sheet
Address: 0x21, Reset: 0x0003, Name: PFD_CTRL1
Table 34. Bit Descriptions for PFD_CTRL1
Bits
Bit Name
Settings
Description
Reset
0x0
Access
RW
15
UNUSED
Unused.
[14:13] REF_MUX_SEL
Reference output divide ratio/VPTAT/SCAN/LOCK_DET.
0x0
RW
000 LOCK_DET.
001 VPTAT.
010 REFCLK.
011 REFCLK/2.
100 REFCLK × 2.
101 REFCLK/8.
110 REFCLK/4.
111 SCAN.
12
PFD_POLARITY
REFSEL
PFD polarity.
Positive.
Negative.
0x0
0x3
RW
RW
0
1
[11:0]
Reference input divide ratio.
Rev. 0 | Page 48 of 61
Data Sheet
ADRF6614
Address: 0x22, Reset: 0x000A, Name: VCO_CTRL1
Table 35. Bit Descriptions for VCO_CTRL1
Bits
Bit Name
Settings
Description
Reset
0x0
Access
RW
[15:12] VCO_LDO_R4
VCO LDO R4 resistor control setting.
VCO LDO R2 resistor control setting.
External LO amplitude.
00 −0.8 dBm/15 mA.
01 4.6 dBm/28 mA.
10 7.5 dBm/40 mA.
11 9.2 dBm/49 mA.
LO divider.
00 Divide by 1.
01 Divide by 2.
10 Divide by 4.
11 Divide by 8.
[11:8]
[7:6]
VCO_LDO_R2
LO_DRV_LVL
0x0
RW
0x0
RW
[5:3]
[2:0]
LO_DIV
0x1
0x2
RW
RW
VCO_SEL
Select VCO core/external LO.
000 VCO_0 4.6 GHz to 5.7 GHz.
001 VCO_1 4.02 GHz to 4.6 GHz.
010 VCO_2 3.5 GHz to 4.02 GHz.
011 VCO_3 2.85 GHz to 3.5 GHz.
100 VCO_4 3.050 GHz to 3.094 GHz
101 VCO_5 3.336 GHz to 3.416 GHz
110 External LO/VCO.
111 None
Rev. 0 | Page 49 of 61
ADRF6614
Data Sheet
Address: 0x30, Reset: 0x0000, Name: BALUN_CTRL
Table 36. Bit Descriptions for BALUN_CTRL
Bits
Bit Name
Settings
Description
Reset
0x0
0x0
Access
RW
RW
[15:14] UNUSED
[13:11] VGS
Unused.
Mixer VGS bias.
[10:8]
[7:4]
[3:0]
LPF
BAL_COUT
RESERVED
Mixer output IF low-pass filter.
Set balun COUT (both channels).
Reserved, set to 0x0.
0x0
0x0
0x0
RW
RW
RW
Address: 0x40, Reset: 0x0010, Name: PFD_CTRL2
Table 37. Bit Descriptions for PFD_CTRL2
Bits
Bit Name
UNUSED
ABLDLY
Settings
Description
Reset
0x0
Access
RW
[15:9]
[8:5]
Unused.
Set antibacklash delay.
0x0
RW
00 0 ns.
01 0.5 ns.
10 0.75 ns.
11 0.9 ns.
Rev. 0 | Page 50 of 61
Data Sheet
ADRF6614
Bits
Bit Name
Settings
Description
Reset
Access
[4:2]
CPCTRL
Set charge pump control.
0x4
RW
000 Both on.
001 Pump down.
010 Pump up.
011 Tristate.
100 PFD.
101 Unused.
110 Unused.
111 Unused.
[1:0]
CLKEDGE
Set PFD edge sensitivity.
0x0
RW
00 Divider and reference down edge.
01 Divider down edge, reference up edge.
10 Divider up edge, reference down edge.
11 Divider and reference up edge.
Address: 0x42, Reset: 0x000E, Name: DITH_CTRL1
Table 38. Bit Descriptions for DITH_CTRL1
Bits
[15:4]
3
Bit Name
UNUSED
DITH_EN
Settings
Description
Reset
0x0
Access
RW
Unused register bits.
Set dither enable.
Disable.
0x1
RW
0
1
Enable.
[2:1]
0
DITH_MAG
Dither magnitude.
Highest bit of 17-bit dither value.
0x3
0x0
RW
RW
DITH_VAL_H
Address: 0x43, Reset: 0x0001, Name: DITH_CTRL2
Table 39. Bit Descriptions for DITH_CTRL2
Bits
Bit Name
Settings
Description
Reset
Access
[15:0]
DITH_VAL_L
Lowest 16 bits of 17-bit dither value.
0x1
RW
Rev. 0 | Page 51 of 61
ADRF6614
Data Sheet
Address: 0x44, Reset: 0x0000, Name: SYNTH_FCNTN_CTRL
Table 40. Bit Descriptions for SYNTH_FCNTN_CTRL
Bits
Bit Name
Settings
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
[15:6]
UNUSED
Unused.
5
4
3
2
1
0
DIV_SDM_DIS
VCOCNT_CG_DIS
BANDCAL_CG_DIS
SDM_CG_DIS
SDM_DIVD_CLR
BANDCAL_DIVD_CLR
Disable sigma-delta modulator (SDM) divider.
Disable built in self test (BIST) clock.
Disable VCO band calibration (BANDCAL) clock.
Disable SDM clock.
Clear SDM divider.
Clear BANDCAL divider.
Address: 0x45, Reset: 0x0020, Name: VCO_CTRL2
Table 41. Bit Descriptions for VCO_CTRL2
Bits
[15:8]
7
Bit Name
Settings
Description
Reset
0x0
Access
RW
UNUSED
Unused.
VCO_BAND_SRC
Set VCO band source.
Automatic
Manual
0x0
RW
0
1
[6:0]
BAND
Set VCO band.
0x20
RW
Rev. 0 | Page 52 of 61
Data Sheet
ADRF6614
Address: 0x46, Reset: 0x0000, Name: VCO_CTRL3
Table 42. Bit Descriptions for VCO_CTRL3
Bits
[15:8]
7
Bit Name
Settings
Description
Reset
0x0
0x0
Access
UNUSED
VCO_CNTR_DONE
VCO_BAND
Unused.
RW
R
R
Read back BIST counter status.
Read back output of band capacitor mux.
[6:0]
0x0
Address: 0x47, Reset: 0x0000, Name: VCO_CNTR_CTRL
Table 43. Bit Descriptions for VCO_CNTR_CTRL
Bits
[15:4]
[3:2]
1
Bit Name
Settings
Description
Reset
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
UNUSED
Unused.
VCO_CNTR_REFCNT
VCO_CNTR_CLR
VCO_CNTR_EN
BIST counter integration interval.
Clear BIST counter.
Enable BIST counter.
0
Address: 0x48, Reset: 0x0000, Name: VCO_CNTR_RB
Table 44. Bit Descriptions for VCO_CNTR_RB
Bits
Bit Name
Settings
Description
Reset
Access
[15:0]
VCO_CNTR_RB
Read back output of BIST counter.
0x0
R
Rev. 0 | Page 53 of 61
ADRF6614
Data Sheet
Address: 0x49, Reset: 0x0000, Name: VTUNE_DAC_CTRL
Table 45. Bit Descriptions for VTUNE_DAC_CTRL
Bits
Bit Name
Settings
Description
Reset
0x0
Access
RW
[15:14] UNUSED
Unused.
[13:9]
[8:0]
VTUNE_DAC_SLOPE
VTUNE_DAC_OFFSET
Set VTUNE proportional to absolute temperature (PTAT ) DAC.
Set VTUNE zero to absolute temperature (ZTAT ) DAC.
0x0
0x0
RW
RW
Address: 0x4A, Reset: 0x0000, Name: VCO_BUF_LDO
Table 46. Bit Descriptions for VCO_BUF_LDO
Bits
Bit Name
Settings
Description
Reset
0x0
0x0
Access
RW
RW
[15:8]
[7:4]
[3:0]
UNUSED
VCOBUF_LDO_R4
VCOBUF_LDO_R2
Unused.
VCOBUF LDO R4 control.
VCOBUF LDO R2 control.
0x0
RW
Rev. 0 | Page 54 of 61
Data Sheet
ADRF6614
EVALUATION BOARD
An evaluation board is available for the ADRF6614. The standard
evaluation board schematic is presented in Figure 119. The USB
interface circuitry schematic is presented in Figure 121 and/or
Figure 120. The evaluation board layout is shown in Figure 122
and Figure 123. The evaluation board is fabricated using
Rogers® 3003 material. Table 47 details the configuration for the
mixer characterization. The evaluation board software is
available on www.analog.com.
Rev. 0 | Page 55 of 61
ADRF6614
Data Sheet
2
0 9 5 1 - 1 4 1
D
G N
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
P A
- 1 T O U I F
+ 1 T O U I F
C
1 1 C V C
T U O X M U
D G N
- 2 T U O I F
+ 2 T U O P I F
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
D N
C
D N
C V C 3
_ I F V C C
I F C C V _
L E
C L K
N I
F
R E
N _ C S
K L S C
O I S D
C V C 2
1 O L D
3 O L D
4 O L D
2 1 C V C
U T O C P
P L L O 2 P L 5 D
P L L O 3 P L 3 D
N T H C _ S V Y C
A
D A T
Y N T H C _ S V C
5 S P I O 2 P L D
D
G N
E P
- T U O L O
+ T U O L O
D
Figure 119. Evaluation Board, Main Circuitry
Rev. 0 | Page 56 of 61
Data Sheet
ADRF6614
3
0 9 5 1 - 1 1 4
6
M T T 8 - 2 1 0 S M L
8 6 0 M T T - 2 1 S M L
C
V C
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
P A
D
D
G N
P U E K W A
8 D F _ P D 0
9 D F _ P D 1
0 1 D 2 _ D F P
1 1 D 3 _ D F P
2 1 D 4 _ D F P
3 1 D 5 _ D F P
4 1 D 6 _ D F P
5 1 D 7 _ D F P
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
V C C
G N
B
_ U S 3 V 3
7 D F _ 7 P B
6 D F _ 6 P B
5 D F _ 5 P B
4 D F _ 4 P B
3 D F _ 3 P B
2 D F _ 2 P B
1 D F _ 1 P B
0 D F _ 0 P B
D
G N
U T O K C L
V C C
C
V C
G N
P A
B
_ U S 3 V 3
S D A
S C L
D
D
D
Figure 120. Evaluation Board, Legacy USB Interface
Rev. 0 | Page 57 of 61
ADRF6614
Data Sheet
Figure 121. Evaluation Board, Analog Devices, Inc. SDP-S USB Interface
Rev. 0 | Page 58 of 61
Data Sheet
ADRF6614
Table 47. Evaluation Board Bill of Materials
Components
Description
Default Conditions
C1, C2, C8, C11, C12,
C13, C14, C15, C18,
C19, C20, C23, C26,
C27
Power supply decoupling. Nominal supply decoupling consists of a
0.1 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.
C1, C2, C26, C27 = 0.1 μF (size 0402)
C8, C11, C12, C13, C14, C15, C18, C19
C20, C23 = 10 pF (size 0402)
C6, C7, C24, C25
RF input interface. The input channels are ac-coupled through C6 and
C24. C7 and C25 provide bypassing for the center tap of the RF input
baluns.
C6, C24 = 22 pF (size 0402)
C7, C25 = 22 pF (size 0402)
C3, C4, C5, C28, C29, IF output interface. The open-collector IF output interfaces are biased
C3, C4, C5, C28, C29, C30 = 120 pF (size 0402)
L1, L2, L3, L4 = 470 nH (size 0603)
R20, R23 = open
R21, R22 = 0 Ω (size 0402)
T1, T2 = TC4-1W+ (Mini-Circuits®)
C30, L1, L2, L3, L4,
R20, R21, R22, R23,
T1, T2
through pull-up choke Inductors L1, L2, L3, and L4. T1 and T2 are 4:1
impedance transformers used to provide single-ended IF output
interfaces, with C5 and C30 providing center tap bypassing. Remove
R21 and R22 for balanced output operation.
C17
LO interface. C17 provides ac coupling for the local oscillator input.
Bias control. R1and R2 set the bias point for the internal IF amplifier.
C17 = 22 pF (size 0402)
R1, R2 = 910 Ω (size 0402)
R1, R2
Figure 122. Evaluation Board, Top Layer
Rev. 0 | Page 59 of 61
ADRF6614
Data Sheet
Figure 123. Evaluation Board, Bottom Layer
Rev. 0 | Page 60 of 61
Data Sheet
ADRF6614
OUTLINE DIMENSIONS
7.10
7.00 SQ
6.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
37
36
48
1
0.50
BSC
*
EXPOSED
PAD
5.70
5.60 SQ
5.50
24
13
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-2
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
Figure 124. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
CP-48-13
ADRF6614ACPZ-R7
ADRF6614-EVALZ
−40°C to +85°C
48-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14115-0-3/16(0)
Rev. 0 | Page 61 of 61
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