ADRV9008BBCZ-2REEL_技术文档

Integrated Dual RF Transmitters and

Observation Receiver

ADRV9008-2

Data Sheet

global system for mobile communications (MC GSM) mode,

which has higher inband spurious-free dynamic range (SFDR),

the maximum large signal bandwidth is 75 MHz.

FEATURES

Dual transmitters

Dual input shared observation receiver

Maximum tunable transmitter synthesis bandwidth: 450 MHz

Maximum observation receiver bandwidth: 450 MHz

Fully integrated fractional-N RF synthesizers

Fully integrated clock synthesizer

Multichip phase synchronization for RF LO and baseband

clocks

The observation path consists of a wide bandwidth direct

conversion receiver with state of the art dynamic range. The

complete receive subsystem includes dc offset correction,

quadrature correction, and digital filtering, thus eliminating the

need for these functions in the digital baseband. Several

auxiliary functions such as analog-to-digital converters (ADCs),

digital-to-analog converters (DACs), and general-purpose

inputs/outputs (GPIOs) for power amplifier (PA) and radio

frequency (RF) front-end control are also integrated.

JESD204B datapath interface

Tuning range (center frequency): 75 MHz to 6000 MHz

APPLICATIONS

2G/3G/4G/5G macrocell base stations

Active antenna systems

Massive multiple input, multiple output (MIMO)

Phased array radars

Electronic warfare

The fully integrated phase-locked loops (PLLs) provide high

performance, low power fractional-N RF frequency synthesis for

the transmitter and receiver sections. An additional synthesizer

generates the clocks needed for the converters, digital circuits, and

the serial interface. Special precautions have been taken to

provide the isolation required in high performance base station

applications. All voltage controlled oscillators (VCOs) and loop

filter components are integrated.

Military communications

Portable test equipment

GENERAL DESCRIPTION

The high speed JESD204B interface supports up to 12.288 Gbps

lane rates, resulting in two lanes per transmitter in the widest

bandwidth mode and two lanes for the observation path

receiver in the widest bandwidth mode.

The ADRV9008-2 is a highly integrated, RF agile transmit

subsystem offering dual-channel transmitters, an observation path

receiver, integrated synthesizers, and digital signal processing

functions. The IC delivers a versatile combination of high

performance and low power consumption required by

2G/3G/4G/5G macrocell base stations, and active antenna

applications.

The core of the ADRV9008-2 can be powered directly from

1.3 V regulators and 1.8 V regulators and is controlled via a

standard 4-wire serial port. Comprehensive power-down modes

are included to minimize power consumption in normal use.

The ADRV9008-2 is packaged in a 12 mm × 12 mm 196-ball

chip scale ball grid array (CSP_BGA).

The transmitters use an innovative direct conversion modulator

that achieves multicarrier macrocell base station quality

performance and low power. In 3G/4G mode, the maximum

transmitter large signal bandwidth is 200 MHz. In multicarrier

Rev. 0

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADRV9008-2

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 69

Transmitter.................................................................................. 69

Observation Receiver................................................................. 69

Clock Input.................................................................................. 69

Synthesizers................................................................................. 69

Serial Peripheral Interface (SPI)............................................... 69

JTAG Boundary Scan................................................................. 69

Power Supply Sequence ............................................................. 69

GPIO_x Pins ............................................................................... 70

Auxiliary Converters.................................................................. 70

JESD204B Data Interface .......................................................... 70

Applications Information.............................................................. 71

PCB Layout and Power Supply Recommendations............... 71

PCB Material and Stackup Selection ....................................... 71

Fanout and Trace Space Guidelines......................................... 73

Component Placement and Routing Guidelines ................... 74

RF and JESD204B Transmission Line Layout ........................ 79

Isolation Techniques Used on the ADRV9008-2W/PCBZ... 83

RF Port Interface Information.................................................. 85

Outline Dimensions....................................................................... 95

Ordering Guide .......................................................................... 95

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Current and Power Consumption Specifications................... 13

Timing Diagrams........................................................................ 14

Absolute Maximum Ratings.......................................................... 15

Reflow Profile.............................................................................. 15

Thermal Management ............................................................... 15

Thermal Resistance .................................................................... 15

ESD Caution................................................................................ 15

Pin Configuration and Function Descriptions........................... 16

Typical Performance Characteristics ........................................... 23

75 MHz to 525 MHz Band ........................................................ 23

650 MHz to 3000 MHz Band.................................................... 36

3400 MHz to 4800 MHz Band.................................................. 47

5100 MHz to 5900 MHz Band.................................................. 57

Transmitter Output Impedance................................................ 67

Observation Receiver Input Impedance.................................. 67

Terminology .................................................................................... 68

REVISION HISTORY

9/2018—Revision 0: Initial Version

Rev. 0 | Page 2 of 95

Data Sheet

ADRV9008-2

FUNCTIONAL BLOCK DIAGRAM

ADRV9008-2

ORX1

ORX1_IN+

ORX2

SYNCIN0±

SYNCIN1±

SERDOUT0±

SERDOUT1±

SERDOUT2±

SERDOUT3±

SERDIN0±

SERDIN1±

SERDIN2±

SERDIN3±

SYNCOUT0±

SYNCOUT1±

SYSREFIN±

GP_INTERRUPT

ORXx_ENABLE

TXx_ENABLE

RESET

ORX1_IN–

ORX2_IN+

ADC

LPF

ORX2_IN–

DIGITAL

PROCESSING

DECIMATION

pFIR

RF_EXT_LO_I/O+

RF_EXT_LO_I/O–

ARM

Cortex-M3

RF LO

SYNTHESIZER

AGC

DC OFFSET

QEC

TX1

TX2

TX1_OUT+

LOCAL

OSCILLATOR

LEAKAGE

TX1_OUT–

TX2_OUT+

DAC

SCLK

JESD204B

LPF

TX2_OUT–

CS

SDO

SDIO

GPIOs, AUXILIARY ADCs,

AND AUXILIARY DACs

REF_CLK_IN+

REF_CLK_IN–

CLOCK

GENERATION

GPIO_3p3_x

GPIO_x

AUXADC_x

Figure 1.

Rev. 0 | Page 3 of 95

ADRV9008-2

Data Sheet

SPECIFICATIONS

Electrical characteristics at VDDA1P3¹= 1.3 V, VDDD1P3_DIG = 1.3 V, VDDA1P8_TX = 1.8 V, T_J= full operating temperature range.

Local oscillator frequency (f_LO) = 1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer to the

Typical Performance Characteristics section for input/output circuit path loss. The device configuration profile for the 75 MHz to

525 MHz frequency range is as follows: transmitter = 50 MHz/100 MHz bandwidth (inphase quadrature (IQ) rate = 122.88 MHz),

observation receiver = 100 MHz bandwidth (IQ rate = 122.88 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.

Unless otherwise specified, the device configuration for all other frequency ranges is as follows: transmitter = 200 MHz/450 MHz

bandwidth (IQ rate = 491.52 MHz), observation receiver = 450 MHz bandwidth (IQ rate = 491.52 MHz), JESD204B rate = 9.8304 GSPS,

and device clock = 245.76 MHz.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

TRANSMITTERS

Center Frequency

Transmitter (Tx)

Synthesis Bandwidth

(BW)

75

6000

450

MHz

Transmitter Large Signal

Bandwidth (3G/4G)

Transmitter Large Signal

Bandwidth (MC GSM)

Peak-to-Peak Gain

Deviation

200

75

MHz

dB

Low intermediate frequency (IF)

mode

450 MHz bandwidth, compensated

by programmable finite impulse

response (FIR) filter

Any 20 MHz bandwidth span,

compensated by programmable FIR

filter

1.0

0.1

1

Gain Slope

dB

Deviation from Linear

Phase

Degrees 450 MHz bandwidth

Transmitter Attenuation

Power Control Range

0

32

dB

Signal-to-noise ratio (SNR) maintained

for attenuation between 0 dB and

20 dB

Transmitter Attenuation

Power Control

Resolution

Transmitter Attenuation

Integral Nonlinearity

Transmitter Attenuation

Differential Nonlinearity

0.05

0.1

INL

dB

For any 4 dB step

Monotonic

DNL

0.04

Transmitter Attenuation

Serial Peripheral

Interface 2 (SPI 2)

Timing

See Figure 4

Time from CS Going

High to Change in

Transmitter

t_SCH

19.5

6.5

24

ns

dB

Attenuation

Time Between

Consecutive

Microattenuation

Steps

t_ACH

8.1

A large change in attenuation can

be broken up into a series of smaller

attenuation changes

Time Required to Reach t_DCH

Final Attenuation

Value

800

+0.5

Time required to complete the

change in attenuation from start

attenuation to final attenuation

value

Maximum Attenuation

Overshoot During

Transition

−1.0

Rev. 0 | Page 4 of 95

Data Sheet

ADRV9008-2

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Change in Attenuation

0.5

dB

per Microstep

Maximum Attenuation

Change when CS

Goes High

32

dB

Adjacent Channel Leakage

Ratio (ACLR) (LTE)

20 MHz LTE at −12 dBFS

−67

−64

−60

dB

75 MHz < f ≤ 2800 MHz

2800 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

In Band Noise Floor

0 dB attenuation, in band noise falls

1 dB for each dB of attenuation for

attenuation between 0 dB and 20 dB

−147

−148

−149

−150.5

dBm/Hz 75 MHz < f ≤ 600 MHz

dBm/Hz 600 MHz < f ≤ 3000 MHz

dBm/Hz 3000 MHz < f ≤ 4800 MHz

dBm/Hz 4800 MHz < f ≤ 6000 MHz

Out of Band Noise Floor

0 dB attenuation, 3 × bandwidth/2

offset

−147

−153

−154

−155.5

dBm/Hz 75 MHz < f ≤ 600 MHz

dBm/Hz 600 MHz < f ≤ 3000 MHz

dBm/Hz 3000 MHz < f ≤ 4800 MHz

dBm/Hz 4800 MHz < f ≤ 6000 MHz

Interpolation Images

MC GSM Mode

3G/4G Mode

−95

−80

85

dBc

dB

Transmitter to

75 MHz < f ≤ 600 MHz

Transmitter Isolation

75

70

65

56

dB

600 MHz < f ≤ 2800 MHz

2800 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 5700 MHz

5700 MHz < f ≤ 6000 MHz

Image Rejection

Within Large Signal

Bandwidth

Quadrature error correction (QEC)

active

70

65

62

60

40

dB

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 4000 MHz

4000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Assumes that distortion power

density is 25 dB below desired

power density

Beyond Large Signal

Bandwidth

Maximum Output Power

0 dBFS, continuous wave (CW) tone

into 50 Ω load, 0 dB transmitter

attenuation

9

7

6

4.5

dBm

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

0 dB transmitter attenuation

Third-Order Output

Intermodulation

Intercept Point

OIP3

29

27

23

dBm

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 4000 MHz

4000 MHz < f ≤ 6000 MHz

Rev. 0 | Page 5 of 95

ADRV9008-2

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Third-Order

Intermodulation

IM3

−70

dBc

2 × GSMK carriers, ΣP_OUT

−12 dBFS rms

=

The two carriers can be placed

anywhere within the transmitter band

such that the IM3 products fall within

the transmitter band or within 10 MHz

of the band edges

Carrier Leakage

With LO leakage correction active,

0 dB attenuation, scales decibel for

decibel with attenuation, measured

in 1 MHz bandwidth, resolution

bandwidth, and video bandwidth =

100 kHz, rms detector, 100 trace

average

Carrier Offset from

Local Oscillator (LO)

−84

dBFS

75 MHz < f ≤ 600 MHz

−82

−80

−71

dBFS

600 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Carrier on LO

Error Vector Magnitude

(Third Generation

EVM

Partnership Project

(3GPP) Test Signals)

75 MHz LO²

1900 MHz LO

3800 MHz LO

0.5

0.7

1.1

50

%

Ω

300 kHz RF PLL loop bandwidth

50 kHz RF PLL loop bandwidth

300 kHz RF PLL loop bandwidth

Differential (see Figure 265)

5900 MHz LO

Output Impedance

OBSERVATION RECEIVER

Center Frequency

Gain Range

Z_OUT

ORx

75

6000

MHz

dB

30

Third-order input intermodulation

intercept point (IIP3) improves decibel

for decibel for the first 18 dB of gain

attenuation, QEC performance

optimized for 0 dB to 6 dB of

attenuation only

Analog Gain Step

0.5

1

dB

For attenuator steps from 0 dB to

6 dB

450 MHz bandwidth, compensated

by programmable FIR filter

Any 20 MHz bandwidth span,

compensated by programmable FIR

filter

Peak-to-Peak Gain

Deviation

Gain Slope

0.1

Deviation from Linear

Phase

1

Degrees 450 MHz RF bandwidth

Observation Receiver

Bandwidth

450

MHz

Observation Receiver

Alias Band Rejection

60

dB

Due to digital filters

Maximum Useable Input

Level

P_HIGH

0 dB attenuation, increases decibel

for decibel with attenuation,

continuous wave corresponds to

−1 dBFS at ADC

−11

−9.5

−8

−58.5

−57.5

dBm

dBFS

75 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

450 MHz integration bandwidth

491.52 MHz integration bandwidth

Integrated Noise

Rev. 0 | Page 6 of 95

Data Sheet

ADRV9008-2

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Second-Order Input

Intermodulation

Intercept Point

IIP2

62

dBm

Maximum observation receiver gain,

(P_HIGH– 14) dB per tone (see the

Terminology section), 75 MHz < f ≤

600 MHz

62

dBm

Maximum observation receiver gain,

(P_HIGH– 8) dB per tone (see the

Terminology section), 600 MHz < f ≤

3000 MHz

Third-Order Input

Intermodulation

Intercept Point

IIP3

Narrow Band

4

dBm

75 MHz < f ≤ 300 MHz, (P_HIGH− 14)

dB per tone

300 MHz < f ≤ 600 MHz, (P_HIGH− 14)

dB per tone

11

IM3 product < 130 MHz at

baseband, (P_HIGH− 8) dB per tone

12

11

7

6

dBm

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Wide Band

Third-Order

Intermodulation

Product

IM3

IM3 product < 130 MHz at

baseband, two tones, each at (P_HIGH

− 12) dB

−70

−67

−62

−80

dBc

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

IM5 product < 50 MHz at baseband,

two tones, each at (P_HIGH− 12) dB,

600 MHz < f ≤ 6000 MHz

Fifth-Order

Intermodulation

Product (1800 MHz)

IM5

Seventh-Order

Intermodulation

Product (1800 MHz)

Spurious-Free Dynamic

Range

IM7

−80

70

dBc

dB

IM7 product < 50 MHz at baseband,

two tones, each at (P_HIGH− 12) dB,

600 MHz < f ≤ 6000 MHz

Non IMx related spurs, does not

include HDx, (P_HIGH− 9) dB input

signal, 600 MHz < f ≤ 6000 MHz

SFDR

Harmonic Distortion

(P_HIGH− 11) dB input signal

Second-Order Harmonic

Distortion Product

HD2

HD3

−80

dBc

(P_HIGH– 11) dB input signal, 75 MHz <

f ≤ 600 MHz

(P_HIGH– 9) dB input signal, 600 MHz <

f ≤ 6000 MHz

In band HD falls within 100 MHz

Out of band HD falls within

225 MHz

−80

−70

−60

dBc

Third-Order Harmonic

Distortion Product

In band HD falls within 100 MHz

Out of band HD falls within 225

MHz

Image Rejection

QEC active

Within Large Signal

Bandwidth

Outside Large Signal

Bandwidth

65

55

dB

Rev. 0 | Page 7 of 95

ADRV9008-2

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Input Impedance

Isolation

Transmitter 1 (Tx1) to

Observation

100

Ω

Differential (see Figure 266)

75 MHz < f ≤ 600 MHz

100

dB

Receiver 1 (ORx1)

and Transmitter 2

(Tx2) to Observation

Receiver 2 (ORx2)

65

55

105

dB

600 MHz < f ≤ 5300 MHz

5300 MHz < f ≤ 6000 MHz

75 MHz < f ≤ 600 MHz

Tx1 to ORx 2 and Tx2 to

ORx 1

65

55

dB

600 MHz < f ≤ 5300 MHz

5300 MHz < f ≤ 6000 MHz

LO SYNTHESIZER

LO Frequency Step

2.3

Hz

1.5 GHz to 2.8 GHz, 76.8 MHz phase

frequency detector (PFD) frequency

LO Spur

Integrated Phase Noise

75 MHz LO

−85

dBc

Excludes integer boundary spurs

2 kHz to 18 MHz

Narrow PLL loop bandwidth

(50 kHz)

Narrow PLL loop bandwidth

(50 kHz)

0.014

0.2

°rms

1900 MHz LO

3800 MHz LO

5900 MHz LO

Spot Phase Noise

75 MHz LO

0.36

0.54

°rms

Wide PLL loop bandwidth (300 kHz)

Narrow PLL loop bandwidth

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

1900 MHz LO

100 kHz Offset

200 kHz Offset

400 kHz Offset

600 kHz Offset

800 kHz Offset

1.2 MHz Offset

1.8 MHz Offset

6 MHz Offset

10 MHz Offset

3800 MHz LO

100 kHz Offset

1.2 MHz Offset

10 MHz Offset

5900 MHz LO

100 kHz Offset

1.2 MHz Offset

10 MHz Offset

−126.5

−132.8

−150.1

−150.7

dBc/Hz

−100

−115

−120

−129

−132

−135

−140

−150

−153

dBc/Hz

Wide PLL loop bandwidth

−104

−125

−145

dBc/Hz

−99

−119.7

−135.4

dBc/Hz

LO PHASE

SYNCHRONIZATION

Phase Deviation

1.6

ps/°C

Change in LO delay per temperature

change

Rev. 0 | Page 8 of 95

Data Sheet

ADRV9008-2

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

EXTERNAL LO INPUT

Input Frequency

f_EXTLO

300

0

8000

12

MHz

Input frequency must be 2× the

desired LO frequency

50 Ω matching at the source

f_EXTLO≤ 2 GHz, add 0.5 dBm/GHz

above 2 GHz

f_EXTLO= 8 GHz

Input Signal Power

dBm

3

6

dBm

External LO Input Signal

Differential

To ensure adequate QEC

Phase Error

Amplitude Error

Duty Cycle Error

3.6

1

2

ps

dB

%

Even-Order Harmonics

CLOCK SYNTHESIZER

Integrated Phase Noise

1966.08 MHz LO

−50

dBc

1 kHz to 100 MHz

PLL optimized for close in phase

noise

0.4

°rms

Spot Phase Noise

1966.08 MHz LO

100 kHz Offset

1 MHz Offset

−109

−129

−149

dBc/Hz

10 MHz Offset

REFERENCE CLOCK

(REF_CLK_IN )

Frequency Range

Signal Level

10

0.3

1000

2.0

MHz

V p-p

AC-coupled, common-mode voltage

(V_CM) = 618 mV, for best spurious

performance, use <1 V p-p input

clock

AUXILIARY CONVERTERS

ADC

Resolution

12

Bits

Input Voltage

Minimum

Maximum

0.05

VDDA_

V

3P3 − 0.05

DAC

Resolution

Output Voltage

Minimum

Maximum

10

Bits

Includes four offset levels

0.7

VDDA_

V

1 V V_REF

2.5 V V_REF

3P3 − 0.3

Output Drive Capability

10

mA

DIGITAL SPECIFICATIONS

(CMOS)—SDIO, SDO,

SCLK, CS GPIO_x,

TXx_ENABLE,

ORXx_ENABLE

Logic Inputs

Input Voltage

High Level

VDD_

INTERFACE

× 0.8

0

VDD_INTERFACE

V

Low Level

VDD_

INTERFACE × 0.2

Input Current

Rev. 0 | Page 9 of 95

ADRV9008-2

Data Sheet

Parameter

High Level

Symbol

Min

−10

Typ

Max

+10

Unit

μA

Test Conditions/Comments

Low Level

Logic Outputs

Output Voltage

High Level

VDD_

V

INTERFACE

× 0.8

Low Level

VDD_

V

INTERFACE × 0.2

Drive Capability

3

mA

DIGITAL SPECFICATIONS

(CMOS)—GPIO_3p3_x

Logic Inputs

Input Voltage

High Level

VDDA_3P3

× 0.8

0

VDDA_

3P3

VDDA_

V

Low Level

3P3 × 0.2

Input Current

High Level

Low Level

−10

+10

μA

Logic Outputs

Output Voltage

High Level

VDDA_

V

3P3 × 0.8

Low Level

VDDA_

V

3P3 × 0.2

Drive Capability

4

mA

DIGITAL SPECIFICATIONS

(LVDS)

Logic Inputs

(SYSREF_IN ,

SYNCINx )

Input Voltage Range

Input Differential

Voltage Threshold

Receiver Differential

Input Impedance

825

−100

1675

+100

mV

Each differential input in the pair

Internal termination enabled

100

Ω

Logic Outputs

(SYNCOUTx )

Output Voltage

High

Low

Output Differential

Voltage

1375

mV

1025

225

Programmable in 75 mV steps

Output Offset Voltage

SPI TIMING

1200

mV

See the UG-1295 for more

information.

SCLK Period

t_CP

t_MP

t_SC

20

10

3

ns

SCLK Pulse Width

CS Setup to First SCLK

Rising Edge

Last SCLK Falling Edge to t_HC

CS Hold

0

2

ns

SDIO Data Input Setup to t_S

SCLK

Rev. 0 | Page 10 of 95

Data Sheet

ADRV9008-2

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SDIO Data Input Hold to

SCLK

t_H

0

ns

SCLK Rising Edge to

Output Data Delay

(3-Wire or 4-Wire

Mode)

Bus Turnaround Time,

Read After Bits per

Pixel (BPP) Drives Last

Address Bit

t_CO

3

8

ns

t_HZM

t_H

0

t_CO

Bus Turnaround Time,

Read After ADRV9008-2

Drives Last Data Bit

t_HZS

t_CO

JESD204B DATA OUTPUT

TIMING

AC-coupled

Unit Interval

UI

81.38

3125

320

12,288

ps

Mbps

Data Rate per Channel

Nonreturn to Zero

(NRZ)

Rise Time

Fall Time

Output Common-Mode

Voltage

t_R

t_F

V_CM

24

0

39.5

39.4

ps

V

20% to 80% in 100 Ω load

AC-coupled

1.8

Differential Output

Voltage

V_DIFF

360

600

770

mV

Short-Circuit Current

Differential Termination

Impedance

I_DSHORT

−100

80

+100

120

mA

Ω

94.2

Total Jitter

Uncorrelated Bounded

High Probability Jitter

Duty Cycle Distortion

SYSREF_IN Setup Time

to REF_CLK_IN

15.13

0.56

ps

Bit error rate (BER) = 10⁻¹⁵

UBHPJ

DCD

0.369

ps

ns

2.5

See Figure 2

SYSREF_IN Hold Time

to REF_CLK_IN

−1.5

ns

See Figure 2

Latency

t_{LAT_FRM}

REF_CLK_IN = 245.76 MHz

116.5

Clock

cycles

Observation receiver bandwidth =

450 MHz, IQ rate = 491.52 MHz, lane

rate = 9830.4 MHz, number of

converters (M) = 4, number of lanes

(L) = 2, converter resolution (N) = 16,

number of samples per converter

(S) = 1

237.02

89.4

ns

Clock

cycles

Observation receiver bandwidth =

200 MHz, IQ rate = 245.76 MHz, lane

rate = 9830.4 MHz, M = 2, L = 2,

N = 16, S = 1

364.18

ns

JESD204B DATA INPUT

TIMING

AC-coupled

Unit Interval

Data Rate per Channel

(NRZ)

UI

81.38

3125

320

12288

ps

Mbps

Differential Voltage

V_TTSource Impedance

Differential Impedance

V_DIFF

Z_TT

Z_RDIFF

125

80

750

30

120

mV

Ω

8.9

105.1

Rev. 0 | Page 11 of 95

ADRV9008-2

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Termination Voltage

AC-Coupled

Latency

V_TT

1.267

1.33

V

t_{LAT_DEFRM}

74.45

Clock

cycles

Device clock = 245.76 MHz,

transmitter bandwidth = 200 MHz,

IQ rate = 491.52 MHz, lane rate =

9830.4 MHz, M = 2, L = 2, N = 16, S = 1

153.5

ns

¹VDDA1P3 refers to all analog 1.3 V supplies, including: VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_RF_VCO_LDO,

VDDA1P3_RF_LO, VDDA1P3_DES, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.

²Test equipment phase noise performance limited.

Rev. 0 | Page 12 of 95

Data Sheet

ADRV9008-2

CURRENT AND POWER CONSUMPTION SPECIFICATIONS

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY CHARACTERISTICS

VDDA1P3¹Analog Supply

VDDD1P3_DIG Supply

VDDA1P8_TX Supply

VDDA1P8_BB Supply

VDD_INTERFACE Supply

1.267

1.71

1.3

1.8

1.33

1.89

2.625

V

CMOS and LVDS supply, 1.8 V to 2.5 V

nominal range

VDDA_3P3 Supply

3.135

3.3

3.465

V

POSITIVE SUPPLY CURRENT

LO at 2600 MHz

450 MHz Transmitter Bandwidth,

Observation Receiver Disabled

Two transmitters enabled

VDDA1P3¹Analog Supply

VDDD1P3_DIG Supply

VDDA1P8_TX Supply

1978

611

455

mA

Transmitter QEC active

Transmitter RF attenuation = 0 dB, full

scale continuous wave

135

mA

Transmitter RF attenuation = 15 dB, full

scale continuous wave

VDD_INTERFACE Supply

VDDA1P8_BB Supply

VDDA_3P3 Supply

8

68

3

mA

VDD_INTERFACE = 2.5 V

No Auxiliary DAC x or AUXADC_x

enabled, if enabled, AUXADC_x adds

2.7 mA and each Auxiliary DAC x adds

1.5 mA

Total Power Dissipation

4.34

3.76

W

Typical supply voltages, 0 dB

transmitter attenuation, transmitter

QEC active

Typical supply voltages, 15 dB

transmitter attenuation, transmitter

QEC active

450 MHz Transmitter Bandwidth,

Observation Receiver Enabled

Two transmitters enabled

VDDA1P3¹Analog Supply

VDDD1P3_DIG Supply

2059

1501

mA

Transmitter QEC tracking active,

observation receiver QEC enabled

VDDA1P8_TX Supply

455

135

mA

Transmitter RF attenuation = 0 dB, full

scale continuous wave

Transmitter RF attenuation = 15 dB, full

scale continuous wave

VDD_INTERFACE Supply

VDDA1P8_BB Supply

VDDA_3P3 Power Supply

8

63

3

mA

VDD_INTERFACE = 2.5 V

No Auxiliary DAC x or AUXADC_x

enabled, if enabled, AUXADC_x adds

2.7 mA and each Auxiliary DAC x adds

1.5 mA

Total Power Dissipation

5.59

5.01

W

Typical supply voltages, 0 dB

transmitter attenuation, transmitter

QEC active

Typical supply voltages, 15 dB

transmitter attenuation, transmitter

QEC active

¹VDDA1P3 refers to all analog 1.3 V supplies, including: VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_RF_VCO_LDO,

VDDA1P3_RF_LO, VDDA1P3_DES, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.

Rev. 0 | Page 13 of 95

ADRV9008-2

Data Sheet

TIMING DIAGRAMS

AT DEVICE PINS

REF_CLK_IN± DELAY

IN REFERENCE TO SYSREF_IN±

AT DEVICE CORE

t’_H

t_H

t_S

t’_S

REF_CLK_IN±

t_H= –1.5ns

t_S= +2.5ns

CLK DELAY = 2ns

t’_H= +0.5ns

t’_S= +0.5ns

NOTES

1. t_HAND t_SARE THE HOLD AND SETUP TIMES FOR THE REF_CLK_IN± PINS. t’_HAND t’_SREFER TO THE

DELAYED HOLD AND SETUP TIMES AT THE DEVICE CORE IN REFERENCE TO THE SYSREF_N± SIGNALS

DUE TO AN INTERNAL BUFFER THAT THE SIGNAL PASSES THROUGH.

Figure 2. SYSREF_IN Setup and Hold Timing

t_H

t_S

REF_CLK_IN±

SYSREF_IN±

t_H= –1.5ns

t_S= +2.5ns

VALID SYSREF

INVALID SYSREF

Figure 3. SYSREF_IN Setup and Hold Timing Examples, Relative to Device Clock

SCLK

SDIO

t_DCH

CS

Tx

ATTENUATION

t_SCHt_ACH

Figure 4. Transmitter Attenuation Update via SPI 2 Port

Rev. 0 | Page 14 of 95

Data Sheet

ADRV9008-2

ABSOLUTE MAXIMUM RATINGS

exposed die package to provide the customer with the most

effective method of controlling the die temperature. The exposed

die allows cooling of the die directly. Figure 5 shows the profile

view of the device mounted to a user printed circuit board (PCB)

and a heat sink (typically the aluminum case) to keep the junction

(exposed die) below the maximum junction temperature shown

in Table 3. The device is designed for a lifetime of 10 years when

operating at the maximum junction temperature.

Table 3.

Parameter

Rating

VDDA1P3¹to VSSA

VDDD1P3_DIG to VSSD

VDD_INTERFACE to VSSA

VDDA_3P3 to VSSA

VDDA1P8_TX to VSSA

−0.3 V to +1.4 V

−0.3 V to +3.0 V

−0.3 V to +3.9 V

−0.3 V to +2.0 V

VDD_INTERFACE Logic Inputs and

Outputs to VSSD

−0.3 V to VDD_

INTERFACE + 0.3 V

THERMAL RESISTANCE

JESD204B Logic Outputs to VSSA

JESD204B Logic Inputs to VSSA

−0.3 V to VDDA1P3_SER

−0.3 V to VDDA1P3_DES

+ 0.3 V

Thermal performance is directly linked to PCB design and

operating environment. Careful attention to PCB thermal

design is required.

Input Current to any Pin Except

Supplies

10 mA

θ_JAis the natural convection junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure. θ_JCis

the junction to case thermal resistance.

Reflow Profile

260°C

Maximum Input Power into RF Port

Maximum Transmitter Voltage

Standing Wave Ratio (VSWR)

23 dBm (peak)

3:1

Thermal resistance data for the ADRV9008-2 mounted on both

a JEDEC 2S2P test board and a 10-layer Analog Devices, Inc.,

evaluation board is listed in Table 4. Do not exceed the absolute

maximum junction temperature rating in Table 3. Ten-layer

PCB entries refer to the 10-layer Analog Devices evaluation

board, which more accurately reflects the PCB used in customer

applications.

Maximum Junction Temperature

Storage Temperature Range

110°C

−65°C to +150°C

¹VDDA1P3 refers to all analog 1.3 V supplies, including: VDDA1P3_RF_SYNTH,

VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_RF_VCO_LDO,

VDDA1P3_RF_LO, VDDA1P3_DES, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH,

VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and

VDDA1P3_AUX_VCO_LDO.

Table 4. Thermal Resistance^{1, 2}

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Package Type

θ_JA

θ_{JC_TOP}

θ_JB

Ψ_JT

Ψ_JB

Unit

BC-196-13

21.1

0.04

4.9

0.3

4.9

°C/W

¹For the θ_JCtest, 100 µm thermal interface material (TIM) is used. TIM is

assumed to have 3.6 thermal conductivity watts/(meter × Kelvin).

²Using enhanced heat removal techniques such as PCB, heat sink, and airflow

improves the thermal resistance values.

REFLOW PROFILE

ESD CAUTION

The ADRV9008-2 reflow profile is in accordance with the

JEDEC JESD204B criteria for Pb-free devices. The maximum

reflow temperature is 260°C.

THERMAL MANAGEMENT

The ADRV9008-2 is a high power device that can dissipate over

3 W depending on the user application and configuration.

Because of the power dissipation, the ADRV9008-2 uses an

CUSTOMER CASE (HEAT SINK)

CUSTOMER THERMAL FILLER

SILICON (DIE)

IC PROFILE

PACKAGE SUBSTRATE

CUSTOMER PCB

Figure 5. Typical Thermal Management Solution

Rev. 0 | Page 15 of 95

ADRV9008-2

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

B

C

D

E

F

VSSA

ORX2_IN+

ORX2_IN–

VSSA

ORX1_IN+

ORX1_IN–

VSSA

VDDA1P3_

RX_RF

VSSA

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

VSSA

VDDA_3P3

VSSA

VDDA1P3_

RF_VCO_LDO RF_VCO_LDO

VDDA1P3_

AUX_VCO_

LDO

GPIO_3p3_0 GPIO_3p3_3

GPIO_3p3_1 GPIO_3p3_4

VDDA1P3_

RX_TX

VDDA1P1_

RF_VCO

VDDA1P3_

RF_LO

GPIO_3p3_9

RBIAS

VSSA

VDDA1P1_

AUX_VCO

GPIO_3p3_8 GPIO_3p3_10

GPIO_3p3_2 GPIO_3p3_5 GPIO_3p3_6 VDDA1P8_BB VDDA1P3_BB

REF_CLK_IN+ REF_CLK_IN–

AUX_

SYNTH_OUT

AUXADC_3 VDDA1P8_TX GPIO_3p3_7 GPIO_3p3_11

VSSA

AUXADC_0

VSSA

AUXADC_1

VSSA

AUXADC_2

VSSA

VDDA1P3_

CLOCK_

SYNTH

VDDA1P3_

RF_SYNTH

VDDA1P3_

AUX_SYNTH

G

H

J

VSSA

RF_SYNTH_

VTUNE

TX2_OUT–

TX2_OUT+

VSSA

GPIO_2

GPIO_3

VSSD

VSSA

SDIO

SCLK

VSSA

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

SERDIN1+

SERDIN3–

GPIO_11

GPIO_10

GPIO_9

GPIO_8

TX1_OUT+

TX1_OUT–

VSSA

GPIO_18

RESET

GP_

INTERRUPT

TEST

GPIO_1

GPIO_0

SDO

K

L

SYSREF_IN+ SYSREF_IN–

GPIO_5

GPIO_6

GPIO_4

GPIO_7

CS

VSSA

SYNCIN1–

SYNCIN0–

SYNCIN1+

SYNCIN0+

VDDD1P3_

DIG

VDDD1P3_

DIG

VSSD

SYNCOUT1– SYNCOUT1+

SYNCOUT0– SYNCOUT0+

VDDA1P1_

CLOCK_VCO

M

N

P

ORX1_

ENABLE

TX1_

ENABLE

ORX2_

ENABLE

TX2_

ENABLE

VSSA

GPIO_17

SERDIN1–

VSSA

VDD_

INTERFACE

VDDA1P3_

CLOCK_

VCO_ LDO

SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+

VSSA

VDDA1P3_

SER

VDDA1P3_

DES

SERDIN0–

SERDIN3+

SERDIN0+

SERDIN2–

VSSA

AUX_SYNTH_

VTUNE

VSSA

SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+

VDDA1P3_

SER

VDDA1P3_

DES

SERDIN2+

ADRV9008-2

Figure 6. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

Analog Supply Voltage (V_SS).

A1, A4 to A11, A14, B2 to B6, B9 Input

to B14, C4, C9, C11, D3 to D9,

D11, D12, E6, E9, F1, F2, F5 to

F10, F12 to F14, G1 to G4, G6,

G10 to G14, H2 to H10, H13,

J2, J13, K1, K2, K13, K14, L1,

L2, M2, M9, N2, N7, N14, P2,

P3, P10

VSSA

A2

Input

ORX2_IN+

Differential Input for Observation Receiver 2. When this pin is

unused, connect to GND.

Rev. 0 | Page 16 of 95

Data Sheet

ADRV9008-2

Pin No.

Type

Mnemonic

Description

A3

Input

ORX2_IN−

Differential Input for Observation Receiver 2. When this pin is

unused, connect to GND.

A12

A13

Input

ORX1_IN+

ORX1_IN−

Differential Input for Observation Receiver 1. When this pin is

unused, connect to GND.

Differential Input for Observation Receiver 1. When this pin is

unused, connect to GND.

B1

B7

Input

VDDA1P3_RX_RF

RF_EXT_LO_I/O−

Observation Receiver Supply.

Differential External LO Input/Output. If this pin is used for the

external LO, the input frequency must be 2× the desired carrier

frequency. When this pin is unused, do not connect.

B8

C1

Input

RF_EXT_LO_I/O+

GPIO_3p3_0

Differential External LO Input/Output. If this pin is used for the

external LO, the input frequency must be 2× the desired carrier

frequency. When this pin is unused, do not connect.

General-Purpose Inputs and Outputs (GPIO) Pin Referenced to

3.3 V Supply. The alternative function is Auxiliary DAC 4.

Because this pin contains an input stage, control the voltage

on the pin. When unused, this pin can be tied to ground

through a resistor to safeguard against misconfiguration, or this

pin can be left floating, programmed as an output, and driven low.

Input/

output

C2

Input/

output

GPIO_3p3_3

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. Because this pin contains an input stage, control the

voltage on the pin. When unused, this pin can be tied to

ground through a resistor to safeguard against misconfiguration,

or this pin can be left floating, programmed as an output, and

driven low.

C3

Input

VDDA1P3_RX_TX

1.3 V Supply for Transmitter/Observation Receiver Baseband

Circuits. This pin can power the transimpedance

amplifier/transmitter (TIA/TX), transconductance/baseband

(GM/BB) filter/auxiliary DACs circuits.

RF VCO LDO Supply Inputs. Connect Pin C5 to Pin C6. Use a

separate trace on the PCB back to a common supply point.

C5, C6

VDDA1P3_RF_VCO_LDO

C7

C8

Input

VDDA1P1_RF_VCO

VDDA1P3_RF_LO

1.1 V VCO Supply. Decouple this pin with a 1 µF capacitor.

1.3 V LO Generator for RF Synthesizer. This pin is sensitive to

supply noise.

C10

C12

Input

VDDA1P3_AUX_VCO_LDO

VDDA_3P3

1.3 V Supply.

General-Purpose Output Pull-Up Voltage and Auxiliary DAC

Supply Voltage.

C13

Input/

output

GPIO_3p3_9

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. The alternative function is Auxiliary DAC 9. Because this

pin contains an input stage, control the voltage on the pin.

When unused, this pin can be tied to ground through a resistor

to safeguard against misconfiguration, or this pin can be left

floating, programmed as an output, and driven low.

C14

D1

Input/

output

RBIAS

Bias Resistor. Tie this pin to ground using a 14.3 kΩ resistor. This

pin generates an internal current based on an external 1%

resistor.

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. The alternative function is Auxiliary DAC 5. Because this

pin contains an input stage, control the voltage on the pin.

When unused, this pin can be tied to ground through a resistor

to safeguard against misconfiguration, or this pin can be left

floating, programmed as an output, and driven low.

Input/

output

GPIO_3p3_1

D2

Input/

output

GPIO_3p3_4

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. The alternative function is Auxiliary DAC 6. Because this

pin contains an input stage, control the voltage on the pin.

When unused, this pin can be tied to ground through a resistor

to safeguard against misconfiguration, or this pin can be left

floating, programmed as an output, and driven low.

D10

Input

VDDA1P1_AUX_VCO

1.1 V VCO Supply. Decouple this pin with a 1 µF capacitor.

Rev. 0 | Page 17 of 95

ADRV9008-2

Data Sheet

Pin No.

Type

Mnemonic

Description

D13

Input/

output

GPIO_3p3_8

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. The alternative function is Auxiliary DAC 1. Because this

pin contains an input stage, control the voltage on the pin.

When unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or this pin can be left floating,

programmed as an output, and driven low.

D14

E1

Input/

output

GPIO_3p3_10

GPIO_3p3_2

GPIO_3p3_5

GPIO_3p3_6

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. The alternative function is Auxiliary DAC 0. Because this

pin contains an input stage, control the voltage on the pin.

When unused, this pin can be tied to ground through a resistor

to safeguard against misconfiguration, or this pin can be left

floating, programmed as an output, and driven low.

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. Because this pin contains an input stage, control the

voltage on the pin. When unused, this pin can be tied to

ground through a resistor to safeguard against misconfiguration,

or this pin can be left floating, programmed as an output, and

driven low.

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. The alternative function is Auxiliary DAC 7. Because this

pin contains an input stage, control the voltage on the pin.

When unused, this pin can be tied to ground through a resistor

to safeguard against misconfiguration, or this pin can be left

floating, programmed as an output, and driven low.

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. The alternative function is Auxiliary DAC 8. Because this

pin contains an input stage, control the voltage on the pin.

When unused, this pin can be tied to ground through a resistor

to safeguard against misconfiguration, or this pin can be left

floating, programmed as outputs, and driven low.

Input/

output

E2

Input/

output

E3

Input/

output

E4

E5

E7

E8

Input

VDDA1P8_BB

VDDA1P3_BB

REF_CLK_IN+

REF_CLK_IN−

1.8 V Supply for the ADC and DAC.

1.3 V Supply for the ADC, DAC, and auxiliary ADC.

Device Clock Differential Input.

Device Clock Differential Input Negative.

Auxiliary PLL Output. When this pin is unused, do not connect.

E10

Output AUX_SYNTH_OUT

E11, F3, F4, F11

Input

AUXADC_0 through

AUXADC_3

Auxiliary ADC Inputs. When these pins are unused, connect

these pins to GND with a pull-down resistor or connect these

pins directly to GND.

E12

E13

Input

Input/

output

VDDA1P8_TX

GPIO_3p3_7

1.8 V Supply for Transmitter.

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. The alternative function is Auxiliary DAC 2. Because this

pin contains an input stage, control the voltage on the pin.

When unused, this pin can be tied to ground through a resistor

to safeguard against misconfiguration, or this pin can be left

floating, programmed as an output, and driven low.

E14

Input/

output

GPIO_3p3_11

General-Purpose Inputs and Outputs Pin Referenced to 3.3 V

Supply. The alternative function is Auxiliary DAC 3. Because this

pin contains an input stage, control the voltage on the pin.

When unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or this pin can be left floating,

programmed as an output, and driven low.

G5

G7

Input

VDDA1P3_CLOCK_SYNTH

VDDA1P3_RF_SYNTH

VDDA1P3_AUX_SYNTH

1.3 V Supply Input for Clock Synthesizer. Use a separate trace

on the PCB back to a common supply point.

1.3 V RF Synthesizer Supply Input. This pin is sensitive to

aggressors.

1.3 V Auxiliary Synthesizer Supply Input.

RF Synthesizer PLL Tuning Voltage (V_TUNE) Output.

G8

G9

Output RF_SYNTH_VTUNE

Rev. 0 | Page 18 of 95

Data Sheet

ADRV9008-2

Pin No.

Type

Mnemonic

Description

H1

Output TX2_OUT−

Transmitter 2 Negative Output. When unused, do not connect

this pin.

H11

H12

Input/

output

GPIO_12

GPIO_11

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin

can be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed as

an output, and driven low.

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin

can be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed as

an output, and driven low.

Input/

output

H14

J1

Output TX1_OUT+

Output TX2_OUT+

Transmitter 1 Positive Output. When unused, do not connect

this pin.

Transmitter 2 Positive Output. When unused, do not connect

this pin.

J3

Input/

output

GPIO_18

Digital GPIO, 1.8 V to 2.5 V. The joint test action group (JTAG)

function is test clock (TCLK). Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin

can be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed as

an output, and driven low.

J4

J5

Input

RESET

Active Low Chip Reset.

Output GP_INTERRUPT

General-Purpose Digital Interrupt Output Signal. When unused,

do not connect this pin.

J6

J7

Input

TEST

Pin Used for JTAG Boundary Scan. When unused, connect this

pin to GND.

Input/

output

GPIO_2

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0.

Because this pin contains an input stage, control the voltage

on the pin. When unused, this pin can be tied to ground

through a resistor to safeguard against misconfiguration, or the

pin can be left floating, programmed as an output, and driven

low.

J8

J9

Input/

output

GPIO_1

SDIO

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0.

Because this pin contains an input stage, control the voltage

on the pin. When unused, this pin can be tied to ground through

a resistor to safeguard against misconfiguration, or the pin can be

left floating, programmed as an output, and driven low.

Input/

output

Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire

Mode.

J10

J11

Output SDO

Serial Data Output. In SPI 3-wire mode, do not connect this pin.

Input/

GPIO_13

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin can

be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed as

an output, and driven low.

output

J12

J14

Input/

output

GPIO_10

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin

can be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed as

an output, and driven low.

Output TX1_OUT−

Transmitter 1 Negative Output. When unused, do not connect

this pin.

K3

K4

K5

Input

Input/

SYSREF_IN+

SYSREF_IN−

GPIO_5

LVDS Positive Input.

LVDS Negative Input.

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test data output

(TDO). Because this pin contains an input stage, control the

voltage on the pin. When unused, this pin can be tied to ground

through a resistor to safeguard against misconfiguration, or the

pin can be left floating, programmed as an output, and driven low.

output

Rev. 0 | Page 19 of 95

ADRV9008-2

Data Sheet

Pin No.

Type

Mnemonic

Description

K6

Input/

output

GPIO_4

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test rest (TRST).

Because this pin contains an input stage, control the voltage on

the pin. When unused, this pin can be tied to ground through a

resistor to safeguard against misconfiguration, or the pin can be

left floating, programmed as an output, and driven low.

K7

K8

Input/

output

GPIO_3

GPIO_0

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1.

Because this pin contains an input stage, control the voltage on

the pin. When unused, this pin can be tied to ground through a

resistor to safeguard against misconfiguration, or the pin can be

left floating, programmed as an output, and driven low.

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1.

Because this pin contains an input stage, control the voltage

on the pin. When unused, this pin can be tied to ground through

a resistor to safeguard against misconfiguration, or the pin can be

left floating, programmed as an output, and driven low.

Input/

output

K9

K10

K11

Input

SCLK

CS

Serial Data Bus Clock.

Serial Data Bus Chip Select, Active Low.

Input/

output

GPIO_14

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin can

be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed as

an output, and driven low.

K12

Input/

output

GPIO_9

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin

can be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed

as an output, and driven low.

L3

L4

L5

Input

SYNCIN1−

SYNCIN1+

GPIO_6

LVDS Negative Input. When unused, connect this pin to GND

with a pull-down resistor or connect this pin directly to GND.

LVDS Positive Input. When unused, connect this pin to GND

with a pull-down resistor or connect this pin directly to GND.

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test data input

(TDI). Because this pin contains an input stage, control the

voltage on the pin. When unused, this pin can be tied to

ground through a resistor to safeguard against misconfiguration,

or the pin can be left floating, programmed as an output, and

driven low.

Input/

output

L6

Input/

output

GPIO_7

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test mode

select input (TMS). Because this pin contains an input stage,

control the voltage on the pin. When unused, this pin can be

tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed

as an output, and driven low.

L7, L10

L8, L9

Input

VSSD

VDDD1P3_DIG

Digital Supplies.

1.3 V Digital Core. Connect L8 and L9 with a separate trace to

common supply point.

L11

Input/

output

GPIO_15

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin can

be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed

as an output, and driven low.

L12

Input/

output

GPIO_8

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin

can be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed as

an output, and driven low.

L13

L14

M1

Output SYNCOUT1−

Output SYNCOUT1+

LVDS Negative Output. When unused, do not connect this pin.

LVDS Positive Output. When unused, do not connect this pin.

1.1 V VCO Supply. Decouple this pin with a 1 µF capacitor.

Input

VDDA1P1_CLOCK_VCO

Rev. 0 | Page 20 of 95

Data Sheet

ADRV9008-2

Pin No.

Type

Mnemonic

Description

M3

Input

SYNCIN0−

JESD204B Receiver Channel 0 Data Link LVDS Input. This pin

forms the sync signal associated with observation receiver channel

data on the JESD204B interface. When unused, connect this

pin to GND with a pull-down resistor or directly to GND.

M4

Input

SYNCIN0+

JESD204B Receiver Channel 0 Data Link LVDS Input. This pin

forms the sync signal associated with observation receiver channel

data on the JESD204B interface. When unused, connect this

pin to GND with a pull-down resistor or connect this pin

directly to GND.

M5

M6

M7

M8

M10

Input

ORX1_ENABLE

TX1_ENABLE

ORX2_ENABLE

TX2_ENABLE

GPIO_17

Observation Receiver 1 Enable Pin. When unused, connect this

pin to GND with a pull-down resistor or connect this pin

directly to GND.

Transmitter 1 Enable Pin. When unused, connect this pin to

GND with a pull-down resistor or connect this pin directly to

GND.

Observation Receiver 2 Enable Pin. When unused, connect this

pin to GND with a pull-down resistor or connect this pin

directly to GND.

Transmitter 2 Enable Pin. When unused, connect this pin to

GND with a pull-down resistor or connect this pin directly to

GND.

Input/

output

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin

can be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed as

an output, and driven low.

M11

Input/

output

GPIO_16

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, control the voltage on the pin. When unused, this pin

can be tied to ground through a resistor to safeguard against

misconfiguration, or the pin can be left floating, programmed as

outputs, and driven low.

M12

M13

Input

VDD_INTERFACE

Input/Output Interface Supply, 1.8 V to 2.5 V.

Output SYNCOUT0−

JESD204B Transmitter Channel Data Link LVDS Output. This pin

forms the sync signal associated with transmitter channel data on

the JESD204B interface. When unused, do not connect this pin.

M14

Output SYNCOUT0+

JESD204B Transmitter Channel Data Link LVDS Output. This pin

forms the sync signal associated with transmitter channel data on

the JESD204B interface. When unused, do not connect this pin.

N1

N3

Input

VDDA1P3_CLOCK_VCO_LDO 1.3 V Separate Trace to Common Supply Point.

Output SERDOUT3−

RF Current Mode Logic (CML) Differential Negative Output 3.

When unused, do not connect this pin.

N4

N5

N6

Output SERDOUT3+

Output SERDOUT2−

Output SERDOUT2+

RF CML Differential Positive Output 3. When unused, do not

connect this pin.

RF CML Differential Negative Output 2. When unused, do not

connect this pin.

RF CML Differential Positive Output 2. When unused, do not

connect this pin.

N8, P8

N9, P9

N10

Input

VDDA1P3_SER

VDDA1P3_DES

SERDIN1−

1.3 V Supply for JESD204B Serializer.

1.3 V Supply for JESD204B Deserializer.

RF CML Differential Negative Input 1. When unused, do not

connect this pin.

N11

N12

N13

P1

Input

SERDIN1+

SERDIN0−

SERDIN0+

RF CML Differential Positive Input 1. When unused, do not

connect this pin.

RF CML Differential Negative Input 0. When unused, do not

connect this pin.

RF CML Differential Positive Input 0. When unused, do not

connect this pin.

Auxiliary Synthesizer V_TUNEOutput.

Output AUX_SYNTH_VTUNE

Rev. 0 | Page 21 of 95

ADRV9008-2

Data Sheet

Pin No.

Type

Mnemonic

Description

P4

Output SERDOUT1−

Output SERDOUT1+

Output SERDOUT0−

Output SERDOUT0+

RF CML Differential Negative Output 1. When unused, do not

connect this pin.

RF CML Differential Positive Output 1. When unused, do not

connect this pin.

RF CML Differential Negative Output 0. When unused, do not

connect this pin.

RF CML Differential Positive Output 0. When unused, do not

connect this pin.

P5

P6

P7

P11

P12

P13

P14

Input

SERDIN3−

SERDIN3+

SERDIN2−

SERDIN2+

RF CML Differential Negative Input 3. When unused, do not

connect this pin.

RF CML Differential Positive Input 3. When unused, do not

connect this pin.

RF CML Differential Negative Input 2. When unused, do not

connect this pin.

RF CML Differential Positive Input 2. When unused, do not

connect this pin.

Rev. 0 | Page 22 of 95

Data Sheet

ADRV9008-2

TYPICAL PERFORMANCE CHARACTERISTICS

The temperature settings refer to the die temperature.

75 MHz TO 525 MHz BAND

15

14

13

12

11

10

9

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

+110°C ATTN = 20dB

+110°C ATTN = 15dB

+110°C ATTN = 10dB

+110°C ATTN = 5dB

+110°C ATTN = 0dB

+25°C ATTN = 20dB

+25°C ATTN = 15dB

+25°C ATTN = 10dB

+25°C ATTN = 5dB

+25°C ATTN = 0dB

–40°C ATTN = 20dB

–40°C ATTN = 15dB

–40°C ATTN = 10dB

–40°C ATTN = 5dB

–40°C ATTN = 0dB

8

7

6

5

4

3

2

1

0

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

75

125

175

225

275

325

375

425

475

525

–25

–20

–15

–10

–5

5

10

15

20

25

TRANSMITTER LO FREQUENCY (MHz)

300

BASEBAND OFFSET AND TRANSMITTER ATTENUATION

FREQUENCY (MHz)

Figure 7. Transmitter Continuous Wave (CW) Output Power vs. Transmitter LO

Frequency, Transmitter QEC and External LO Leakage Active, Transmitter

50 MHz/100 MHz Bandwidth Mode, IQ Rate = 122.88 MHz, Attenuation = 0 dB,

Not De-Embedded

Figure 9. Transmitter Image Rejection vs. Baseband Offset Frequency and

Transmitter Attenuation, QEC Trained with Three Tones Placed at 10 MHz,

48 MHz, and 100 MHz (Tracking On), Total Combined Power = −10 dBFS,

Correction Then Frozen (Tracking Turned Off), CW Tone Swept Across Large

Signal Bandwidth, LO = 300 MHz

0

–10

+110°C ATTN = 20dB

+110°C ATTN = 15dB

+110°C ATTN = 10dB

+110°C ATTN = 5dB

+110°C ATTN = 0dB

+25°C ATTN = 20dB

+25°C ATTN = 15dB

+25°C ATTN = 10dB

+25°C ATTN = 5dB

+25°C ATTN = 0dB

–40°C ATTN = 20dB

–40°C ATTN = 15dB

–40°C ATTN = 10dB

–40°C ATTN = 5dB

–40°C ATTN = 0dB

+110°C ATTN = 20dB

+110°C ATTN = 15dB

+110°C ATTN = 10dB

+110°C ATTN = 5dB

+110°C ATTN = 0dB

+25°C ATTN = 20dB

+25°C ATTN = 15dB

+25°C ATTN = 10dB

+25°C ATTN = 5dB

+25°C ATTN = 0dB

–40°C ATTN = 20dB

–40°C ATTN = 15dB

–40°C ATTN = 10dB

–40°C ATTN = 5dB

–40°C ATTN = 0dB

–10

–30

–20

–30

–40

–50

–60

–70

–80

–90

–100

–50

–70

–90

–110

–25

–20

–15

–10

–5

5

10

15

20

25

–25

–20

–15

–10

–5

5

10

15

20

25

75.2

525

BASEBAND OFFSET FREQUENCY AND

TRANSMITTER ATTENUATION (MHz)

BASEBAND OFFSET FREQUENCY AND

TRANSMITTER ATTENUATION (MHz)

Figure 8. Transmitter Image Rejection vs. Baseband Offset Frequency and

Transmitter Attenuation, QEC Trained with Three Tones Placed at 10 MHz,

48 MHz, and 100 MHz (Tracking On), Total Combined Power = −10 dBFS,

Correction Then Frozen (Tracking Turned Off), CW Tone Swept Across Large

Signal Bandwidth, LO = 75.2 MHz

Figure 10. Transmitter Image Rejection vs. Baseband Offset Frequency and

Transmitter Attenuation, QEC Trained with Three Tones Placed at 10 MHz,

48 MHz, and 100 MHz (Tracking On), Total Combined Power = −10 dBFS,

Correction Then Frozen (Tracking Turned Off), CW Tone Swept Across Large

Signal Bandwidth, LO = 525 MHz

Rev. 0 | Page 23 of 95

ADRV9008-2

Data Sheet

0.5

–140

–145

–150

–155

–160

–165

–170

525MHz = +110°C

Tx1 = +110°C

0.4

0.3

300MHz = +110°C

75MHz = +110°C

525MHz = +25°C

300MHz = +25°C

75MHz = +25°C

525MHz = –40°C

300MHz = –40°C

75MHz = –40°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–50 –40 –30 –20 –10

0

10

20

30

40

50

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

BASEBAND OFFSET FREQUENCY (MHz)

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 11. Transmitter Pass Band Flatness vs. Baseband Offset Frequency, Off

Chip Match Response De-Embedded, LO = 300 MHz, Calibrated at 25°C

Figure 14. Transmitter Noise vs. Transmitter Attenuator Setting, Offset = 50 MHz

–75

–77

–79

–81

–83

–85

–40

Tx1 +110°C (LOWER)

Tx1 +110°C (UPPER)

Tx1 +25°C (LOWER)

Tx1 +25°C (UPPER)

Tx1 –40°C (LOWER)

Tx1 –40°C (UPPER)

Tx2 +110°C (LOWER)

Tx2 +110°C (UPPER)

Tx2 +25°C (LOWER)

Tx2 +25°C (UPPER)

Tx2 –40°C (LOWER)

Tx2 –40°C (UPPER)

–45

–50

–55

–60

–65

–70

–75

–87

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–89

–91

–93

–95

0

2

4

6

8

10

12

14

16

18

20

75

125

175

225

275

325

375

425

475

525

TRANSMITTER ATTENUATOR SETTING (dB)

SIGNAL OFFSET = 0MHz

TRANSMITTER LO FREQUENCY (MHz)

Figure 15. Transmitter Adjacent Channel Leakage Ratio vs. Transmitter

Attenuator Setting, Signal Offset = 0 MHz, LO = 75 MHz, LTE = 20 MHz, Peak to

Average Ratio (PAR) = 12 dB, DAC Boost Normal, Upper Side and Lower Side,

Performance Limited by Spectrum Analyzer at Higher Attenuation Settings

Figure 12. Transmitter LO Leakage vs. Transmitter LO Frequency, Transmitter

Attenuation = 0 dB, Baseband Tone Frequency = 10 MHz, Tracked

–40

0

Tx1 +110°C (LOWER)

Tx1 +110°C (UPPER)

Tx1 +25°C (LOWER)

Tx1 +25°C (UPPER)

Tx1 –40°C (LOWER)

Tx1 –40°C (UPPER)

Tx2 +110°C (LOWER)

Tx2 +110°C (UPPER)

Tx2 +25°C (LOWER)

Tx2 +25°C (UPPER)

Tx2 –40°C (LOWER)

Tx2 –40°C (UPPER)

10

–45

–50

–55

–60

–65

–70

–75

Tx1 – Tx2

20

Tx2 – Tx1

30

40

50

60

70

80

90

100

110

120

0

2

4

6

8

10

12

14

16

18

20

0

100

200

300

400

500

600

TRANSMITTER ATTENUATOR SETTING (dB)

SIGNAL OFFSET = 0MHz

TRANSMITTER LO FREQUENCY (MHz)

Figure 16. Transmitter Adjacent Channel Leakage Ratio vs. Transmitter

Attenuator Setting, Signal Offset = 0 MHz, LO = 300 MHz, LTE = 20 MHz, PAR =

12 dB, DAC Boost Normal, Upper Side and Lower Side, Performance Limited by

Spectrum Analyzer at Higher Attenuation Settings

Figure 13. Transmitter to Transmitter Isolation vs. Transmitter LO Frequency,

Temperature = 25°C

Rev. 0 | Page 24 of 95

Data Sheet

ADRV9008-2

–40

–45

–50

–55

–60

–65

–70

–75

50

45

40

35

30

25

20

15

10

5

Tx1 +110°C (LOWER)

Tx1 +110°C (UPPER)

Tx1 +25°C (LOWER)

Tx1 +25°C (UPPER)

Tx1 –40°C (LOWER)

Tx1 –40°C (UPPER)

Tx2 +110°C (LOWER)

Tx2 +110°C (UPPER)

Tx2 +25°C (LOWER)

Tx2 +25°C (UPPER)

Tx2 –40°C (LOWER)

Tx2 –40°C (UPPER)

+110°C

+25°C

–40°C

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

SIGNAL OFFSET = 0MHz

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 17. Transmitter Adjacent Channel Leakage Ratio vs. Transmitter

Attenuator Setting, Signal Offset = 0 MHz, LO = 525 MHz, LTE = 20 MHz, PAR =

12 dB, DAC Boost Normal, Upper Side and Lower Side, Performance Limited by

Spectrum Analyzer at Higher Attenuation Settings

Figure 20. Transmitter OIP3 Right vs. Transmitter Attenuator Setting, LO =

525 MHz, Total RMS Power = −12 dBFS, 20 MHz/25 MHz Tones

50

45

40

35

30

25

20

45

+110°C

+25°C

–40°C

40

35

30

25

20

15

10

5

15

10

5

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

5

10

15

20

25

10

TRANSMITTER ATTENUATOR SETTING (dB)

BASEBAND TONE PAIR SWEPT ACROSS PASS BAND (MHz)

Figure 18. Transmitter OIP3 Right vs. Transmitter Attenuator Setting, LO = 75 MHz,

Total Root Mean Square (RMS) Power = −12 dBFS, 20 MHz/25 MHz Tones

Figure 21. Transmitter OIP3 Right vs. Baseband Tone Pair Swept Across Pass Band,

LO = 75 MHz, Total RMS Power = −12 dBFS, Transmitter Attenuation = 4 dB

50

45

40

35

30

25

20

45

+110°C

+25°C

–40°C

40

35

30

25

20

15

10

5

15

10

5

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

5

10

15

20

25

10

TRANSMITTER ATTENUATOR SETTING (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 19. Transmitter OIP3 Right vs. Transmitter Attenuator Setting, LO =

300 MHz, Total RMS Power = −12 dBFS, 20 MHz/25 MHz Tones

Figure 22. Transmitter OIP3 Right vs. Baseband Frequency Offset, LO =

300 MHz, Total RMS Power = −12 dBFS, Transmitter Attenuation = 4 dB

Rev. 0 | Page 25 of 95

ADRV9008-2

Data Sheet

50

45

40

35

30

25

20

0

–20

+110°C = (UPPER)

+110°C = (HD2)

+25°C = (UPPER)

+25°C = (HD2)

–40°C = (UPPER)

–40°C = (HD2)

–40

–60

–80

15

10

5

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–100

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

5

10

15

20

25

TRANSMITTER ATTENUATOR SETTING (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 23. Transmitter OIP3 Right vs. Baseband Frequency Offset, LO =

525 MHz, Total RMS Power = −12 dBFS, Transmitter Attenuation = 4 dB

Figure 26. Transmitter HD2 vs. Transmitter Attenuator Setting, Baseband

Frequency = 10 MHz, LO = 525 MHz, CW = −15 dBFS

0

+110°C = (UPPER)

+110°C = (HD2)

+25°C = (UPPER)

+25°C = (HD2)

–40°C = (UPPER)

–40°C = (HD2)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–20

–40

–60

–80

–100

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 24. Transmitter HD2 vs. Transmitter Attenuator Setting, Baseband

Frequency = 10 MHz, LO = 75 MHz, CW = −15 dBFS

Figure 27. Transmitter HD3 vs. Transmitter Attenuator Setting, LO = 75 MHz,

CW = −15 dBFS, Baseband Frequency = 10 MHz

0

+110°C = (UPPER)

+110°C = (HD2)

+25°C = (UPPER)

+25°C = (HD2)

–40°C = (UPPER)

–40°C = (HD2)

–10

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–20

–40

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–100

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 25. Transmitter HD2 vs. Transmitter Attenuator Setting, Baseband

Frequency = 10 MHz, LO = 300 MHz, CW = −15 dBFS

Figure 28. Transmitter HD3 vs. Transmitter Attenuator Setting, LO =

300 MHz, CW = −15 dBFS, Baseband Frequency = 10 MHz

Rev. 0 | Page 26 of 95

Data Sheet

ADRV9008-2

0

–10

0

–10

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 32. Transmitter HD3 Image Appears on Same Side as Desired Signal

vs. Transmitter Attenuator Setting, LO = 525 MHz, CW = −15 dBFS

Figure 29. Transmitter HD3 vs. Transmitter Attenuator Setting, LO =

525 MHz, CW = −15 dBFS, Baseband Frequency = 10 MHz

0

0.03

–10

Tx1 = +110°C

+110°C

+25°C

–40°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–20

–30

0.02

–40

0.01

0

–50

–60

–70

–80

–90

–0.01

–0.02

–100

–110

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 30. Transmitter HD3 Image Appears on Same Side as Desired Signal

vs. Transmitter Attenuator Setting, LO = 75 MHz, CW = −15 dBFS

Figure 33. Transmitter Attenuator Step Error vs. Transmitter Attenuator

Setting, LO = 75 MHz, Baseband Frequency = 10 MHz, Backoff = 15 dBFS

0

0.03

–10

Tx1 = +110°C

+110°C

+25°C

–40°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–20

–30

0.02

–40

0.01

0

–50

–60

–70

–80

–90

–0.01

–0.02

–100

–110

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 34. Transmitter Attenuator Step Error vs. Transmitter Attenuator

Setting, LO = 300 MHz, Baseband Frequency = 10 MHz, Backoff = 15 dBFS

Figure 31. Transmitter HD3 Image Appears on Same Side as Desired Signal

vs. Transmitter Attenuator Setting, LO = 300 MHz, CW = −15 dBFS

Rev. 0 | Page 27 of 95

ADRV9008-2

Data Sheet

0.03

–30

–32

–34

–36

–38

–40

–42

–44

–46

–48

–50

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.02

0.01

0

–0.01

–0.02

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

5

10

15

20

25

TRANSMITTER ATTENUATOR SETTING (dB)

TRANSMITTER ATTENUATION (dB)

Figure 35. Transmitter Attenuator Step Error vs. Transmitter Attenuator

Setting, LO = 525 MHz, Baseband Frequency = 10 MHz, Backoff = 15 dBFS

Figure 38. Transmitter EVM vs. Transmitter Attenuation, LTE = 20 MHz,

Signal Centered on DC, LO = 525 MHz

–30

0

–32

–34

–36

–38

–40

–42

–44

–46

–48

–50

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0

5

10

15

20

25

75

125

175

225

275

325

375

425

475

525

TRANSMITTER ATTENUATION (dB)

LO FREQUENCY (MHz)

Figure 36. Transmitter EVM vs. Transmitter Attenuation, LTE = 20 MHz, Signal

Centered on DC, LO = 75 MHz

Figure 39. Observation Receiver LO Leakage vs. LO Frequency, 75 MHz,

300 MHz, and 525 MHz, Attenuation = 0 dB

–30

25

20

15

–32

–34

–36

–38

–40

–42

–44

–46

–48

–50

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

10

5

0

5

10

15

20

25

0

1

2

3

4

5

6

7

8

9

10

TRANSMITTER ATTENUATION (dB)

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

Figure 37. Transmitter EVM vs. Transmitter Attenuation, LTE = 20 MHz,

Signal Centered on DC, LO = 300 MHz

Figure 40. Observation Receiver Noise Figure vs. Observation Receiver

Attenuator Setting, LO = 75 MHz, Total Nyquist Integration Bandwidth

Rev. 0 | Page 28 of 95

Data Sheet

ADRV9008-2

25

20

15

10

5

80

75

70

65

60

55

50

45

40

+110°C

+25°C

–40°C

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

0

1

2

3

4

5

6

7

8

9

10

305 310 315 320 325 330 335 340 345 350 355

306 311 316 321 326 331 336 341 346 351 356

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

f1 OFFSET FREQUENCY (MHz)

Figure 41. Observation Receiver Noise Figure vs. Observation Receiver

Attenuator Setting, LO = 300 MHz, Total Nyquist Integration Bandwidth

Figure 44. Observation Receiver IIP2, Sum and Difference Products vs. f1

Offset Frequency, Tones Separated by 1 MHz Swept Across Pass Band at

−25 dBm Each, LO = 300 MHz, Attenuation = 0 dB

25

20

15

80

75

70

65

60

+110°C

+25°C

–40°C

10

5

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

55

50

IIP2 DIFF +25°C

IIP2 DIFF –40°C

45

0

40

0

1

2

3

4

5

6

7

8

9

10

530 535 540 545 550 555 560 565 570 575 380

531 536 541 546 551 556 561 566 571 576 381

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

f1 OFFSET FREQUENCY (MHz)

Figure 42. Observation Receiver Noise Figure vs. Observation Receiver

Attenuator Setting, LO = 525 MHz, Total Nyquist Integration Bandwidth

Figure 45. Observation Receiver IIP2, Sum and Difference Products vs. f1

Offset Frequency, Tones Separated by 1 MHz Swept Across Pass Band at

−25 dBm Each, LO = 525 MHz, Attenuation = 0 dB

80

75

70

65

60

55

100

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

95

90

85

80

75

70

65

60

55

50

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

50

45

40

35

30

0

2

4

6

8

10

12

14

16

18

20

80

85

86

90

91

95

96

100

101

105

106

110

111

115

116

120

121

OBSERVATION RECEIVER ATTENUATION (dB)

81

f1 OFFSET FREQUENCY (MHz)

Figure 43. Observation Receiver IIP2, Sum and Difference Products vs. f1

Offset Frequency, Tones Separated by 1 MHz Swept Across Pass Band at

−25 dBm Each, LO = 75 MHz, Attenuation = 0 dB

Figure 46. Observation Receiver IIP2, Sum and Difference Products vs. Observation

Receiver Attenuation, LO = 75 MHz, Tone 1 = 95 MHz, Tone 2 = 96 MHz at

−25 dBm Plus Attenuation

Rev. 0 | Page 29 of 95

ADRV9008-2

Data Sheet

100

80

70

60

50

40

30

20

10

0

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

95

90

85

80

75

70

65

60

55

50

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

0

2

4

6

8

10

12

14

16

18

20

302 302 302 302 302 302 302 302 302 302 302

307 312 317 322 327 332 337 342 347 352 357

OBSERVATION RECEIVER ATTENUATION (dB)

INTERMODULATION FREQUENCY (MHz)

Figure 50. Observation Receiver IIP2, f1 − f2 vs. Intermodulation Frequency,

LO = 300 MHz, Tone 1 = 302 MHz, Tone 2 = Swept, −25 dBm Each,

Attenuation = 0 dB

Figure 47. Observation Receiver IIP2, Sum and Difference Products vs.

Observation Receiver Attenuation, LO = 300 MHz, Tone 1 = 320 MHz,

Tone 2 = 321 MHz at −25 dBm Plus Attenuation

80

70

60

50

95

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

90

85

80

75

70

65

60

55

50

40

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

30

20

10

0

527

532

0

2

4

6

8

10

12

14

16

18

20

527

542

527

547

527

552

527

557

527

562

527

567

527

572

527

577

527

582

OBSERVATION RECEIVER ATTENUATION (dB)

INTERMODULATION FREQUENCY

Figure 48. Observation Receiver IIP2, Sum and Difference Products vs. Observation

Receiver Attenuation, LO = 525 MHz, Tone 1 = 545 MHz, Tone 2 = 546 MHz at

−25 dBm Plus Attenuation

Figure 51. Observation Receiver IIP2, f1 − f2 vs. Intermodulation Frequency, LO =

525 MHz, Tone 1 = 527 MHz, Tone 2 = Swept, −25 dBm Each, Attenuation = 0 dB

80

70

60

50

40

90

IIP2 SUM +110°C

85

80

75

70

65

60

55

50

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

30

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

20

10

0

77

82

0

2

4

6

8

10

12

14

16

18

20

77

87

77

92

77

97

77

102

77

107

OBSERVATION RECEIVER ATTENUATION (dB)

INTERMODULATION FREQUENCY (MHz)

Figure 49. Observation Receiver IIP2, f1 − f2 vs. Intermodulation Frequency,

LO = 75 MHz, Tone 1 = 77 MHz, Tone 2 = Swept, −25 dBm Each,

Attenuation = 0 dB Change

Figure 52. Observation Receiver IIP2, f1 − f2 vs. Observation Receiver

Attenuation, LO = 75 MHz, Tone 1 = 77 MHz, Tone 2 = 97 MHz at

−25 dBm Plus Attenuation

Rev. 0 | Page 30 of 95

Data Sheet

ADRV9008-2

90

85

80

75

70

65

60

55

50

25

20

15

10

5

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

0

2

4

6

8

10

12

14

16

18

20

305 310 315 320 325 330 335 340 345 350 355

OBSERVATION RECEIVER ATTENUATION (dB)

306 311 316 321 326 331 336 341 346 351 356

f1 OFFSET FREQUENCY (MHz)

Figure 53. Observation Receiver IIP2, f1 − f2 vs. Observation Receiver

Attenuation, LO = 300 MHz, Tone 1 = 302 MHz, Tone 2 = 322 MHz at

−25 dBm Plus Attenuation

Figure 56. Observation Receiver IIP3, 2f1 − f2 vs. f1 Offset Frequency, LO =

300 MHz, Attenuation = 0 dB, Tones Separated by 1 MHz Swept Across Pass Band

at −25 dBm Each

90

85

80

75

70

25

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

20

15

10

5

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

65

60

55

50

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

Figure 54. Observation Receiver IIP2, f1 − f2 vs. Observation Receiver Attenuation,

LO = 525 MHz, Tone 1 = 527 MHz, Tone 2 = 547 MHz at −25 dBm Plus

Attenuation

Figure 57. Observation Receiver IIP3, 2f1 − f2 vs. Observation Receiver

Attenuation, LO = 75 MHz, Tone 1 = 100 MHz, Tone 2 = 101 MHz at −24 dBm

Plus Attenuation

10

25

9

8

7

6

5

4

3

2

1

0

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

20

15

10

5

0

2

4

6

8

10

80

81

85

86

90

91

95

96

100 105 110 115 120 125 130

101 106 111 116 121 126 131

ATTENUATION (dB)

INTERMODULATION FREQUENCY (MHz)

Figure 58. Observation Receiver IIP3, 2f1 − f2 vs. Attenuation, LO = 300 MHz,

Tone 1 = 345 MHz, Tone 2 = 346 MHz at − 24 dBm Plus Attenuation

Figure 55. Observation Receiver IIP3, 2f1 − f2 vs. Intermodulation Frequency, LO

= 75 MHz, Attenuation = 0 dB, Tones Separated by 1 MHz Swept Across Pass Band

at −25 dBm Each

Rev. 0 | Page 31 of 95

ADRV9008-2

Data Sheet

18

–70

–75

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

16

14

12

10

8

–80

–85

–90

–95

–100

–105

–110

–115

–120

+110°C = 10dB

+25°C = 10dB

–40°C = 10dB

+110°C = 0dB

+25°C = 0dB

–40°C = 0dB

6

4

2

0

–50 –40 –30 –20 –10

0

10

20

30

40

50

302 302 302 302 302 302 302 302 302 302 302

307 312 317 322 327 332 337 342 347 352 357

BASEBAND FREQUENCY OFFSET (MHz) AND ATTENUATION

SWEPT PASS BAND FREQUENCY (MHz)

Figure 62. Observation Receiver Image Rejection vs. Baseband Frequency

Offset and Attenuation, CW Signal Swept Across the Band,

LO = 300 MHz

Figure 59. Observation Receiver IIP3, 2f1 − f2 vs. Swept Pass Band Frequency,

LO = 300 MHz, Attenuation = 0 dB, Tone 1 = 302 MHz, Tone 2 = Swept Across

the Pass Band, Tones Separated by 1 MHz Swept Across Pass Band at

−19 dBm Each

20

22

+110°C

+25°C

–40°C

IIP3 = +110°C

20

18

16

14

12

10

8

IIP3 = +25°C

IIP3 = –40°C

18

16

14

12

10

8

6

4

0

1

2

3

4

5

6

7

8

9

10

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

Figure 63. Observation Receiver Gain vs. Observation Receiver Attenuation,

LO = 75 MHz

Figure 60. Observation Receiver IIP3, 2f1 − f2 vs. Observation Receiver

Attenuation, LO = 300 MHz, Tone 1 = 302 MHz, Tone 2 = 352 MHz at

−19 dBm Plus Attenuation

20

–70

–75

–80

–85

–90

–95

+110°C

+25°C

–40°C

18

16

14

12

10

8

–100

–105

–110

–115

–120

+110°C = 10dB

+25°C = 10dB

–40°C = 10dB

+110°C = 0dB

+25°C = 0dB

–40°C = 0dB

6

4

0

1

2

3

4

5

6

7

8

9

10

–50 –40 –30 –20 –10

0

10

20

30

40

50

OBSERVATION RECEIVER ATTENUATION (dB)

BASEBAND FREQUENCY OFFSET (MHz) AND ATTENUATION

Figure 64. Observation Receiver Gain vs. Observation Receiver Attenuation,

LO = 300 MHz

Figure 61. Observation Receiver Image Rejection vs. Baseband Frequency

Offset and Attenuation, CW Signal Swept Across the Band,

LO = 75 MHz

Rev. 0 | Page 32 of 95

Data Sheet

ADRV9008-2

0.5

0.4

+110°C

+25°C

–40°C

0.4

0.3

0.2

0.1

0.2

0

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–1.0

0

–0.1

–0.2

–0.3

–0.4

–0.5

I RIPPLE = +110°C

I RIPPLE = +25°C

I RIPPLE = –40°C

Q RIPPLE = +110°C

Q RIPPLE = +25°C

Q RIPPLE = –40°C

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATOR (dB)

BASEBAND OFFSET FREQUENCY (MHz)

Figure 65. Observation Receiver Gain Step Error vs. Observation Receiver

Attenuator, LO = 75 MHz

Figure 68. Normalized Observation Receiver Baseband Flatness vs. Baseband

Offset Frequency, LO = 75 MHz, Attenuation = 0 dB

0

0.5

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.4

–20

–40

0.3

0.2

0.1

–60

0

–0.1

–0.2

–0.3

–0.4

–0.5

–80

–100

–120

0

5

10

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATION (dB)

OBSERVATION RECEIVER ATTENUATOR (dB)

Figure 69. Observation Receiver DC Offset vs. Observation Receiver

Attenuation, LO = 75 MHz, Baseband Frequency = 50 MHz

Figure 66. Observation Receiver Gain Step Error vs. Observation Receiver

Attenuator, LO = 325 MHz

0

0.5

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.4

–20

–40

0.3

0.2

0.1

–60

0

–0.1

–0.2

–0.3

–0.4

–0.5

–80

–100

–120

0

5

10

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATION (dB)

OBSERVATION RECEIVER ATTENUATOR (dB)

Figure 70. Observation Receiver DC Offset vs. Observation Receiver

Attenuation, LO = 325 MHz, Baseband Frequency = 50 MHz

Figure 67. Observation Receiver Attenuator Gain Step Error vs. Observation

Receiver Attenuator, LO = 525 MHz

Rev. 0 | Page 33 of 95

ADRV9008-2

Data Sheet

0

–10

–30

HD2 RIGHT ATTN = 0 +110°C

HD3 RIGHT dBc = +110°C

HD3 RIGHT dBc = +25°C

HD3 RIGHT dBc = –40°C

HD3 LEFT dBc = = +110°C

HD3 LEFT dBc = +25°C

HD3 LEFT dBc = –40°C

HD2 RIGHT ATTN = 10 +110°C

HD2 LEFT ATTN = 0 +110°C

HD2 LEFT ATTN = 10 +110°C

HD2 RIGHT ATTN = 0 +25°C

HD2 RIGHT ATTN = 10 +25°C

HD2 LEFT ATTN = 0 +25°C

HD2 LEFT ATTN = 10 +25°C

HD2 RIGHT ATTN = 0 –40°C

HD2 RIGHT ATTN = 10 –40°C

HD2 LEFT ATTN = 0 –40°C

HD2 LEFT ATTN = 10 –40°C

–20

–40

–50

–70

–60

–90

–80

–110

–130

–150

–100

–120

–50

–30

–10

10

30

50

–50

–40

–30

–20

–10

10

20

30

40

50

300

FREQUENCY OFFSET FROM LO

OFFSET FREQUENCY (MHz)

Figure 74. Observation Receiver HD3 Left and Right vs. Frequency Offset from

LO, Tone Level = −22 dBm at Attenuation = 0 dB, LO = 300 MHz

Figure 71. Observation Receiver HD2 vs. Offset Frequency and Attenuation,

LO = 75 MHz, Tone Level = −21 dBm Plus Attenuation

–10

0

HD2 RIGHT ATTN = 0 +110°C

HD2 RIGHT ATTN = 10 +110°C

HD2 LEFT ATTN = 0 +110°C

HD3 RIGHT dBc = +110°C

HD3 RIGHT dBc = +25°C

HD3 RIGHT dBc = –40°C

–30

–20

HD2 LEFT ATTN = 10 +110°C

HD2 RIGHT ATTN = 0 +25°C

HD2 RIGHT ATTN = 10 +25°C

HD3 LEFT dBc = = +110°C

HD3 LEFT dBc = +25°C

HD3 LEFT dBc = –40°C

–50

–40

HD2 LEFT ATTN = 0 +25°C

HD2 LEFT ATTN = 10 +25°C

HD2 RIGHT ATTN = 0 –40°C

HD2 RIGHT ATTN = 10 –40°C

HD2 LEFT ATTN = 0 –40°C

HD2 LEFT ATTN = 10 –40°C

–70

–90

–60

–80

–110

–130

–150

–100

–120

–50

–30

–10

10

30

50

–50

–40

–30

–20

–10

10

20

30

40

50

525

FREQUENCY OFFSET FROM LO

OFFSET FREQUENCY (MHz)

Figure 72. Observation Receiver HD2 vs. Offset Frequency and Attenuation,

LO = 300 MHz, Tone Level = −22 dBm Plus Attenuation

Figure 75. Observation Receiver HD3 Left and Right vs. Frequency Offset from

LO, Tone Level −22 dBm at Attenuation = 0 dB, LO = 525 MHz

–10

0

Tx1 TO ORx1

Tx2 TO ORx1

Tx1 TO ORx2

Tx2 TO ORx2

HD3 RIGHT dBc = +110°C

HD3 RIGHT dBc = +25°C

HD3 RIGHT dBc = –40°C

HD3 LEFT dBc = = +110°C

HD3 LEFT dBc = +25°C

HD3 LEFT dBc = –40°C

10

–30

20

30

–50

40

50

–70

–90

60

70

80

90

–110

–130

–150

100

110

120

130

140

–50

–40

–30

–20

–10

10

20

30

40

50

0

100

200

300

400

500

600

75

FREQUENCY OFFSET FROM LO

LO FREQUENCY (MHz)

Figure 73. Observation Receiver HD3 Left and Right vs. Frequency Offset from

LO, Tone Level = −21 dBm at Attenuation = 0 dB, LO = 75 MHz

Figure 76. Transmitter to Observation Receiver Isolation vs. LO Frequency,

Temperature = 25°C

Rev. 0 | Page 34 of 95

Data Sheet

ADRV9008-2

–80

–85

–90

–80

–85

–90

100Hz = –110.00dBc/Hz

1kHz = –120.75dBc/Hz

10kHz = –126.54dBc/Hz

100kHz = –132.76dBc/Hz

1MHz = –150.09dBc/Hz

10MHz = –151.09dBc/Hz

100MHz = –150.74dBc/Hz

100Hz = –95.48dBc/Hz

1kHz = –103.55dBc/Hz

10kHz = –109.36dBc/Hz

100kHz = –116.28dBc/Hz

1MHz = –144.62dBc/Hz

10MHz = –152.33dBc/Hz

100MHz = –152.85dBc/Hz

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

–165

–170

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

–165

–170

100

1k

10k

100k

1M

10M

100M

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 77. LO Phase Noise vs. Frequency Offset, LO = 75 MHz, PLL Loop

Bandwidth = 50 kHz

Figure 79. LO Phase Noise vs. Frequency Offset, LO = 525 MHz, PLL Loop

Bandwidth = 50 kHz

–80

100Hz = –99.81dBc/Hz

–85

1kHz

= –108.20dBc/Hz

–90

–95

10kHz = –114.24dBc/Hz

100kHz = –120.82dBc/Hz

1MHz = –147.16dBc/Hz

10MHz = –152.38dBc/Hz

100MHz = –152.51dBc/Hz

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

–165

–170

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 78. LO Phase Noise vs. Frequency Offset, LO = 300 MHz, PLL Loop

Bandwidth = 50 kHz

Rev. 0 | Page 35 of 95

ADRV9008-2

Data Sheet

650 MHz TO 3000 MHz BAND

0

1.0

0.8

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–0.25

–0.50

–0.75

–1.00

–1.25

–1.50

–1.75

–2.00

–2.25

–2.50

–2.75

–3.00

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–225 –175 –125 –75

–25

25

75

125

175

225

BASEBAND OFFSET FREQUENCY (MHz)

LO FREQUENCY (MHz)

Figure 80. Transmitter Matching Circuit Path Loss vs. LO Frequency (Can be

Used for De-Embedding Performance Data)

Figure 83. Transmitter Pass Band Flatness vs. Baseband Offset Frequency,

LO = 2600 MHz

14

–70

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

+110°C

+25°C

–40°C

13

–72

–74

–76

–78

–80

–82

–84

–86

–88

–90

12

11

10

9

8

7

6

5

4

650 850 1050 1250 1450 1650 1850 2050 2250 2450 2650 2850

TRANSMITTER LO FREQUENCY (MHz)

Figure 81. Transmitter CW Output Power vs. Transmitter LO Frequency,

Transmitter QEC and External LO Leakage Active, Transmitter in

200 MHz/450 MHz Bandwidth Mode, IQ Rate = 491.52 MHz, Attenuation =

0 dB (Not De-Embedded)

Figure 84. Transmitter LO Leakage vs. Transmitter LO Frequency, Transmitter

Attenuation = 0 dB

0

+110°C ATTN = 25

+110°C ATTN = 20

+110°C ATTN = 15

+110°C ATTN = 10

+110°C ATTN = 5

+110°C ATTN = 0

+25°C ATTN = 25

+25°C ATTN = 20

+25°C ATTN = 15

+25°C ATTN = 10

+25°C ATTN = 5

+25°C ATTN = 0

–40°C ATTN = 25

–40°C ATTN = 20

–40°C ATTN = 15

–40°C ATTN = 10

–40°C ATTN = 5

–40°C ATTN = 0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Tx1 – Tx2

20

Tx2 – Tx1

40

60

80

100

120

–100

–50

0

50

100

600

1000

1400

1800

2200

2600

3000

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

TRANSMITTER LO FREQUENCY (MHz)

Figure 82. Transmitter Image Rejection vs. Baseband Frequency Offset and

Attenuation, QEC Trained with Three Tones Placed at 10 MHz, 50 MHz, and

100 MHz (Tracking On), Total Combined Power = −6 dBFS, Correction Then

Frozen (Tracking Turned Off), CW Tone Swept Across Large Signal

Bandwidth

Figure 85. Transmitter to Transmitter Isolation vs. Transmitter LO Frequency,

Temperature = 25°C

Rev. 0 | Page 36 of 95

Data Sheet

ADRV9008-2

–145

–150

–155

–160

–165

–40

–45

–50

–55

–60

–65

–70

–75

Tx1 +110°C (LOWER)

Tx1 +110°C (UPPER)

Tx1 +25°C (LOWER)

Tx1 +25°C (UPPER)

Tx1 –40°C (LOWER)

Tx1 –40°C (UPPER)

Tx2 +110°C (LOWER)

Tx2 +110°C (UPPER)

Tx2 +25°C (LOWER)

Tx2 +25°C (UPPER)

Tx2 –40°C (LOWER)

Tx2 –40°C (UPPER)

2600MHz = +110°C

1800MHz = +110°C

650MHz = +110°C

2600MHz = +25°C

1800MHz = +25°C

650MHz = +25°C

2600MHz = –40°C

1800MHz = –40°C

650MHz = –40°C

–170

–175

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

0

2

4

6

8

10

2850

12

14

16

18

20

TRANSMITTER ATTENUATOR SETTING (dB)

SIGNAL OFFSET 90MHz

Figure 86. Transmitter Noise vs. Transmitter Attenuator Setting

Figure 89. Transmitter Adjacent Channel Leakage Ratio vs. Transmitter

Attenuator Setting, Signal Offset = 90 MHz, LO = 2850 MHz, LTE = 20 MHz,

PAR = 12 dB, Upper Side and Lower Side

–40

35

Tx1 +110°C (LOWER)

Tx1 +110°C (UPPER)

Tx1 +25°C (LOWER)

Tx1 +25°C (UPPER)

Tx1 –40°C (LOWER)

Tx1 –40°C (UPPER)

Tx2 +110°C (LOWER)

Tx2 +110°C (UPPER)

Tx2 +25°C (LOWER)

Tx2 +25°C (UPPER)

Tx2 –40°C (LOWER)

Tx2 –40°C (UPPER)

+110°C

+25°C

–40°C

30

–45

–50

–55

–60

–65

–70

–75

25

20

15

10

5

0

–5

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

0

2

4

6

8

10

650

12

14

16

18

20

TRANSMITTER ATTENUATOR SETTING (dB)

SIGNAL OFFSET 90MHz

Figure 87. Transmitter Adjacent Channel Leakage Ratio vs. Transmitter

Attenuator Setting, Signal Offset = 90 MHz, LO = 650 MHz, LTE = 20 MHz,

PAR = 12 dB, Upper Side and Lower Side

Figure 90. Transmitter OIP3, Right or Upper Sideband Response vs.

Transmitter Attenuator Setting, LO = 850 MHz, Digital Backoff per Tone =

15 dB

–40

40

+110°C

+25°C

–40°C

Tx1 +110°C (LOWER)

Tx1 +110°C (UPPER)

Tx1 +25°C (LOWER)

Tx1 +25°C (UPPER)

Tx1 –40°C (LOWER)

Tx1 –40°C (UPPER)

Tx2 +110°C (LOWER)

Tx2 +110°C (UPPER)

Tx2 +25°C (LOWER)

Tx2 +25°C (UPPER)

Tx2 –40°C (LOWER)

Tx2 –40°C (UPPER)

35

30

–45

–50

–55

–60

–65

–70

–75

25

20

15

10

5

0

–5

–10

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

0

2

4

6

8

10

1850

12

14

16

18

20

TRANSMITTER ATTENUATOR SETTING (dB)

SIGNAL OFFSET 90MHz

Figure 91. Transmitter OIP3 Right vs. Transmitter Attenuator Setting, LO =

1850 MHz, Digital Backoff per Tone = 15 dB

Figure 88. Transmitter Adjacent Channel Leakage Ratio vs. Transmitter

Attenuator Setting, Signal Offset = 90 MHz, LO = 1850 MHz,

LTE = 20 MHz, PAR = 12 dB, Upper Side and Lower Side

Rev. 0 | Page 37 of 95

ADRV9008-2

Data Sheet

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

+110°C

+25°C

–40°C

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

0

–5

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 85 90 95

TRANSMITTER ATTENUATOR SETTING (dB)

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 90 95 100

2850

BASEBAND TONE PAIR SWEPT ACROSS PASS BAND (MHz)

Figure 92. Transmitter OIP3 Right vs. Transmitter Attenuator Setting, LO =

2650 MHz, Digital Backoff per Tone = 15 dB

Figure 95. Transmitter OIP3 Right vs. Baseband Tone Pair Swept Across Pass Band,

LO = 2850 MHz, Digital Backoff per Tone = 15 dB

0

45

40

35

30

25

+110°C = (UPPER)

+110°C = (HD2)

+25°C = (UPPER)

+25°C = (HD2)

–40°C = (UPPER)

–40°C = (HD2)

–20

–40

–60

20

Tx1 = +110°C

–80

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

15

10

5

–100

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 85 90 95

TRANSMITTER ATTENUATOR SETTING (dB)

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 90 95 100

850

BASEBAND TONE PAIR SWEPT ACROSS PASS BAND (MHz)

Figure 93. Transmitter OIP3 Right vs. Baseband Tone Pair Swept Across Pass Band,

LO = 850 MHz, Digital Backoff per Tone = 15 dB

Figure 96. Transmitter HD2 vs. Transmitter Attenuator Setting, Baseband

Frequency = 10 MHz, LO = 1850 MHz, Digital Backoff = 15 dB

45

40

35

30

25

0

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

20

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

15

10

5

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 85 90 95

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

650

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 90 95 100

1850

TRANSMITTER ATTENUATOR SETTING (dB)

BASEBAND TONE PAIR SWEPT ACROSS PASSBAND (MHz)

Figure 94. Transmitter OIP3 Right vs. Baseband Tone Pair Swept Across Pass Band,

LO = 1850 MHz, Digital Backoff per Tone = 15 dB

Figure 97. Transmitter HD3 vs. Transmitter Attenuator Setting,

LO = 650 MHz, Digital Backoff = 15 dB

Rev. 0 | Page 38 of 95

Data Sheet

ADRV9008-2

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.025

0.020

0.015

0.010

0.005

0

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

+110°C

+25°C

–40°C

–0.005

–0.010

–0.015

–0.020

–0.025

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

1850

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 98. Transmitter HD3 vs. Transmitter Attenuator Setting,

LO = 1850 MHz, Digital Backoff = 15 dB,

Figure 101. Transmitter Attenuator Step Error vs. Transmitter Attenuator

Setting, LO = 650 MHz

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 650.0MHz

#RES BW 1.0MHz

SPAN 1.000GHz

SWEEP 1.007s (3001pts)

#VBW 1.0kHz

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

2850

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 99. Transmitter HD3 vs. Transmitter Attenuation Setting,

LO = 2850 MHz, Digital Backoff = 15 dB

Figure 102. Transmitter Output Spurious, Transmitter 1 = 650 MHz,

LTE = 5 MHz, Offset = 10 MHz, RMS = −12 dBFS, Temperature = 25°C

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–20

–40

–60

–80

–100

–120

CENTER 650.0MHz

#RES BW 1.0MHz

SPAN 1.000GHz

SWEEP 1.007s (3001pts)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

#VBW 1.0kHz

1850

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 100. Transmitter HD3 Image Appears on Same Side as Desired Signal

vs. Transmitter Attenuation Setting, LO = 1850 MHz,

Digital Backoff = 15 dB

Figure 103. Transmitter Output Spurious, Transmitter 2 = 650 MHz,

LTE = 5 MHz, Offset = 10 MHz, RMS = −12 dBFS, Temperature = 25°C

Rev. 0 | Page 39 of 95

ADRV9008-2

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 650.0MHz

#RES BW 1.0MHz

SPAN 1.000GHz

SWEEP 1.007s (3001pts)

#VBW 1.0kHz

CENTER 650.0MHz

#RES BW 1.0MHz

SPAN 1.000GHz

SWEEP 1.007s (3001pts)

#VBW 1.0kHz

Figure 104. Transmitter Output Spurious, Transmitter 1 = 1850 MHz,

LTE = 5 MHz, Offset = 10 MHz, RMS = −12 dBFS, Temperature = 25°C

Figure 107. Transmitter Output Spurious, Transmitter 2 = 2850 MHz,

LTE = 5 MHz, Offset = 10 MHz, RMS = −12 dBFS, Temperature = 25°C

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–0.25

–0.50

–0.75

–1.00

–1.25

–1.50

–1.75

–2.00

–2.25

–2.50

–2.75

–3.00

CENTER 650.0MHz

#RES BW 1.0MHz

SPAN 1.000GHz

SWEEP 1.007s (3001pts)

#VBW 1.0kHz

LO FREQUENCY (MHz)

Figure 108. Observation Receiver Matching Circuit Path Loss vs. LO

Frequency, Can be Used for De-Embedding Performance Data

Figure 105. Transmitter Output Spurious, Transmitter 2 = 1850 MHz,

LTE = 5 MHz, Offset = 10 MHz, RMS = −12 dBFS, Temperature = 25°C

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+110°C

–10

+25°C

–40°C

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 650.0MHz

#RES BW 1.0MHz

SPAN 1.000GHz

SWEEP 1.007s (3001pts)

650 850 1050 1250 1450 1650 1850 2050 2250 2450 2650 2850

#VBW 1.0kHz

TRANSMITTER LO FREQUENCY (MHz)

Figure 109. Observation Receiver LO Leakage vs. Transmitter LO Frequency

Figure 106. Transmitter Output Spurious, Transmitter 1 = 2850 MHz,

LTE = 5 MHz, Offset = 10 MHz, RMS = −12 dBFS, Temperature = 25°C

Rev. 0 | Page 40 of 95

Data Sheet

ADRV9008-2

24

80

75

70

65

60

55

50

45

40

+110°C

+25°C

–40°C

23

22

21

20

19

18

17

16

15

14

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

650 850 1050 1250 1450 1650 1850 2050 2250 2450 2650 2850

2856 2876 2896 2916 2936 2956 2976 2996 3016 3036 3056 3076 3096 3116

2855 2875 2895 2915 2935 2955 2975 2995 3015 3035 3055 3075 3095 3115

OBSERVATION RECEIVER LO FREQUENCY (MHz)

SWEPT PASS BAND FREQUENCY (MHz)

Figure 110. Observation Receiver Noise Figure vs. Observation Receiver LO

Frequency, Total Nyquist Integration Bandwidth

Figure 113. Observation Receiver IIP2, Sum and Difference Products vs.

Swept Pass Band Frequency, Tones Separated by 1 MHz Swept Across Pass

Band at −19 dBm Each, LO = 2850 MHz, Attenuation = 0 dB,

75

70

65

60

80

75

70

65

60

55

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

IIP2 SUM +110°C

50

45

40

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

55

50

0

2

4

6

8

10

656 676 696 716 736 756 776 796 806 826 846 866 886 906

655 675 695 715 735 755 775 795 805 825 845 865 885 905

OBSERVATION RECEIVER ATTENUATION (dB)

SWEPT PASS BAND FREQUENCY (MHz)

Figure 111. Observation Receiver IIP2, Sum and Difference Products vs.

Swept Pass Band Frequency, Tones Separated by 1 MHz Swept Across Pass

Band at −19 dBm Each, LO = 650 MHz, Attenuation = 0 dB

Figure 114. Observation Receiver IIP2, Sum and Difference Products vs.

Observation Receiver Attenuation, Tone 1 = 1845 MHz, Tone 2 = 1846 MHz

at −19 dBm Plus Attenuation, LO = 1800 MHz

80

75

70

65

60

80

70

60

50

40

30

55

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

20

10

0

50

45

40

662 682 702 722 742 762 782 802 822 842 862 882 902

1806 1826 1846 1866 1886 1906 1926 1946 1966 1986 2006 2026 2046 2066

1805 1825 1845 1865 1885 1905 1925 1945 1965 1985 2005 2025 2045 2065

f2 OFFSET FREQUENCY (MHz)

SWEPT PASS BAND FREQUENCY (MHz)

Figure 112. Observation Receiver IIP2, Sum and Difference Products vs.

Swept Pass Band Frequency, Tones Separated by 1 MHz Swept Across Pass

Band at −19 dBm Each, LO = 1800 MHz, Attenuation = 0 dB

Figure 115. Observation Receiver IIP2, f1 − f2 vs. f2 Offset Frequency, LO =

650 MHz, Tone 1 = 652 MHz, Tone 2 = Swept at −19 dBm Each, Observation

Receiver Attenuation = 0 dB

Rev. 0 | Page 41 of 95

ADRV9008-2

Data Sheet

80

70

60

50

40

30

25

20

15

10

5

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

20

10

0

656 676 696 716 736 756 776 796 816

875 895 915 935

876 896 916 936

836 856

835 855

655 675 695 715 735 755 775 795 815

f2 OFFSET FREQUENCY (MHz)

f1 OFFSET FREQUENCY (MHz)

Figure 116. Observation Receiver IIP2, f1 − f2 vs. f2 Offset Frequency, LO =

1800 MHz, Tone 1 = 1802 MHz, Tone 2 = Swept at −19 dBm Each,

Attenuation = 0 dB

Figure 119. Observation Receiver IIP3, 2f1 − f2 vs. f1 Offset Frequency, LO =

650 MHz, Attenuation = 0 dB, Tones Separated by 1 MHz Swept Across Pass

Band at −19 dBm Each

80

70

60

50

40

25

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

20

15

10

5

30

IIP2 SUM +110°C

20

10

0

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

0

1805 1825 1845 1865 1885 1905 1925 1945 1965 1985 2005 2025 2045

1806 1826 1846 1866 1886 1906 1926 1946 1966 1986 2006 2026 2046

f2 OFFSET FREQUENCY (MHz)

f1 OFFSET FREQUENCY (MHz)

Figure 117. Observation Receiver IIP2, f1 − f2 vs. f2 Offset Frequency, LO =

2850 MHz, Tone 1 = 2852 MHz, Tone 2 = Swept at −19 dBm Each,

Attenuation = 0 dB

Figure 120. Observation Receiver IIP3, 2f1 − f2 vs. f1 Offset Frequency, LO =

1800 MHz, Attenuation = 0 dB, Tones Separated by 1 MHz Swept Across Pass

Band at −19 dBm Each

80

75

70

65

25

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

20

15

10

5

60

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

55

IIP2 DIFF –40°C

50

0

2

4

6

8

10

2855

2885

2886

2915

2916

2945

2946

2975

2976

3005

3006

3035

3036

3065

3066

3095

3096

2856

OBSERVATION RECEIVER ATTENUATION (dB)

f1 OFFSET FREQUENCY (MHz)

Figure 118. Observation Receiver IIP2, f1 − f2 vs. Observation Receiver

Attenuation, LO = 1800 MHz, Tone 1 = 1802 MHz, Tone 2 = 1902 MHz at

−19 dBm Plus Attenuation

Figure 121. Observation Receiver IIP3, 2f1 − f2 vs. f1 Offset Frequency, LO =

2850 MHz, Attenuation = 0 dB, Tones Separated by 1 MHz Swept Across Pass

Band at −19 dBm Each

Rev. 0 | Page 42 of 95

Data Sheet

ADRV9008-2

24

22

20

18

16

14

12

10

8

30

25

20

15

10

5

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

ORx2 = +110°C

ORx2 = +25°C

ORx2 = –40°C

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

6

0

2862

2

4

6

8

10

2892

2922

2952

2982

3012

3042

3072

3102

OBSERVATION RECEIVER ATTENUATION (dB)

INTERMODULATION FREQUENCY (MHz)

Figure 122. Observation Receiver IIP3, 2f1 − f2 vs. Observation Receiver

Attenuation, LO = 1800 MHz, Tone 1 = 1895 MHz, Tone 2 = 1896 MHz at

−19 dBm Plus Attenuation

Figure 125. Observation Receiver IIP3, 2f1 − f2 vs. Intermodulation

Frequency, LO = 2850 MHz, Tone 1 = 2852 MHz, Tone 2 = Swept at −19 dBm

Each

25

24

22

20

18

16

14

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

ORx2 = +110°C

ORx2 = +25°C

ORx2 = –40°C

20

15

10

5

12

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

10

8

0

662

6

692

722

752

782

812

842

872

902

0

2

4

6

8

10

INTERMODULATION FREQUENCY (MHz)

OBSERVATION RECEIVER ATTENUATION (dB)

Figure 123. Observation Receiver IIP3, 2f1 − f2 vs. Intermodulation

Frequency, LO = 650 MHz, Tone 1 = 652 MHz, Tone 2 = Swept at

−19 dBm Each

Figure 126. Observation Receiver IIP3, 2f1 − f2 vs. Observation Receiver

Attenuation, LO = 1800 MHz, Tone 1 = 1802 MHz, Tone 2 = 1922 MHz at

−19 dBm Plus Attenuation

25

0

+110°C = 11.5dB

+110°C = 0dB

+25°C = 11.5dB

+25°C = 0dB

–40°C = 11.5dB

–40°C = 0dB

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

ORx2 = +110°C

ORx2 = +25°C

ORx2 = –40°C

–20

–40

20

15

10

5

–60

–80

–100

–120

0

1812

1842

1872

1902

1932

1962

1992

2022

2052

INTERMODULATION FREQUENCY (MHz)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 127. Observation Receiver Image Rejection vs. Baseband Frequency Offset,

CW Signal Swept Across the Band, LO = 650 MHz

Figure 124. Observation Receiver IIP3, 2f1 − f2 vs. Intermodulation

Frequency, LO = 1800 MHz, Tone 1 = 1802 MHz, Tone 2 = Swept at

−19 dBm Each

Rev. 0 | Page 43 of 95

ADRV9008-2

Data Sheet

18

16

14

12

10

8

0

+110°C = 11.5dB

+110°C = 0dB

+25°C = 11.5dB

+25°C = 0dB

–40°C = 11.5dB

–40°C = 0dB

+110°C

+25°C

–40°C

–20

–40

–60

–80

–100

–120

6

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATION (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 128. Observation Receiver Image Rejection vs. Baseband Frequency Offset,

CW Signal Swept Across the Band, LO = 1850 MHz

Figure 131. Observation Receiver Gain vs. Observation Receiver Attenuation,

LO = 1800 MHz

18

0

+110°C = 11.5dB

+110°C = 0dB

+25°C = 11.5dB

+25°C = 0dB

–40°C = 11.5dB

–40°C = 0dB

+110°C

+25°C

–40°C

16

–20

–40

14

12

10

8

–60

–80

–100

–120

6

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATION (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 129. Observation Receiver Image Rejection vs. Baseband Frequency Offset,

CW Signal Swept Across the Band, LO = 2850 MHz

Figure 132. Observation Receiver Gain vs. Observation Receiver Attenuation,

LO = 2800 MHz

18

0.5

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.4

16

14

12

10

8

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

6

0

1

2

3

4

5

6

7

8

9

10 11 12

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATION (dB)

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

Figure 133. Observation Receiver Attenuator Step Accuracy vs. Observation

Receiver Attenuator Setting, LO = 2600 MHz

Figure 130. Observation Receiver Gain vs. Observation Receiver Attenuation,

LO = 650 MHz

Rev. 0 | Page 44 of 95

Data Sheet

ADRV9008-2

0.5

0

–20

+110°C = 0 (RIGHT)

+110°C = 11.5 (RIGHT)

+110°C = 0 (LEFT)

+110°C = 11.5 (LEFT)

+25°C = 0 (RIGHT)

+25°C = 11.5 (RIGHT)

+25°C = 0 (LEFT)

+110°C

+25°C

–40°C

0.4

+25°C = 11.5 (LEFT)

–40°C = 0 (RIGHT)

–40°C = 11.5 (RIGHT)

–40°C = 0 (LEFT)

0.3

0.2

–40°C = 11.5 (LEFT)

–40

0.1

–60

0

–0.1

–0.2

–0.3

–0.4

–0.5

–80

–100

–120

–100

–75

–50

–25

0

25

50

75

100

OFFSET AND ATTENUATION FREQUENCY (MHz)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 137. Observation Receiver HD2 vs. Offset Frequency and Attenuation,

LO = 1850 MHz, Tone Level = −20 dBm at Attenuation = 0 dB

Figure 134. Observation Receiver Pass Band Flatness vs. Baseband Frequency

Offset, LO = 1800 MHz

0

HD2 RIGHT ATTENUATION = 0dB, +110°C

HD2 RIGHT ATTENUATION = 11.0dB, +110°C

+110°C

+25°C

–40°C

–20

–40

–20

–40

HD2 LEFT ATTENUATION = 0dB, +110°C

HD2 LEFT ATTENUATION = 11.5dB, +110°C

HD2 RIGHT ATTENUATION = 0dB, +25°C

HD2 RIGHT ATTENUATION = 11.5dB, +25°C

HD2 LEFT ATTENUATION = 0dB, +25°C

HD2 LEFT ATTENUATION = 11.5dB, +25°C

HD2 RIGHT ATTENUATION = 0dB, –40°C

HD2 RIGHT ATTENUATION = 11.5dB, –40°C

HD2 LEFT ATTENUATION = 0dB, –40°C

HD2 LEFT ATTENUATION = 11.5dB, –40°C

–60

–80

–100

–120

–100

–75

–50

–25

0

25

50

75

100

0

1

2

3

4

5

6

7

8

9

10

OFFSET FREQUENCY AND ATTENUATION (MHz)

OBSERVATION RECEIVER ATTENUATION (dB)

Figure 138. Observation Receiver HD2 vs. Offset Frequency and Attenuation,

LO = 2850 MHz, Tone Level = −20 dBm at

Figure 135. Observation Receiver DC Offset vs. Observation Receiver

Attenuation, LO = 1850 MHz

Attenuation = 0 dB

0

HD3 RIGHT dBc = +110°C

+110°C = 0 (RIGHT)

+110°C = 11.5 (RIGHT)

+110°C = 0 (LEFT)

+110°C = 11.5 (LEFT)

+25°C = 0 (RIGHT)

+25°C = 11.5 (RIGHT)

+25°C = 0 (LEFT)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

HD3 RIGHT dBc = +25°C

HD3 RIGHT dBc = –40°C

HD3 LEFT dBc = = +110°C

HD3 LEFT dBc = +25°C

HD3 LEFT dBc = –40°C

+25°C = 11.5 (LEFT)

–40°C = 0 (RIGHT)

–40°C = 11.5 (RIGHT)

–40°C = 0 (LEFT)

–40°C = 11.5 (LEFT)

–100

–75

–50

–25

0

25

50

75

100

–100

–75

–50

–25

25

50

75

100

650

OFFSET FREQUENCY (MHz)

OFFSET AND ATTENUATION FREQUENCY (MHz)

Figure 136. Observation Receiver HD2 vs. Offset Frequency and Attenuation,

LO = 650 MHz, Tone Level = −20 dBm at Attenuation = 0 dB

Figure 139. Observation Receiver HD3, Left and Right vs. Offset Frequency,

LO = 650 MHz, Tone Level = −20 dBm at Attenuation = 0 dB

Rev. 0 | Page 45 of 95

ADRV9008-2

Data Sheet

0

20

HD3 RIGHT dBc = +110°C

Tx1 TO ORx1

Tx2 TO ORx1

Tx1 TO ORx2

Tx2 TO ORx2

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

HD3 RIGHT dBc = +25°C

HD3 RIGHT dBc = –40°C

HD3 LEFT dBc = +110°C

HD3 LEFT dBc = +25°C

HD3 LEFT dBc = –40°C

40

60

80

100

120

–100

–75

–50

–25

25

50

75

100

1850

OFFSET FREQUENCY (MHz)

LO FREQUENCY (MHz)

Figure 143. Transmitter to Observation Receiver Isolation vs. LO Frequency,

Temperature = 25°C

Figure 140. Observation Receiver HD3, Left and Right vs. Offset Frequency,

LO = 1850 MHz, Tone Level = −20 dBm at Attenuation = 0 dB

0

–70

–80

HD3 RIGHT dBc = +110°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

HD3 RIGHT dBc = +25°C

HD3 RIGHT dBc = –40°C

HD3 LEFT dBc = = +110°C

HD3 LEFT dBc = +25°C

HD3 LEFT dBc = –40°C

–90

–100

–110

–120

–130

–140

–150

–160

–170

100

1k

10k

100k

1M

10M

–100

–75

–50

–25

25

50

75

100

100M

2850

OFFSET FREQUENCY (MHz)

FREQUENCY OFFSET (Hz)

Figure 141. Observation Receiver HD3, Left and Right vs. Offset Frequency,

LO = 2850 MHz, Tone Level = −20 dBm at Attenuation = 0 dB

Figure 144. LO Phase Noise vs. Frequency Offset, LO = 1900 MHz, Spectrum

Analyzer Limits Far Out Noise

0

+110°C RIGHT = 11.5dBc

+110°C RIGHT = 0dBc

+110°C LEFT = 11.5dBc

+110°C LEFT = 0dBc

+25°C RIGHT = 11.5dBc

+25°C RIGHT = 0dBc

+25°C LEFT = 11.5dBc

+25°C LEFT = 0dBc

–40°C RIGHT = 11.5dBc

–40°C RIGHT = 0dBc

–40°C LEFT = 11.5dBc

–40°C LEFT = 0dBc

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–75

–50

–25

25

50

75

100

1850

OFFSET FREQUENCY (MHz)

Figure 142. Observation Receiver HD3, Left and Right vs. Offset Frequency,

LO = 1850 MHz, Observation Receiver Attenuation = 0 dB and 11.5 dB

Rev. 0 | Page 46 of 95

Data Sheet

ADRV9008-2

3400 MHz TO 4800 MHz BAND

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–40°C ATTENUATION = 0MHz

–40°C ATTENUATION = 5MHz

–40°C ATTENUATION = 10MHz

–40°C ATTENUATION = 15MHz

–40°C ATTENUATION = 20MHz

–40°C ATTENUATION = 25MHz

+110°C ATTENUATION = 0MHz

+110°C ATTENUATION = 5MHz

+110°C ATTENUATION = 10MHz

+110°C ATTENUATION = 15MHz

+110°C ATTENUATION = 20MHz

+110°C ATTENUATION = 25MHz

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

+25°C ATTENUATION = 0MHz

+25°C ATTENUATION = 5MHz

+25°C ATTENUATION = 10MHz

+25°C ATTENUATION = 15MHz

+25°C ATTENUATION = 20MHz

+25°C ATTENUATION = 25MHz

3400

3600

3800

4000

4200

4400

4600

4800

5000

–100

–50

0

50

100

LO FREQUENCY (MHz)

BASEBAND OFFSET FREQUENCY (MHz)

Figure 145. Transmitter Path Loss vs. LO Frequency (Simulation), Can be Used for

De-Embedding Performance Data

Figure 148. Transmitter Image Rejection vs. Baseband Offset Frequency and

Attenuation, QEC Trained with Three Tones (Tracking On), Total Combined Power

= −6 dBFS, Correction Then Frozen (Tracking Turned Off), Continuous Wave Tone

Swept Across Large Signal Bandwidth, LO = 4600 MHz

10

9

1.0

0.9

0.8

0.7

0.6

Tx1 = –40°C

Tx2 = –40°C

Tx1 = +25°C

Tx2 = +25°C

Tx1 = +110°C

Tx2 = +110°C

8

0.5

0.4

7

0.3

0.2

6

0.1

0.0

5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–1.0

4

3

Tx1 = –40°C

Tx2 = –40°C

2

Tx1 = +25°C

Tx2 = +25°C

1

Tx1 = +110°C

Tx2 = +110°C

0

3400

3600

3800

4000

4200

4400

4600

4800

–225 –175 –125 –75

–25

25

75

125

175

225

TRANSMITTER LO FREQUENCY (MHz)

BASEBAND OFFSET FREQUENCY (MHz)

Figure 146. Transmitter Continuous Wave Output Power vs. Transmitter LO

Frequency, Transmitter QEC and External LO Leakage Active, Transmitter in

200 MHz/450 MHz Bandwidth Mode, IQ Rate = 491.52 MHz, Attenuation =0 dB,

Not De-Embedded

Figure 149. Transmitter Pass Band Flatness vs. Baseband Offset Frequency, Off

Chip Match Response De-Embedded, LO = 3600 MHz

0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

+110°C ATTENUATION = 0MHz

+110°C ATTENUATION = 5MHz

+110°C ATTENUATION = 10MHz

+110°C ATTENUATION = 15MHz

+110°C ATTENUATION = 20MHz

+110°C ATTENUATION = 25MHz

–40°C ATTENUATION = 0MHz

–40°C ATTENUATION = 5MHz

–40°C ATTENUATION = 10MHz

–40°C ATTENUATION = 15MHz

–40°C ATTENUATION = 20MHz

–40°C ATTENUATION = 25MHz

Tx1 = –40°C

Tx2 = –40°C

Tx1 = +25°C

Tx2 = +25°C

Tx1 = +110°C

Tx2 = +110°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+25°C ATTENUATION = 0MHz

+25°C ATTENUATION = 5MHz

+25°C ATTENUATION = 10MHz

+25°C ATTENUATION = 15MHz

+25°C ATTENUATION = 20MHz

+25°C ATTENUATION = 25MHz

0.1

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–1.0

–100

–50

0

50

100

–225 –175 –125 –75

–25

25

75

125

175

225

BASEBAND OFFSET FREQUENCY AND ATTENUATION (MHz)

BASEBAND OFFSET FREQUENCY (MHz)

Figure 147. Transmitter Image Rejection vs. Baseband Offset Frequency and

Attenuation, QEC Trained with Three Tones Placed at 10 MHz, 50 MHz, and

100 MHz (Tracking On), Total Combined Power = −6 dBFS, Correction Then

Frozen (Tracking Turned Off), Continuous Wave Tone Swept Across Large Signal

Bandwidth, LO = 3700 MHz

Figure 150. Transmitter Pass Band Flatness vs. Baseband Offset Frequency, Off

Chip Match Response De-Embedded, LO = 4600 MHz

Rev. 0 | Page 47 of 95

ADRV9008-2

Data Sheet

40

35

30

25

20

15

10

5

–70

Tx1 = –40°C

Tx2 = –40°C

–72

+110°C

+25°C

–40°C

Tx1 = +25°C

Tx2 = +25°C

–74

Tx1 = +110°C

Tx2 = +110°C

–76

–78

–80

–82

–84

–86

–88

0

–5

–10

–90

3700

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

4600

TRANSMITTER ATTENUATOR SETTING (dB)

TRANSMITTER LO FREQUENCY (MHz)

Figure 154. Transmitter OIP3, Right vs. Transmitter Attenuator Setting,

LO = 3600 MHz, Total RMS Power = −12 dBFS.

Figure 151. Transmitter LO Leakage vs. Transmitter LO Frequency,

Transmitter Attenuation = 0 dB

35

0

Tx1 TO Tx2 0dB

10

30

25

20

15

10

5

+110°C

+25°C

–40°C

Tx2 TO Tx1 0dB

20

30

40

50

60

70

0

80

–5

–10

90

100

3400

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

3600

3800

4000

4200

4400

4600

4800

TRANSMITTER ATTENUATOR SETTING (dB)

TRANSMITTER LO FREQUENCY (MHz)

Figure 155. Transmitter OIP3, Right vs. Transmitter Attenuator Setting,

LO = 4600 MHz, Total RMS Power = −12 dBFS

Figure 152. Transmitter to Transmitter Isolation vs. Transmitter LO

Frequency, Temperature = 25°C

40

35

30

25

20

–145

4600MHz = +110°C

4600MHz = +25°C

4600MHz = –40°C

3600MHz = +110°C

3600MHz = +25°C

3600MHz = –40°C

–150

–155

–160

–165

–170

–175

15

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

10

5

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

TRANSMITTER ATTENUATOR SETTING (dB)

3600

BASEBAND TONE PAIR SWEPT ACROSS PASS BAND (MHz)

Figure 153. Transmitter Noise vs. Transmitter Attenuator Setting

Figure 156. Transmitter OIP3, Right vs. Baseband Tone Pair Swept Across Pass

Band, LO = 3600 MHz, Total RMS Power = −12 dBFS

Rev. 0 | Page 48 of 95

Data Sheet

ADRV9008-2

0

–20

40

35

30

25

20

15

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–40

–60

–80

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

10

5

–100

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

3600

TRANSMITTER ATTENUATOR SETTING (dB)

5

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

10

4600

BASEBAND TONE PAIR SWEPT ACROSS PASS BAND (MHz)

Figure 157. Transmitter OIP3, Right vs. Baseband Tone Pair Swept Across Pass

Band, LO = 4600 MHz, Total RMS Power = −12 dBFS

Figure 160. Transmitter HD3 vs. Transmitter Attenuator Setting,

LO = 3600 MHz, CW = −15 dBFS, Baseband Frequency = 10 MHz

0

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

+110°C = HD2

+25°C = HD2

–40°C = HD2

+110°C = UPPER HD2

+25°C = UPPER HD2

–40°C = UPPER HD2

–20

–40

–20

–40

–60

–80

–100

–120

–100

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

4600

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 158. Transmitter HD2 vs. Transmitter Attenuator Setting, Baseband

Frequency = 10 MHz, LO = 3600 MHz, CW = −15 dBFS

Figure 161. Transmitter HD3 vs. Transmitter Attenuator Setting,

LO = 4600 MHz, CW = −15 dBFS, Baseband Frequency = 10 MHz

0

+110°C = HD2

+25°C = HD2

–40°C = HD2

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

–20

+110°C = UPPER HD2

+25°C = UPPER HD2

–40°C = UPPER HD2

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–40

–60

–40

–60

–80

–100

–120

–100

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10

3600

12

14

16

18

20

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 159. Transmitter HD2 vs. Transmitter Attenuator Setting, Baseband

Frequency = 10 MHz, LO = 4600 MHz, CW = −15 dBFS

Figure 162. Transmitter HD3 Image Appears on Same Side as Desired Signal vs.

Transmitter Attenuator Setting, LO = 3600 MHz, CW = −15 dBFS

Rev. 0 | Page 49 of 95

ADRV9008-2

Data Sheet

0

–30

–32

–34

–36

–38

–40

–42

–44

–46

–48

–50

Tx1 = +110°C

+110°C

+25°C

–40°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–20

–40

–60

–80

–100

–120

0

2

4

6

8

10

12

14

16

18

20

0

5

10

15

20

25

4600

TRANSMITTER ATTENUATOR SETTING (dB)

TRANSMITTER ATTENUATION (dBm)

Figure 163. Transmitter HD3 Image Appears on Same Side as Desired Signal vs.

Transmitter Attenuator Setting, LO = 4600 MHz, CW = −15 dBFS

Figure 166. Transmitter EVM vs. Transmitter Attenuation, LTE = 20 MHz, Signal

Centered on DC, LO = 3600 MHz

–30

0.05

0.04

0.03

0.02

0.01

0

+110°C

+25°C

–40°C

–32

–34

–36

–38

–40

–42

–44

–46

–48

–50

–0.01

–0.02

+110°C

+25°C

–40°C

–0.03

–0.04

–0.05

0

5

10

15

20

25

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATION (dBm)

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 167. Transmitter EVM vs. Transmitter Attenuation,

LTE = 20 MHz, Signal Centered on DC, LO = 4600 MHz

Figure 164. Transmitter Attenuator Step Error vs. Transmitter Attenuator

Setting, LO = 3600 MHz

–10

–20

0.05

0.04

0.03

0.02

0.01

0

Tx OUTPUT

ANALYZER NO SIGNAL

–30

–40

–50

–60

–70

–80

–90

–100

–0.01

–0.02

+110°C

+25°C

–40°C

–0.03

–0.04

–0.05

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

FREQUENCY (MHz)

Figure 168. Amplitude vs. Frequency, Transmitter Output Spurious,

Transmitter 1 = 4600 MHz, LTE = 5 MHz, Offset = 10 MHz, RMS Ripple in Noise

Floor due to Spectrum Analyzer = −12 dBFS, Temperature = 25°C

Figure 165. Transmitter Attenuator Step Error vs. Transmitter Attenuator

Setting, LO = 4600 MHz

Rev. 0 | Page 50 of 95

Data Sheet

ADRV9008-2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

34

32

30

28

26

24

22

20

18

16

14

+110°C

+25°C

–40°C

3400

3600

3800

4000

4200

4400

4600

4800

5000

0

1

2

3

4

5

6

7

8

9

10

LO FREQUENCY (MHz)

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

Figure 169. Observation Receiver Off Chip Matching Circuit Path Loss vs. LO

Frequency (Simulation), Can be Used for De-Embedding Performance Data

Figure 172. Observation Receiver Noise Figure vs. Observation Receiver

Attenuator Setting, LO = 4600 MHz, Total Nyquist Integration Bandwidth

80

75

70

65

60

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+110°C

+25°C

–40°C

55

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

50

45

40

3600

4600

3606 3626 3646 3666 3686 3706 3726 3746 3766 3786 3806 3826

3605 3625 3645 3665 3685 3705 3725 3745 3765 3785 3805 3825

LO FREQUENCY (MHz)

f1 OFFSET FREQUENCY (MHz)

Figure 170. Observation Receiver LO Leakage vs. LO Frequency from

3600 MHz to 4600 MHz

Figure 173. Observation Receiver IIP2, Sum and Difference Products vs. f1

Offset Frequency, Tones Separated by 1 MHz Swept Across

Pass Band at −22 dBm Each, LO = 3600 MHz, Attenuation = 0 dB

32

80

75

70

65

60

+110°C

+25°C

–40°C

30

28

26

24

22

20

18

16

14

55

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

50

45

40

4606 4626 4646 4666 4686 4706 4726 4746 4766 4786 4806 4826

4605 4625 4645 4665 4685 4705 4725 4745 4765 4785 4805 4825

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

f1 OFFSET FREQUENCY (MHz)

Figure 174. Observation Receiver IIP2, Sum and Difference Products vs. f1

Offset Frequency, Tones Separated by 1 MHz Swept Across Pass Band at

−22 dBm Each, LO = 4600 MHz, Attenuation = 0 dB

Figure 171. Observation Receiver Noise Figure vs. Observation Receiver

Attenuator Setting, LO = 3600 MHz, Total Nyquist Integration Bandwidth

Rev. 0 | Page 51 of 95

ADRV9008-2

Data Sheet

80

75

70

65

60

55

50

80

70

60

50

40

30

20

10

0

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

INTERMODULATION FREQUENCY (MHz)

Figure 175. Observation Receiver IIP2, Sum and Difference Products vs.

Observation Receiver Attenuation, LO = 3600 MHz, Tone 1 = 3645 MHz,

Tone 2 = 3646 MHz at −22 dBm Plus Attenuation

Figure 178. Observation Receiver IIP2, f1 − f2 vs. Intermodulation Frequency,

LO = 4600 MHz, Tone 1 = 4602 MHz, Tone 2 = Swept, −22 dBm Each,

Attenuation = 0 dB

80

75

70

65

80

75

70

65

60

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

55

IIP2 DIFF –40°C

50

0

2

4

6

8

10

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

Figure 176. Observation Receiver IIP2, Sum and Difference Products vs.

Observation Receiver Attenuation, LO = 4600 MHz, Tone 1 = 4645 MHz,

Tone 2 = 4646 MHz at −22 dBm Plus Attenuation

Figure 179. Observation Receiver IIP2, f1 − f2 vs. Observation Receiver

Attenuation, LO = 3600 MHz, Tone 1 = 3602 MHz, Tone 2 = 3702 MHz at

−22 dBm Plus Attenuation

80

70

60

50

40

80

75

70

65

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

30

20

10

0

60

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

55

50

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

INTERMODULATION FREQUENCY (MHz)

Figure 177. Observation Receiver IIP2, f1 − f2 vs. Intermodulation Frequency,

LO = 3600 MHz, Tone 1 = 3602 MHz, Tone 2 = Swept, −22 dBm Each,

Attenuation = 0 dB

Figure 180. Observation Receiver IIP2, f1 − f2 vs. Observation Receiver

Attenuation, LO = 4600 MHz, Tone 1 = 4602 MHz, Tone 2 = 4612 MHz at

−22 dBm Plus Attenuation

Rev. 0 | Page 52 of 95

Data Sheet

ADRV9008-2

25

20

15

10

5

30

28

26

24

22

20

18

16

14

12

10

8

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

6

0

3605 3625 3645 3665 3685 3705 3725 3745 3765 3785 3805 3825

3606 3626 3646 3666 3686 3706 3726 3746 3766 3786 3806 3826

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

f1 OFFSET FREQUENCY (MHz)

Figure 181. Observation Receiver IIP3, f1 − f2 vs. f1 Offset Frequency, LO =

3600 MHz, Attenuation = 0 dB, Tones Separated by 1 MHz Swept Across Pass

Band at −22 dBm Each

Figure 184. Observation Receiver IIP3, 2f1 − f2 vs. Observation Receiver

Attenuation, LO = 4600 MHz, Tone 1 = 4695 MHz, Tone 2 = 4696 MHz at

−22 dBm Plus Attenuation

25

30

25

20

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

20

15

10

5

15

INPUT IP3 SUM +110°C

INPUT IP3 SUM +25°C

INPUT IP3 SUM –40°C

INPUT IP3 DIFF +110°C

INPUT IP3 DIFF +25°C

INPUT IP3 DIFF –40°C

10

5

0

4606 4626 4646 4666 4686 4706 4726 4746 4766 4786 4806 4826

4605 4625 4645 4665 4685 4705 4725 4745 4765 4785 4805 4825

f1 OFFSET FREQUENCY (MHz)

INTERMODULATION FREQUENCY (MHz)

Figure 185. Observation Receiver IIP3, 2f1 − f2 vs. Intermodulation

Frequency, LO = 3600 MHz, Tone 1 = 3602 MHz, Tone 2 = Swept, −22 dBm

Each

Figure 182. Observation Receiver IIP3, 2f1 − f2 vs. f1 Offset Frequency,

LO = 4600 MHz, Attenuation = 0 dB, Tones Separated by 1 MHz Swept Across Pass

Band at −22 dBm Each

30

25

20

30

28

26

24

22

20

18

16

14

12

15

IIP3 SUM +110°C

IIP3 SUM +25°C

IIP3 SUM –40°C

IIP3 DIFF +110°C

IIP3 DIFF +25°C

IIP3 DIFF –40°C

10

5

10

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

8

6

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

INTERMODULATION FREQUENCY (MHz)

Figure 186. Observation Receiver IIP3, 2f1 − f2 vs. Intermodulation

Frequency, LO = 4600 MHz, Tone 1 = 4602 MHz, Tone 2 Swept,

−22 dBm Each

Figure 183. Observation Receiver IIP3, 2f1 − f2 vs. Observation Receiver

Attenuation, LO = 3600 MHz, Tone 1 = 3695 MHz, Tone 2 = 3696 MHz at

−22 dBm Plus Attenuation

Rev. 0 | Page 53 of 95

ADRV9008-2

Data Sheet

30

28

26

24

22

20

18

16

14

12

10

8

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+110°C = 10dB

+25°C = 10dB

–40°C = 10dB

+110°C = 0dB

+25°C = 0dB

–40°C = 0dB

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

6

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 187. Observation Receiver IIP3, 2f1 to f2 vs. Observation Receiver

Attenuation, LO = 3600 MHz, Tone 1 = 3602 MHz, Tone 2 = 3722 MHz,

−22 dBm Plus Attenuation Each

Figure 190. Observation Receiver Image Rejection vs. Baseband Frequency Offset,

CW Signal Swept Across the Band, LO = 4600 MHz

18

30

28

26

24

22

20

18

16

14

12

+110°C

+25°C

–40°C

16

14

12

10

8

10

6

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

8

6

4

0

1

2

3

4

5

6

7

8

9

10

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

Figure 188. Observation Receiver IIP3, 2f1 − f2 vs. Observation Receiver

Attenuation, LO = 4600 MHz, Tone 1 = 4602 MHz, Tone 2 = 4722 MHz at

−22 dBm Plus Attenuation Each

Figure 191. Observation Receiver Gain vs. Observation Receiver Attenuation,

LO = 3600 MHz

18

0

+110°C = 10dB

–10

+110°C

+25°C

–40°C

16

+25°C = 10dB

–40°C = 10dB

+110°C = 0dB

+25°C = 0dB

–40°C = 0dB

–20

–30

–40

14

12

10

8

–50

–60

–70

–80

6

–90

4

–100

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATION (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 189. Observation Receiver Image Rejection vs. Baseband Frequency Offset,

CW Signal Swept Across the Band, LO = 3600 MHz

Figure 192. Observation Receiver Gain vs. Observation Receiver Attenuation,

LO = 4600 MHz

Rev. 0 | Page 54 of 95

Data Sheet

ADRV9008-2

0.5

0.4

+110°C

+25°C

–40°C

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

+110°C

+25°C

–40°C

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 196. Observation Receiver Pass Band Flatness vs. Baseband Frequency

Offset, LO = 4600 MHz

Figure 193. Observation Receiver Gain Step Error vs. Observation Receiver

Attenuator Setting, LO = 3600 MHz

0

0.5

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

0.4

0.3

+110°C

+25°C

–40°C

–20

0.2

–40

–60

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–80

–100

–120

0

5

10

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATION (dB)

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

Figure 197. Observation Receiver DC Offset vs. Observation Receiver

Attenuation, LO = 3600 MHz

Figure 194. Observation Receiver Gain Step Error vs. Observation Receiver

Attenuator Setting, LO = 4600 MHz

0

0.5

0.4

0.3

0.2

0.1

0

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

–20

–40

–60

–0.1

–80

–0.2

–0.3

–0.4

–0.5

+110°C

+25°C

–40°C

–100

–120

0

5

10

OBSERVATION RECEIVER ATTENUATION (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 195. Observation Receiver Pass Band Flatness vs. Baseband Frequency

Offset, LO = 3600 MHz

Figure 198. Observation Receiver DC Offset vs. Observation Receiver

Attenuation, LO = 4600 MHz

Rev. 0 | Page 55 of 95

ADRV9008-2

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+110°C = 0 (RIGHT)

+110°C = 11.5 (RIGHT)

+110°C = 0 (LEFT)

+110°C = 11.5 (LEFT)

+25°C = 0 (RIGHT)

+25°C = 11.5 (RIGHT)

+25°C = 0 (LEFT)

HD3 RIGHT dBc = +110°C

HD3 RIGHT dBc = +25°C

HD3 RIGHT dBc = –40°C

HD3 LEFT dBc = = +110°C

HD3 LEFT dBc = +25°C

HD3 LEFT dBc = –40°C

+25°C = 11.5 (LEFT)

–40°C = 0 (RIGHT)

–40°C = 11.5 (RIGHT)

–40°C = 0 (LEFT)

–20

–40

–40°C = 11.5 (LEFT)

–60

–80

–100

–120

–100

–75

–50

–25

0

25

50

75

100

–90.0

–67.5

–45.0

–22.5

22.5

45.0

67.5

90.0

OFFSET FREQUENCY (MHz)

Figure 199. Observation Receiver HD2 vs. Offset Frequency, LO = 3600 MHz,

Tone Level = −20 dBm Plus Attenuation

Figure 202. Observation Receiver HD3, Left and Right vs. Offset Frequency,

LO = 4600 MHz, Tone Level = −20 dBm

0

+110°C = 0 (RIGHT)

+110°C = 11.5 (RIGHT)

+110°C = 0 (LEFT)

+110°C = 11.5 (LEFT)

+25°C = 0 (RIGHT)

+25°C = 11.5 (RIGHT)

+25°C = 0 (LEFT)

Tx1 TO ORx1

+25°C = 11.5 (LEFT)

–40°C = 0 (RIGHT)

–40°C = 11.5 (RIGHT)

–40°C = 0 (LEFT)

Tx2 TO ORx1

Tx1 TO ORx2

Tx2 TO ORx2

20

40

–20

–40

–40°C = 11.5 (LEFT)

60

–60

80

–80

100

120

140

–100

–120

–100

–75

–50

–25

0

25

50

75

100

3400

3600

3800

4000

4200

4400

4600

4800

OFFSET FREQUENCY (MHz)

LO FREQUENCY (MHz)

Figure 200. Observation Receiver HD2 vs. Offset Frequency, LO = 4600 MHz,

Tone Level = −20 dBm Plus Attenuation

Figure 203. Transmitter to Observation Receiver Isolation vs. LO Frequency,

Temperature = 25°C

–70

–80

0

HD3 RIGHT dBc = +110°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

HD3 RIGHT dBc = +25°C

HD3 RIGHT dBc = –40°C

HD3 LEFT dBc = = +110°C

HD3 LEFT dBc = +25°C

HD3 LEFT dBc = –40°C

–90

–110

–120

–130

–140

–150

–160

–170

100

1k

10k

100k

1M

10M

100M

–90.0

–67.5

–45.0

–22.5

22.5

45.0

67.5

90.0

FREQUENCY OFFSET (Hz)

OFFSET FREQUENCY (MHz)

Figure 201. Observation Receiver HD3, Left and Right vs. Offset Frequency,

LO = 3600 MHz, Tone Level = −20 dBm

Figure 204. LO Phase Noise vs. Frequency Offset, LO = 3800 MHz, PLL Loop

Bandwidth = 300 kHz, Spectrum Analyzer Limits Far Out Noise

Rev. 0 | Page 56 of 95

Data Sheet

ADRV9008-2

5100 MHz TO 5900 MHz BAND

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+110°C = 20dB

+110°C = 15dB

+110°C = 10dB

+110°C = 5dB

+110°C = 0dB

+25°C = 20dB

+25°C = 15dB

+25°C = 10dB

+25°C = 5dB

+25°C = 0dB

–40°C = 20dB

–40°C = 15dB

–40°C = 10dB

–40°C = 5dB

–40°C = 0dB

–0.5

–1.0

–1.5

–2.0

–2.5

5000

5200

5400

5600

5800

6000

LO FREQUENCY (MHz)

BASEBAND OFFSET FREQUENCY (MHz)

Figure 205. Transmitter Path Loss vs. LO Frequency (Simulation), Useful for

De-Embedding Performance Data

Figure 208. Transmitter Image Rejection vs. Baseband Offset Frequency, QEC

Trained with Three Tones Placed at 10 MHz, 50 MHz, and 100 MHz (Tracking

On), Total Combined Power = −6 dBFS, Correction Then Frozen (Tracking

Turned Off), CW Tone Swept Across Large Signal Bandwidth, LO = 5500 MHz

0

10

+110 – 20

+110 – 15

+110 – 10

+110 – 5

+110 – 0

+25 – 20

+25 – 15

+25 – 10

+25 – 5

+25 – 0

–40 – 20

–40 – 15

–40 – 10

–40 – 5

–40 – 0

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

9

8

7

6

5

4

3

2

1

0

5100

5300

5500

5700

5900

–100 –80 –60 –40 –20

0

20

40

60

80

100

BASEBAND OFFSET FREQUENCY (MHz)

TRANSMITTER LO FREQUENCY (MHz)

Figure 209. Transmitter Image Rejection vs. Baseband Offset Frequency, QEC

Trained with Three Tones Placed at 10 MHz, 50 MHz, and 100 MHz (Tracking

On), Total Combined Power = −6 dBFS, Correction Then Frozen (Tracking

Turned Off), CW Tone Swept Across Large Signal Bandwidth, LO = 5900 MHz

Figure 206. Transmitter CW Output Power vs. Transmitter LO Frequency,

Transmitter QEC, and External LO Leakage Active, Bandwidth Mode =

200 MHz/450 MHz, IQ Rate = 491.52 MHz, Attenuation = 0 dB,

Not De-Embedded

1.0

0

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

+110°C = 20dB

+110°C = 15dB

+110°C = 10dB

+110°C = 5dB

+110°C = 0dB

+25°C = 20dB

+25°C = 15dB

+25°C = 10dB

+25°C = 5dB

+25°C = 0dB

–40°C = 20dB

–40°C = 15dB

–40°C = 10dB

–40°C = 5dB

–40°C = 0dB

0.8

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–225 –175 –125 –75

–25

25

75

125

175

225

BASEBAND OFFSET FREQUENCY (MHz)

Figure 210. Transmitter Pass Band Flatness vs. Baseband Offset Frequency,

Off Chip Match Response De-Embedded, LO = 5700 MHz, Measurements

Performed with Device Calibrated at 25°C

Figure 207. Transmitter Image Rejection vs. Baseband Offset Frequency, QEC

Enabled (Tracking On) with Three Tones Placed at 10 MHz, 50 MHz, and

100 MHz Offset from LO, Total Combined Power = −6 dBFS, Correction Then

Frozen (Tracking Turned Off), CW Tone Swept Across Large Signal

Bandwidth, LO = 5100 MHz

Rev. 0 | Page 57 of 95

ADRV9008-2

Data Sheet

–70

–40

–45

–50

–55

–60

–65

–70

–75

Tx1 = +110°C

Tx2 = +110°C (LOWER)

Tx2 = +110°C (UPPER)

Tx2 = +25°C (LOWER)

Tx2 = +25°C (UPPER)

Tx2 = –40°C (LOWER)

Tx2 = –40°C (UPPER)

Tx2 = +110°C (LOWER)

–72

–74

–76

–78

–80

–82

–84

–86

–88

–90

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

Tx2 = +110°C (UPPER)

Tx2 = +25°C (LOWER)

Tx2 = +25°C (UPPER)

Tx2 = –40°C (LOWER)

Tx2 = –40°C (UPPER)

5100

5500

TRANSMITTER LO FREQUENCY (MHz)

5900

0

2

4

6

8

10

12

14

16

18

20

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 211. Transmitter LO Leakage vs. Transmitter LO Frequency,

Transmitter Attenuation = 0 dB

Figure 214. Transmitter Adjacent Channel Leakage Ratio vs. Transmitter

Attenuator Setting, LO = 5100 MHz, LTE = 20 MHz, PAR = 12 dB, DAC Boost

Normal, Upper Side and Lower Side, Decreasing ACLR at Higher Attenuation

due to Spectrum Analyzer Noise Floor

0

–40

Tx2 = +110°C (LOWER)

Tx2 = +110°C (UPPER)

Tx2 = +25°C (LOWER)

Tx2 = +25°C (UPPER)

Tx2 = –40°C (LOWER)

Tx2 = –40°C (UPPER)

Tx2 = +110°C (LOWER)

Tx2 = +110°C (UPPER)

Tx2 = +25°C (LOWER)

Tx2 = +25°C (UPPER)

Tx2 = –40°C (LOWER)

Tx2 = –40°C (UPPER)

Tx1 TO Tx2

Tx2 TO Tx1

10

20

–45

–50

–55

–60

–65

–70

–75

30

40

50

60

70

80

90

100

5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000

0

2

4

6

8

10

12

14

16

18

20

TRANSMITTER LO FREQUENCY (MHz)

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 212. Transmitter to Transmitter Isolation vs. Transmitter LO Frequency,

Temperature = 25°C

Figure 215. Transmitter Adjacent Channel Leakage Ratio vs. Transmitter

Attenuator Setting, LO = 5500 MHz, LTE = 20 MHz, PAR = 12 dB, DAC Boost

Normal, Upper Side and Lower Side, Decreasing ACLR at Higher Attenuation

Due to Spectrum Analyzer Noise Floor

–150

–40

5100MHz = +110°C

5100MHz = +25°C

5100MHz = –40°C

5500MHz = +110°C

5500MHz = +25°C

5500MHz = –40°C

Tx2 = +110°C (LOWER)

Tx2 = +110°C (UPPER)

Tx2 = +25°C (LOWER)

Tx2 = +25°C (UPPER)

Tx2 = –40°C (LOWER)

Tx2 = –40°C (UPPER)

Tx2 = +110°C (LOWER)

Tx2 = +110°C (UPPER)

Tx2 = +25°C (LOWER)

Tx2 = +25°C (UPPER)

Tx2 = –40°C (LOWER)

Tx2 = –40°C (UPPER)

–45

–50

–55

–60

–65

–70

–155

–160

–165

–170

–175

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

14

16

18

20

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 216. Transmitter Adjacent Channel Leakage Ratio vs. Transmitter

Attenuator Setting, LO = 5900 MHz, LTE = 20 MHz, PAR = 12 dB, DAC Boost

Normal, Upper Side and Lower Side, Decreasing ACLR at Higher Attenuation

Due to Spectrum Analyzer Noise Floor

Figure 213. Transmitter Noise vs. Transmitter Attenuator Setting

Rev. 0 | Page 58 of 95

Data Sheet

ADRV9008-2

40

35

30

25

20

15

10

5

30

25

20

15

10

5

+110°C

+25°C

–40°C

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

TRANSMITTER ATTENUATOR SETTING (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 220. Transmitter OIP3, Right vs. Baseband Frequency Offset,

LO = 5100 MHz, Total RMS Power = −12 dBFS Power, Transmitter

Attenuation = 4 dB

Figure 217. Transmitter OIP3, Right vs. Transmitter Attenuator Setting,

LO = 5100 MHz, Total RMS Power = −12 dBFS

35

30

25

20

15

+110°C

+25°C

–40°C

30

25

20

15

10

5

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

10

Tx2 = –40°C

5

0

–5

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

5

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

10

TRANSMITTER ATTENUATOR SETTING (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 218. Transmitter OIP3, Right vs. Transmitter Attenuator Setting,

LO = 5500 MHz, Total RMS Power = −12 dBFS

Figure 221. Transmitter OIP3, Right vs. Baseband Frequency Offset,

LO = 5500 MHz, Total RMS Power = −12 dBFS, Transmitter Attenuation =

4 dB

35

30

25

20

15

+110°C

+25°C

–40°C

30

25

20

15

10

5

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

10

Tx2 = –40°C

5

0

–5

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

5

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

10

TRANSMITTER ATTENUATOR SETTING (dB)

5900

BASEBAND FREQUENCY OFFSET (MHz)

Figure 222. Transmitter OIP3, Right vs. Baseband Frequency Offset,

LO = 5900 MHz, Total RMS Power = −12 dBFS, Transmitter

Attenuation = 4 dB

Figure 219. Transmitter OIP3, Right vs. Transmitter Attenuator Setting,

LO = 5800 MHz, Total RMS Power = −12 dBFS

Rev. 0 | Page 59 of 95

ADRV9008-2

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

+110°C (HD2)

+25°C (HD2)

–40°C (HD2)

+110°C (UPPER)

+25°C (UPPER)

–40°C (UPPER)

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–20

–40

–60

–80

–100

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

5100

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 223. Transmitter HD2 vs. Transmitter Attenuator Setting, Baseband

Frequency = 10 MHz, LO = 5100 MHz, CW = −15 dBFS

Figure 226. Transmitter HD3 on Opposite Sideband vs. Transmitter

Attenuator Setting, LO = 5100 MHz, CW = −15 dBFS, Baseband Frequency =

10 MHz

0

+110°C (HD2)

+25°C (HD2)

–40°C (HD2)

+110°C (UPPER)

+25°C (UPPER)

–40°C (UPPER)

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–20

–40

–60

–80

–100

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 227. Transmitter HD3 on Opposite Sideband vs. Transmitter

Attenuator Setting, LO = 5500 MHz, CW = −15 dBFS, Baseband Frequency =

10 MHz

Figure 224. Transmitter HD2 vs. Transmitter Attenuator Setting, Baseband

Frequency = 10 MHz, LO = 5500 MHz, CW = −15 dBFS

0

+110°C (HD2)

+25°C (HD2)

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–40°C (HD2)

+110°C (UPPER)

+25°C (UPPER)

–20

–40°C (UPPER)

–40

–60

–80

–100

–120

–100

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 225. Transmitter HD2 vs. Transmitter Attenuator Setting, Baseband

Frequency = 10 MHz, LO = 5900 MHz, CW = −15 dBFS

Figure 228. Transmitter HD3 on Opposite Sideband vs. Transmitter

Attenuator Setting, LO = 5900 MHz, CW = −15 dBFS, Baseband Frequency =

10 MHz

Rev. 0 | Page 60 of 95

Data Sheet

ADRV9008-2

0

–10

0.06

0.05

0.04

0.03

0.02

0.01

0

+110°C

+25°C

–40°C

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–20

–30

–40

–50

–60

–70

–80

–90

–0.01

–0.02

–0.03

–100

–110

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 229. Transmitter HD3 on Same Sideband as Signal vs. Transmitter

Attenuation Setting, LO = 5100 MHz, CW = −15 dBFS

Figure 232. Transmitter Attenuator Step Error vs. Transmitter Attenuator

Setting, LO = 5100 MHz

0

0.07

+110°C

+25°C

–40°C

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–10

–20

0.06

0.05

0.04

0.03

0.02

0.01

0

–30

–40

–50

–60

–70

–80

–90

–0.01

–0.02

–0.03

–100

–110

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 230. Transmitter HD3 on Same Sideband as Signal vs. Transmitter

Attenuator Setting, LO = 5500 MHz, CW = −15 dBFS

Figure 233. Transmitter Attenuator Step Error vs. Transmitter Attenuator

Setting, LO = 5500 MHz

0

0.09

+110°C

+25°C

–40°C

0.08

Tx1 = +110°C

Tx1 = +25°C

Tx1 = –40°C

Tx2 = +110°C

Tx2 = +25°C

Tx2 = –40°C

–10

–20

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

–30

–40

–50

–60

–70

–80

–0.01

–0.02

–0.03

–0.04

–0.05

–90

–100

–110

–120

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

TRANSMITTER ATTENUATOR SETTING (dB)

Figure 231. Transmitter HD3 on Same Sideband as Signal vs. Transmitter

Attenuator Setting, LO = 5900 MHz, CW = −15 dBFS

Figure 234. Transmitter Attenuator Step Error vs. Transmitter Attenuator

Setting, LO = 5900 MHz

Rev. 0 | Page 61 of 95

ADRV9008-2

Data Sheet

–30

–32

–34

–36

–38

–40

–42

–44

–46

–48

–50

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

+110°C

+25°C

–40°C

5000

5200

5400

5600

5800

6000

0

5

10

15

20

25

TRANSMITTER ATTENUATION (dBm)

LO FREQUENCY (MHz)

Figure 235. Transmitter EVM vs. Transmitter Attenuation, LTE = 20 MHz,

Signal Centered on DC, LO = 5100 MHz

Figure 238. Observation Receiver Path Loss vs. LO Frequency (Simulation),

Can be Used for De-Embedding Performance Data

–30

0

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

–32

–34

–36

–38

–40

–42

–44

–46

–48

–50

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

5

10

15

20

25

5200

5300

5400

5500

5600

5700

5800

5900

TRANSMITTER ATTENUATION (dBm)

LO FREQUENCY (MHz)

Figure 236. Transmitter EVM vs. Transmitter Attenuation, LTE = 20 MHz,

Signal Centered on DC, LO = 5500 MHz

Figure 239. Observation Receiver LO Leakage vs. LO Frequency, 5200 MHz,

5500 MHz, and 5900 MHz

–30

36

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

–32

–34

–36

–38

–40

–42

–44

–46

–48

–50

34

32

30

28

26

24

22

20

18

16

0

5

10

15

20

25

0

1

2

3

4

5

6

7

8

9

10

TRANSMITTER ATTENUATION (dBm)

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

Figure 237. Transmitter EVM vs. Transmitter Attenuation, LTE = 20 MHz,

Signal Centered on DC, LO = 5900 MHz

Figure 240. Observation Receiver Noise Figure vs. Observation Receiver

Attenuator Setting, LO = 5200 MHz, Total Nyquist Integration Bandwidth

Rev. 0 | Page 62 of 95

Data Sheet

ADRV9008-2

36

85

80

75

70

65

60

55

50

+110°C

+25°C

–40°C

34

32

30

28

26

24

22

20

18

16

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

0

1

2

3

4

5

6

7

8

9

10

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

OBSERVATION RECEIVER ATTENUATION (dB)

Figure 244. Observation Receiver IIP2, Sum and Difference Products vs.

Observation Receiver Attenuation, LO = 5700 MHz, Tone 1 = 5725 MHz,

Tone 2 = 5726 MHz at −19 dBm Plus Attenuation

Figure 241. Observation Receiver Noise Figure vs. Observation Receiver

Attenuator Setting, LO = 5500 MHz, Total Nyquist Integration Bandwidth

36

80

70

60

50

40

+110°C

+25°C

–40°C

34

32

30

28

26

24

22

20

18

16

30

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

20

10

0

1

2

3

4

5

6

7

8

9

10

5702 5702 5702 5702 5702 5702 5702 5702 5702 5702 5702 5702

5722 5742 5762 5782 5802 5822 5842 5862 5882 5902 5922 5942

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

INTERMODULATION FREQUENCY (MHz)

Figure 242. Observation Receiver Noise Figure vs. Observation Receiver

Attenuator Setting, LO = 5800 MHz, Total Nyquist Integration Bandwidth

Figure 245. Observation Receiver IIP2, f1 − f2 vs. Intermodulation Frequency,

LO = 5700 MHz, Tone 1 = 5702 MHz, Tone 2 Swept,

−19 dBm Each, Attenuation = 0 dB

80

75

70

65

60

80

75

70

65

55

60

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

50

55

45

IIP2 DIFF –40°C

40

50

5705 5725 5745 5765 5785 5805 5825 5845 5865 5885 5905 5925

5706 5726 5746 5766 5786 5806 5826 5846 5866 5886 5906 5926

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

f1 OFFSET FREQUENCY (MHz)

Figure 246. Observation Receiver IIP2, f1 – f2 vs. Observation Receiver

Attenuation, LO = 5700 MHz, Tone 1 = 5702 MHz, Tone 2 = 5802 MHz at

−19 dBm Plus Attenuation

Figure 243. Observation Receiver IIP2, Sum and Difference Products vs. f1 Offset

Frequency, Tones Separated by 1 MHz Swept Across Pass Band at −19 dBm Each,

LO = 5700 MHz, Attenuation = 0 dB

Rev. 0 | Page 63 of 95

ADRV9008-2

Data Sheet

25

30

28

26

24

22

20

18

16

14

12

10

8

20

15

10

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

5

6

0

2

4

6

8

10

5705 5758 5745 5765 5785 5805 5825 5845 5865 5885 5905 5925

5706 5726 5746 5766 5786 5806 5826 5846 5866 5886 5906 5926

OBSERVATION RECEIVER ATTENUATION (dB)

f1 OFFSET FREQUENCY (MHz)

Figure 250. Observation Receiver IIP3, 2f1 − f2 vs. Observation Receiver

Attenuation, LO = 5700 MHz, Tone 1 = 5702 MHz, Tone 2 = 5822 MHz at

−19 dBm Plus Attenuation

Figure 247. Observation Receiver IIP3, 2f1 − f2 vs. f1 Offset Frequency,

LO = 5700 MHz, Attenuation = 0 dB, Tones Separated by 1 MHz Swept Across

Pass Band at −19 dBm Each

0

30

28

26

24

22

20

18

16

+110°C = 10dB

+25°C = 10dB

–40°C = 10dB

+110°C = 0dB

+25°C = 0dB

–40°C = 0dB

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

IIP3 = +110°C

IIP3 = +25°C

IIP3 = –40°C

14

12

10

8

6

0

2

4

6

8

10

OBSERVATION RECEIVER ATTENUATION (dB)

BASEBAND FREQUENCY OFFSET ATTENUATION (MHz)

Figure 251. Observation Receiver Image Rejection vs. Baseband Frequency

Offset Attenuation, CW Signal Swept Across the Band, LO = 5200 MHz

Figure 248. Observation Receiver IIP3, 2f1 − f2 vs. Observation Receiver

Attenuation, LO = 5700 MHz, Tone 1 = 5745 MHz, Tone 2 = 5746 MHz at

−19 dBm Plus Attenuation

25

20

15

0

+110°C = 10dB

+25°C = 10dB

–40°C = 10dB

+110°C = 0dB

+25°C = 0dB

–40°C = 0dB

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10

ORx1 = +110°C

ORx1 = +25°C

ORx1 = –40°C

5

0

5702 5702 5702 5702 5702 5702 5702 5702 5702 5702 5702 5702

5722 5742 5762 5782 5802 5822 5842 5862 5882 5902 5922 5942

BASEBAND FREQUENCY OFFSET (MHz)

f1 OFFSET FREQUENCY (MHz)

Figure 252. Observation Receiver Image Rejection vs. Baseband Frequency

Offset, CW Signal Swept Across the Band, LO = 5700 MHz

Figure 249. Observation Receiver IIP3, 2f1 − f2 vs. f1 Offset Frequency,

LO = 5700 MHz, Tone 1 = 5702 MHz, Tone 2 = 5722 MHz at −22 dBm Plus

Attenuation Each

Rev. 0 | Page 64 of 95

Data Sheet

ADRV9008-2

18

16

14

12

10

8

0.5

0.4

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

6

4

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATION (dB)

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

Figure 253. Observation Receiver Gain vs. Observation Receiver Attenuation,

LO = 5200 MHz

Figure 256. Observation Receiver Gain Step Error vs. Observation Receiver

Attenuator Setting, LO = 5600 MHz

16

0.5

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.4

0.3

14

0.2

0.1

12

10

8

0

–0.1

–0.2

–0.3

–0.4

–0.5

6

4

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATION (dB)

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

Figure 254. Observation Receiver Gain vs. Observation Receiver Attenuation,

LO = 5700 MHz

Figure 257. Observation Receiver Gain Step Error vs. Observation Receiver

Attenuator Setting, LO = 5600 MHz

0.5

0.7

+110°C

+25°C

–40°C

0.6

0.5

+110°C

+25°C

–40°C

0.4

0.3

0.4

0.2

0.1

0.3

0.2

0

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

0

1

2

3

4

5

6

7

8

9

10

OBSERVATION RECEIVER ATTENUATOR SETTING (dB)

BASEBAND OFFSET FREQUENCY (MHz)

Figure 255. Observation Receiver Gain Step Error vs. Observation Receiver

Attenuator Setting, LO = 5200 MHz

Figure 258. Observation Receiver Pass Band Flatness vs. Baseband Offset

Frequency, LO = 5700 MHz

Rev. 0 | Page 65 of 95

ADRV9008-2

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

HD3 RIGHT dBc = +110°C

HD3 RIGHT dBc = +25°C

HD3 RIGHT dBc = –40°C

HD3 LEFT dBc = = +110°C

HD3 LEFT dBc = +25°C

HD3 LEFT dBc = –40°C

+110°C = 0dB (RIGHT)

+25°C = 0dB (LEFT)

+25°C = 10dB (LEFT)

–40°C = 0dB (RIGHT)

–40°C = 10dB (RIGHT)

–40°C = 0dB (LEFT)

–40°C = 10dB (LEFT)

+110°C = 10dB (RIGHT)

+110°C = 0dB (LEFT)

+110°C = 10dB (LEFT)

+25°C = 0dB (RIGHT)

+25°C = 10dB (RIGHT)

–20

–40

–60

–80

–100

–120

–100

–90.0

–67.5

–45.0

–22.5

22.5

45.0

67.5

90.0

–75

–50

–25

0

25

50

75

100

OFFSET FREQUENCY (MHz)

Figure 262. Observation Receiver HD3, Left and Right vs. Offset Frequency,

LO = 5700 MHz, Tone Level = −20 dBm

Figure 259. Observation Receiver HD2 vs. Offset Frequency, LO = 5200 MHz,

Tone Level = −20 dBm Plus Attenuation

0

+110°C = 0dB (RIGHT)

+110°C = 10dB (RIGHT)

+110°C = 0dB (LEFT)

+110°C = 10dB (LEFT)

+25°C = 0dB (RIGHT)

+25°C = 10dB (RIGHT)

+25°C = 0dB (LEFT)

+25°C = 10dB (LEFT)

–40°C = 0dB (RIGHT)

–40°C = 10dB (RIGHT)

–40°C = 0dB (LEFT)

–40°C = 10dB (LEFT)

TX1 TO ORX1

TX2 TO ORX1

TX1 TO ORX2

TX2 TO ORX2

10

–20

–40

20

30

40

50

60

70

80

90

–60

–80

–100

–120

–100

5000

5200

5400

5600

5800

6000

–75

–50

–25

0

25

50

75

100

LO FREQUENCY (MHz)

OFFSET FREQUENCY (MHz)

Figure 263. Transmitter to Observation Receiver Isolation vs. LO Frequency,

Temperature = 25°C

Figure 260. Observation Receiver HD2 vs. Offset Frequency, LO = 5700 MHz,

Tone Level = −20 dBm Plus Attenuation

–20

0

1: 100kHz, –99.0710dBc/Hz

HD3 RIGHT dBc = +110°C

–30

2: 1.2MHz, –119.6888dBc/Hz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

HD3 RIGHT dBc = +25°C

HD3 RIGHT dBc = –40°C

HD3 LEFT dBc = = +110°C

HD3 LEFT dBc = +25°C

HD3 LEFT dBc = –40°C

–40

–50

3: 10MHz, –135.4019dBc/Hz

START 2kHz

CENTER 9.001MHz

SPAN 17.998MHz

–60

–70

–80

–90

1

–100

–110

–120

–130

–140

–150

–160

–170

–180

2

3

–90.0

–67.5

–45.0

–22.5

22.5

45.0

67.5

90.0

100

1k

10k

100k

1M

10M

100M

OFFSET FREQUENCY (MHz)

FREQUENCY OFFSET (MHz)

Figure 264. LO Phase Noise vs. Frequency Offset, LO = 5900 MHz, PLL Loop

Bandwidth > 300 kHz, Spectrum Analyzer Limits Far Out Noise

Figure 261. Observation Receiver HD3, Left and Right vs. Offset Frequency,

LO = 5200 MHz, Tone Level = −20 dBm

Rev. 0 | Page 66 of 95

Data Sheet

ADRV9008-2

TRANSMITTER OUTPUT IMPEDANCE

TX PORT SIMULATED IMPEDANCE: SEDZ

M26

M21

FREQUENCY = 3.000GHz

S (1,1) = 0.368 / 150.626

FREQUENCY = 100.0MHz

S (1,1) = 0.143 / –7.865

IMPEDANCE = 66.439 – j2.654

M28

IMPEDANCE = 24.355 + j10.153

M27

M29

M22

FREQUENCY = 4.000GHz

S (1,1) = 0.484 / –107.379

IMPEDANCE = 25.118 + j30.329

FREQUENCY = 300.0MHz

S (1,1) = 0.141 / –25.589

IMPEDANCE = 64.063 – j7.987

M26

M28

M23

FREQUENCY = 5.000GHz

S (1,1) = 0.569 / 70.352

IMPEDANCE = 35.932 + j56.936

FREQUENCY = 500.0MHz

S (1,1) = 0.145 / –42.661

IMPEDANCE = 60.623 – j12.201

M21

M22

M23

M25

M24

M29

M24

FREQUENCY = 6.000GHz

S (1,1) = 0.614 / 36.074

IMPEDANCE = 81.032 + j94.014

FREQUENCY = 1.000GHz

S (1,1) = 0.164 / –84.046

IMPEDANCE = 49.000 – j16.447

M25

FREQUENCY = 2.000GHz

S (1,1) = 0.247 / 155.186

IMPEDANCE = 31.131 – j6.860

FREQUENCY (0Hz TO 6.000GHz)

Figure 265. Transmitter Output Impedance Series Equivalent Differential Impedance (SEDZ)

OBSERVATION RECEIVER INPUT IMPEDANCE

ORX PORT SIMULATED IMPEDANCE: SEDZ

M20

M15

FREQUENCY = 3.000GHz

S (1,1) = 0.104 / –66.720

IMPEDANCE = 53.262 – j10.292

FREQUENCY = 100.0MHz

S (1,1) = 0.391 / –1.848

IMPEDANCE = 114.099 – j3.397

M23

M22

M21

M16

FREQUENCY = 4.000GHz

S (1,1) = 0.116 / –104.276

IMPEDANCE = 46.060 + j10.522

FREQUENCY = 300.0MHz

S (1,1) = 0.389 / –5.601

IMPEDANCE = 112.639 – j10.091

M21

M22

M17

M15

M16

FREQUENCY = 5.000GHz

S (1,1) = 0.342 / 75.761

IMPEDANCE = 46.551 + j34.914

FREQUENCY = 500.0MHz

S (1,1) = 0.385 / –9.396

IMPEDANCE = 109.556 – j16.156

M17

M20

M18

M19

M23

M18

FREQUENCY = 6.000GHz

S (1,1) = 0.525 / 53.007

IMPEDANCE = 56.249 + j65.146

FREQUENCY = 1.000GHz

S (1,1) = 0.362 / –19.087

IMPEDANCE = 97.259 – j26.513

FREQUENCY = 2.000GHz

S (1,1) = 0.267 / –39.928

IMPEDANCE = 70.189 – j25.940

FREQUENCY (0Hz TO 6.000GHz)

Figure 266. Observation Receiver Input Impedance SEDZ

Rev. 0 | Page 67 of 95

ADRV9008-2

Data Sheet

TERMINOLOGY

Large Signal Bandwidth

Observation Bandwidth

Large signal bandwidth, otherwise known as instantaneous

bandwidth or signal bandwidth, is the bandwidth over which

there are large signals. For example, for Band 42 LTE, the large

signal bandwidth is 200 MHz.

Observation bandwidth is the 1 dB bandwidth of the observation

receiver. With the observation receiver sharing the transmitter

LO, the observation receiver sees similar power densities, such

as those in the occupied bandwidth and synthesis bandwidth of

the transmitter.

Occupied Bandwidth

Occupied bandwidth is the total bandwidth of the active signals.

For example, three 20 MHz carriers have a 60 MHz occupied

bandwidth, regardless of where the carriers are placed within

the large signal bandwidth.

Backoff

Backoff is the difference (in dB) between full scale and the rms

signal power.

P_HIGH

Synthesis Bandwidth

P_HIGHis the largest signal that can be applied without overloading

Synthesis bandwidth is the bandwidth over which digital

predistortion (DPD) linearization is transmitted. Synthesis

bandwidth is the 1 dB bandwidth of the transmitter. The power

density of the signal outside the occupied bandwidth is assumed

to be 25 dB below the signal in the occupied bandwidth, which

also assumes that the unlinearized power amplifier (PA)

achieves 25 dB ACLR.

the ADC for the observation receiver input. This input level

results in slightly less than full scale at the digital output because

of the nature of the continuous time Σ-Δ ADCs, which, for

example, exhibit a soft overload in contrast to the hard clipping

of pipeline ADCs.

Rev. 0 | Page 68 of 95

Data Sheet

ADRV9008-2

THEORY OF OPERATION

The ADRV9008-2 is a highly integrated RF transmitter

subsystem capable of configuration for a wide range of

applications. The device integrates all RF, mixed-signal, and

digital blocks necessary to provide all transmitter traffic and

DPD observation receiver functions in a single device.

Programmability allows the transmitter to be adapted for use in

many time division duplexes (TDDs) and 2G/3G/4G/5G cellular

standards. The ADRV9008-2 contains four high speed serial

interface links for the transmitter chain, and four high speed

links for the observation receiver chain. The links are

JESD204B, Subclass 1 compliant.

CLOCK INPUT

The ADRV9008-2 requires a differential clock connected to the

REF_CLK_IN_ pins. The frequency of the clock input must be

between 10 MHz and 1000 MHz and must have very low phase

noise because this signal generates the RF LO and internal

sampling clocks.

SYNTHESIZERS

RF PLL

The ADRV9008-2 contains a fractional-N PLL to generate the

RF LO for the signal paths. The PLL incorporates an internal

VCO and loop filter, requiring no external components. The

LOs on multiple chips can be phase synchronized to support

active antenna systems and beamforming applications.

The ADRV9008-2 also provides tracking correction of dc offset

QEC errors, and transmitter LO leakage to maintain high

performance under varying temperatures and input signal

conditions. The device also includes test modes that allow

system designers to debug designs during prototyping and to

optimize radio configurations.

Clock PLL

The ADRV9008-2 contains a PLL synthesizer that generates all

the baseband related clock signals and serialization/deserial-

ization (SERDES) clocks. This PLL is programmed based on the

data rate and sample rate requirements of the system.

TRANSMITTER

The ADRV9008-2 transmitter section consists of two identical

and independently controlled channels that provide all digital

processing, mixed-signal, and RF blocks necessary to implement a

direct conversion system while sharing a common frequency

synthesizer. The digital data from the JESD204B lanes pass through

a fully programmable, 128-tap FIR filter with variable interpolation

rates. The FIR output is sent to a series of interpolation filters

that provide additional filtering and interpolation prior to reaching

the DAC. Each 14-bit DAC has an adjustable sample rate.

SERIAL PERIPHERAL INTERFACE (SPI)

The ADRV9008-2 uses an SPI interface to communicate with

the baseband processor (BBP). This interface can be configured

as a 4-wire interface with dedicated receiver and transmitter

ports, or it can be configured as a 3-wire interface with a

bidirectional data communications port. This bus allows the

BBP to set all device control parameters using a simple address

data serial bus protocol.

When converted to baseband analog signals, the inphase (I) and

quadrature (Q) signals are filtered to remove sampling artifacts

and are fed to the upconversion mixers. Each transmitter chain

provides a wide attenuation adjustment range with fine

granularity to optimize SNR.

Write commands follow a 24-bit format. The first five bits set

the bus direction and the number of bytes to transfer. The next

11 bits set the address where data is written. The final 8 bits are

the data to be transferred to the specific register address.

Read commands follow a similar format with the exception that

the first 16 bits are transferred on the SDIO pin and the final

eight bits are read from the ADRV9008-2, either on the SDO

pin in 4-wire mode or on the SDIO pin in 3-wire mode.

OBSERVATION RECEIVER

The ADRV9008-2 contains an independent DPD observation

receiver front end. The observation receiver shares the common

frequency synthesizer with the transmitter.

JTAG BOUNDARY SCAN

The observation receiver is a direct conversion system that

contains a programmable attenuator stage, followed by matched

I and Q mixers, baseband filters, and ADCs.

The ADRV9008-2 provides support for JTAG boundary scan.

Five dual function pins are associated with the JTAG interface.

Use these pins, listed in Table 5, to access the on-chip test access

port. To enable the JTAG functionality, set the GPIO_3 pin

through the GPIO_0 pin to 1001, and then pull the TEST pin

high.

The continuous time Σ-Δ ADCs have inherent antialiasing that

reduces the RF filtering requirement.

The ADC outputs can be conditioned further by a series of

decimation filters and a programmable FIR filter with additional

decimation settings. The sample rate of each digital filter block

is adjustable by changing decimation factors to produce the

desired output data rate.

POWER SUPPLY SEQUENCE

The ADRV9008-2 requires a specific power-up sequence to

avoid undesired power-up currents. In the optimal power-up

sequence, the VDDD1P3_DIG and the VDDA1P3 supplies

(VDDA1P3 includes all 1.3 V domains) power up first and at the

same time. If these supplies cannot be powered up simultaneously,

the VDDD1P3_DIG supply must power up first. Power up the

Rev. 0 | Page 69 of 95

ADRV9008-2

Data Sheet

VDDA_3P3, VDDA1P8_BB, VDDA1P8_TX, VDDA1P3_DES,

and VDDA1P3_SER supplies after the 1.3 V supplies. The

VDD_INTERFACE supply can be powered up at any time. Note

that no device damage occurs if this sequence is not followed.

However, failure to follow this sequence may result in higher

than expected power-up currents. It is also recommended to

running. The SPI reads provide the last value latched at the ADC

output. The auxiliary ADC can also be multiplexed to a built in,

diode-based temperature sensor.

Auxiliary DAC x

The ADRV9008-2 contains 10 identical auxiliary DACs

(auxiliary DAC x) that can be used for bias or other system

functionality. The auxiliary DACs are 10 bits, have an output

voltage range of approximately 0.7 V to VDDA_3P3 − 0.3 V,

and have an output drive of 10 mA.

RESET

toggle the

signal after power stabilizes, prior to

configuration. The power-down sequence is not critical. If a

power-down sequence is followed, remove the VDDD1P3_DIG

supply last to avoid any back biasing of the digital control lines.

JESD204B DATA INTERFACE

GPIO_x PINS

The digital data interface for the ADRV9008-2 uses JEDEC

JESD204B Subclass 1. The serial interface operates at speeds of

up to 12.288 Gbps. The benefits of the JESD204B interface

include a reduction in required board area for data interface

routing, resulting in smaller total system size. Four high speed

serial lanes are provided for the transmitter, and four high speed

lanes are provided for the observation receiver. The

ADRV9008-2 supports single-lane or dual-lane interfaces as

well as fixed and floating point data formats for observation

receiver data.

The ADRV9008-2 provides 19, 1.8 V to 2.5 V GPIO signals that

can be configured for numerous functions. When configured as

outputs, certain pins can provide real-time signal information

to the BBP, allowing the BBP to determine observation receiver

performance. A pointer register selects the information that is

output to these pins. Signals used for manual gain mode,

calibration flags, state machine states, and various observation

receiver parameters are among the outputs that can be

monitored on these pins. Additionally, certain pins can be

configured as inputs and used for various functions, such as

setting the observation receiver gain in real time.

Table 6. Observation Path Interface Rates

JESD204B

Twelve 3.3 V GPIO_x pins are also included on the device.

These pins provide control signals to external components.

Bandwidth Output Rate

Lane Rate

(Mbps)

Number of

Lanes

(MHz)

(MSPS)

245.76

307.2

AUXILIARY CONVERTERS

AUXADC_x

200

9830.4

12288

9830.4

4915.2

1

2

4

The ADRV9008-2 contains an auxiliary ADC that is

multiplexed to four input pins (AUXADC_x). The auxiliary

ADC is 12 bits with an input voltage range of 0.05 V to

VDDA_3P3 − 0.05 V. When enabled, the auxiliary ADC is free

250

307.2

450

491.52

Table 7. Transmitter Interface Rates (Other Output Rates, Bandwidth, and JESD204B Lanes Also Supported)

Single-Channel Operation Dual-Channel Operation

JESD204B Lane JESD204B Number

Input Rate

(MSPS)

JESD204B Lane

Rate (Mbps)

JESD204B Number

of Lanes

Bandwidth (MHz)

Rate (Mbps)

of Lanes

200

250

450

245.76

307.2

9830.4

12288

9830.4

1

2

9830.4

12288

9830.4

2

4

491.52

TRANSMIT

HALF-BAND

FILTER 1

1, 2

TRANSMIT FIR

FILTER

(INTERPOLATION

1, 2, 4)

DIGITAL

GAIN

QUADRATURE

CORRECTION

HALF-BAND

FILTER 2

1, 2

I/Q DAC

JESD204B

Figure 267. Transmitter Datapath Filter Implementation

RECEIVE

HALF-BAND

3

RECEIVE

HALF-BAND

2

RECEIVE

HALF-BAND

1

DIG

GAIN

FIR

(DEC 1, 2, 4)

DC

JESD204B

ADC

CORRECTION

Figure 268. Observation Receiver Datapath Filter Implementation

Rev. 0 | Page 70 of 95

Data Sheet

ADRV9008-2

APPLICATIONS INFORMATION

PCB LAYOUT AND POWER SUPPLY

RECOMMENDATIONS

13 are crucial to maintaining the RF signal integrity and,

ultimately, the ADRV9008-2 performance. Layer 3 and Layer 12

are used to route power supply domains. To keep the RF section

of the ADRV9008-2 isolated from the fast transients of the digital

section, the JESD204B interface lines are routed on Layer 5 and

Layer 10. Those layers have impedance control set to a 100 Ω

differential. The remaining digital lines from the ADRV9008-2

are routed on Inner Layer 7 and Inner Layer 8. RF traces on the

outer layers must be a controlled impedance to get the best

performance from the device. The inner layers on this board

use 0.5 ounce copper or 1 ounce copper. The outer layers use

1.5 ounce copper so that the RF traces are less prone to pealing.

Ground planes on this board are full copper floods with no

splits except for vias, through-hole components, and isolation

structures. The ground planes must route entirely to the edge of

the PCB under the Surface-Mount Type A (SMA) connectors to

maintain signal launch integrity. Power planes can be pulled

back from the board edge to decrease the risk of shorting from

the board edge.

Overview

The ADRV9008-2 device is a highly integrated RF agile transceiver

with significant signal conditioning integrated on one chip. Due

to the increased complexity of the device and its high pin count,

careful PCB layout is important to get the optimal performance.

This data sheet provides a checklist of issues to look for and

guidelines on how to optimize the PCB to mitigate performance

issues. The goal of this data sheet is to help achieve the optimal

performance from the ADRV9008-2 while reducing board

layout effort. This data sheet assumes that the reader is an

experienced analog and RF engineer with an understanding of

RF PCB layout and RF transmission lines. This data sheet

discusses the following issues and provides guidelines for

system designers to achieve the optimal performance for the

ADRV9008-2:

•

PCB material and stack up selection

Fanout and trace space layout guidelines

Component placement and routing guidelines

RF and JESD204B transmission line layout

Isolation techniques used on the ADRV9008-2W/PCBZ

Power management considerations

Unused pin instructions

PCB MATERIAL AND STACKUP SELECTION

Figure 269 shows the PCB stackup used for the ADRV9008-

2W/PCBZ. Table 8 and Table 9 list the single-ended and

differential impedence for the stackup shown in Figure 269. The

dielectric material used on the top and the bottom layers is 8

mil Rogers 4350B. The remaining dielectric layers are FR4-370

HR. The board design uses the Rogers laminate for the top and

the bottom layers for the low loss tangent at high frequencies.

The ground planes under the Rogers laminate (Layer 2 and

Layer 13) are the reference planes for the transmission lines

routed on the outer surfaces. These layers are solid copper

planes without any splits under the RF traces. Layer 2 and Layer

Figure 269. ADRV9008-2W/PCBZ Trace Impedance and Stackup

Rev. 0 | Page 71 of 95

ADRV9008-2

Data Sheet

Table 8. Evaluation Board Single-Ended Impedance and Stackup¹

Finished

Trace Single-

Ended

Single-

Ended

Reference

Layers

Finished

Designed

Trace Single-

Calculated

Impedance

(Ω)

Board

Layer Copper % Copper (oz.) (oz.)

Starting

Copper

Single-Ended

Impedance

Ended (inches) (inches)

1

2

3

4

5

6

7

8

N/A

65

50

65

50

65

50

65

50

65

50

65

0.5

1

0.5

1

0.5

1

0.5

1

0.5

1

0.5

1.71

1

0.5

1

0.5

1

50 Ω 10ꢀ

N/A

50 Ω 10ꢀ

N/A

50 Ω 10ꢀ

N/A

50 Ω 10ꢀ

N/A

0.0155

N/A

0.0045

N/A

0.0049

N/A

0.0045

N/A

0.0135

N/A

0.0042

N/A

0.0039

N/A

0.0039

N/A

49.97

N/A

49.79

N/A

50.05

N/A

49.88

N/A

2

N/A

4, 6

N/A

6, 9

N/A

9, 11

N/A

13

9

10

11

12

13

14

1

1.64

N/A

50 Ω 10ꢀ

N/A

0.0155

N/A

0.0135

N/A

49.97

¹N/A means not applicable.

Table 9. Evaluation Board Differential Impedance and Stackup¹

Designed

Trace

(inches)

Designed Gap

Differential

(inches)

Finished

Trace

(inches)

Finished Gap

Differential

(inches)

Differential

Reference

Impedance (Ω) Layers

Differential

Layer Impedance

Calculated

1

100 Ω 10ꢀ

50 Ω 10ꢀ

N/A

0.008

0.0032

N/A

0.006

0.004

0.007

0.0304

N/A

0.007

0.0056

99.55

50.11

N/A

2

N/A

4, 6

N/A

6, 9

N/A

9, 11

N/A

13

3

4

5

6

7

8

9

10

N/A

100 Ω 10ꢀ

N/A

100 Ω 10ꢀ

N/A

100 Ω 10ꢀ

N/A

100 Ω 10ꢀ

50 Ω 10ꢀ

0.0036

N/A

0.0036

0.0038

N/A

0.0036

N/A

0.008

0.032

0.0064

0.0034

N/A

0.0034

N/A

0.003

N/A

0.007

0.004

0.0065

99.95

N/A

100.51

N/A

100.80

N/A

99.55

50.11

0.0064

0.0062

0.0066

0.0064

0.006

0.007

11

12

13

14

13

¹N/A means not applicable.

Rev. 0 | Page 72 of 95

Data Sheet

ADRV9008-2

The JESD204B interface signals are routed on two signal layers

that use impedance control (Layer 5 and Layer 10). The spacing

between the BGA pads is 17.5 mil. After the signal is on the

inner layers, a 3.6 mil trace (50 Ω) connects the JESD204B

signal to the field programmable gate array (FPGA) mezzanine

card (FMC) connector. The recommended BGA land pad size is

15 mil.

FANOUT AND TRACE SPACE GUIDELINES

The ADRV9008-2 device uses a 196-ball chip scale package ball

grid array (CSP_BGA), 12 × 12 mm package. The pitch between

the pins is 0.8 mm. This small pitch makes it impractical to route all

signals on a single layer. RF pins are placed on the outer edges of

the ADRV9008-2 package. The location of the pins helps route the

critical signals without a fanout via. Each digital signal is routed

from the BGA pad using a 4.5 mil trace. The trace is connected to

the BGA using a via in the pad structure. The signals are buried in

the inner layers of the board for routing to other parts of the

system.

Figure 270 shows the fanout scheme of the ADRV9008-2W/PCBZ.

As mentioned before, the ADRV9008-2W/PCBZ uses a via in

the pad technique. This routing approach can be used for the

ADRV9008-2 if there are no issues with manufacturing

capabilities.

4.5mil TRACE

AIR GAP = 17.5mil

JESD204B INTERFACE

TRACE WIDTH = 3.6mil

PAD SIZE = 15mil

VIA SIZE = 14mil

Figure 270. Trace Fanout Scheme on the ADRV9008-2W/PCBZ (PCB Layer Top and Layer 5 Enabled)

Rev. 0 | Page 73 of 95

ADRV9008-2

Data Sheet

The observation receiver and transmitter baluns and the

COMPONENT PLACEMENT AND ROUTING

GUIDELINES

matching circuits affect the overall RF performance of the

ADRV9008-2 transceiver. Make every effort to optimize the

component selection and placement to avoid performance

degradation. The RF Routing Guidelines section describes

proper matching circuit placement and routing in more detail.

Refer to the RF Port Interface Information section for more

information.

The ADRV9008-2 transceiver requires few external components

to function, but those that are used require careful placement

and routing to optimize performance. This section provides a

checklist for properly placing and routing critical signals and

components.

Signals with Highest Routing Priority

To achieve the desired level of isolation between RF signal

paths, use the technique described in the Isolation Techniques

Used on the ADRV9008-2W/PCBZ section in customer

designs.

RF lines and JESD204B interface signals are the signals that are

most critical and must be routed with the highest priority.

Figure 271 shows the general directions in which each of the

signals must be routed so that they can be properly isolated

from noisy signals.

In cases in which ADRV9008-2 is used, install a 10 µF capacitor

near the transmitter balun(s) VDDA1P8_TX dc feed(s) for RF

transmitter outputs. This acts as a reservoir for the transmitter

supply current. The Transmitter Balun DC Feed Supplies

section discusses more details about the transmitter output

power supply configuration.

VSSA

ORX2_IN+

VSSA

ORX2_IN–

VSSA

ORX1_IN+

VSSA

ORX1_IN–

VSSA

VDDA1P3_

RX_RF

VSSA

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

VDDA1P3_

RF_VCO_LDO RF_VCO_LDO

VDDA1P3_

AUX_VCO_

LDO

GPIO_3p3_0

GPIO_3p3_1

GPIO_3p3_2

VSSA

GPIO_3p3_3

GPIO_3p3_4

GPIO_3p3_5

VSSA

VDDA1P3_

RX_TX

VDDA1P1_

RF_VCO

VDDA1P3_

RF_LO

VSSA

VDDA_3P3

GPIO_3p3_9

GPIO_3p3_8

GPIO_3p3_7

VSSA

RBIAS

VSSA

GPIO_3p3_6

AUXADC_0

VSSA

TEST

VSSA

VDDA1P1_

AUX_VCO

VSSA

GPIO_3p3_10

GPIO_3p3_11

VSSA

VDDA1P8_BB VDDA1P3_BB

REF_CLK_IN+ REF_CLK_IN–

AUX_

SYNTH_OUT

AUXADC_3

AUXADC_2

VSSA

VDDA1P8_TX

AUXADC_1

VSSA

VDDA1P3_

CLOCK_

SYNTH

VDDA1P3_

RF_SYNTH

VDDA1P3_

AUX_SYNTH

VSSA

RF_SYNTH_

VTUNE

VSSA

TX2_OUT–

TX2_OUT+

VSSA

GPIO_2

GPIO_3

VSSD

VSSA

GPIO_1

GPIO_0

VSSA

SDIO

SCLK

VSSA

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

SERDIN1+

SERDIN3–

GPIO_11

GPIO_10

GPIO_9

VSSA

TX1_OUT+

TX1_OUT–

VSSA

GPIO_18

RESET

GP_

INTERRUPT

SDO

VSSA

SYSREF_IN+

SYNCIN1–

SYNCIN0–

SERDOUT3–

VSSA

SYSREF_IN–

SYNCIN1+

SYNCIN0+

SERDOUT3+

SERDOUT1–

GPIO_5

GPIO_6

GPIO_4

GPIO_7

CS

VSSA

VDDD1P3_

DIG

VDDD1P3_

DIG

VSSD

GPIO_8

SYNCOUT1–

SYNCOUT0–

SERDIN0+

SERDIN2–

SYNCOUT1+

SYNCOUT0+

VSSA

VDDA1P1_

VSSA

ORX1_

ENABLE

TX1_

ENABLE

ORX2_

ENABLE

TX2_

ENABLE

VSSA

GPIO_17

SERDIN1–

VSSA

VDD_

INTERFACE

CLOCK_VCO

VDDA1P3_

CLOCK_

VCO_ LDO

VSSA

SERDOUT2–

SERDOUT1+

SERDOUT2+

SERDOUT0–

VSSA

VDDA1P3_

SER

VDDA1P3_

DES

SERDIN0–

SERDIN3+

AUX_SYNTH_

VTUNE

VSSA

SERDOUT0+

VDDA1P3_

SER

VDDA1P3_

DES

SERDIN2+

Figure 271. RF Input/Output, REF_CLK_IN , and JESD204B Signal Routing Guidelines

Rev. 0 | Page 74 of 95

Data Sheet

ADRV9008-2

Figure 272 shows placement for ac coupling capacitors and a

100 Ω termination resistor near the ADRV9008-2 REF_CLK_IN

pins. Shield the traces with ground flooding that is surrounded

with vias staggered along the edge of the trace pair. The trace

pair creates a shielded channel that shields the reference clock

from any interference from other signals. Refer to the ADRV9008-

2W/PCBZ layout, including board support files included with the

evaluation board software, for exact details.

Routing Guidelines section outlines recommendations for

JESD204B interface routing. Provide appropriate isolation

between interface differential pairs. The Isolation Between

JESD204B Lines section provides guidelines for optimizing

isolation.

The RF_EXT_LO_I/O− pin (B7) and the RF_EXT_LO_I/O+

pin (B8) on the ADRV9008-2 are internally dc biased. If an

external LO is used, connect it via ac coupling capacitors.

Route the JESD204B interface at the beginning of the PCB

design and with the same priority as the RF signals. The RF

AC COUPLING

CAPS

100ΩTERMINATION

RESISTOR

TO ADRV9008-2

BGA BALLS

Figure 272. REF_CLK_IN Routing Recommendation

Rev. 0 | Page 75 of 95

ADRV9008-2

Data Sheet

Signals with Second Routing Priority

When the recommendation is to use a trace to connect power to

a particular domain, ensure that this trace is surrounded by

ground.

Power supply quality has direct impact on overall system

performance. To achieve optimal performance, users should

follow recommendations regarding ADRV9008-2 power supply

routing. The following recommendations outline how to route

different power domains that can be connected together

directly and that can be tied to the same supply, but are

separated by a 0 Ω placeholder resistor or ferrite bead (FB).

Figure 273 shows an example of such traces routed on the

ADRV9008-2W/PCBZ on Layer 12. Each trace is separated

from any other signal by the ground plane and vias. Separating

the traces from other signals is essential to providing necessary

isolation between the ADRV9008-2 power domains.

Figure 273. Layout Example of Power Supply Domains Routed with Ground Shielding (Layer 12 to Power)

Rev. 0 | Page 76 of 95

Data Sheet

ADRV9008-2

Each power supply pin requires a 0.1 µF bypass capacitor near

the pin at a minimum. Place the ground side of the bypass

capacitor so that ground currents flow away from other power

pins and the bypass capacitors.

capacitors are placed. The recommendation is to connect a

ferrite bead between a power plane and the ADRV9008-2 at a

distance away from the device The ferrite bead and the resevoir

capacitor provide stable voltage to the ADRV9008-2 during

operation by isolating the pin or pins that the network is connected

to from the power plane. Then, shield that trace with ground and

provide power to the power pins on the ADRV9008-2. Place a 100

nF capacitor near the power supply pin with the ground side of

the bypass capacitor placed so that ground currents flow away

from other power pins and the bypass capacitors.

For the domains shown in Figure 274, like the domains powered

through a 0 Ω placeholder resistor or ferrite bead, place the 0 Ω

placeholder resistors or ferrite beads further away from the

device. Space 0 Ω placeholder resistors or ferrite beads apart

from each other to ensure the electric fields on the ferrite beads

do not influence each other. Figure 275 shows an example of

how the ferrite beads, reservoir capacitors, and decoupling

TRACE THROUGH 0Ω RES. TO 1.3V ANALOG PLANE (AP)

MAINTAIN LOWEST POSSIBLE IMPEDANCE

TRACE THROUGH 0.1Ω RESISTOR TO AP

TRACE THROUGH 0Ω TO AP

VSSA

ORX2_IN+

VSSA

ORX2_IN–

VSSA

ORX1_IN+

ORX1_IN–

VSSA

TRACE THROUGH

VDDA1P3_

RX_RF

VSSA

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

VSSA

0Ω TO AP

TRACE THROUGH

TRACE THROUGH FB

TO 3.3V PLANE

VDDA1P3_

RF_VCO_LDO RF_VCO_LDO

VDDA1P3_

AUX_VCO_

LDO

0Ω TO AP

GPIO_3p3_0

GPIO_3p3_1

GPIO_3p3_2

VSSA

GPIO_3p3_3

GPIO_3p3_4

GPIO_3p3_5

VSSA

VDDA1P3_

RX_TX

VDDA1P1_

RF_VCO

VDDA1P3_

RF_LO

VSSA

VDDA_3P3

GPIO_3p3_9

GPIO_3p3_8

GPIO_3p3_7

VSSA

RBIAS

VSSA

GPIO_3p3_6

AUXADC_0

VSSA

TEST

VSSA

VDDA1P1_

AUX_VCO

VSSA

GPIO_3p3_10

GPIO_3p3_11

VSSA

TRACE THROUGH

0Ω TO 1.8V PLANE

TRACE THROUGH

0Ω TO 1.8V PLANE

VDDA1P8_BB VDDA1P3_BB

REF_CLK_IN+ REF_CLK_IN–

AUX_

SYNTH_OUT

AUXADC_3

AUXADC_2

VSSA

VDDA1P8_TX

TRACE THROUGH

AUXADC_1

VSSA

0Ω TO AP

TRACE THROUGH

0Ω TO AP

TRACE THROUGH

VDDA1P3_

CLOCK_

SYNTH

VDDA1P3_

RF_SYNTH

VDDA1P3_

AUX_SYNTH

0Ω TO AP

VSSA

RF_SYNTH_

VTUNE

VSSA

TRACE THROUGH

1Ω RESISTOR TO AP

TX2_OUT–

TX2_OUT+

VSSA

GPIO_2

GPIO_3

VSSD

VSSA

GPIO_1

GPIO_0

VSSA

SDIO

SCLK

VSSA

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

SERDIN1+

SERDIN3–

GPIO_11

GPIO_10

GPIO_9

VSSA

TX1_OUT+

TX1_OUT–

VSSA

GPIO_18

RESET

GP_

INTERRUPT

SDO

VSSA

SYSREF_IN+

SYNCIN1–

SYNCIN0–

SERDOUT3–

VSSA

SYSREF_IN–

SYNCIN1+

SYNCIN0+

SERDOUT3+

SERDOUT1–

GPIO_5

GPIO_6

GPIO_4

GPIO_7

CS

VSSA

WIDE TRACE TO

1.3V DIGITAL SUPPLY

HIGH CURRENT

VSSA

VDDD1P3_

DIG

VDDD1P3_

DIG

VSSD

GPIO_8

SYNCOUT1–

SYNCOUT0–

SERDIN0+

SERDIN2–

SYNCOUT1+

SYNCOUT0+

VSSA

TRACE THROUGH

FB TO INTERFACE SUPPLY

VDDA1P1_

VSSA

ORX1_

ENABLE

TX1_

ENABLE

ORX2_

ENABLE

TX2_

ENABLE

VSSA

GPIO_17

SERDIN1–

VSSA

VDD_

INTERFACE

CLOCK_VCO

TRACE THROUGH 0Ω

VDDA1P3_

CLOCK_

VCO_ LDO

TO 1.3V JESD204B SUPPLY

VSSA

SERDOUT2–

SERDOUT1+

SERDOUT2+

SERDOUT0–

VSSA

VDDA1P3_

SER

VDDA1P3_

DES

SERDIN0–

SERDIN3+

TRACE THROUGH

0Ω TO AP

AUX_SYNTH_

VTUNE

VSSA

SERDOUT0+

VDDA1P3_

SER

VDDA1P3_

DES

SERDIN2+

TRACE THROUGH FB

TO 1.3V JESD204B SUPPLY

Figure 274. Power Supply Domains Interconnection Guidelines

Rev. 0 | Page 77 of 95

ADRV9008-2

Data Sheet

0Ω RESISTOR

PLACEHOLDERS

FOR FERRITE BEADS

RESERVOIR

CAPACITORS

DUT

1µ + 100nF bypass

CAPS ORIENTED SUCH

THAT CURRENTS FLOW

AWAY FROM OTHER

POWER PINS

0Ω RESISTOR

PLACEHOLDERS

FOR FERRITE BEADS

Figure 275. Placement Example of 0 Ω Resistor Placeholders for Ferrite Beads, Reservoir and Bypass Capacitors on the ADRV9008-2W/PCBZ (Layer 12 to Power Layer

and Bottom Layer)

Rev. 0 | Page 78 of 95

Data Sheet

ADRV9008-2

Signals with Lowest Routing Priority

When routing analog signals such as GPIO_3p3_x/Auxiliary

DAC x or AUXADC_x, it is recommended to route them away

from the digital section (Row H through Row P). Do not cross

the analog section of the ADRV9008-2 highlighted by a red-

dotted line in Figure 276 by any digital signal routing.

As a last step while designing the PCB layout, route signals

shown in Figure 276. The following list outlines the

recommended order of signal routing:

1. Use ceramic 1 µF bypass capacitors at the VDDA1P1_RF_

VCO, VDDA1P1_AUX_VCO, and VDDA1P1_CLOCK_

VCO pins. Place them as close as possible to the ADRV9008-2

device with the ground side of the bypass capacitor placed so

that ground currents flow away from other power pins and the

bypass capacitors, if at all possible.

When routing digital signals from rows H and below, it is

important to route them away from the analog section (Row A

through Row G). Do not cross the analog section of the

ADRV9008-2 highlighted by a red-dotted line in Figure 276 by

any digital signal routing.

2. Connect a 14.3 kΩ resistor to the RBIAS pin (C14). This

resistor must have a 1% tolerance.

RF AND JESD204B TRANSMISSION LINE LAYOUT

RF Routing Guidelines

3. Pull the TEST pin (J6) to ground for normal operation.

The device has support for JTAG boundary scan, and this

pin is used to access that function. Refer to the JTAG

Boundary Scan section for JTAG boundary scan

information.

The ADRV9008-2W/PCBZ use microstrip type lines for

observation receiver and transmitter RF traces. In general,

Analog Devices, Inc. does not recommend using vias to route

RF traces unless a direct line route is not possible.

RESET

4. Pull the

pin (J4) high with a 10 kΩ resistor to

VDD_INTERFACE for normal operation. To reset the

RESET

device, drive the

pin low.

ORX2_IN+

VSSA

ORX2_IN–

VSSA

ORX1_IN+

VSSA

ORX1_IN–

VSSA

1µF CAPACITOR

VDDA1P3_

RX_RF

VSSA

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

VDDA1P3_

RF_VCO_LDO RF_VCO_LDO

VDDA1P3_

AUX_VCO_

LDO

GPIO_3p3_0

GPIO_3p3_1

GPIO_3p3_2

VSSA

GPIO_3p3_3

GPIO_3p3_4

VDDA1P3_

RX_TX

VDDA1P1_

RF_VCO

VDDA1P3_

RF_LO

VSSA

VDDA_3P3

GPIO_3p3_9

GPIO_3p3_8

GPIO_3p3_7

VSSA

RBIAS

14.3kΩ RESISTOR

VSSA

TEST

VSSA

VDDA1P1_

AUX_VCO

VSSA

GPIO_3p3_10

GPIO_3p3_11

VSSA

GPIO_3p3_5

GPIO_3p3_6

AUXADC_0

VSSA

VDDA1P8_BB VDDA1P3_BB

REF_CLK_IN+ REF_CLK_IN–

AUX_

SYNTH_OUT

AUXADC_3

AUXADC_2

VSSA

VDDA1P8_TX

VSSA

AUXADC_1

VSSA

VDDA1P3_

CLOCK_

SYNTH

VDDA1P3_

RF_SYNTH

VDDA1P3_

AUX_SYNTH

VSSA

RF_SYNTH_

VTUNE

VSSA

ALL DIGITAL

GPIO SIGNALS

ROUTED BELOW

THE RED LINE

TX2_OUT–

TX2_OUT+

VSSA

GPIO_2

GPIO_3

VSSD

VSSA

GPIO_1

GPIO_0

VSSA

SDIO

SCLK

VSSA

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

SERDIN1+

SERDIN3–

GPIO_11

GPIO_10

GPIO_9

VSSA

TX1_OUT+

TX1_OUT–

VSSA

GPIO_18

RESET

GP_

INTERRUPT

SDO

VSSA

SYSREF_IN+

SYNCIN1–

SYNCIN0–

SERDOUT3–

VSSA

SYSREF_IN–

SYNCIN1+

SYNCIN0+

SERDOUT3+

SERDOUT1–

GPIO_5

GPIO_6

GPIO_4

GPIO_7

CS

VSSA

VDDD1P3_

DIG

VDDD1P3_

DIG

VSSD

GPIO_8

SYNCOUT1–

SYNCOUT0–

SERDIN0+

SERDIN2–

SYNCOUT1+

SYNCOUT0+

VSSA

VDDA1P1_

VSSA

ORX1_

ENABLE

TX1_

ENABLE

ORX2_

ENABLE

TX2_

ENABLE

VSSA

GPIO_17

SERDIN1–

VSSA

VDD_

INTERFACE

1µF CAPACITOR

CLOCK_VCO

VDDA1P3_

CLOCK_

VCO_ LDO

VSSA

SERDOUT2–

SERDOUT1+

SERDOUT2+

SERDOUT0–

VSSA

VDDA1P3_

SER

VDDA1P3_

DES

SERDIN0–

SERDIN3+

AUX_SYNTH_

VTUNE

VSSA

SERDOUT0+

VDDA1P3_

SER

VDDA1P3_

DES

SERDIN2+

Figure 276. Auxiliary ADC, Analog, and Digital GPIO Signals Routing Guidelines

Rev. 0 | Page 79 of 95

ADRV9008-2

Data Sheet

Differential lines from the balun to the observation receiver and

transmitter pins need to be as short as possible. Make the length

of the single-ended transmission line also short to minimize the

effects of parasitic coupling. It is important to note that these

traces are the most critical when optimizing performance and

are, therefore, routed before any other routing. These traces

have the highest priority if trade-offs are needed.

Figure 277 and Figure 278 show pi matching networks on the

single-ended side of the baluns. The observation receiver front

end is dc biased internally, so the differential side of the balun

is ac-coupled. The system designer can optimize the RF

performance with a proper selection of the balun, matching

components, and ac coupling capacitors. The external LO

traces and the REF_CLK_IN traces may require matching

components as well to ensure optimal performance.

All the RF signals mentioned previously must have a solid ground

reference under each trace. Do not run any of the critical traces

over a section of the reference plane that is discontinuous. The

ground flood on the reference layer must extend all the way to

the edge of the board. This flood length ensures signal integrity

for the SMA launch when an edge launch connector is used.

Refer to the RF Port Interface Information section for more

information on RF matching recommendations for the device.

Figure 277. Pi Network Matching Components Available on Transmitter

Outputs

Figure 278. Pi Network Matching Components Available on Observation Receiver Inputs

Rev. 0 | Page 80 of 95

Data Sheet

ADRV9008-2

Transmitter Balun DC Feed Supplies

conducting the current necessary for the transmitter outputs to

operate. To reduce switching transients when attenuation

settings change, power the balun dc feed or transmitter output

chokes directly by the 1.8 V plane. Design the geometry of the

1.8 V plane so that each balun supply or each set of two chokes

is isolated from the other. This geometry can affect tansmitter to

transmitter isolation. Figure 279 shows the layout configuration

used on the ADRV9008-2W/PCBZ.

Each transmitter requires approximately 200 mA supplied

through an external connection. On the ADRV9008-2 and

ADRV9009 evaluation boards, bias voltages are supplied at the

dc feed of the baluns. Layout of both boards allows the use of

external chokes to provide a 1.8 V power domain to the

ADRV9008-2 outputs. This configuration is useful in scenarios

where a balun used at the transmitter output is not capable of

Tx OUTPUT / BALUN

1.8V SUPPLY FEED

Figure 279. Transmitter Power Supply Planes (VDDA1P8_TX) on the ADRV9008-2W/PCBZ

Rev. 0 | Page 81 of 95

ADRV9008-2

Data Sheet

Both the positive and negative transmitter pins must be biased

with 1.8 V. This biasing is accomplished on the evaluation board

through dc capacitors chokes and decoupling capacitors, as

shown in Figure 280. Match both chokes and their layout to

avoid potential current spikes. A difference in parameters

between both chokes can cause unwanted emission at transmitter

outputs. Place the decoupling capacitors that are near the

transmitter balun as close as possible to the dc feed of the balun

or the ground pin. Make orientation of the capacitor perpendicular

to the device so that the return current forms as small a loop as

possible with the ground pins surrounding the transmitter input.

A combination network of capacitors is used to provide a

wideband and low impedance ground path and helps to

eliminate transmitter spectrum spurs and dampens the

transients.

Routing Recommendations

Route the differential pairs on a single plane using a solid

ground plane as a reference on the layers above and/or below

these traces.

All JESD204B lane traces must be impedance controlled to achieve

50 Ω to ground. It is recommended that the differential pair be

coplanar and loosely coupled. An example of a typical

configuration is a 5 mil trace width and 15 mil edge to edge

spacing, with the trace width maximized as shown in Figure 281.

Match trace widths with pin and ball widths while maintaining

impedance control. If possible, use 1 oz. copper trace widths of

at least 8 mil (200 µm). The coupling capacitor pad size must

match JESD204B lane trace widths If trace width does not

match pad size, use a smooth transition between different

widths.

TX OUTPUT

The pad area for all connector and passive component choices

must be minimized due to a capacitive plate effect that leads to

problems with signal integrity.

DC FEED

CHOKES

Reference planes for impedance controlled signals must not be

segmented or broken for the entire length of a trace.

DECOUPLING

CAPACITORS

1.8V TX POWER

DOMAIN FEED

The REF_CLK_IN signal trace and the SYSREF signal trace

are impedance controlled for characteristic impedence (Z_O) =

50 Ω.

CONDUCTING

RESISTORS

BALUN

Stripline Transmission Lines vs. Microstrip Transmission

Lines

Stripline transmission lines have less singal loss and emit less

electromagnetic interference than microstrip transmission lines.

However, stripline transmission lines require the use of vias that

add line inductance, increasing the difficulty of controlling the

impedance.

BALUN

DECOUPLING

CAPACITORS

Microstrip transmission lines are easier to implement if the

component placement and density allow routing on the top

layer. Microstrip transmission lines make controlling the

impedance easier.

If the top layer of the PCB is used by other circuits or signals, or

if the advantages of stripline transmission lines are more

desirable over the advantages of microstrip transmission lines,

follow these recommendations:

Figure 280. Transmitter DC Chokes and Balun Feed Supply

•

Minimize the number of vias.

JESD204B Trace Routing Recommendations

Use blind vias where possible to eliminate via stub effects,

and use micro vias to minimize via inductance.

When using standard vias, use a maximum via length to

minimize the stub size. For example, on an 8-layer board,

use Layer 7 for the stripline pair.

The ADRV9008-2 transceiver uses the JESD204B, high speed

serial interface. To ensure optimal performance of this interface,

keep the differential traces as short as possible by placing the

ADRV9008-2 as close as possible to the FPGA or BBP, and

route the traces directly between the devices. Use a PCB

material with a low dielectric constant (< 4) to minimize loss.

For distances greater than 6 inches, use a premium PCB

material, such as RO4350B or RO4003C.

•

Place a pair of ground vias in close proximity to each via

pair to minimize the impedance discontinuity.

Route the JESD204B lines on the top side of the board as a

differential 100 Ω pair (microstrip). For the ADRV9008-

2W/PCBZ, the JESD204B differential signals are routed on

inner layers of the board (Layer 5 and Layer 10) as differential

Rev. 0 | Page 82 of 95

Data Sheet

ADRV9008-2

100 Ω pairs (stripline). To minimize potential coupling, these

signals are placed on an inner layer using a via embedded in the

component footprint pad where the ball connects to the PCB.

The ac coupling capacitors (100 nF) on these signals are placed

near the connector and away from the chip to minimize

coupling. The JESD204B interface can operate at frequencies of

up to 12 GHz. Ensure that signal integrity from the chip to the

connector is maintained.

To meet these isolation goals with significant margin, isolation

structures are introduced.

Figure 282 shows the isolation structures used on the ADRV9008-

2W/PCBZ. These structures consist of a combination of slots and

square apertures. These structures are present on every copper

layer of the PCB stack. The advantage of using square apertures

is that signals can be routed between the openings without

affecting the isolation benefits of the array of apertures. When

using these isolation structures, make sure to place ground vias

around the slots and apertures.

ISOLATION TECHNIQUES USED ON THE

ADRV9008-2W/PCBZ

Isolation Goals

Significant isolation challenges were overcome in designing the

ADRV9008-2W/PCBZ. The following isolation requirements are

used to accurately evaluate the ADRV9008-2 transceiver

performance:

•

Transmitter to transmitter, 75 dB out to 6 GHz

Transmitter to observation receiver, 65 dB out to 6 GHz

Tx

DIFF A

Tx

DIFF B

Tx DIFF A

Tx DIFF B

TIGHTLY COUPLED

DIFFERENTIAL Tx LINES

LOOSELY COUPLED

DIFFERENTIAL Tx LINES

Figure 281. Routing JESD204B, Differential A and Differential B Correspond to Differential Positive Signals or Negative Signals (One Differential Pair)

Figure 282. Isolation Structures on the ADRV9008-2W/PCBZ

Rev. 0 | Page 83 of 95

ADRV9008-2

Data Sheet

Figure 283. Current Steering Vias Placed Next to Isolation Structures

Figure 283 outlines the methodology used on the ADRV9008-

2W/PCBZ. When using slots, ground vias must be placed at the

ends of the slots and along the sides of the slots. When using

square apertures, at least one single ground via must be placed

adjacent to each square. These vias must be through-hole vias

from the top to the bottom layer. The function of these vias is to

steer return current to the ground planes near the apertures.

Isolation Between JESD204B Lines

The JESD204B interface uses eight line pairs that can operate at

speeds of up to 12 GHz. When configuring the PCB layout,

ensure these lines are routed according to the rules outlined in

the JESD204B Trace Routing Recommendations section. In

addition, use isolation techniques to prevent crosstalk between

different JESD204B lane pairs.

For accurate slot spacing and square apertures layout, use

simulation software when designing a PCB for the ADRV9008-2

transceiver. Spacing between square apertures must be no more

than 1/10 of a wavelength. Calculate the wavelength using

Equation 1:

Figure 284 shows a technique used on the ADRV9008-2W/PCBZ

that involves via fencing. Placing ground vias around each

JESD204B pair provides isolation and decreases crosstalk. The

spacing between vias is 1.2 mm.

Figure 284 shows the rule provided in Equation 1 JESD204B

lines are routed on Layer 5 and Layer 10 so that the lines use

stripline structures. The dielectric material used in the inner

layers of the ADRV9008-2W/PCBZ PCB is FR4-370HR.

300

(1)

Wavelength (m) =

Frequency (MHz) ×

E

R

where E_Ris the dielectric constant of the isolator material. For

RO4003C material, microstrip structure (+ air) E_R= 2.8. For FR4-

370HR material, stripline structure E_R= 4.1.

For accurate spacing of the JESD204B fencing vias, use layout

simulation software. Input the following data into Equation 1 to

calculate the wavelength and square aperture spacing:

For example, if the maximum RF signal frequency is 6 GHz,

and E_R= 2.8 for RO4003C material, microstrip structure (+ air),

the minimum wavelength is approximately 29.8 mm.

•

The maximum JESD204B signal frequency is

approximately 12 GHz.

•

For FR4-370HR material, stripline structure, E_R= 4.1, the

minimum wavelength is approximately 12.4 mm.

To follow the 1/10 wavelength spacing rule, square aperture

spacing must be 2.98 mm or less.

To follow the 1/10 wavelength spacing rule, spacing between

vias must be 1.24 mm or less. The minimum spacing

recommendation according to transmission line theory is 1/4

wavelength.

Rev. 0 | Page 84 of 95

Data Sheet

ADRV9008-2

1.24mm

Figure 284. Via Fencing Around JESD204B Lines, PCB Layer 10

RF Port Impedance Data

RF PORT INTERFACE INFORMATION

This section provides the port impedance data for all

transmitters and observation receivers in the ADRV9008-2

integrated transceiver. Please note the following:

This section details the RF transmitter and observation receiver

interfaces for optimal device performance. This section also

includes data for the anticipated ADRV9008-2 RF port

impedance values and examples of impedance matching

networks used in the evaluation platform. This section also

provides information on board layout techniques and balun

selection guidelines.

•

Z_Ois defined as 50 Ω.

The ADRV9008-2 ball pads are the reference plane for this

data.

•

Single-ended mode port impedance data is not available.

However, a rough assessment is possible by taking the

differential mode port impedance data and dividing both

the real and imaginary components by 2.

Contact Analog Devices applications engineering for the

impedance data in Touchstone format.

The ADRV9008-2 is a highly integrated transceiver with

transmit and observation (DPD) receive signal chains. External

impedance matching networks are required on transmitter and

observation receiver ports to achieve performance levels

indicated on the data sheet.

•

Analog Devices recommends the use of simulation tools in the

design and optimization of impedance matching networks. To

achieve the closest match between computer simulated results

and measured results, accurate models of the board

environment, surface-mount device (SMD) components

(including baluns and filters), and ADRV9008-2 port

impedances are required.

Rev. 0 | Page 85 of 95

ADRV9008-2

Data Sheet

1.0

2.0

0.5

m21

m26

FREQUENCY = 100MHz

M28

FREQUENCY = 3GHz

S(1,1) = 0.368/150.626

S(1,1) = 0.143/–7.865

IMPEDANCE = 66.439 – j2.654

M27

IMPEDANCE = 24.355 + j10.153

M29

0.2

m22

5.0

m27

FREQUENCY = 300MHz

S(1,1) = 0.141/–25.589

IMPEDANCE = 64.063 – j7.987

FREQUENCY = 4GHz

S(1,1) = 0.484/107.379

IMPEDANCE = 25.118 + j30.329

M26

m23

m28

FREQUENCY = 500MHz

S(1,1) = 0.145/–42.661

IMPEDANCE = 60.623 – j12.201

M21

M23

FREQUENCY = 5GHz

S(1,1) = 0.569/70.352

IMPEDANCE = 35.932 + j56.936

0

M22

M24

M25

m24

m29

FREQUENCY = 1GHz

S(1,1) = 0.164/–84.046

IMPEDANCE = 49.000 + j16.447

FREQUENCY = 6GHz

S(1,1) = 0.614/36.074

IMPEDANCE = 81.032 + j94.014

–0.2

–5.0

m25

FREQUENCY = 2GHz

S(1,1) = 0.247/–155.186

IMPEDANCE = 31.131 – j6.860

–0.5

–2.0

–1.0

FREQUENCY (0.000Hz TO 6.000Hz)

Figure 285. Transmitter 1 and Transmitter 2 SEDZ and Parallel Equivalent Differential Impedance (PEDZ) Data

1.0

2.0

0.5

m15

FREQUENCY = 100MHz

S(1,1) = 0.391/–1.848

IMPEDANCE = 114.099 – j3.397

m20

FREQUENCY = 3GHz

S(1,1) = 0.104/–66.720

IMPEDANCE = 53.262 – j10.292

0.2

M23

m16

5.0

FREQUENCY = 300MHz

S(1,1) = 0.389/–5.601

IMPEDANCE = 112.639 – j10.091

M22

M21

M20

m21

FREQUENCY = 4GHz

S(1,1) = 0.116/104.276

IMPEDANCE = 46.060 + j10.522

m17

FREQUENCY = 500MHz

S(1,1) = 0.385/–9.396

IMPEDANCE = 109.556 – j16.156

M15

M16

M17

M18

0

m22

M19

FREQUENCY = 5GHz

S(1,1) = 0.342/75.761

IMPEDANCE = 46.551 + j34.914

m18

FREQUENCY = 1GHz

S(1,1) = 0.362–19.087

IMPEDANCE = 97.259 – j26.513

m23

FREQUENCY = 6GHz

S(1,1) = 0.525/53.007

IMPEDANCE = 56.249 + j65.146

–0.2

–5.0

m19

FREQUENCY = 2GHz

S(1,1) = 0.267/–39.928

IMPEDANCE = 70.789 – j25.940

–0.5

–2.0

–1.0

FREQUENCY (0Hz TO 6GHz)

Figure 286. Observation Receiver 1 and Observation Receiver 2 SEDZ and PEDZ Data

Rev. 0 | Page 86 of 95

Data Sheet

ADRV9008-2

1.0

2.0

0.5

900

800

700

600

500

400

300

200

100

0

350

300

250

200

150

100

50

m1

FREQUENCY = 100MHz

S(1,1) = 0.018/–149.643

IMPEDANCE = 48.491 – j0.866

R_PEDZ

L_OR_C_PE

X_STATUS

M5

M6

0.2

m2

5.0

m7

FREQUENCY = 750MHz

S(1,1) = 0.074/–123.043

IMPEDANCE = 45.753 – j5.744

FREQUENCY = 5GHz

L_OR_C_PE = 1.336

m8

FREQUENCY = 5GHz

R_PEDZ = 31.172

m9

FREQUENCY = 5GHz

X_STATUS = 1

m3

M4

FREQUENCY = 1.5GHz

S(1,1) = 0.147/–138.745

IMPEDANCE = 39.362 – j7.804

M1

0

M2

M3

m4

FREQUENCY = 3GHz

S(1,1) = 0.292/–175.424

IMPEDANCE = 27.426 – j1.397

–0.2

–5.0

m5

FREQUENCY = 6GHz

S(1,1) = 0.538/123.271

IMPEDANCE = 18.885 – j23.935

m6

FREQUENCY = 12GHz

S(1,1) = 0.757/46.679

IMPEDANCE = 40.002 – j103.036

0

–0.5

–2.0

0

2

4

6

8

10

12

FREQUENCY (GHz)

–1.0

FREQUENCY (100MHz TO 12GHz)

Figure 287. RF_EXT_LO_I/O SEDZ and PEDZ Data

1.0

2.0

0.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

13E+5

1.2E+5

1.1E+5

1.0E+5

9.0E+4

8.0E+4

7.0E+4

6.0E+4

5.0E+4

4.0E+4

m1

FREQUENCY = 100MHz

S(1,1) = 0.999/–1.396

IMPEDANCE = 159.977 – j4.099E3

R_PEDZ

L_OR_C_PE

X_STATUS

0.2

m2

5.0

m7

FREQUENCY = 250MHz

S(1,1) = 0.999/–3.480

IMPEDANCE = 30.567 – j1.645E3

FREQUENCY = 1GHz

L_OR_C_PE = 0.389

m8

FREQUENCY = 1GHz

R_PEDZ = 4.761E4

m9

FREQUENCY = 1GHz

X_STATUS = 0

m3

FREQUENCY = 500MHz

M1

0

S(1,1) = 0.999/–6.952

M2

M3

M4

M5

IMPEDANCE = 9.723 – j823.070

m4

FREQUENCY = 750MHz

S(1,1) = 0.998/–10.431

IMPEDANCE = 5.273 – j547.733

–0.2

–5.0

m5

FREQUENCY = 1GHz

S(1,1) = 0.999/–13.925

IMPEDANCE = 3.521 – j409.400

–0.5

–2.0

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

FREQUENCY (GHz)

–1.0

FREQUENCY (0.000Hz TO 1.100GHz)

Figure 288. REF_CLK_IN SEDZ and PEDZ Data, On Average, the Real Part of the Parallel Equivalent Differential Impedance (R_P) = ~ 70 kΩ

Rev. 0 | Page 87 of 95

ADRV9008-2

Data Sheet

For the highest accuracy, electromagnetic momentum (EM)

modelling result of the PCB artwork, S11, S22, and S21 of the

matching components and balun must be used in the

simulations.

Advanced Design System (ADS) Setup Using the

DataAccessComponent and SEDZ File

Analog Devices supplies the port impedance as an .s1p file that

can be downloaded from the ADRV9008-2 product page. This

format allows simple interfacing to the ADS by using the

DataAccessComponent. In Figure 289, Term 1 is the single-

ended input or output, and Term 2 is the differential input or

output RF port on the device. The pi on the single-ended side

and the differential pi configuration on the differential side

allow maximum flexibility in designing matching circuits. The

pi configuration is suggested for all design layouts because the

pi configuration can step the impedance up or down as needed

with appropriate component population.

Transmitter Bias and Port Interface

This section considers the dc biasing of the ADRV9008-2

transmitter outputs and how to interface to each transmitter

port. The ADRV9008-2 transmitters operate over a range of

frequencies. At full output power, each differential output side

draws approximately 100 mA of dc bias current. The transmitter

outputs are dc biased to a 1.8 V supply voltage using either RF

chokes (wire wound inductors) or a transformer center tap

connection.

The mechanics of setting up a simulation for impedance

measurement and impedance matching is as follows:

Careful design of the dc bias network is required to ensure

optimal RF performance levels. When designing the dc bias

network, select components with low dc resistance to minimize

the voltage drop across the series parasitic resistance element

with either of the suggested dc bias schemes suggested in

Figure 290. The R_DCRresistors indicate the parasitic elements. As

the impedance of the parasitics increases, the voltage drop (ΔV)

across the parasitic element increases, which causes the transmitter

RF performance (P_O,1dB, P_O,MAX, and so on) to degrade. The

choke inductance (L_C) must be at least 3× times higher than the

load impedance at the lowest desired frequency so that it does

not degrade the output power (see Table 10).

1. The DataAccessComponent block reads the RF port .s1p

file. This file is the device RF port reflection coefficient.

2. The two equations convert the RF port reflection coefficient

to a complex impedance. The result is the RX_SEDZ

variable.

3. The RF port calculated complex impedance (RX_SEDZ) is

used to define the Term 2 impedance.

4. Term 2 is used in a differential mode, and Term 1 is used in

a single-ended mode.

5. Setting up the simulation this way allows one to measure

the input reflection (S11), output reflection (S22), and

through reflection (S21) of the three-port system without

complex math operations within the display page.

Figure 289. Simulation Setup in ADS with SEDZ .s1p Files and DataAccessComponent

Table 10. Sample Wire Wound DC Bias Choke Resistance vs. Size vs. Inductance

Inductance (nH)

Resistance (Size: 0603) (Ω)

Resistance (Size: 1206) (Ω)

100

200

300

400

500

600

0.10

0.15

0.16

0.28

0.45

0.52

0.08

0.10

0.12

0.14

0.15

0.20

Rev. 0 | Page 88 of 95

Data Sheet

ADRV9008-2

The recommended dc bias network is shown in Figure 291. This

network has fewer parasitics and fewer total components.

TX1_OUT+/

TX2_OUT+

I

= ~100mA

– ΔV +

BIAS

R

1.8V

DCR

Figure 292 through Figure 295 identify four basic differential

transmitter output configurations. Except in cases in which

impedance is already matched, impedence matching networks

(balun single-ended port) are required to achieve optimum

device performance. In applications in which the transmitter is

not connected to another circuit that requires or can tolerate dc

bias on the transmitter outputs, the transmitter outputs must be

ac-coupled because of the dc bias voltage applied to the

differential output lines of the transmitter.

Tx1 OR Tx2

OUTPUT

STAGE

R

I

DCR

C

BIAS

B

TX1_OUT–/

TX2_OUT–

– ΔV +

Figure 291. RF DC Bias Configurations Showing Parasitic Losses Due to

Center Tapped Transformers

TX1_OUT+/

TX2_OUT+

1.8V

Tx1 OR Tx2

OUTPUT

STAGE

The recommended RF transmitter interface is shown in Figure 290

to Figure 295, featuring a center tapped balun. This configuration

offers the lowest component count of the options presented.

C

B

TX1_OUT–/

TX2_OUT–

Descriptions of the transmitter port interface schemes are as

follows:

Figure 292. RF Transmitter Interface Configurations

1.8V

•

In Figure 292, the center tapped transformer passes the

bias voltage directly to the transmitter outputs.

In Figure 293, RF chokes bias the differential transmitter

output lines. Additional coupling capacitors (C_C) are added

in the creation of a transmission line balun.

C

L

B

C

TX1_OUT+/

TX2_OUT+

C

1.8V

•

Tx1 OR Tx2

OUTPUT

STAGE

C

TX1_OUT–/

TX2_OUT–

•

In Figure 294, RF chokes are used to bias the differential

transmitter output lines and connect to a transformer.

In Figure 295, RF chokes bias the differential output lines

that are ac-coupled to the input of a driver amplifier.

Figure 293. RF Transmitter Interface Configurations

1.8V

C

L

B

If a transmitter balun that requires a set of external dc bias chokes is

selected, careful planning is required. It is necessary to find the

optimum compromise between the choke physical size, choke

dc resistance, and the balun low frequency insertion loss. In

commercially available dc bias chokes, resistance decreases as size

increases. As choke inductance increases, resistance increases. It is

undesirable to use physically small chokes with high inductance

because small chokes exhibit the greatest resistance. For example,

the voltage drop of a 500 nH, 0603 choke at 100 mA is roughly

50 m V.

C

TX1_OUT+/

TX2_OUT+

1.8V

Tx1 OR Tx2

OUTPUT

STAGE

TX1_OUT–/

TX2_OUT–

Figure 294. RF Transmitter Interface Configurations

1.8V

C

L

B

C

V

= 1.8V

DC

TX1_OUT+/

TX2_OUT+

C

1.8V

C

L

C

Tx1 OR Tx2

OUTPUT

STAGE

L

B

DRIVER

AMPLIFIER

C

–

R

–

R

C

DCR

TX1_OUT–/

TX2_OUT–

TX1_OUT+/

TX2_OUT+

ΔV

+

ΔV

+

I

= ~100mA

BIAS

V

= 1.8 – ΔV

Tx1 OR Tx2

OUTPUT

STAGE

BIAS

Figure 295. RF Transmitter Interface Configurations

1.8V

TX1_OUT–/

TX2_OUT–

I

= ~100mA

BIAS

Figure 290. RF DC Bias Configurations Showing Parasitic Losses Due to Wire

Wound Chokes

Rev. 0 | Page 89 of 95

ADRV9008-2

Data Sheet

ORX1_IN–

ORX1_IN+

General Observation Receiver Path Interface

OBSERVATION

RECEIVER

INPUT

The ADRV9008-2 has two observation, or DPD, receivers

(Observation Receiver 1 and Observation Receiver 2). The

observation receivers can support up to 450 MHz bandwidth. The

observation receiver channels are designed for differential use.

STAGE

(MIXER OR LNA)

Figure 296. Differential Observation Receiver Interface Using a Transformer

The ADRV9008-2 differential signals of the observation receivers

interface to an integrated mixer. The mixer input pins have a dc

bias of approximately 0.7 V and may need to be ac-coupled,

depending on the common-mode voltage level of the external

circuit.

C

ORX1_IN–

OBSERVATION

RECEIVER

INPUT

STAGE

C

(MIXER OR LNA)

C

ORX1_IN+

Important considerations for the observation receiver port

interface are as follows:

Figure 297. Differential Observation Receiver Interface Using a Transmission

Line Balun

Impedance Matching Network Example

•

The device to be interfaced (filter, balun, transmit/receive

(T/R) switch, external low noise amplifier (LNA), external

PA, and so on).

The observation receiver maximum safe input power is

23 dBm (peak).

The observation receiver optimum dc bias voltage is 0.7 V

bias to ground.

The board design (reference planes, transmission lines,

impedance matching, and so on).

Impedance matching networks are required to achieve the

ADRV9008-2 data sheet performance levels. This section

provides a description of matching network topologies and

components used on the ADRV9008-2W/PCBZ.

•

Device models, board models, and balun and SMD component

models are required to build an accurate system level

simulation. The board layout model can be obtained from an

EM simulator. The balun and SMD component models can be

obtained from the device vendors or built locally. Contact

Analog Devices applications engineering for ADRV9008-2

modeling details.

Figure 296 and Figure 297 show possible differential

observation receiver port interface circuits. The options in

Figure 296 and Figure 297 are valid for all observation receiver

inputs operating in differential mode, although only the

Observation Receiver 1 signal names are indicated. Impedance

matching may be necessary to obtain the performance levels.

The impedance matching network provided in this section is

not evaluated in terms of mean time to failure (MTTF) in high

volume production. Consult with component vendors for long-

term reliability concerns. Consult with balun vendors to

determine appropriate conditions for dc biasing.

Given wide RF bandwidth applications, SMD balun devices

function well. Decent loss and differential balance are available

in a relatively small (0603, 0805) package.

Figure 299 and Figure 300 show that in a generic port impedance

matching network, the shunt or series elements may be a resistor,

inductor, or capacitor.

Rev. 0 | Page 90 of 95

Data Sheet

ADRV9008-2

ORX+

ORX IN

ORX–

Figure 298. Impedance Matching Topology

Rev. 0 | Page 91 of 95

ADRV9008-2

Data Sheet

RF OUTPUT 1

C307

VDCA1P8_TX

0.1µF

AGND

C323

DNI

L323

DNI

L307

43nH

AGND

R307

TX1_OUT+

TX1_BAL+

T302

TCM1-83X+

0Ω

J303

1

C337

18pF

R309

5

4

3

2

C339

DNI

C338

DNI

RFO_1

0Ω

C312

DNI

C314

DNI

5

4 3 2

R308

TX1_OUT–

TX1_BAL–

AGND

0Ω

NC

1

6

AGND

L308

43nH

C325

DNI

C344

L325

DNI

51pF

C345

AGND

C308

0.1µF

VDCA1P8_TX

75pF

C346

AGND

10pF

C347

27pF

AGND

RF OUTPUT 2

C315

VDDA1P8_TX

0.1µF

AGND

C327

DNI

L327

DNI

L315

43nH

AGND

R310

TX2_OUT+

TX2_BAL+

T303

TCM1-83X+

0Ω

J304

C336

18pF

R312

5

4

3

2

1

C342

DNI

C341

DNI

RFO_2

0Ω

C320

DNI

C322

DNI

5

4 3 2

R311

TX2_OUT–

TX2_BAL–

AGND

0Ω

NC

1

6

AGND

L316

43nH

C329

DNI

C348

L329

DNI

10pF

C349

AGND

C316

0.1µF

VDDA1P8_TX

27pF

C350

AGND

51pF

C351

75pF

AGND

Figure 299. Transmitter 1 and Transmitter 2 Generic Matching Network Topology

Rev. 0 | Page 92 of 95

Data Sheet

ADRV9008-2

T205

TCM1-83X+

ORX1

J203

1

C250

18pF

ORX1_UNBAL

ORX1_IN–

ORX1_BAL–

R219

R216

3

2

5

4

0Ω

2

3 4 5

C215

DNI

C217

DNI

C218

DNI

C221

DNI

NC

AGND

6

1

ORX1_IN+

R220

AGND

ORX1_BAL+

C244

10pF

DNI

C245

27pF

0Ω

AGND

ORX2

T207

TCM1-83X+

J204

C251

18pF

ORX2_UNBAL

ORX2_IN–

R223

0Ω

R226

ORX2_BAL–

3

2

5

1

4

0Ω

2

3

4

5

C222

DNI

C224

DNI

C228

DNI

C225

DNI

NC

1

AGND

6

AGND

ORX2_IN+

R227

C247

27pF

ORX2_BAL+

C246

10pF

0Ω

DNI

AGND

Figure 300. Observation Receiver 1 and Observation Receiver 2 Generic Matching Network Topology

Rev. 0 | Page 93 of 95

ADRV9008-2

Data Sheet

Table 11 and Table 12 show the selected balun and component

values used for the matching network sets. Refer to the

ADRV9008-2 schematics for a wideband matching example that

operates across the entire device frequency range with

somewhat reduced performance.

The RF matching used in the ADRV9008-2W/PCBZ allows the

ADRV9008-2 to operate across the entire chip frequency range

with slightly reduced performance.

Table 11. Observation Receiver 1 and Observation Receiver 2 Evaluation Board Matching Components for Frequency Band 75 MHz

to 6000 MHz

Component

Value

C215, C22

Do not install (DNI)

R216, R223

0 Ω

C217, C224

DNI

C250, C251

18 pF

C218, C225

DNI

R219/R220, R226/R227

C221, C228

0 Ω

DNI

T205, T207

Mini circuits TCM1-83X+

Table 12. Transmitter 1 and Transmitter 2 Evaluation Board Matching Components¹for Frequency Band 75 MHz to 6000 MHz

Component

Value

C314, C322

DNI

R309, R312

0 Ω

C312, C320

DNI

C337, C336

18 pF

C338, C342

DNI

R307/R308, R310/R311

C339, C341

0 Ω

DNI

T302, T303

Mini circuits TCM1-83X+

¹These matches provide VDDA1P8_TX to the TXx_OUT pins through the balun.

Rev. 0 | Page 94 of 95

Data Sheet

ADRV9008-2

OUTLINE DIMENSIONS

12.10

12.00 SQ

11.90

A1 BALL

PAD CORNER

A1 BALL

CORNER

14 13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

PIN A1

INDICATOR

10.40 SQ

7.755 REF

K

L

0.80

M

N

P

TOP VIEW

BOTTOM VIEW

0.80 REF

8.090 REF

DETAIL A

1.27

1.18

1.09

0.91

0.84

0.77

DETAIL A

0.39

0.34

0.29

0.44 REF

0.50

0.45

0.40

SEATING

PLANE

COPLANARITY

0.12

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

Figure 301. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-196-13)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range²

Package Description

Package Option

ADRV9008BBCZ-2

ADRV9008BBCZ-2REEL

ADRV9008-2W/PCBZ

−40°C to +85°C

196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Pb-Free Evaluation Board, 75 MHz to 6000 MHz

BC-196-13

¹Z = RoHS Compliant Part.

²See the Thermal Management section.

registered trademarks are the property of their respective owners.

D16833-0-9/18(0)

Rev. 0 | Page 95 of 95


型号：	ADRV9008BBCZ-2REEL
厂家：	ADI
描述：	Integrated Dual RF Transmitters and Observation Receiver
文件：	总95页 (文件大小：2478K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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