ADSP-21262SKBC-200_技术文档

SHARC^®Processor

ADSP-21262

DAI incorporates two precision clock generators (PCGs), an

input data port (IDP) which includes the parallel data

acquisition port (PDAP), and three programmable timers,

all under software control through the signal routing unit

(SRU)

On-chip memory—2M bits of on-chip SRAM and a dedicated

4M bits of on-chip mask-programmable ROM

Six independent synchronous serial ports provide a variety

of serial communication protocols including TDM and I²S

modes

The ADSP-21262 is available with a 200 MHz core instruction

rate. For complete ordering information, see Ordering

Guide on Page 44.

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high precision signal processing

applications

The ADSP-21262 SHARC DSP is code compatible with all

other SHARC DSPs

Single-Instruction Multiple-Data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point/32-bit fixed-

point/40-bit extended precision floating-point computa-

tional units, each with a multiplier, ALU, shifter, and

register file

High bandwidth I/O—A parallel port, SPI port, six serial

ports, digital audio interface (DAI), and JTAG

DUAL PORTED MEMORY

BLOCK 0

DUAL PORTED MEMORY

BLO CK 1

CORE PROCESSOR

INSTRUCTION

SRAM

CACHE

TIMER

1 MBIT

ROM

1 MBIT

ROM

32

؋

48-BIT

2 MBIT

DAG1

8

؋

4

؋

32

DAG2

8

؋

4

؋

32

PROGRAM

SEQUENCER

ADDR

DATA

ADDR

DATA

32

P M ADDRES S BUS

DM ADDRESS BUS

64

PM DATA BUS

DM DATA BUS

IOD

(32)

IOA

(18)

DMA CONTROLLER

PX REGISTER

4

22 CHANNE LS

GPIO FLAGS/

IRQ/TIMEXP

PROCESSING

EL EMENT

(PEX)

PROCESSING

ELEMENT

(PEY)

4

SPI PORT (1)

16

ADDRES S/

DATA BUS / GPIO

3

6

CONTROL/GP IO

SERIAL PORTS (6)

JTAG TEST & EMULATION

PARALLEL

PORT

IOP

REGISTERS

(MEMORY MAPPED)

20

SIGNAL

RO UTI NG

UNIT

INPUT

DATA PORTS (8)

PARALLEL DATA

ACQUISITION PORT

CO NTROL,

STATUS,

DATA BUFFERS

PRECISION CLOCK

GENERATORS (2)

S

3

TIMERS (3)

DIGITAL AUDIO INTERFACE

I/O PROCESSOR

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

ADSP-21262

8- to 32-bit and 16- to 32-bit word packing options

Programmable wait state options: 2 to 31 CCLK

Digital audio interface (DAI) includes six serial ports, two pre-

cision clock generators, an input data port, three

programmable timers and a signal routing unit

Serial ports provide:

Six dual data line serial ports that operate at up to 50 Mbits/s

for a 200 MHz core on each data line — each has a clock,

frame sync, and two data lines that can be configured as

either a receiver or transmitter pair

Left-justified sample pair and I²S support, programmable

direction for up to 24 simultaneous receive or transmit

channels using two I²S compatible stereo devices per serial

port

TDM support for telecommunications interfaces including

128 TDM channel support for telephony interfaces such as

H.100/H.110

KEY FEATURES

At 200 MHz (5 ns) core instruction rate, the ADSP-21262

operates at 1200 MFLOPS peak/800 MFLOPS sustained

performance whether operating on fixed or floating point

data

400 MMACS sustained performance at 200 MHz

Super Harvard Architecture—three independent buses for

dual data fetch, instruction fetch, and nonintrusive, zero-

overhead I/O

2M bits on-chip dual-ported SRAM (1M bit block 0, 1M bit

block 1) for simultaneous access by core processor and

DMA

4M bits on-chip dual-ported mask-programmable ROM

(2M bits in block 0 and 2M bits in block 1)

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single instruction multiple data (SIMD) architecture

provides:

Up to 12 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port provides an additional input path to the DSP

core configurable as either eight channels of I²S or serial

data or as seven channels plus a single 20-bit wide syn-

chronous parallel data acquisition port

Supports receive audio channel data in I²S, left-justified

sample pair, or right-justified mode

Signal routing unit provides configurable and flexible

connections between all DAI components, six serial ports,

an input data port, two precision clock generators, three

timers, 10 interrupts, six flag inputs, six flag outputs, and

20 SRU I/O pins (DAI_Px)

Serial peripheral interface (SPI)

Master or slave serial boot through SPI

Full-duplex operation

Master-slave mode multimaster support

Open drain outputs

Two computational processing elements

Concurrent execution— Each processing element executes

the same instruction, but operates on different data

Parallelism in buses and computational units allows: Sin-

gle cycle executions (with or without SIMD) of a multiply

operation; an ALU operation; a dual memory read or

write; and an instruction fetch

Transfers between memory and core at up to four 32-bit

floating- or fixed-point words per cycle, sustained

2.4G Bytes/s bandwidth at 200 MHz core instruction rate.

In addition, 900M Bytes/sec is available via DMA

Accelerated FFT butterfly computation through a multiply

with add and subtract instruction

DMA controller supports:

22 zero-overhead DMA channels for transfers between

ADSP-21262 internal memory and serial ports (12), the

input data port (IDP) (8), SPI-compatible port (1), and the

parallel port (1)

Programmable baud rates, clock polarities, and phases

3 Muxed Flag/IRQ lines

1 Muxed Flag/Timer expired line

ROM based security features:

32-bit background DMA transfers at core clock speed, in par-

allel with full-speed processor execution

Asynchronous parallel/external port provides:

Access to asynchronous external memory

16 multiplexed address/data lines support 24-bit address

external address range with 8-bit data or 16-bit address

external address range with 16-bit data

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

66M Byte per sec transfer rate for 200 MHz core rate

256 word page boundaries

JTAG background telemetry for enhanced emulation

features

IEEE 1149.1 JTAG standard test access port and on-chip

emulation

External memory access in a dedicated DMA channel

Dual voltage: 3.3 V I/O, 1.2 V core

Available in 136-ball BGA and 144-lead LQFP packages

Lead free packages are also available

Rev. A

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ADSP-21262

TABLE OF CONTENTS

General Description ..................................................4

ADSP-21262 Family Core Architecture .......................4

SIMD Computational Engine ................................4

Independent, Parallel Computation Units .................5

Data Register File ................................................5

Single-Cycle Fetch of Instruction and Four Operands ..5

Instruction Cache ...............................................5

Interrupts ........................................................20

Core Timer ......................................................20

Timer PWM_OUT Cycle Timing ..........................21

Timer WDTH_CAP Timing ................................21

DAI Pin to Pin Direct Routing .............................22

Precision Clock Generator (Direct Pin Routing) .......23

Flags ..............................................................24

Memory Read–Parallel Port .................................25

Memory Write—Parallel Port ..............................27

Serial Ports ......................................................29

Input Data Port (IDP) ........................................32

Parallel Data Acquisition Port (PDAP) ...................33

SPI Interface—Master ........................................34

SPI Interface—Slave ...........................................35

JTAG Test Access Port and Emulation ...................36

Output Drive Currents ..........................................37

Test Conditions ...................................................37

Capacitive Loading ...............................................37

Environmental Conditions .....................................38

Thermal Characteristics .........................................38

136-Ball BGA Pin Configurations ................................39

144-LQFP Pin Configurations ....................................42

Package Dimensions................................................ 43

Ordering Guide ......................................................44

Data Address Generators With Zero-Overhead

Hardware Circular Buffer Support .......................5

Flexible Instruction Set ........................................6

ADSP-21262 Memory and I/O Interface Features ..........6

Dual-Ported On-Chip Memory ..............................6

DMA Controller .................................................6

Digital Audio Interface (DAI) ................................6

Serial Ports ........................................................6

Serial Peripheral (Compatible) Interface ...................8

Parallel Port ......................................................8

Timers .............................................................8

ROM Based Security ............................................8

Program Booting ................................................8

Phase-Locked Loop ............................................8

Power Supplies ...................................................8

Target Board JTAG Emulator Connector .....................9

Development Tools ................................................9

Designing an Emulator-Compatible DSP

Board (Target) ................................................. 10

REVISION HISTORY

Additional Information ......................................... 10

Pin Function Descriptions ........................................ 11

Address Data Pins as FLAGs .................................. 14

Boot Modes ........................................................ 14

Core Instruction Rate to CLKIN Ratio Modes ............. 14

Address Data Modes ............................................. 14

ADSP-21262 Specifications ....................................... 15

Recommended Operating Conditions ....................... 15

Electrical Characteristics ........................................ 15

Absolute Maximum Ratings ................................... 16

ESD Sensitivity .................................................... 16

Timing Specifications ........................................... 16

Power-up Sequencing ........................................ 18

Clock Input ..................................................... 19

Clock Signals ................................................... 19

Reset ............................................................. 20

4/04–Data Sheet Changed from Rev. 0 to Rev. A

Added notes to AD pins ............................................11

Added V_IHCLKINand V_ILCLKINspecifications .....................15

Changed specifications (t_ALERW, and t_ALEHZ) ................25-28

Updated 136-BGA package drawing ............................43

Rev. A

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May 2004

ADSP-21262

GENERAL DESCRIPTION

The ADSP-21262 SHARC DSP is a member of the SIMD

SHARC family of DSPs featuring Analog Devices Super Har-

vard Architecture. The ADSP-21262 is source code compatible

with the ADSP-21160 and ADSP-21161 DSPs as well as with

first generation ADSP-2106x SHARC processors in SISD (Sin-

gle-Instruction, Single-Data) mode. Like other SHARC DSPs,

the ADSP-21262 is a 32-bit/40-bit floating-point processor opti-

mized for high precision signal processing applications with its

dual-ported on-chip SRAM, mask-programmable ROM, multi-

ple internal buses to eliminate I/O bottlenecks, and an

innovative Digital Audio Interface (DAI).

• Three Programmable Interval Timers with PWM Genera-

tion, PWM Capture/Pulse Width Measurement, and

External Event Counter Capabilities

• On-chip dual-ported SRAM (2M bits)

• On-chip dual-ported mask-programmable ROM (4M bits)

• JTAG test access port

The block diagram of the ADSP-21262 IOP on Page 1, illus-

trates the following architectural features:

• 8- or 16-bit parallel port that supports interfaces to off-chip

memory peripherals

As shown in the functional block diagram on Page 1, the ADSP-

21262 uses two computational units to deliver a 5 to 10 times

performance increase over the ADSP-2106x on a range of DSP

algorithms. Fabricated in a state-of-the-art, high speed, CMOS

process, the ADSP-21262 DSP achieves an instruction cycle

time of 5 ns at 200 MHz. With its SIMD computational hard-

ware, the ADSP-21262 can perform 1200 MFLOPS running at

200 MHz.

• DMA controller

• Six full duplex serial ports

• SPI compatible interface

• Digital Audio Interface that includes two precision clock

generators (PCG), an input data port (IDP), six serial ports,

eight serial interfaces, a 20-bit synchronous parallel input

port, 10 interrupts, six flag outputs, six flag inputs, three

timers, and a flexible signal routing unit (SRU)

Table 1 shows performance benchmarks for the ADSP-21262.

Figure 2 on Page 5 shows one sample configuration of a SPORT

using the precision clock generator to interface with an I²S ADC

and an I²S DAC with a much lower jitter clock than the serial

port would generate itself. Many other SRU configurations are

possible.

Table 1. ADSP-21262 Benchmarks (at 200 MHz)

Benchmark Algorithm

Speed

(at 200 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 46 µs

FIR Filter (per tap)¹

IIR Filter (per biquad)¹

2.5 ns

10 ns

ADSP-21262 FAMILY CORE ARCHITECTURE

The ADSP-21262 is code compatible at the assembly level with

the ADSP-21266, ADSP-21160 and ADSP-21161, and with the

first generation ADSP-2106x SHARC DSPs. The ADSP-21262

shares architectural features with the ADSP-2126x and

ADSP-2116x SIMD SHARC family of DSPs, as detailed in the

following sections.

Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1]

22.5 ns

40 ns

Divide (y/×)

15 ns

Inverse Square Root

¹Assumes two files in multichannel SIMD mode

22.5 ns

SIMD Computational Engine

The ADSP-21262 contains two computational processing ele-

ments that operate as a Single-Instruction Multiple-Data

(SIMD) engine. The processing elements are referred to as PEX

and PEY and each contains an ALU, multiplier, shifter, and reg-

ister file. PEX is always active, and PEY may be enabled by

setting the PEYEN mode bit in the MODE1 register. When this

mode is enabled, the same instruction is executed in both pro-

cessing elements, but each processing element operates on

different data. This architecture is efficient at executing math

intensive DSP algorithms.

The ADSP-21262 continues SHARC’s industry leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features. These

features include 2 Mbits dual-ported SRAM memory, 4 Mbits

dual-ported ROM, an I/O processor that supports 22 DMA

channels, six serial ports, an SPI interface, external parallel bus,

and Digital Audio Interface (DAI).

The block diagram of the ADSP-21262 on Page 1 illustrates the

following architectural features:

• Two processing elements, each containing an ALU, Multi-

plier, Shifter, and Data Register File

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

Rev. A

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May 2004

ADSP-21262

ADSP-212 62

CLKO UT

CLKIN

CLOCK

ALE

XTAL

2

LATCH

AD15-0

ADDR

CLK_CFG1-0

PARALLEL

PORT

RAM, ROM

BOOT ROM

I/O DEVICE

BOO TCFG 1-0

FLA G3 -1

DATA

OE

3

RD

WR

WE

FLAG0

CS

ADC

(OPTIONAL)

CLK

DAI_P1

DAI_P2

DAI_P3

FS

SDAT

SCLK0

SFS0

SRU

SD0A

SD0B

DAC

(OPTIONAL)

CLK

DAI_P 18

SPORT0

SPO RT1

SPORT2

FS

DAI_P 19

DAI_P20

SDAT

SPORT3

SPORT4

SPORT5

CLK

FS

PCG A

PCGB

DAI

RESET

JTAG

6

Figure 2. ADSP-21262 System Sample Configuration

Independent, Parallel Computation Units

Single-Cycle Fetch of Instruction and Four Operands

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

The ADSP-21262 features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1 on Page 1). With the ADSP-21262’s separate pro-

gram and data memory buses and on-chip instruction cache,

the processor can simultaneously fetch four operands (two over

each data bus) and one instruction (from the cache), all in a sin-

gle cycle.

Instruction Cache

The ADSP-21262 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Register File

A general-purpose data register file is contained in each

processing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

register files, combined with the ADSP-2126x enhanced Har-

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0-R15 and in PEY as S0-S15.

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

The ADSP-21262’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

signal processing, and are commonly used in digital filters and

Rev. A

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ADSP-21262

Fourier transforms. The two DAGs of the ADSP-21262 contain

sufficient registers to allow the creation of up to 32 circular buff-

ers (16 primary register sets, 16 secondary). The DAGs

automatically handle address pointer wraparound, reduce over-

head, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

(PDAP), or the parallel port. Twenty-two channels of DMA are

available on the ADSP-21262—one for the SPI interface, 12 via

the serial ports, eight via the Input Data Port, and one via the

processor’s parallel port. Programs can be downloaded to the

ADSP-21262 using DMA transfers. Other DMA features

include interrupt generation upon completion of DMA trans-

fers, and DMA chaining for automatic linked DMA transfers.

Flexible Instruction Set

Digital Audio Interface (DAI)

The 48-bit instruction word accommodates a variety of parallel

operations for concise programming. For example, the

ADSP-21262 can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

The Digital Audio Interface (DAI) provides the ability to con-

nect various peripherals to any of the DSPs 20 DAI pins

(DAI_P[20:1]).

Programs make these connections using the Signal Routing

Unit (SRU, shown in Figure 1).

ADSP-21262 MEMORY AND I/O INTERFACE

FEATURES

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This provides easy use of the

DAI associated peripherals for a much wider variety of applica-

tions by using a larger set of algorithms than is possible with

nonconfigurable signal paths.

The ADSP-21262 adds the following architectural features to

the SIMD SHARC family core.

Dual-Ported On-Chip Memory

The DAI also includes six serial ports, two precision clock gen-

erators (PCGs), an input data port (IDP), six flag outputs and

six flag inputs, and three timers. The IDP provides an additional

input path to the DSP core configurable as either eight channels

of I²S or serial data, or as seven channels plus a single 20-bit

wide synchronous parallel data acquisition port. Each data

channel has its own DMA channel that is independent from the

ADSP-21262's serial ports.

The ADSP-21262 contains two megabits of internal SRAM and

four megabits of internal mask-programmable ROM. Each

block can be configured for different combinations of code and

data storage (see ADSP-21262 Memory Map on Page 7). Each

memory block is dual-ported for single-cycle, independent

accesses by the core processor and I/O processor. The dual-

ported memory, in combination with three separate on-chip

buses, allows two data transfers from the core and one from the

I/O processor, in a single cycle.

For complete information on using the DAI, see the

ADSP-2126x SHARC DSP Peripherals Manual.

The ADSP-21262’s SRAM can be configured as a maximum of

64K words of 32-bit data, 128K words of 16-bit data, 42K words

of 48-bit instructions (or 40-bit data), or combinations of differ-

ent word sizes up to two megabits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-

ing-point storage format is supported that effectively doubles

the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point for-

mats is performed in a single instruction. While each memory

block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Serial Ports

The ADSP-21262 features six synchronous serial ports that pro-

vide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices

AD183x family of audio codecs, DACs, or ADCs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has its own dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous

receive or transmit pins that support up to 24 transmit or 24

receive channels of serial data when all six SPORTs are enabled,

or six full duplex TDM streams of 128 channels per frame.

Using the DM bus and PM buses, with one dedicated to each

memory block assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

The serial ports operate at up to one-quarter of the DSP core

clock rate, providing each with a maximum data rate of

50M bits/s for a 200 MHz core. Serial port data can be automat-

ically transferred to and from on-chip memory via dedicated

DMA channels. Each of the serial ports can work in conjunction

with another serial port to provide TDM support. One SPORT

provides two transmit signals while the other SPORT provides

the two receive signals. The frame sync and clock are shared.

DMA Controller

The ADSP-21262’s on-chip DMA controller allows zero-over-

head data transfers without processor intervention. The DMA

controller operates independently and invisibly to the processor

core, allowing DMA operations to occur while the core is simul-

taneously executing its program instructions. DMA transfers

can occur between the ADSP-21262’s internal memory and its

serial ports, the SPI-compatible (Serial Peripheral Interface)

port, the IDP (Input Data Port), Parallel Data Acquisition Port

Rev. A

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May 2004

ADSP-21262

ADDRESS

IOP REGISTERS

0x0000 0000 - 0x0003 FFFF

0x0004 0000

BLOCK 0 SRAM (1Mbit)

0x0004 3FFF

RESERVED

0x0004 4000 - 0x0005 7FFF

0x0005 8000

BLOCK 0 ROM (2 Mbit)

LONG WORD

ADDRESS

SPACE

ADDRESS

0x0005 FFFF

0x0006 0000

0x0020 0000

RESERVED

0x00FF FFFF

0x0100 0000

BLOCK 1 SRAM (1 Mbit)

0x0006 3FFF

RESERVED

0x0006 4000 - 0x0007 7FFF

0x0007 8000

BLOCK 1 ROM (2 Mbit)

EXTERNAL DMA

1, 4

0x0007 FFFF

0x0008 0000

ADDRESS SPACE

0x02FF FFFF

0x0300 0000

BLOCK 0 SRAM (1 Mbit)

RESERVED

0x0008 7FFF

0x3FFF FFFF

0x0008 8000 - 0x000A FFFF

0x000B 0000

NORMAL WORD

ADDRESS

2

EXTERNAL MEMORY

SPACE

BLOCK 0 ROM (2 Mbit)

0x000B FFFF

0x000C 0000

SPACE

BLOCK 1 SRAM (1 Mbit)

RESERVED

0x000C 7FFF

0x000C 8000 - 0x000E FFFF

0x000F 0000

3

1

BLOCK 1 ROM (2 Mbit)

EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE BY THE

CORE. DMA MUST BE USED TO READ OR WRITE TO THIS

MEMORY USING THE SPI OR PARALLEL PORT.

0x000F FFFF

0x0010 0000

2

3

4

BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE

(0x000A 0000 - 0x000A AAAA).

BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE

(0x000E 0000 - 0x000E AAAA).

BLOCK 0 SRAM (1 Mbit)

0x0010 FFFF

USE THE EXTERNAL ADDRESSES LISTED HERE WITH THE

PARALLEL PORT DMA REGISTERS. THE PARALLEL PORT

GENERATES ADDRESS WITHIN THE

0x0011 0000 - 0x0015 FFFF

RESERVED

0x0016 0000

RANGE 0x0000 0000-0x00FF FFFF.

BLOCK 0 ROM (2 Mbit)

0x0017 FFFF

0x0018 0000

SHORT WORD

ADDRESS

SPACE

BLOCK 1 SRAM (1 Mbit)

0x0018 FFFF

0x0019 0000 - 0x001D FFFF

0x001E 0000

RESERVED

BLOCK 1 ROM (2 Mbit)

0x001F FFFF

INTERNAL MEMORY

SPACE

Figure 3. ADSP-21262 Memory Map

Rev. A

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May 2004

ADSP-21262

Serial ports operate in four modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I²S mode

Timers

The ADSP-21262 has a total of four timers: a core timer able to

generate periodic software interrupts and three general-purpose

timers that can generate periodic interrupts and be indepen-

dently set to operate in one of three modes:

• Left-justified sample pair mode

• Pulse Waveform Generation mode

• Pulse Width Count/Capture mode

• External Event Watchdog mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

The core timer can be configured to use FLAG3 as a Timer

Expired output signal, and each general-purpose timer has one

bidirectional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables all three

general-purpose timers independently.

Each of the serial ports supports the left-justified sample pair

and I²S protocols (I²S is an industry standard interface com-

monly used by audio codecs, ADCs and DACs), with two data

pins, allowing four left-justified Sample Pair or I²S channels

(using two stereo devices) per serial port, with a maximum of up

to 24 audio channels. The serial ports permit little-endian or

big-endian transmission formats and word lengths selectable

from 3 bits to 32 bits. For the left-justified sample pair and I²S

modes, data-word lengths are selectable between 8 bits and 32

bits. Serial ports offer selectable synchronization and transmit

modes as well as optional µ-law or A-law companding selection

on a per channel basis. Serial port clocks and frame syncs can be

internally or externally generated.

ROM Based Security

The ADSP-21262 has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the DSP does not boot-load any exter-

nal code, executing exclusively from internal SRAM/ROM.

Additionally, the DSP is not freely accessible via the JTAG port.

Instead, a unique 64-bit key, which must be scanned in through

the JTAG or Test Access Port will be assigned to each customer.

The device will ignore a wrong key. Emulation features and

external boot modes are only available after the correct key is

scanned.

Serial Peripheral (Compatible) Interface

Serial Peripheral Interface (SPI) is an industry standard syn-

chronous serial link, enabling the ADSP-21262 SPI-compatible

port to communicate with other SPI-compatible devices. SPI is

an interface consisting of two data pins, one device select pin,

and one clock pin. It is a full-duplex synchronous serial inter-

face, supporting both master and slave modes. The SPI port can

operate in a multimaster environment by interfacing with up to

four other SPI-compatible devices, either acting as a master or

slave device. The ADSP-21262 SPI compatible peripheral imple-

mentation also features programmable baud rates up to

37.5 MHz, clock phases, and polarities. The ADSP-21262 SPI

compatible port uses open drain drivers to support a multimas-

ter configuration and to avoid data contention.

Program Booting

The internal memory of the ADSP-21262 boots at system

power-up from an 8-bit EPROM via the parallel port, an SPI

master, an SPI slave or an internal boot. Booting is determined

by the Boot Configuration (BOOTCFG1-0) pins. Selection of

the boot source is controlled via the SPI as either a master or

slave device, or it can immediately begin executing from ROM.

Phase-Locked Loop

The ADSP-21262 uses an on-chip Phase-Locked Loop (PLL) to

generate the internal clock for the core. On power-up, the

CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1.

After booting, numerous other ratios can be selected via soft-

ware control. The ratios are made up of software configurable

numerator values from 1 to 32 and software configurable divi-

sor values of 1, 2, 4, 8, and 16.

Parallel Port

The Parallel Port provides interfaces to SRAM and peripheral

devices. The multiplexed address and data pins (AD15-0) can

access 8-bit devices with up to 24 bits of address, or 16-bit

devices with up to 16 bits of address. In either mode, 8- or 16-

bit, the maximum data transfer rate is one-third the core clock

speed. As an example, for a clock rate of 200 MHz, this is equiv-

alent to 66M Bytes/sec.

Power Supplies

The ADSP-21262 has separate power supply connections for the

DMA transfers are used to move data to and from internal

memory. Access to the core is also facilitated through the paral-

lel port register read/write functions. The RD, WR, and ALE

(Address Latch Enable) pins are the control pins for the

parallel port.

internal (V_DDINT), external (V_DDEXT), and analog (A_VDD/A_VSS

)

power supplies. The internal and analog supplies must meet the

1.2 V requirement. The external supply must meet the 3.3 V

requirement. All external supply pins must be connected to the

same power supply.

Note that the analog supply (A_VDD) powers the ADSP-21262’s

clock generator PLL. To produce a stable clock, programs

should provide an external circuit to filter the power input to

Rev. A

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ADSP-21262

the A_VDDpin. Place the filter as close as possible to the pin. For

an example circuit, see Figure 4. To prevent noise coupling, use

a wide trace for the analog ground (A_VSS) signal and install a

decoupling capacitor as close as possible to the pin. Note that

the A_VSSand A_VDDpins specified in Figure 4 are inputs to the

SHARC and not the analog ground plane on the board.

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

10⍀

V_DDINT

A_VDD

• View mixed C/C++ and assembly code (interleaved source

and object information)

0.1␮F

0.01␮F

A_VSS

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

Figure 4. Analog Power (A_VDD) Filter Circuit

• Trace instruction execution

TARGET BOARD JTAG EMULATOR CONNECTOR

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21262

processor to monitor and control the target board processor

during emulation. Analog Devices DSP Tools product line of

JTAG emulators provides emulation at full processor speed,

allowing inspection and modification of memory, registers, and

processor stacks. The processor’s JTAG interface ensures that

the emulator will not affect target system loading or timing.

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate emulator hardware user’s guide.

• Control how the development tools process inputs and

generate outputs

DEVELOPMENT TOOLS

• Maintain a one-to-one correspondence with the tool’s

command line switches

The ADSP-21262 is supported with a complete set of

CROSSCORE^TMsoftware and hardware development tools,

including Analog Devices emulators and VisualDSP++^TMdevel-

opment environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-21262.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

Threads, Critical and Unscheduled regions, Semaphores,

Events, and Device flags. The VDK also supports Priority-based,

Preemptive, Cooperative, and Time-Sliced scheduling

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The SHARC has

architectural features that improve the efficiency of compiled

C/C++ code.

approaches. In addition, the VDK was designed to be scalable. If

the application does not use a specific feature, the support code

for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK based objects, and visualizing the

system state, when debugging an application that uses the VDK.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

VisualDSP++ Component Software Engineering (VCSE) is

Analog Devices’ technology for creating, using, and reusing

software components (independent modules of substantial

functionality) to quickly and reliably assemble software applica-

tions. Download components from the Web and drop them into

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ADSP-21262

the application. Publish component archives from within

VisualDSP++. VCSE supports component implementation in

C/C++ or assembly language.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the DSP or external memory with the drag

of the mouse, examine run time stack and heap usage. The

Expert Linker is fully compatible with the existing Linker Defi-

nition File (LDF), allowing the developer to move between the

graphical and textual environments.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21262

architecture and functionality. For detailed information on the

ADSP-2126x family core architecture and instruction set, refer

to the ADSP-2126x DSP Core Manual and the ADSP-21160

SHARC DSP Instruction Set Reference.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC processor PC plug-in cards. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

DESIGNING AN EMULATOR-COMPATIBLE DSP

BOARD (TARGET)

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-

circuit emulation is assured by the use of the processor’s JTAG

interface—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the DSP, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The DSP must be halted to send data and commands,

but once an operation has been completed by the emulator, the

DSP system is set running at full speed with no impact on sys-

tem timing.

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ADSP-21262

PIN FUNCTION DESCRIPTIONS

ADSP-21262 pin definitions are listed below. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-

tified as asynchronous (A) can be asserted asynchronously to

CLKIN (or to TCK for TRST). Tie or pull unused inputs to

• DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI,

and AD15-0 (NOTE: These pins have pull-up resistors.)

The following symbols appear in the Type column of Table 2:

A = Asynchronous, G = Ground, I = Input, O = Output, P =

Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) =

Open Drain, and T = Three-State.

V_DDEXTor GND, except for the following:

Table 2. Pin Descriptions

Type

State During and Function

After Reset

AD15-0

I/O/T

Three-state with

pull-up enabled

Parallel Port Address/Data. The ADSP-21262 parallel port and its corresponding

DMA unit output addresses and data for peripherals on these multiplexed pins. The

multiplex state is determined by the ALE pin. The parallel port can operate in either

8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address

Data Modes on Page 14 for details of the AD pin operation.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper

16 external address bits, A23-8; ALE is used in conjunction with an external latch to

retain the values of the A23-8.

For 16-bit mode: ALE is automatically asserted whenever a change occurs in the

address bits, A15-0; ALE is used in conjunction with an external latch to retain the

values of the A15-0. To use these pins as flags (FLAGS15-0) set (=1) Bit 20 of the

SYSCTL register and disable the parallel port. When used as an input, the IDP Channel

0 can use these pins for parallel input data.

RD

O

Output only, driven Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or

high¹

16-bit data from an external memory device. When AD15-0 are flags, this pin remains

deasserted.

WR

ALE

Output only, driven Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or

high¹

16-bit data to an external memory device. When AD15-0 are flags, this pin remains

deasserted.

Output only, driven Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a new

low¹

address on the parallel port address pin. On reset, ALE is active high. However, it can

be reconfigured using software to be active low. When AD15-0 are flags, this pin

remains deasserted.

FLAG3-0

I/O/A

Three-state

Flag Pins. Each flag pin is configured via control bits as either an input or output. As

an input, it can be tested as a condition. As an output, it can be used to signal external

peripherals. These pins can be used as an SPI interface slave select output during SPI

mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals.

In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an

SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When Bit

16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.

When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.

When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.

When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which

indicates that the system timer has expired.

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ADSP-21262

Table 2. Pin Descriptions (Continued)

Type

State During and Function

After Reset

DAI_P20-1

I/O/T

Three-state with

programmable

pull-up

Digital Audio Interface Pins. These pins provide the physical interface to the SRU.

The SRU configuration registers define the combination of on-chip peripheral inputs

or outputs connected to the pin and to the pin’s output enable. The configuration

registers oftheseperipheralsthendeterminetheexactbehaviorof thepin. Anyinput

or output signal present in the SRU may be routed to any of these pins. The SRU

provides the connection from the serial ports, input data port, precision clock gener-

ators, and timer to the DAI_P20-1 pins. These pins have internal 22.5 kΩ pull-up

resistors which are enabled on reset. These pull-ups can be disabled in the

DAI_PIN_PULLUP register.

SPICLK

I/O

Three-state with

pull-up enabled

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls

the rate at which data is transferred. The master may transmit data at a variety of

baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that

is active during data transfers, only for the length of the transferred word. Slave

devicesignoretheserialclockiftheslaveselectinputisdriveninactive(HIGH). SPICLK

is used to shift out and shift in the data driven on the MISO and MOSI lines. The data

is always shifted out on one clock edge and sampled on the opposite edge of the

clock. Clock polarity and clock phase relative to data are programmable into the

SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ internal

pull-up resistor.

SPIDS

I

Input only

Serial Peripheral Interface Slave Device Select. An active low signal used to select

the DSP as an SPI slave device. This input signal behaves like a chip select, and is

provided by the master device for the slave devices. In multimaster mode the DSP’s

SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that

an error has occurred, as some other device is also trying to be the master device. If

asserted low when the device is in master mode, it is considered a multimaster error.

For a single-master, multiple-slave configuration where flag pins are used, this pin

must be tied or pulled high to V_DDEXTon the master device. For ADSP-21262 to ADSP-

21262 SPI interaction, any of the master ADSP-21262's flag pins can be used to drive

the SPIDS signal on the ADSP-21262 SPI slave device.

MOSI

MISO

I/O (O/D)

Three-state with

pull-up enabled

SPI Master Out Slave In. If the ADSP-21262 is configured as a master, the MOSI pin

becomes a data transmit (output) pin, transmitting output data. If the ADSP-21262

is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving

input data. In an ADSP-21262 SPI interconnection, the data is shifted out from the

MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI

has a 22.5 kΩ internal pull-up resistor.

Three-state with

pull-up enabled

SPI Master In Slave Out. If the ADSP-21262 is configured as a master, the MISO pin

becomes a data receive (input) pin, receiving input data. If the ADSP-21262 is

configured as a slave, the MISO pin becomes a data transmit (output) pin, trans-

mitting output data. In an ADSP-21262 SPI interconnection, the data is shifted out

from the MISO output pin of the slave and shifted into the MISO input pin of the

master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D

by setting the OPD bit in the SPICTL register.

Note: Only one slave is allowed to transmit data at any given time. To enable broadcast

transmission to multiple SPI slaves, the DSP's MISO pin may be disabled by setting

(=1) Bit 5 (DMISO) of the SPICTL register.

BOOTCFG1-0

I

Input only

Boot Configuration Select. Selects the boot mode for the DSP. The BOOTCFG pins

must be valid before reset is asserted. See Table 4 on Page 14 for a description of the

boot modes.

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ADSP-21262

Table 2. Pin Descriptions (Continued)

Type

State During and Function

After Reset

CLKIN

I

Input only

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21262 clock input.

It configures the ADSP-21262 to use either its internal clock generator or an external

clock source. Connecting the necessary components to CLKIN and XTAL enables the

internal clock generator. Connecting the external clock to CLKIN while leaving XTAL

unconnected configures the ADSP-21262 to use the external clock source such as an

external clock oscillator. The core is clocked either by the PLL output or this clock

input depending on the CLKCFG1-0 pin settings. CLKIN may not be halted, changed,

or operated below the specified frequency.

XTAL

O

I

Output only²

Input only

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

CLKCFG1-0

Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 5

on Page 14 for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multi-

plier and divider in the PMCTL register at any time after the core comes out of reset.

RSTOUT/CLKOUT

RESET

O

Output only

Input only

Input only³

Reset Out/Local Clock Out. Drives out the core reset signal to an external device.

CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can be

switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL

register. The default is reset out.

I/A

Processor Reset. Resets the ADSP-21262 to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from the hardware reset vector address. The RESET input must

be asserted (low) at power-up.

TCK

TMS

TDI

I

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the ADSP-21262.

I/S

Three-state with

pull-up enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ

internal pull-up resistor.

Three-state with

pull-up enabled

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

TDO

TRST

O

Three-state⁴

Test Data Output (JTAG). Serial scan output of the boundary scan path.

I/A

Three-state with

pull-up enabled

Test Reset (JTAG). Resets the test state machine. TRSTmust be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21262. TRST has a

22.5 kΩ internal pull-up resistor.

EMU

O (O/D)

Three-state with

pull-up enabled

Emulation Status. Must be connected to the ADSP-21262 Analog Devices DSP Tools

product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ

internal pull-up resistor.

V_DDINT

V_DDEXT

A_VDD

P

Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor

(13 pins on the BGA package, 32 pins on the LQFP package).

I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the

LQFP package).

Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL

(clock generator). This pin has the same specifications as V_DDINT, except that added

filtering circuitry is required. For more information, see Power Supplies on Page 8.

A_VSS

G

Analog Power Supply Return.

GND

Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

¹RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.

²Output only is a three-state driver with its output path always enabled.

³Input only is a three-state driver with both output paths.

⁴Three-state is a three-state driver.

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ADSP-21262

ADDRESS DATA PINS AS FLAGS

ADDRESS DATA MODES

To use these pins as flags (FLAGS15-0) set (=1) Bit 20 of the

SYSCTL register and disable the parallel port.

The following table shows the functionality of the AD pins for

8-bit and 16-bit transfers to the parallel port. For 8-bit data

transfers, ALE latches address bits A23-A8 when asserted, fol-

lowed by address bits A7-A0 and data bits D7-D0 when

deasserted. For 16-bit data transfers, ALE latches address bits

A15-A0 when asserted, followed by data bits D15-D0 when

deasserted.

Table 3. AD[15:0] to Flag Pin Mapping

AD Pin

AD0

Flag Pin

FLAG8

FLAG9

FLAG10

FLAG11

FLAG12

FLAG13

FLAG14

FLAG15

FLAG0

FLAG1

FLAG2

FLAG3

FLAG4

FLAG5

FLAG6

FLAG7

AD1

Table 6. Address/Data Mode Selection

AD2

AD3

EP Data

Mode

ALE

AD7-0

Function

AD15-8

Function

AD4

8-bit

Asserted

A15-8

D7-0

A7-0

D7-0

A23-16

A7-0

AD5

8-bit

Deasserted

Asserted

AD6

16-bit

A15-8

D15-8

AD7

Deasserted

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

BOOT MODES

Table 4. Boot Mode Selection

BOOTCFG1-0

Booting Mode

00

01

10

11

SPI Slave Boot

SPI Master Boot

Parallel Port boot via EPROM

Internal Boot Mode (ROM code only)

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

Table 5. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1-0

Core to CLKIN Ratio

00

01

10

11

3:1

16:1

8:1

Reserved

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ADSP-21262

ADSP-21262 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

Min

Parameter¹

Max

Unit

V_DDINT

A_VDD

V_DDEXT

V_IH

Internal (Core) Supply Voltage

1.14

3.13

2.0

1.26

3.47

V

Analog (PLL) Supply Voltage

External (I/O) Supply Voltage

High Level Input Voltage², @ V_DDEXT= max

Low Level Input Voltage²@ V_DDEXT= min

High Level Input Voltage³, @ V_DDEXT= max

Low Level Input Voltage, @ V_DDEXT= min

Ambient Operating Temperature^{4, 5}

V_DDEXT+ 0.5

+0.8

V

V_IL

–0.5

1.74

–0.5

0

V

V_{IH_CLKIN}

V_{IL_CLKIN}

T_AMB

V_DDEXT+ 0.5

+1.28

V

+70

°C

1

Specifications subject to change without notice.

²Applies to input and bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

³Applies to input pin CLKIN.

⁴See Thermal Characteristics on Page 38 for information on thermal specifications.

⁵See Engineer-to-Engineer Note (No. 216) for further information.

ELECTRICAL CHARACTERISTICS

Parameter¹

V_OH

Test Conditions

Min

Max

Unit

V

High Level Output Voltage²

Low Level Output Voltage²

High Level Input Current^{4, 5}

Low Level Input Current⁴

Low Level Input Current Pull-Up⁵

Three-State Leakage Current ^{6, 7, 8}

Three-State Leakage Current⁶

Three-State Leakage Current Pull-Up⁷

Supply Current (Internal)^{9, 10, 11}

Supply Current (Analog)¹²

@ V_DDEXT= min, I_OH= –1.0 mA³

@ V_DDEXT= min, I_OL= 1.0 mA³

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

2.4

V_OL

0.4

10

V

I_IH

µA

mA

pF

I_IL

10

I_ILPU

@ V_DDEXT= max, V_IN= 0 V

200

10

I_OZH

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

I_OZL

10

I_OZLPU

I_DD-INTYP

AI_DD

C_IN

@ V_DDEXT= max, V_IN= 0 V

200

500

10

t_CCLK= 5.0 ns, V_DDINT= 1.2 V, T_AMB= +25°C

A_VDD= max

Input Capacitance^{13, 14}

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 1.2 V

4.7

¹Specifications subject to change without notice.

²Applies to output and bidirectional pins: AD15-0, RD, WR, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

³See Output Drive Currents on Page 37 for typical drive current capabilities.

⁴Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

⁵Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

⁶Applies to three-statable pins: FLAG3-0.

⁷Applies to three-statable pins with 22.5 kΩ pull-ups: AD15-0, DAI_Px, SPICLK, MISO, MOSI.

⁸Applies to open-drain output pins: EMU, MISO, MOSI.

⁹Typical internal current data reflects nominal operating conditions.

¹⁰See Engineer-to-Engineer Note (No. 216) for further information.

¹¹Characterized, but not tested.

¹²Characterized, but not tested.

¹³Applies to all signal pins.

¹⁴Guaranteed, but not tested.

Rev. A

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ADSP-21262

ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

1

Internal (Core) Supply Voltage (V_DDINT

)

–0.3 V to +1.4 V

–0.3 V to +3.8 V

+ 0.5 V

1

Analog (PLL) Supply Voltage (A_VDD

)

1

External (I/O) Supply Voltage (V_DDEXT

)

1

Input Voltage–0.5 V to V_DDEXT

1

Output Voltage Swing–0.5 V to V_DDEXT

Load Capacitance¹

+ 0.5 V

200 pF

Storage Temperature Range¹

–65°C to +150°C

125°C

Junction Temperature under Bias

¹Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only;

functional operation of the device at these or any other conditions greater than those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADSP-21262 features proprietary ESD protection circuitry, permanent

damage may occuron devices subjected to highenergy electrostaticdischarges. Therefore,

proper ESD precautions are recommended to avoid performance degradation or loss of

functionality.

Table 8. Clock Periods

TIMING SPECIFICATIONS

The ADSP-21262’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, serial ports, and parallel port (as required for read/write

strobes in asynchronous access mode). During reset, program

the ratio between the DSP’s internal clock frequency and exter-

nal (CLKIN) clock frequency with the CLKCFG1-0 pins. To

determine switching frequencies for the serial ports, divide

down the internal clock, using the programmable divider con-

trol of each port (DIVx for the serial ports).

Timing

Requirements

Description¹

t_CK

CLKIN Clock Period

t_CCLK

(Processor) Core Clock Period

Serial Port Clock Period = (t_CCLK) × SR

SPI Clock Period = (t_CCLK) × SPIR

t_SCLK

t_SPICLK

¹where:

SR = serial port-to-core clock ratio (wide range, determined by

SPORT CLKDIV)

The ADSP-21262’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the DSP uses an internal phase-locked loop (PLL). This

PLL-based clocking minimizes the skew between the system

clock (CLKIN) signal and the DSP’s internal clock (the clock

source for the parallel port logic and I/O pads).

SPIR = SPI-to-Core Clock Ratio (wide range, determined by

SPIBAUD register)

DAI_Px = Serial Port Clock

SPICLK = SPI Clock

Figure 5 shows Core to CLKIN ratios of 3:1, 8:1, and 16:1 with

external oscillator or crystal. Note that more ratios are possible

and can be set through software using the power management

control register (PMCTL). For more information, see the

ADSP-2126x SHARC DSP Core Manual.

Note the definitions of various clock periods that are a function

of CLKIN and the appropriate ratio control (Table 7 and

Table 8).

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times.

Table 7. ADSP-21262 CLKOUT and CCLK Clock

Generation Operation

Timing

Description

Calculation

Requirements

CLKIN

CCLK

Input Clock

Core Clock

1/t_CK

1/t_CCLK

See Figure 30 on Page 37 under Test conditions for voltage ref-

erence levels.

Rev. A

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May 2004

ADSP-21262

Switching characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

CLKOUT

CLKIN

XTAL

PLL

3:1, 8:1,

16:1

XTAL

OSC

CCLK

(CORE CLOCK)

PLLICLK

Timingrequirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

CLK-CFG [1:0]

Figure 5. Core Clock and System Clock Relationship to CLKIN

Rev. A

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May 2004

ADSP-21262

Power-Up Sequencing

The timing requirements for DSP startup are given in Table 9.

Table 9. Power-Up Sequencing Timing Requirements (DSP Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

t_IVDDEVDD

t_CLKVDD

t_CLKRST

RESET Low Before V_DDINT/V_DDEXTon

V_DDINTon Before V_DDEXT

CLKIN Valid After V_DDINT/V_DDEXTvalid¹

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

0

ns

–50

0

10²

20³

200

ms

µs

t_PLLRST

µs

Switching Characteristic

4, 5

t_CORERST

DSP Core Reset Deasserted After RESET Deasserted

4096t_CK

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for startup time.

Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles.

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁵The 4096 cycle count depends on t_SRSTspecification in Table 11. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

RESET

t_{RS TVDD}

V

DDINT

t_{IVDD EVDD}

V

t_{C LK VD D}

DDEXT

CLKIN

t_CLKRST

CLK_CFG1-0

t_{CO RE RST}

t_{PLLR ST}

RSTOUT*

*MULTIPLEXED W ITH CLKOUT

Figure 6. Power-Up Sequencing

Rev. A

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May 2004

ADSP-21262

Clock Input

Table 10. Clock Input

Parameter

200 MHz

Min

Unit

Max

Timing Requirements

t_CK

CLKIN Period

15¹

6¹

160²

80²

3

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V – 2.0 V)

CCLK Period³

5

10

¹Applies only for CLKCFG1-0 = 00 and default values for PLL control bits in PMCTL.

²Applies only for CLKCFG1-0 = 01 and default values for PLL control bits in PMCTL.

³Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_CCLK

.

t_CK

CLKIN

t_CKH

t_CKL

Figure 7. Clock Input

Clock Signals

The ADSP-21262 can use an external clock or a crystal. See

CLKIN pin description. The programmer can configure the

ADSP-21262 to use its internal clock generator by connecting

the necessary components to CLKIN and XTAL. Figure 8 shows

the component connections used for a crystal operating in fun-

damental mode. Note that the clock rate is achieved using a

12.5 MHz crystal and a PLL multiplier ratio 16:1

(CCLK:CLKIN).

CLKIN

XTAL

1M⍀

C1

C2

X1

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL

SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

Figure 8. 200 MHz Operation with a 12.5 MHz Fundamental Mode

Crystal

Rev. A

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May 2004

ADSP-21262

Reset

Table 11. Reset

Parameter

Min

Max

Unit

Timing Requirements

t_WRST

t_SRST

RESET Pulse Width Low¹

4t_CK

8

ns

RESET Setup Before CLKIN Low

¹Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_WRST

t_SRST

RESET

Figure 9. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts. Also applies to DAI_P[20:1] pins

when configured as interrupts.

Table 12. Interrupts

Parameter

Min

2 × t_CCLK+ 2

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

ns

DAI_P20-1

(FLAG2-0)

(IRQ2-0)

t_IPW

Figure 10. Interrupts

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Table 13. Core Timer

Parameter

Min

Max

Unit

ns

Switching Characteristic

t_WCTIM

CTIMER Pulse Width

4 × t_CCLK– 1

FLAG3

(CTIMER)

t_WCTIM

Figure 11. Core Timer

Rev. A

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May 2004

ADSP-21262

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer[2:0] in

PWM_OUT (pulse width modulation) mode. Timer signals are

routed to the DAI_P[20:1] pins through the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P[20:1] pins.

Table 14. Timer[2:0] PWM_OUT Timing

Parameter

Min

2 t_CCLK– 1

Max

Unit

Switching Characteristic

t_PWMO

Timer[2:0] Pulse Width Output

2(2³¹– 1) t_CCLK

ns

t_PWMO

DAI_P[20:1]

(TIMER[2:0])

Figure 12. Timer[2:0] PWM_OUT Timing

Timer WDTH_CAP Timing

The following timing specification applies to Timer[2:0] in

WDTH_CAP (pulse width count and capture) mode. Timer sig-

nals are routed to the DAI_P[20:1] pins through the SRU.

Therefore, the timing specifications provided below are valid at

the DAI_P[20:1] pins.

Table 15. Timer[2:0] Width Capture Timing

Parameter

Min

2 t_CCLK

Max

Unit

Timing Requirement

t_PWI

Timer[2:0] Pulse Width

2(2³¹– 1) t_CCLK

ns

t_PWI

DAI_P[20:1]

(TIMER[2:0])

Figure 13. Timer[2:0] Width Capture Timing

Rev. A

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ADSP-21262

DAI Pin to Pin Direct Routing

For direct pin connections only (for example DAI_PB01_I to

DAI_PB02_O).

Table 16. DAI Pin to Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI Pin Input Valid to DAI Output Valid

1.5

10

ns

DAI_Pn

DAI_Pm

t_DPIO

Figure 14. DAI Pin to Pin Direct Routing

Rev. A

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May 2004

ADSP-21262

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P07 – DAI_P20).

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the Precision Clock Generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 17. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

t_PCGIW

t_STRIG

t_HTRIG

Input Clock Period

20

2

ns

PCG Trigger Setup Before Falling Edge of PCG Input Clock

PCG Trigger Hold After Falling Edge of PCG Input Clock

2

Switching Characteristics

t_DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After PCG Input

Clock

2.5

10

ns

t_DTRIG

PCG Output Clock and Frame Sync Delay After PCG Trigger

Output Clock Period

2.5 + 2.5 × t_PCGOW10 + 2.5 × t_PCGOWns

40 ns

t_PCGOW

t_STRIG

DAI_Pn

PCG_TRIGx_I

t_PCGIW

t_HTRIG

DAI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

DAI_Py

PCG_CLKx_O

t_PCGOW

DAI_Pz

PCG_FSx_O

t_DTRIG

Figure 15. Precision Clock Generator (Direct Pin Routing)

Rev. A

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May 2004

ADSP-21262

Flags

The timing specifications provided below apply to the

FLAG[3:0] and DAI_P[20:1] pins, the parallel port, and the

serial peripheral interface (SPI). See Table 2 on Page 11 for

more information on flag use.

Table 18. Flags

Parameter

Min

Max

Unit

Timing Requirement

t_FIPW

FLAG[3:0] IN Pulse Width

2 × t_CCLK+ 3

ns

Switching Characteristic

t_FOPWFLAG[3:0] OUT Pulse Width

2 × t_CCLK– 1

ns

DAI_P[20:1]

(FLAG3-0

)

IN

(AD[15:0])

t_FIPW

DAI_P[20:1]

(FLAG3-0

)

OUT

(AD[15:0])

t_FOPW

Figure 16. Flags

Rev. A

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May 2004

ADSP-21262

Memory Read—Parallel Port

Use these specifications for asynchronous interfacing to

memories (and memory-mapped peripherals) when the

ADSP-21262 is accessing external memory space.

Table 19. 8-Bit Memory Read Cycle

Parameter

Min

Max

Unit

Timing Requirements

t_DRS

t_DRH

t_DAD

Address/Data [7:0] Setup Before RD High

Address/Data [7:0] Hold After RD High

Address [15:8] to Data Valid

3.3

0

ns

D + 0.5 × t_CCLK– 3.5

ns

Switching Characteristics

t_ALEW

t_ALERW

t_ADAS

t_ADAH

t_ALEHZ

t_RW

ALE Pulse Width

2 × t_CCLK– 2

ns

ALE Deasserted to Read/Write Asserted

Address/Data [15:0] Setup Before ALE Deasserted¹

Address/Data [15:0] Hold After ALE Deasserted¹

ALE Deasserted¹to Address/Data[7:0] In High Z

RD Pulse Width

1 × t_CCLK– 0.5

2.5 × t_CCLK– 2.0

0.5 × t_CCLK– 0.8

D – 2

0.5 × t_CCLK+ 2.0

t_ADRH

Address/Data [15:8] Hold After RD High

0.5 × t_CCLK– 1 + H

D = (Data Cycle Duration) × t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

¹On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE

t_ALEW

t_ALERW

t_RW

RD

WR

t_ALEHZ

t_ADAH

t_ADAS

t_ADRH

AD[15:8]

VALID ADDRESS

t_DRS

t_DRH

AD[7:0]

VALID DATA

t_DAD

Figure 17. Read Cycle for 8-Bit Memory Timing

Rev. A

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ADSP-21262

Table 20. 16-Bit Memory Read Cycle

Parameter

Min

Max

Unit

Timing Requirements

t_DRS

t_DRH

Address/Data [15:0] Setup Before RD High

3.3

0

ns

Address/Data [15:0] Hold After RD High

Switching Characteristics

ns

t_ALEW

t_ALERW

t_ADAS

t_ADAH

t_ALEHZ

t_RW

ALE Pulse Width

2 × t_CCLK– 2

1 × t_CCLK– 0.5

2.5 × t_CCLK– 2.0

0.5 × t_CCLK– 0.8

D – 2

ALE Deasserted to Read/Write Asserted

Address/Data [15:0] Setup Before ALE Deasserted¹

Address/Data [15:0] Hold After ALE Deasserted¹

ALE Deasserted¹to Address/Data[15:0] In High Z

RD Pulse Width

0.5t_CCLK+ 2.0

D = (Data Cycle Duration) × t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

¹On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE

t_ALEW

t_ALERW

RD

t_RW

WR

t_ADAH

t_DRS

t_DRH

t_ADAS

VALID ADDRESS

VALID DATA

AD[15:0]

t_ALEHZ

Figure 18. Read Cycle for 16-Bit Memory Timing

Rev. A

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May 2004

ADSP-21262

Memory Write—Parallel Port

Use these specifications for asynchronous interfacing to

memories (and memory-mapped peripherals) when the

ADSP-21262 is accessing external memory space.

Table 21. 8-Bit Memory Write Cycle

Parameter

Min

Max

Unit

Switching Characteristics

t_ALEW

t_ALERW

t_ADAS

t_ADAH

t_WW

ALE Pulse Width

2 × t_CCLK– 2

1 × t_CCLK– 0.5

2.5 × t_CCLK– 2.0

0.5 × t_CCLK– 0.8

D – 2

ns

ALE Deasserted to Read/Write Asserted

Address/Data [15:0] Setup Before ALE Deasserted¹

Address/Data [15:0] Hold After ALE Deasserted ¹

WR Pulse Width

t_ADWL

t_ADWH

t_ALEHZ

t_DWS

Address/Data [15:8] to WR Low

0.5 × t_CCLK– 1.5

0.5 × t_CCLK– 1 + H

0.5 × t_CCLK– 0.8

D

Address/Data [15:8] Hold After WR High

ALE Deasserted¹to Address/Data[15:0] In High Z

Address/Data [7:0] Setup Before WR High

Address/Data [7:0] Hold After WR High

Address/Data to WR High

0.5t_CCLK+ 2.0

t_DWH

0.5 × t_CCLK– 1.5 + H

D

t_DAWH

D = (Data Cycle Duration) × t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

¹On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

t_ALERW

ALE

t_ALEW

t_DAWH

WR

t_WW

RD

t_ALEHZ

t_ADAH

t_ADWL

t_ADWH

t_ADAS

AD[15:8]

VALID ADDRESS

t_DWS

t_DWH

VALID ADDRESS

VALID DATA

AD[7:0]

Figure 19. Write Cycle for 8-Bit Memory Timing

Rev. A

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May 2004

ADSP-21262

Table 22. 16-Bit Memory Write Cycle

Parameter

Min

Max

Unit

Switching Characteristics

t_ALEW

t_ALERW

t_ADAS

t_ADAH

t_WW

ALE Pulse Width

2 × t_CCLK– 2

1 × t_CCLK– 0.5

2.5 × t_CCLK– 2.0

0.5 × t_CCLK– 0.8

D – 2

ns

ALE Deasserted to Read/Write Asserted

Address/Data [15:0] Setup Before ALE Deasserted¹

Address/Data [15:0] Hold After ALE Deasserted¹

WR Pulse Width

ALE Deasserted¹to Address/Data[15:0] In High Z

Address/Data [15:0] Setup Before WR High

Address/Data [15:0] Hold After WR High

t_ALEHZ

t_DWS

0.5 × t_CCLK–0.8

D

0.5t_CCLK+ 2.0

t_DWH

0.5 × t_CCLK– 1.5 + H

D = (Data Cycle Duration) × t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

¹On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE

t_ALEW

t_ALERW

t_WW

WR

RD

t_ALEHZ

t_ADAS

t_ADAH

t_DWS

t_DWH

VALID ADDRESS

AD[15:0]

VALID DATA

Figure 20. Write Cycle for 16-Bit Memory Timing

Rev. A

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May 2004

ADSP-21262

Serial port signals (SCLK, FS, DxA,/DxB) are routed to the

Serial Ports

DAI_P[20:1] pins using the SRU. Therefore, the timing specifi-

cations provided below are valid at the DAI_P[20:1] pins.

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Table 23. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSE

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)¹

2.5

ns

t_HFSE

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)¹

2.5

7

ns

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

Receive Data Setup Before Receive SCLK¹

Receive Data Hold After SCLK¹

SCLK Width

SCLK Period

20

Switching Characteristics

t_DFSE

FS Delay After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)²

7

ns

t_HOFSE

FS Hold After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)2

Transmit Data Delay After Transmit SCLK²

Transmit Data Hold After Transmit SCLK²

2

ns

t_DDTE

t_HDTE

¹Referenced to sample edge.

²Referenced to drive edge.

Table 24. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSI

FS Setup Before SCLK (Externally Generated FS in Either Transmit or

Receive Mode)¹

6

ns

t_HFSI

FSHoldAfterSCLK(ExternallyGeneratedFSinEitherTransmitorReceive

Mode)¹

1.5

6

ns

t_SDRI

t_HDRI

Receive Data Setup Before SCLK¹

Receive Data Hold After SCLK¹

1.5

Switching Characteristics

t_DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode)²

3

ns

t_HOFSI

t_DFSI

t_HOFSI

t_DDTI

FS Hold After SCLK (Internally Generated FS in Transmit Mode)²

FS Delay After SCLK (Internally Generated FS in Receive or Mode)²

FS Hold After SCLK (Internally Generated FS in Receive Mode)²

Transmit Data Delay After SCLK²

–1.0

3

t_HDTI

Transmit Data Hold After SCLK²

–1.0

t_SCLKIW

Transmit or Receive SCLK Width

0.5t_SCLK– 2

0.5t_SCLK+ 2

¹Referenced to the sample edge.

²Referenced to drive edge.

Rev. A

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ADSP-21262

Table 25. Serial Ports—Enable and Three-State

Parameter

Min

2

Max

Unit

Switching Characteristics

t_DDTEN

t_DDTTE

t_DDTIN

Data Enable from External Transmit SCLK¹

Data Disable from External Transmit SCLK¹

Data Enable from Internal Transmit SCLK¹

ns

7

–1

¹Referenced to drive edge.

Table 26. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

t_DDTLFSE

Data Delay from Late External Transmit FS or External Receive FS with

MCE = 1, MFD = 0¹

7

ns

t_DDTENFS

Data Enable for MCE = 1, MFD = 0¹

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DIA_P[20:0]

(SCLK)

t_SFSE/I

t_HFSE/I

DIA_P[20:0]

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DIA_P[20:0]

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE

SAMPLE

DRIVE

DIA_P[20:0]

(SCLK)

t_SFSE/I

t_HFSE/I

DIA_P[20:0]

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DIA_P[20:0]

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

NOTE

SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P[20:1] PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.

Figure 21. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified sample pair mode.

Rev. A

|

Page 30 of 44

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May 2004

ADSP-21262

DATA RECEIVE— INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE— EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(SCLK)

t_DFSI

t_DFSE

t_HFSE

t_HFSI

t_SFSI

t_SFSE

t_HOFSI

t_HOFSE

DAI_P[20:1]

(FS)

DAI_P[20:1]

(FS)

t_HDRE

t_SDRI

t_HDRI

t_SDRE

DAI_P[20:1]

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT — INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT — EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(SCLK)

t_DFSI

t_DFSE

t_HFSI

t_HOFSI

t_SFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P[20:1]

(FS)

DAI_P[20:1]

(FS)

t_DDTE

t_DDTI

t_HDTE

t_HDTI

DAI_P[20:1]

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

DAI_P[20:1]

SCLK (EXT)

SCLK

t_DDTEN

t_DDTTE

DAI_P[20:1]

(DATA CHANNEL A/B)

DRIVE EDGE

DAI_P[20:1]

SCLK (INT)

t_DDTIN

DAI_P[20:1]

(DATA CHANNEL A/B)

Figure 22. Serial Ports

Rev. A

|

Page 31 of 44

|

May 2004

ADSP-21262

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 27. IDP

Signals (SCLK, FS, SDATA) are routed to the DAI_P[20:1] pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P[20:1] pins.

Table 27. Input Data Port

Parameter

Min

Max

Unit

Timing Requirements

t_SISFS

FS Setup Before SCLK Rising Edge¹

FS Hold After SCLK Rising Edge¹

SData Setup Before SCLK Rising Edge¹

SData Hold After SCLK Rising Edge¹

Clock Width

2.5

7

ns

t_SIHFS

t_SISD

t_SIHD

t_IDPCLKW

t_IDPCLK

Clock Period

20

¹DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the Precision Clock Generators (PCG) or SPORTs. PCG's input can be either

CLKIN or any of the DAI pins.

SAMPLE EDGE

t_IDPCLKW

DAI_P[20:1]

(SCLK)

t_SIHFS

t_SISFS

DAI_P[20:1]

(FS)

t_SISD

t_SIHD

DAI_P[20:1]

(SDATA)

Figure 23. IDP Master Timing

Rev. A

|

Page 32 of 44

|

May 2004

ADSP-21262

most significant 16 bits of external PDAP data can be provided

through either the parallel port AD[15:0] or the DAI_P[20:5]

pins. The remaining 4 bits can only be sourced through

DAI_P[4:1]. The timing below is valid at the DAI_P[20:1] pins

or at the AD[15:0] pins.

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 28. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the IDP, see the IDP

chapter of the ADSP-2126x Peripherals Manual. Note that the

Table 28. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

t_SPCLKEN

t_HPCLKEN

t_PDSD

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge¹

PDAP_CLKEN Hold After PDAP_CLK Sample Edge¹

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge¹

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge¹

Clock Width

2.5

7

ns

t_PDHD

t_PDCLKW

t_PDCLK

Clock Period

20

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRBPDAP Strobe Pulse Width

2 × t_CCLK

ns

1 × t_CCLK– 1

1

Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P[20:1]

(PDAP_CLK)

t_SPCLKEN

t_HPCLKEN

DAI_P[20:1]

(PDAP_CLKEN)

t_PDSD

t_PDHD

DATA

DAI_P[20:1]

(PDAP_STROBE)

t_PDSTRB

t_PDHLDD

Figure 24. PDAP Timing

Rev. A

|

Page 33 of 44

|

May 2004

ADSP-21262

SPI Interface—Master

Table 29. SPI Interface Protocol — Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Switching Characteristics

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

8 × t_CCLK

ns

Serial Clock High Period

4 × t_CCLK– 2

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

FLAG3-0 OUT (SPI device select) Low to First SPICLK Edge

Last SPICLK Edge to FLAG3-0 OUT High

Sequential Transfer Delay

3

10

4 × t_CCLK– 2

4 × t_CCLK– 1

t_SPITDM

Timing Requirements

t_SSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

5

2

ns

t_HSPIDM

FLAG3-0

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICHM

t_{D DSPIDM}

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0)

(OUTPUT)

t_SPICLM

SPICLK

(CP = 1)

(OUTPUT)

t_HDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

MSB

LSB

(INPUT)

VALID

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

t_HSPIDM

CPHASE = 0

MSB

VALID

LSB

VALID

MISO

(INPUT)

Figure 25. SPI Master Timing

Rev. A

|

Page 34 of 44

|

May 2004

ADSP-21262

SPI Interface—Slave

Table 30. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Switching Characteristics

t_DSOE

SPIDS Assertion to Data Out Active

0

5

ns

t_DSDHI

t_DDSPIDS

t_HDSPIDS

t_DSOV

SPIDS Deassertion to Data High Impedance

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHASE = 0)

5

7.5

2 × t_CCLK– 2

5 × t_CCLK+ 2

ns

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

Serial Clock Cycle

4 × t_CCLK

ns

Serial Clock High Period

Serial Clock Low Period

2 × t_CCLK– 2

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × t_CCLK+ 1

ns

t_HDS

Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE = 0)

2 × t_CCLK

ns

t_SSPIDS

t_HSPIDS

t_SDPPW

2

2 × t_CCLK

SPIDS

(INPUT)

t_{SPIC HS}

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0)

(INPUT)

t_SPICLS

t_SDSCO

t_SPICHS

SPICLK

(CP = 1)

(INPUT)

t_DSDHI

t_HDSPIDS

t_DDSPIDS

t_DSOE

t_DDSPIDS

MISO

(OUTPUT)

MSB

LSB

t_HSPIDS

CPHASE = 1

t_SSPIDS

MOSI

(INPUT)

MSB VALID

LSB VALID

t_DSOV

t_{DSO E}

t_HDSPIDS

t_DDSPIDS

t_DSDHI

MISO

(OUTPUT)

LSB

MSB

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

MSB VALID

LSB VALID

(INPUT)

Figure 26. SPI Slave Timing

Rev. A

|

Page 35 of 44

|

May 2004

ADSP-21262

JTAG Test Access Port and Emulation

Table 31. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

20

5

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High¹

System Inputs Hold After TCK High¹

TRST Pulse Width

6

7

8

4t_CK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low²

7

ns

10

¹System Inputs = AD15-0, SPIDS, CLKCFG1-0, RESET, BOOTCFG1-0, MISO, MOSI, SPICLK, DAI_Px, FLAG3-0

²System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15-0, RD, WR, FLAG3-0, CLKOUT, EMU, ALE.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 27. IEEE 11499.1 JTAG Test Access Port

Rev. A

|

Page 36 of 44

|

May 2004

ADSP-21262

OUTPUT DRIVE CURRENTS

CAPACITIVE LOADING

Figure 28 shows typical I-V characteristics for the output driv-

ers of the ADSP-21262. The curves represent the current drive

capability of the output drivers as a function of output voltage.

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 29). Figure 33 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 31, Figure 32, and Figure 33 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% – 80%, V =

Min) vs. Load Capacitance.

40

V

OH

30

20

3.3V, 25° C

3.47V, 0° C

12.0

10

0

3.11V, 70° C

10.0

RISE

y = 0.0904x + 1.9426

FALL

-10

3.3V, 25° C

8.0

3.11V, 70° C

-20

6.0

V

-30

-40

OL

3.47V, 0° C

4.0

y = 0.0722x + 1.4042

0

0.5

1

1.5

2

2.5

3

3.5

SWEEP (V

) VOLTAGE (V)

DDEXT

2.0

0

Figure 28. ADSP-21262 Typical Drive

0

20

40

60

80

100

120

TEST CONDITIONS

LOAD CAPACITANCE (pF)

The ac signal specifications (timing parameters) appear in

Table 10 on Page 19 through Table 31 on Page 36. These include

output disable time, output enable time, and capacitive loading.

Figure 31. Typical Output Rise/Fall Time

(20%-80%, V_DDEXT= Max)

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 30. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

12

10

8

RISE

y = 0.0915x + 2.2207

FALL

50⍀

TO

6

4

2

0

1.5V

OUTPUT

y = 0.0728x +1.6336

30pF

0

20

40

60

80

100

120

Figure 29. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

LOAD CAPACITANCE (pF)

Figure 32. Typical Output Rise/Fall Time

(20%-80%, V_DDEXT= Min)

INPUT

OR

1.5V

OUTPUT

Figure 30. Voltage Reference Levels for AC Measurements

Rev. A

|

Page 37 of 44

|

May 2004

ADSP-21262

where:

7

6

5

4

T_A= Ambient Temperature °C

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heat sink is required.

y = 0.0904x - 2.712

Values of θ_JBare provided for package comparison and PCB

design considerations.

3

2

1

0

Table 32. Thermal Characteristics for 136-Ball BGA¹

Parameter

θ_JA

Condition

Typical

28.2

24.4

23.3

20.1

7.0

Unit

°C/W

-1

-2

-3

-4

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

θ_JMA

0

20

40

60

80

100

120

θ_JB

θ_JC

LOAD CAPACITANCE (pF)

Ψ_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.1

Figure 33. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

Ψ_JMT

0.3

Ψ_JMT

0.4

¹The thermal characteristics values provided in this table are modeled values.

ENVIRONMENTAL CONDITIONS

Table 33. Thermal Characteristics for 144-Lead LQFP¹

The ADSP-21262 processor is rated for performance over the

commercial temperature range, T_AMB= 0°C to 70°C.

Parameter

θ_JA

Condition

Typical

32.5

28.9

27.8

7.8

Unit

°C/W

THERMAL CHARACTERISTICS

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

Table 32 and Table 33 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. The junction-to-

case measurement complies with MIL-STD-883. All measure-

ments use a 2S2P JEDEC test board.

θ_JMA

θ_JC

Ψ_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.5

Ψ_JMT

0.8

To determine the Junction Temperature of the device while on

the application PCB, use:

Ψ_JMT

1.0

¹The thermal characteristics values provided in this table are modeled values.

T = T

+ (Ψ × P )

JT

D

J

CASE

where:

T_J= Junction temperature °C

_CASE= Case temperature (°C) measured at the top center of the

T

package

Ψ_JT= Junction-to-Top (of package) characterization parameter

is the Typical value from Table 32 and Table 33.

P_D= Power dissipation (see EE Note #216)

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first order approxi-

mation of T_Jby the equation:

T = T + (θ × P )

J

A

JA

D

Rev. A

|

Page 38 of 44

|

May 2004

ADSP-21262

136-BALL BGA PIN CONFIGURATIONS

The following table and shows the ADSP-21262’s pin names

and their default function after reset (in parentheses). Figure 34

on Page 41 shows the BGA package pin assignments.

Table 34. 136-Ball BGA Pin Assignments

Pin Name

BGA Pin Pin Name

No.

BGA Pin Pin Name

No.

BGA Pin Pin Name

No.

BGA Pin

No.

CLKCFG0

XTAL

TMS

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

E01

E02

E04

E05

E06

E09

E10

E11

E13

E14

CLKCFG1

GND

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

F01

F02

F04

F05

F06

F09

F10

F11

F13

F14

BOOTCFG1

BOOTCFG0

GND

C01

C02

C03

C12

C13

C14

V_DDINT

GND

V_DDINT

D01

D02

D04

D05

D06

D09

D10

D11

D13

D14

V_DDEXT

CLKIN

TRST

TCK

GND

TDI

GND

CLKOUT

TDO

A_VSS

V_DDINT

A_VDD

EMU

V_DDEXT

SPICLK

RESET

V_DDINT

GND

MOSI

MISO

SPIDS

V_DDINT

GND

V_DDINT

GND

FLAG3

GND

FLAG1

FLAG0

GND

AD7

G01

G02

G13

G14

AD6

H01

H02

V_DDINT

V_DDEXT

DAI_P18 (SD5B)

DAI_P17 (SD5A)

H13

H14

GND

DAI_P19 (SCLK45)

GND

FLAG2

DAI_P20 (SFS45)

Rev. A

|

Page 39 of 44

|

May 2004

ADSP-21262

Table 34. 136-Ball BGA Pin Assignments (Continued)

Pin Name

BGA Pin Pin Name

No.

BGA Pin Pin Name

No.

BGA Pin Pin Name

No.

BGA Pin

No.

AD5

J01

AD3

K01

K02

K04

K05

K06

K09

K10

K11

K13

K14

P01

P02

P03

P04

P05

P06

P07

P08

P09

P10

P11

P12

P13

P14

AD2

L01

L02

L04

L05

L06

L09

L10

L11

L13

L14

AD0

M01

M02

M03

M12

M13

M14

AD4

J02

V_DDINT

AD1

WR

GND

J04

GND

J05

GND

J06

GND

DAI_P12 (SD3B)

DAI_P13 (SCLK23)

GND

J09

GND

J10

GND

J11

GND

V_DDINT

J13

GND

DAI_P16 (SD4B)

AD15

J14

DAI_P15 (SD4A)

AD14

DAI_P14 (SFS23)

N01

N02

N03

N04

N05

N06

N07

N08

N09

N10

N11

N12

N13

N14

ALE

AD13

RD

AD12

V_DDINT

AD11

V_DDEXT

AD10

AD8

AD9

V_DDINT

DAI_P1 (SD0A)

DAI_P3 (SCLK0)

DAI_P5 (SD1A)

DAI_P6 (SD1B)

DAI_P7 (SCLK1)

DAI_P8 (SFS1)

DAI_P9 (SD2A)

DAI_P11 (SD3A)

DAI_P2 (SD0B)

V_DDEXT

DAI_P4 (SFS0)

V_DDINT

GND

DAI_P10 SD2B)

Rev. A

|

Page 40 of 44

|

May 2004

ADSP-21262

14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

KEY

V

A

VDD

GND*

DDINT

V

A

I/O SIGNALS

DDEXT

VSS

*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHWAYS TO YOUR PRINTED

CIRCUIT BOARD’S GROUND PLANE.

Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary)

Rev. A

|

Page 41 of 44

|

May 2004

ADSP-21262

144-LEAD LQFP PIN CONFIGURATIONS

The following table shows the ADSP-21262’s pin names and

their default function after reset (in parentheses).

Table 35. 144-Lead LQFP Pin Assignments

Pin Name

LQFP

Pin Name

LQFP

Pin Name

LQFP

Pin Name

LQFP

Pin No.

V_DDINT

CLKCFG0

CLKCFG1

BOOTCFG0

BOOTCFG1

GND

1

V_DDINT

GND

RD

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

V_DDEXT

73

74

75

76

77

78

79

GND

V_DDINT

GND

V_DDINT

GND

V_DDINT

GND

V_DDEXT

GND

V_DDINT

GND

V_DDINT

RESET

SPIDS

GND

V_DDINT

SPICLK

MISO

MOSI

GND

V_DDINT

V_DDEXT

A_VDD

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

2

GND

3

V_DDINT

4

ALE

GND

5

AD15

AD14

AD13

GND

V_DDEXT

AD12

V_DDINT

GND

AD11

AD10

AD9

DAI_P10 (SD2B)

DAI_P11 (SD3A)

DAI_P12 (SD3B)

6

V_DDEXT

GND

7

8

DAI_P13 (SCLK23) 80

V_DDINT

GND

9

DAI_P14 (SFS23)

DAI_P15 (SD4A)

V_DDINT

81

82

83

84

85

86

87

88

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

V_DDINT

GND

V_DDINT

GND

DAI_P16 (SD4B)

DAI_P17 (SD5A)

DAI_P18 (SD5B)

FLAG0

FLAG1

AD7

AD8

DAI_P1 (SD0A) 53

DAI_P19 (SCLK45) 89

GND

V_DDINT

GND

54

55

V_DDINT

GND

90

V_DDINT

GND

91

DAI_P2 (SD0B) 56

DAI_P3 (SCLK0) 57

GND

92

V_DDEXT

GND

V_DDEXT

DAI_P20 (SFS45)

GND

93

GND

V_DDEXT

V_DDINT

GND

58

59

60

61

94

V_DDINT

AD6

95

V_DDINT

FLAG2

FLAG3

V_DDINT

GND

96

A_VSS

AD5

97

GND

CLKOUT

EMU

AD4

DAI_P4 (SFS0) 62

DAI_P5 (SD1A) 63

DAI_P6 (SD1B) 64

DAI_P7 (SCLK1) 65

98

V_DDINT

GND

99

100

101

102

103

104

105

106

107

108

TDO

AD3

V_DDINT

GND

TDI

AD2

V_DDINT

GND

V_DDINT

GND

66

67

68

69

TRST

TCK

V_DDEXT

GND

V_DDINT

GND

TMS

AD1

V_DDINT

GND

CLKIN

XTAL

V_DDEXT

AD0

DAI_P8 (SFS1) 70

DAI_P9 (SD2A) 71

WR

V_DDINT

72

Rev. A

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May 2004

ADSP-21262

PACKAGE DIMENSIONS

The ADSP-21262 is available in a 136-ball BGA package and a

144-lead LQFP package shown in Figure 35 and Figure 36.

10.40 BSC SQ

12.00 BSC SQ

0.80

BSC

TYP

A

B

C

D

E

F

PIN A1 INDICATOR

G

H

J

K

L

M

N

P

0.80

BSC

TYP

14 13 12 11 10 9

8

7

6

5

4

3

2

1

BOTTOM VIEW

TOP VIEW

1.70

MAX

1.31

1.21

1.10

DETAIL A

0.25

MIN

SEATING

PLANE

0.50

0.46

0.40

1. DIMENSIONS ARE IN MILIMETERS (MM).

2. THE ACTUAL POSITION OF THE BALL GRID IS

WITHIN 0.150 MM OF ITS IDEAL POSITION RELATIVE

TO THE PACKAGE EDGES.

0.12 MAX (BALL

COPLANARITY)

(BALL

DIAMETER)

3. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 MM

OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.

4. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR

THE BALL DIAMETER.

DETAIL A

5. CENTER DIMENSIONS ARE NOMINAL.

Figure 35. 136-Ball BGA (BC-136)

Rev. A

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May 2004

ADSP-21262

22.00 BSC SQ

20.00 BSC SQ

109

144

1

108

PIN 1 INDICATOR

0.50

0.27

TYP

BSC

TYP

(LEAD

PITCH)

0.22

0.17

SEATING

PLANE

0.08 MAX (LEAD

COPLANARITY)

1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY

WITH JEDEC STANDARD MS-026-BFB.

0.15

0.05

2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08

OF ITS IDEAL POSITION WHEN MEASURED IN THE

LATERAL DIRECTION.

1.45

1.40

1.35

0.75

3. CENTER DIMENSIONS ARE NOMINAL.

0.60 TYP

0.45

73

3 6

72

37

1.60 MAX

DETAIL A

TOP VIEW (PINS DOWN)

Figure 36. 144-Lead LQFP (ST-144)

ORDERING GUIDE

Part Number

Ambient Temperature Instruction

On-Chip

SRAM

ROM

Operating Voltage Package¹

Range

Rate

ADSP-21262SKBC-200

ADSP-21262SKBCZ200²

ADSP-21262SKSTZ200²

0°C to +70°C

200 MHz

2 Mbit

4 Mbit

1.2 INT/3.3 EXT V

136-Lead BGA

144-Lead LQFP

¹BC indicates Ball Grid Array package. ST indicates Low Profile Quad Flat package.

²Z = Pb-free part. For more information about lead-free package offerings, please visit www.analog.com.

registered trademarks are the property of their respective owners.

D04442–0–4/04(A)

Rev. A

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Page 44 of 44

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May 2004


型号：	ADSP-21262SKBC-200
厂家：	ADI
描述：	SHARC Processor SHARC处理器
文件：	总44页 (文件大小：1303K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21262SKBC-200 [ADI]

相关型号：

ADSP-21262SKBC-200X

ADSP-21262SKBCZ200

ADSP-21262SKSTZ200

ADSP-21262SKSTZX

ADSP-21262_05

ADSP-21266

ADSP-21266SKBC-200X

ADSP-21266SKBC-2B

ADSP-21266SKBCZ-2B

ADSP-21266SKBCZ-2C

ADSP-21266SKBCZ-2D

ADSP-21266SKSTZ-150X