ADSP-21364WSQZ-2AA_技术文档

SHARC^®Processor

ADSP-21364

a

On-chip memory—3M bit of on-chip SRAM and a dedicated

4M bit of on-chip mask-programmable ROM

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for professional audio processing

Code compatible with all other members of the SHARC family

The ADSP-21364 is available with a 333 MHz core instruction

rate and unique audiocentric peripherals such as the digi-

tal audio interface, S/PDIF transceiver, serial ports, 8-

channel asynchronous sample rate converter, precision

clock generators, and more. For complete ordering infor-

mation, see Ordering Guide on Page 53.

At 333 MHz/2 GFLOPs, with unique audio centric peripherals

such as the digital audio interface that includes a high-pre-

cision 8-channel asynchronous sample rate converter

among others, the ADSP-21364 SHARC processor is ideal

for applications that require industry leading equalization,

reverberation and other effects processing

Single-instruction, multiple-data (SIMD) computational

architecture

Two 32-bit IEEE floating-point/32-bit fixed-point/40-bit

extended precision floating-point computational units,

each with a multiplier, ALU, shifter, and register file

4 BLOCKS OF ON-CHIP MEMORY

CORE PROCESSOR

INSTRUCTION

BLOCK 0

SRAM

BLOCK 1

BLOCK 2

BLOCK 3

SRAM

1M BIT

CACHE

TIMER

SRAM

0.5M BIT

SRAM

0.5M BIT

1M BIT ROM

ROM

2M BIT

32 X 48-BIT

2M BIT

ADDR

DATA

ADDR

DATA

ADDR

DATA

ADDR

DATA

DAG1

8X4X32

DAG2

8X4X32

PROGRAM

SEQUENCER

32

PM ADDRESS BUS

32

64

DM ADDRESS BUS

PM DATA BUS

64

DM DATA BUS

IOA

IOD

IOA

IOD

IOA

IOD

IOA

IOD

PX REGISTER

SPI

SPORTS

IDP

PCG

TIMERS

SRC

PROCESSING

ELEMENT

(PEX)

PROCESSING

ELEMENT

(PEY)

IOP REGISTERS

(MEMORY MAPPED)

SIGNAL

ROUTING

UNIT

SPDIF

6

JTAG TEST AND EMULATION

I/O PROCESSOR

AND PERIPHERALS

SEE ADSP-21364 MEMORY

AND I/O INTERFACE FEATURES

SECTION FOR DETAILS

S

Figure 1. Functional Block Diagram—Processor Core

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.326.3113

www.analog.com

ADSP-21364

Up to 12 TDM stream support, each with 128 channels per

frame

KEY FEATURES—PROCESSOR CORE

At 333 MHz (3.0 ns) core instruction rate, the ADSP-21364

performs 2 GFLOPS/666 MMACS

3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit

in blocks 2 and 3) for simultaneous access by core proces-

sor and DMA

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

4M bit on-chip, single-ported mask-programmable ROM (2M

bit in block 0 and 2M bit in block 1)

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single-instruction multiple-data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution

Code compatibility with other SHARC family members at

the assembly level

Companding selection on a per channel basis in TDM mode

Input data port provides an additional input path to the

SHARC core, configurable as eight channels of serial data

or seven channels of serial data and up to a 20-bit wide

parallel data channel

Signal routing unit provides configurable and flexible con-

nections between all DAI components–six serial ports, two

precision clock generators, an input data port with a data

acquisition port, one SPI port, eight channels of asynchro-

nous sample rate converters, three timers, 10 interrupts,

six flag inputs, six flag outputs, and 20 SRU I/O pins

(DAI_Px)

Two serial peripheral interfaces (SPI): primary on dedicated

pins, secondary on DAI pins provide:

Master or slave serial boot through primary SPI

Full-duplex operation

Master slave mode multimaster support

Open drain outputs

Programmable baud rates, clock polarities and phases

3 Muxed Flag/IRQ lines

Parallelism in buses and computational units allows single

cycle execution (with or without SIMD) of a multiply or

ALU operation, a dual memory read or write, and an

instruction fetch

Transfers between memory and core at a sustained 5.4

Gbytes/s bandwidth at 333 MHz core instruction rate

1 Muxed Flag/Timer expired line

DEDICATED AUDIO COMPONENTS

S/PDIF-compatible digital audio receiver/transmitter

supports:

INPUT/OUTPUT FEATURES

DMA controller supports:

25 DMA channels for transfers between ADSP-21364 internal

memory and a variety of peripherals

32-bit DMA transfers at peripheral clock speed, in parallel

with full-speed processor execution

Asynchronous parallel port provides access to asynchronous

external memory

16 multiplexed address/data lines support 24-bit address

external address range with 8-bit data or 16-bit address

external address range with 16-bit data

EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

Left-justified, I²S or right-justified serial data input with

16-, 18-, 20- or 24-bit word widths (transmitter)

Two channel mode and single channel double frequency

(SCDF) mode

Four independent asynchronous sample rate converters

(SRC). Each converter has separate serial input and output

ports, a deemphasis filter providing up to –140dB SNR per-

formance, stereo sample rate converter (SRC) and supports

left-justified, I²S, TDM, and right-justified modes and 24-,

20-, 18-, and 16- audio data word lengths

55 Mbyte per sec transfer rate

External memory access in a dedicated DMA channel

8-bit to 32-bit and 16-bit to 32-bit packing options

Programmable data cycle duration: 2 to 31 CCLK

Digital audio interface (DAI) includes six serial ports, two pre-

cision clock generators, an input data port, three timers,

eight-channel asynchronous sample rate converter, and a

signal routing unit

Six dual data line serial ports that operate at up to 50M bit/s

on each data line—each has a clock, frame sync, and two

data lines that can be configured as either a receiver or

transmitter pair

Pulse-width modulation provides:

16 PWM outputs configured as four groups of four outputs

Supports center-aligned or edge-aligned PWM waveforms

Can generate complementary signals on two outputs in

paired mode or independent signals in nonpaired mode

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Dual voltage: 3.3 V I/O, 1.2 V, or 1.0 V core

Available in 136-ball BGA and 144-lead LQFP Packages

Left-justified sample pair and I²S support, programmable

direction for up to 24 simultaneous receive or transmit

channels using two I²S-compatible stereo devices per

serial port

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110

Rev. 0

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ADSP-21364

CONTENTS

Summary ................................................................1

Key Features—Processor Core ..................................2

Input/Output Features ............................................2

Dedicated Audio Components ..................................2

General Description ..................................................4

ADSP-21364 Family Core Architecture .......................4

ADSP-21364 Memory and I/O Interface Features ..........6

Development Tools ................................................9

Additional Information ......................................... 10

Pin Function Descriptions ........................................ 11

Address Data Pins as Flags ..................................... 14

Address Data Modes ............................................. 14

Boot Modes ........................................................ 14

Core Instruction Rate to CLKIN Ratio Modes ............. 14

ADSP-21364 Specifications ....................................... 15

Recommended Operating Conditions ....................... 15

Electrical Characteristics ........................................ 15

Maximum Power Dissipation ................................. 16

Absolute Maximum Ratings ................................... 16

ESD Sensitivity .................................................... 16

Timing Specifications ........................................... 17

Output Drive Currents .......................................... 45

Test Conditions ................................................... 45

Capacitive Loading ............................................... 45

Thermal Characteristics ........................................ 46

136-Ball BGA Pin Configurations ............................... 47

144-Lead LQFP Pin Configurations ............................. 50

Outline Dimensions ................................................ 51

Ordering Guide ...................................................... 53

REVISION HISTORY

10/05—Revision 0: Initial Version

Rev. 0

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ADSP-21364

GENERAL DESCRIPTION

The ADSP-21364 SHARC processor is a member of the SIMD

SHARC family of DSPs that feature Analog Devices’ Super Har-

vard Architecture. The ADSP-21364 is source code compatible

with the ADSP-2126x, and ADSP-2116x DSPs as well as with

first generation ADSP-2106x SHARC processors in SISD (sin-

gle-instruction, single-data) mode. The ADSP-21364 is a 32-

bit/40-bit floating-point processor optimized for professional

audio applications with a large on-chip SRAM, multiple internal

buses to eliminate I/O bottlenecks, and an innovative digital

audio interface (DAI).

• On-chip mask-programmable ROM (4M bit)

• 8-bit or 16-bit parallel port that supports interfaces to off-

chip memory peripherals

• JTAG test access port

The block diagram of the ADSP-21364 on Page 7, illustrates the

following architectural features:

• DMA controller

• Six full duplex serial ports

• Two SPI-compatible interface ports—primary on dedi-

cated pins secondary on DAI pins

As shown in the functional block diagram on Page 1, the

ADSP-21364 uses two computational units to deliver a signifi-

cant performance increase over previous SHARC processors on

a range of signal processing algorithms. Fabricated in a state-of-

the-art, high speed, CMOS process, the ADSP-21364 processor

achieves an instruction cycle time of 3.0 ns at 333 MHz. With its

SIMD computational hardware, the ADSP-21364 can perform 2

GFLOPS running at 333 MHz.

• Digital audio interface that includes two precision clock

generators (PCG), an input data port (IDP), an S/PDIF

receiver/transmitter, eight channels asynchronous sample

rate converters, six serial ports, eight serial interfaces, a 20-

bit parallel input port, 10 interrupts, six flag outputs, six

flag inputs, three timers, and a flexible signal routing unit

(SRU)

Table 1 shows performance benchmarks for the ADSP-21364

running at 333 MHz.

Figure 2 on Page 5 shows one sample configuration of a SPORT

using the precision clock generators to interface with an I²S

ADC and an I²S DAC with a much lower jitter clock than the

serial port would generate itself. Many other SRU configura-

tions are possible.

Table 1. Benchmarks at 333 MHz

Benchmark Algorithm

Speed

(at 333 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs

ADSP-21364 FAMILY CORE ARCHITECTURE

FIR Filter (per tap)¹

1.5 ns

6.0 ns

The ADSP-21364 is code compatible at the assembly level with

the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the

first generation ADSP-2106x SHARC DSPs. The ADSP-21364

shares architectural features with the ADSP-2126x and

ADSP-2116x SIMD SHARC processors, as detailed in the fol-

lowing sections.

IIR Filter (per biquad)¹

Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1]

13.5 ns

23.9 ns

Divide (y/x)

10.5 ns

16.3 ns

Inverse Square Root

SIMD Computational Engine

¹Assumes two files in multichannel SIMD mode

The ADSP-21364 contains two computational processing ele-

ments that operate as a single-instruction multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter, and register file.

PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive signal

processing algorithms.

The ADSP-21364 continues SHARC’s industry-leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features.

The block diagram of the ADSP-21364 on Page 1, illustrates the

following architectural features:

• Two processing elements, each of which comprises an

ALU, multiplier, shifter and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

• Three programmable interval timers with PWM genera-

tion, PWM capture/pulse width measurement, and

external event counter capabilities

• On-chip SRAM (3M bit)

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ADSP-21364

CLKOUT

CLKIN

XTAL

CLOCK

ALE

2

LATCH

AD1 5-0

ADDR

CLK_CFG1-0

BOOTCFG1-0

FLAG3-1

PARALLEL

PORT

RAM, ROM

BOO T ROM

I/O DEVICE

2

3

DATA

OE

RD

WR

WE

FLAG0

CS

ADC

(OPTIONAL)

CLK

FS

DAI_P1

DAI_ P2

DAI_ P3

SDAT

SCLK0

SFS0

SRU

SD0A

SD0B

DAC

(OPTIONAL)

CLK

DAI_P18

DAI_P19

DAI_ P2 0

SPORT0-5

TIMERS

SPDIF

FS

SDAT

SRC

IDP

SPI

CLK

FS

PCGA

PCGB

DAI

RESET

JTAG

6

Figure 2. ADSP-21364 System Sample Configuration

Independent, Parallel Computation Units

Single-Cycle Fetch of Instruction and Four Operands

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit, single-

precision floating-point, 40-bit, extended-precision floating-

point, and 32-bit, fixed-point data formats.

The ADSP-21364 features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1 on Page 1). With the ADSP-21364’s separate pro-

gram and data memory buses and on-chip instruction cache,

the processor can simultaneously fetch four operands (two over

each data bus) and one instruction (from the cache), all in a sin-

gle cycle.

Instruction Cache

The ADSP-21364 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Register File

A general-purpose data register file is contained in each

processing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

register files, combined with the ADSP-2136x enhanced Har-

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0–R15 and in PEY as S0–S15.

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

The ADSP-21364’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

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ADSP-21364

signal processing, and are commonly used in digital filters and

Fourier transforms. The two DAGs of the ADSP-21364 contain

sufficient registers to allow the creation of up to 32 circular buff-

ers (16 primary register sets, 16 secondary). The DAGs

automatically handle address pointer wraparound, reduce over-

head, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

On-Chip Memory

The ADSP-21364 contains three megabits of internal SRAM.

Each block can be configured for different combinations of code

and data storage (see Table 2 on Page 6). Each memory block

supports single-cycle, independent accesses by the core proces-

sor and I/O processor. The ADSP-21364 memory architecture,

in combination with its separate on-chip buses, allow two data

transfers from the core and one from the I/O processor, in a sin-

gle cycle.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21364 can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

The ADSP-21364’s SRAM can be configured as a maximum of

96K words of 32-bit data, 192K words of 16-bit data, 64K words

of 48-bit instructions (or 40-bit data), or combinations of differ-

ent word sizes up to three megabits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-

ing-point storage format is supported that effectively doubles

the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point for-

mats is performed in a single instruction. While each memory

block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

ADSP-21364 MEMORY AND I/O INTERFACE

FEATURES

The ADSP-21364 adds the following architectural features to

the SIMD SHARC family core.

Table 2. ADSP-21364 Internal Memory Space

IOP Registers 0x0000 0000–0003 FFFF

ExtendedPrecisionNormalor

Long Word (64 Bits)

Instruction Word (48 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

BLOCK 0 ROM

0x0004 0000–0x0004 7FFF

0x0008 0000–0x0008 AAA9

0x0008 0000–0x0008 FFFF

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 BFFF

0x0009 0000–0x0009 7FFF

0x0012 0000–0x0012 FFFF

BLOCK 0 RAM

0x0004 C000–0x0004 FFFF

0x0009 0000–0x0009 5554

0x0009 8000–0x0009 FFFF

0x0013 0000–0x0013 FFFF

BLOCK 1 ROM

0x0005 0000–0x0005 7FFF

0x000A 0000–0x000A AAA9

0x000A 0000–0x000A FFFF

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 BFFF

0x000B 0000–0x000B 7FFF

0x0016 0000–0x0016 FFFF

BLOCK 1 RAM

0x0005 C000–0x0005 FFFF

0x000B 0000–0x000B 5554

0x000B 8000–0x000B FFFF

0x0017 0000–0x0017 FFFF

BLOCK 2 RAM

0x0006 0000–0x0006 1FFF

0x000C 0000–0x000C 2AA9

0x000C 0000–0x000C 3FFF

0x0018 0000–0x0018 7FFF

Reserved

0x0006 2000–0x0006 FFFF

0x000C 4000–0x000D FFFF

0x0018 8000–0x001B FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 1FFF

0x000E 0000–0x000E 2AA9

0x000E 0000–0x000E 3FFF

0x001C 0000–0x001C 7FFF

Reserved

0x0007 2000–0x0007 FFFF

0x000E 4000–0x000F FFFF

0x001C 8000–0x001F FFFF

Reserved

0x0020 0000–0xFFFF FFFF

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ADSP-21364

Using the DM bus and PM buses, with one dedicated to each

memory block assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

Digital Audio Interface (DAI)

The digital audio interface (DAI) provides the ability to connect

various peripherals to any of the SHARC’s DAI pins

(DAI_P20–1).

DMA Controller

Programs make these connections using the signal routing unit

(SRU, shown in Figure 3).

The ADSP-21364’s on-chip DMA controller allows data trans-

fers without processor intervention. The DMA controller

operates independently and invisibly to the processor core,

allowing DMA operations to occur while the core is simulta-

neously executing its program instructions. DMA transfers can

occur between the ADSP-21364’s internal memory and its serial

ports, the SPI-compatible (serial peripheral interface) ports, the

IDP (input data port), the parallel data acquisition port (PDAP),

or the parallel port. Twenty-five channels of DMA are available

on the ADSP-21364—two for the SPI interface, two for mem-

ory-to-memory transfers, 12 via the serial ports, eight via the

input data port, and one via the processor’s parallel port. Pro-

grams can be downloaded to the ADSP-21364 using DMA

transfers. Other DMA features include interrupt generation

upon completion of DMA transfers, and DMA chaining for

automatic linked DMA transfers.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI-

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

The DAI also includes six serial ports, two precision clock gen-

erators (PCGs), eight channels of asynchronous sample rate

converters, an input data port (IDP), an SPI port, six flag out-

puts and six flag inputs, and three timers. The IDP provides an

additional input path to the ADSP-21364 core, configurable as

either eight channels of I²S serial data or as seven channels plus

a single 20-bit wide synchronous parallel data acquisition port.

Each data channel has its own DMA channel that is indepen-

dent from the ADSP-21364’s serial ports.

For complete information on using the DAI, see the ADSP-

2136x SHARC Processor Hardware Reference .

TO PROCESSOR BUSES AND

SYSTEM MEMORY

Serial Ports

IO DATA

BUS (32)

IO ADDRESS

BUS (18)

The ADSP-21364 features six synchronous serial ports that pro-

vide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

4

3

GPIO FLAGS/IRQ/TIMEXP

DMA CONTROLLER

25 CHANNELS

CONTROL/GPIO

16

ADDRESS/DATA BUS/ GPIO

PARALLEL PORT

Serial ports are enabled via 12 programmable and simultaneous

receive or transmit pins that support up to 24 transmit or 24

receive channels of audio data when all six SPORTS are enabled,

or six full duplex TDM streams of 128 channels per frame.

PWM (16)

SPI PORT (1)

4

The serial ports operate at a maximum data rate of 50M bits/s.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

SPI PORT (1)

SERIAL PORTS (6)

INPUT

DATA PORTS (8)

20

PRECISION CLOCK

GENERATORS (2)

Serial ports operate in four modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I²S mode

3

TIMERS (3)

SPDIF (RX/TX)

SRC (8 CHANNELS)

• Left-justified sample pair mode

DIGITAL AUDIO INTERFACE

I/O PROCESSOR

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Figure 3. ADSP-21364 I/O Processor and Peripherals Block Diagram

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ADSP-21364

Each of the serial ports supports the left-justified sample pair

and I²S protocols (I²S is an industry standard interface com-

monly used by audio codecs, ADCs and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I²S channels (using two stereo

devices) per serial port, with a maximum of up to 24 I²S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I²S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional μ-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

The sample rate converter (SRC) contains four SRC blocks and

is the same core as that used in the AD1896 192 kHz stereo

asynchronous sample rate converter providing up to 140 dB

SNR. The SRC block is used to perform synchronous or asyn-

chronous sample rate conversion across independent stereo

channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to con-

vert multichannel audio data without phase mismatches.

Finally, the SRC is used to clean up audio data from jittery clock

sources such as the S/PDIF receiver.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

Parallel Port

The parallel port provides interfaces to SRAM and peripheral

devices. The multiplexed address and data pins (AD15–0) can

access 8-bit devices with up to 24 bits of address, or 16-bit

devices with up to 16 bits of address. In either mode, 8- or 16-

bit, the maximum data transfer rate is 55M bytes/sec.

DMA transfers are used to move data to and from internal

memory. Access to the core is also facilitated through the paral-

lel port register read/write functions. The RD, WR, and ALE

(address latch enable) pins are the control pins for the parallel

port.

The entire PWM module has four groups of four PWM outputs

each. Therefore this module generates 16 PWM outputs in total.

Each PWM group produces two pairs of PWM signals on the

four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode, or double update mode. In single update mode

the duty cycle values are programmable only once per PWM

period. This results in PWM patterns that are symmetrical

around the midpoint of the PWM period. In double update

mode, a second updating of the PWM registers is implemented

at the mid-point of the PWM period. In this mode, it is possible

to produce asymmetrical PWM patterns that produce lower

harmonic distortion in three-phase PWM inverters.

Serial Peripheral (Compatible) Interface

The ADSP-21364 SHARC processor contains two serial periph-

eral interface ports (SPIs). The SPI is an industry standard

synchronous serial link, enabling the ADSP-21364 SPI-compat-

ible port to communicate with other SPI-compatible devices.

The SPI consists of two data pins, one device select pin, and one

clock pin. It is a full-duplex synchronous serial interface, sup-

porting both master and slave modes. The SPI port can operate

in a multimaster environment by interfacing with up to four

other SPI-compatible devices, either acting as a master or slave

device. The ADSP-21364 SPI-compatible peripheral implemen-

tation also features programmable baud rate and clock phase

and polarities. The ADSP-21364 SPI-compatible port uses open

drain drivers to support a multimaster configuration and to

avoid data contention.

Timers

The ADSP-21364 has a total of four timers: a core timer able to

generate periodic software interrupts and three general-purpose

timers that can generate periodic interrupts and be indepen-

dently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

and Synchronous/Asynchronous Sample Rate Converter

The S/PDIF transmitter has no separate DMA channels. It

receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the transmitter

can be formatted as left-justified, I²S, or right-justified with

word widths of 16, 18, 20, or 24 bits.

The core timer can be configured to use FLAG3 as a timer

expired signal, and each general-purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables all three

general-purpose timers independently.

The serial data, clock, and frame sync inputs to the S/PDIF

transmitter are routed through the signal routing unit (SRU).

They can come from a variety of sources such as the SPORTs,

external pins, the precision clock generators (PCGs), or the

sample rate converters (SRC) and are controlled by the SRU

control registers.

Program Booting

The internal memory of the ADSP-21364 boots at system

power-up from an 8-bit EPROM via the parallel port, an SPI

master, an SPI slave or an internal boot. Booting is determined

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ADSP-21364

by the boot configuration (BOOTCFG1–0) pins (see Table 6 on

Page 14). Selection of the boot source is controlled via the SPI as

either a master or slave device.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User's Guide”.

Phase-Locked Loop

DEVELOPMENT TOOLS

The ADSP-21364 uses an on-chip phase-locked loop (PLL) to

generate the internal clock for the core. On power up, the

CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1

(see Table 7 on Page 14). After booting, numerous other ratios

can be selected via software control. The ratios are made up of

software configurable numerator values from 1 to 64 and soft-

ware configurable divisor values of 1, 2, 4, and 8.

The ADSP-21364 is supported with a complete set of

CROSSCORE^®software and hardware development tools,

including Analog Devices emulators and VisualDSP++^®devel-

opment environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-21364.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ run-time library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The SHARC has

architectural features that improve the efficiency of compiled

C/C++ code.

Power Supplies

The ADSP-21364 has separate power supply connections for the

internal (V_DDINT), external (V_DDEXT), and analog (A_VDD/A_VSS

)

power supplies. The internal and analog supplies must meet the

1.2 V requirement for K and B grade models, and the 1.0 V

requirement for W grade models. The external supply must

meet the 3.3 V requirement. All external supply pins must be

connected to the same power supply.

Note that the analog supply pin (A_VDD) powers the ADSP-

21364’s internal clock generator PLL. To produce a stable clock,

it is recommended that PCB designs use an external filter circuit

for the A_VDDpin. Place the filter components as close as possi-

ble to the A_VDD/A_VSSpins. For an example circuit, see Figure 4.

(A recommended ferrite chip is the muRata

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

BLM18AG102SN1D). To reduce noise coupling, the PCB

should use a parallel pair of power and ground planes for

V_DDINTand GND. Use wide traces to connect the bypass capac-

itors to the analog power (A_VDD) and ground (A_VSS) pins. Note

that the A_VDDand A_VSSpins specified in Figure 4 are inputs to

the processor and not the analog ground plane on the board—

the A_VSSpin should connect directly to digital ground (GND) at

the chip.

ADSP-213xx

100nF

10nF

1nF

A

V

VDD

DDINT

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

HI Z FERRITE

BEAD CHIP

• View mixed C/C++ and assembly code (interleaved source

and object information)

A

VSS

• Insert breakpoints

LOCATE ALL COMPONENTS

CLOSE TO A AND A PINS

VDD

VSS

• Set conditional breakpoints on registers, memory,

and stacks

Figure 4. Analog Power (A_VDD) Filter Circuit

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21364 pro-

cessor to monitor and control the target board processor during

emulation. Analog Devices DSP Tools product line of JTAG

emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-

sor stacks. The processor's JTAG interface ensures that the

emulator will not affect target system loading or timing.

• Create custom debugger windows

Rev. 0

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ADSP-21364

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

access port (TAP) on each JTAG DSP. Nonintrusive in-circuit

emulation is assured by the use of the processor’s JTAG inter-

face—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the processor, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The processor must be halted to send data and com-

mands, but once an operation has been completed by the

emulator, the processor system is set running at full speed with

no impact on system timing.

• Control how the development tools process inputs and

generate outputs

• Maintain a one-to-one correspondence with the tool’s

command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation plat-

forms to use as a cost-effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

the VisualDSP++ development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is

Analog Devices’ technology for creating, using, and reusing

software components (independent modules of substantial

functionality) to quickly and reliably assemble software applica-

tions. It also can be used for downloading components from the

Web, dropping them into the application, and publishing com-

ponent archives from within VisualDSP++. VCSE supports

component implementation in C/C++ or assembly language.

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the Visu-

alDSP++ evaluation suite to emulate the on-board processor in-

circuit. This permits the customer to download, execute, and

debug programs for the EZ-KIT Lite system. It also allows in-

circuit programming of the on-board Flash device to store user-

specific boot code, enabling the board to run as a standalone

unit without being connected to the PC.

Use the expert linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the processor or external memory with a

drag of the mouse, and examine run-time stack and heap usage.

The expert linker is fully compatible with the existing linker def-

inition file (LDF), allowing the developer to move between the

graphical and textual environments.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom defined system. Connecting one of Analog Devices JTAG

emulators to the EZ-KIT Lite board enables high speed, non-

intrusive emulation.

ADDITIONAL INFORMATION

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC processor PC plug-in cards. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

This data sheet provides a general overview of the ADSP-21364

architecture and functionality. For detailed information on the

ADSP-2136x family core architecture and instruction set, refer

to the ADSP-2136x SHARC Processor Hardware Reference and

the ADSP-2136x SHARC Processor Programming Reference.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every

developer needs to test and debug hardware and software sys-

tems. Analog Devices has supplied an IEEE 1149.1 JTAG test

Rev. 0

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ADSP-21364

PIN FUNCTION DESCRIPTIONS

ADSP-21364 pin definitions are listed below. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS and TDI). Inputs

identified as asynchronous (A) can be asserted asynchronously

to CLKIN (or to TCK for TRST). Tie or pull unused inputs to

• DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI,

and AD15–0 (Note: These pins have pull-up resistors.)

The following symbols appear in the Type column of Table 3:

A = asynchronous, G = ground, I = input, O = output,

P = power supply, S = synchronous, (A/D) = active drive, (O/D)

= open drain, and T = three-state, (pd) = pull-down resistor,

(pu) = pull-up resistor.

V_DDEXTor GND, except for the following:

Table 3. Pin Descriptions

State During and

After Reset

Type

Function

AD15–0

I/O/T

(pu)

Three-state with

pull-up enabled

Parallel Port Address/Data. The ADSP-21364 parallel port and its corresponding

DMA unit output addresses and data for peripherals on these multiplexed pins. The

multiplex state is determined by the ALE pin. The parallel port can operate in either

8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address

Data Modes on Page 14 for details of the AD pin operation.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper

16 external address bits, A23–8; ALE is used in conjunction with an external latch to

retain the values of the A23–8.

For detailed information on I/O operations and pin multiplexing, see the ADSP-2136x

SHARC Processor Hardware Reference .

RD

O

(pu)

Three-state, driven Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or

high¹

16-bit data from an external memory device. When AD15–0 are flags, this pin remains

deasserted. RD has a 22.5 kΩ internal pull-up resistor.

WR

ALE

O

(pu)

Three-state, driven Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or

high¹

16-bit data to an external memory device. When AD15–0 are flags, this pin remains

deasserted. WR has a 22.5 kΩ internal pull-up resistor.

O

(pd)

Three-state, driven Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives

low¹

a new address on the parallel port address pins. On reset, ALE is active high. However,

it can be reconfigured using software to be active low. When AD15–0 are flags, this

pin remains deasserted. ALE has a 20 kΩ internal pull-down resistor.

FLAG3–0

I/O/A

Three-state

Flag Pins. Each flag pin is configured via control bits as either an input or output. As

an input, it can be tested as a condition. As an output, it can be used to signal external

peripherals. These pins can be used as an SPI interface slave select output during SPI

mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. For

detailed information on I/O operations and pin multiplexing, see the ADSP-2136x

SHARC Processor Hardware Reference

DAI_P20–1

I/O/T

(pu)

Three-state with

programmable

pull-up

Digital Audio Interface Pins. These pins provide the physical interface to the SRU.

The SRU configuration registers define the combination of on-chip peripheral inputs

or outputs connected to the pin and to the pin’s output enable. The configuration

registers of these peripherals then determines the exact behavior of the pin. Any input

or output signal present in the SRU may be routed to any of these pins. The SRU

provides the connection from the serial ports, input data port, precision clock gener-

ators and timers, sample rate converters and SPI to the DAI_P20–1 pins These pins

have internal 22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can

be disabled in the DAI_PIN_PULLUP register.

Rev. 0

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ADSP-21364

Table 3. Pin Descriptions (Continued)

State During and

Type

After Reset

Function

SPICLK

I/O

(pu)

Three-state with

pull-up enabled

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls

the rate at which data is transferred. The master may transmit data at a variety of baud

rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active

during data transfers, only for the length of the transferred word. Slave devices ignore

the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift

out and shift in the data driven on the MISO and MOSI lines. The data is always shifted

out on one clock edge and sampled on the opposite edge of the clock. Clock polarity

and clock phase relative to data are programmable into the SPICTL control register

and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor.

SPIDS

I

Input only

Serial Peripheral Interface Slave Device Select. An active low signal used to select

the processor as an SPI slave device. This input signal behaves like a chip select, and

is provided by the master device for the slave devices. In multimaster mode the

processor’s SPIDS signal can be driven by a slave device to signal to the processor (as

SPI master) that an error has occurred, as some other device is also trying to be the

master device. If asserted low when the device is in master mode, it is considered a

multimaster error. For a single-master, multiple-slave configuration where flag pins

are used, this pin must be tied or pulled high to V_DDEXTon the master device. For

processor to processor SPI interaction, any of the master processor’s flag pins can be

used to drive the SPIDS signal on the SPI slave device.

MOSI

MISO

I/O (O/D)

(pu)

Three-state with

pull-up enabled

SPI Master Out Slave In. If the ADSP-21364 is configured as a master, the MOSI pin

becomes a data transmit (output) pin, transmitting output data. If the processor is

configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input

data. In an SPI interconnection, the data is shifted out from the MOSI output pin of the

master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal

pull-up resistor.

I/O (O/D)

(pu)

Three-state with

pull-up enabled

SPI Master In Slave Out. If the ADSP-21364 is configured as a master, the MISO pin

becomes a data receive (input) pin, receiving input data. If the processor is configured

as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output

data. In a SPI interconnection, the data is shifted out from the MISO output pin of the

slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal

pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL

register.

Note: Only one slave is allowed to transmit data at any given time. To enable broadcast

transmission to multiple SPI-slaves, the processor’s MISO pin may be disabled by

setting (=1) Bit 5 (DMISO) of the SPICTL register.

BOOTCFG1–0

CLKIN

I

Input only

Boot Configuration Select. This pin is used to select the boot mode for the processor.

The BOOTCFG pins must be valid before reset is asserted. See Table 6 for a description

of the boot modes.

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21364 clock input.

It configures the ADSP-21364 to use either its internal clock generator or an external

clock source. Connecting the necessary components to CLKIN and XTAL enables the

internal clock generator. Connecting the external clock to CLKIN while leaving XTAL

unconnected configures the processors to use the external clock source such as an

external clock oscillator. The core is clocked either by the PLL output or this clock input

depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or

operated below the specified frequency.

XTAL

O

I

Output only²

Input only

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

CLKCFG1–0

Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 7

for a description of the clock configuration modes. Note that the operating frequency

can be changed by programming the PLL multiplier and divider in the PMCTL register

at any time after the core comes out of reset.

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ADSP-21364

Table 3. Pin Descriptions (Continued)

State During and

Type

After Reset

Function

RSTOUT/CLKOUT O

Output only

Local Clock Out/Reset Out. Drives out the core reset signal to an external device.

CLKOUT can also be configured as a reset out pin. The functionality can be switched

between the PLL output clock and reset out by setting Bit 12 of the PMCTREG register.

The default is reset out.

RESET

I/A

Input only

Input only³

Processor Reset. Resets the ADSP-21364 to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from the hardware reset vector address. The RESET input must be

asserted (low) at power-up.

TCK

TMS

TDI

I

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the processors.

I/S

(pu)

Three-state with

pull-up enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ

internal pull-up resistor.

I/S

(pu)

Three-state with

pull-up enabled

Three-state⁴

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5

kΩ internal pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TDO

TRST

O

I/A

(pu)

Three-state with

pull-up enabled

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21364. TRST has a 22.5

kΩ internal pull-up resistor.

EMU

O (O/D)

(pu)

Three-state with

pull-up enabled

EmulationStatus. Mustbeconnected totheprocessor’s JTAGemulatorstargetboard

connector only. EMU has a 22.5 kΩ internal pull-up resistor.

V_DDINT

P

Core Power Supply. Nominally +1.2 V dc for the K and B grade models, and 1.0 V dc

for the W grade models, and supplies the processor’s core (13 pins on the BGA

package, 32 pins on the LQFP package).

V_DDEXT

A_VDD

P

I/O Power Supply. Nominally +3.3 V dc. (6 pins on the BGA package, 10 pins on the

LQFP package).

Analog Power Supply. Nominally +1.2 V dc for the K and B grade models, and 1.0 V

dc for the W grade models, and supplies the processor’s internal PLL (clock generator).

This pin has the same specifications as V_DDINT, except that added filtering circuitry is

required. For more information, see Power Supplies on Page 9.

A_VSS

G

Analog Power Supply Return.

GND

Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

¹RD, WR, and ALE are three-stated (and not driven) only when RESET is active.

²Output only is a three-state driver with its output path always enabled.

3

Input only is a three-state driver with both output path and pull-up disabled.

⁴Three-state is a three-state driver with pull-up disabled.

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ADSP-21364

ADDRESS DATA PINS AS FLAGS

BOOT MODES

To use these pins as flags (FLAGS15–0) set (=1) Bit 20 of the

SYSCTL register to disable the parallel port. Then set (=1) Bits

22 to 25 in the SYSCTL register accordingly.

Table 6. Boot Mode Selection

BOOTCFG1–0

Booting Mode

00

01

10

SPI Slave Boot

Table 4. AD15–0 to Flag Pin Mapping

SPI Master Boot

AD Pin

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

Flag Pin

FLAG8

AD Pin

AD8

Flag Pin

FLAG0

FLAG1

FLAG2

FLAG3

FLAG4

FLAG5

FLAG6

FLAG7

Parallel Port Boot via EPROM

FLAG9

AD9

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

FLAG10

FLAG11

FLAG12

FLAG13

FLAG14

FLAG15

AD10

AD11

AD12

AD13

AD14

AD15

For details on processor timing, see Timing Specifications and

Figure 5 on Page 17.

Table 7. Core Instruction Rate/CLKIN Ratio Selection

CLKCFG1–0

Core to CLKIN Ratio

00

01

10

6:1

32:1

16:1

ADDRESS DATA MODES

The following table shows the functionality of the AD pins for

8-bit and 16-bit transfers to the parallel port. For 8-bit data

transfers, ALE latches address Bits A23–A8 when asserted, fol-

lowed by address Bits A7–A0 and data Bits D7–D0 when

deasserted. For 16-bit data transfers, ALE latches address bits

A15–A0 when asserted, followed by data bits D15–D0 when

deasserted.

Table 5. Address/Data Mode Selection

PP Data

Mode

AD7–0

Function

AD15–8

Function

ALE

8-bit

Asserted

Deasserted

Asserted

Deasserted

A15–8

D7–0

A7–0

D7–0

A23–16

A7–0

8-bit

16-bit

A15–8

D15–8

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ADSP-21364

ADSP-21364 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

W Grade

Parameter¹

Min Max

Unit

V_DDINT

A_VDD

Internal (Core) Supply Voltage

1.14 1.26

3.13 3.47

1.14 1.26

3.13 3.47

0.95 1.05

3.13 3.47

2.0

V

Analog (PLL) Supply Voltage

V_DDEXT

External (I/O) Supply Voltage

2

V_IH

High Level Input Voltage @ V_DDEXT= max

Low Level Input Voltage @ V_DDEXT= min

High Level Input Voltage @ V_DDEXT= max

Low Level Input Voltage @ V_DDEXT= min

Ambient Operating Temperature

2.0

V_DDEXT+ 0.5

2.0

V_DDEXT+ 0.5

V

2

V_IL

–0.5 +0.8

1.74 V_DDEXT+ 0.5

–0.5 +1.19

–0.5 +0.8

1.74 V_DDEXT+ 0.5

–0.5 +1.19

–40 +85

–0.5 +0.8

1.74 V_DDEXT+ 0.5

–0.5 +1.19

–40 +105

V

3

V_{IH_CLKIN}

V_{IL_CLKIN}

V

4, 5

T_AMB

0

+70

°C

1

Specifications subject to change without notice.

²Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

³Applies to input pin CLKIN.

⁴See Thermal Characteristics on Page 46 for information on thermal specifications.

⁵See Engineer-to-Engineer Note (No. EE-277) for further information.

ELECTRICAL CHARACTERISTICS

Parameter¹

Test Conditions

Min

Max

Unit

2

V_OH

High Level Output Voltage

Low Level Output Voltage

High Level Input Current

Low Level Input Current

@ V_DDEXT= min, I_OH= –1.0 mA³

@ V_DDEXT= min, I_OL= 1.0 mA³

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

t_CCLK= min, V_DDINT= nom

A_VDD= max

2.4

V

2

V_OL

0.4

10

V

4, 5

I_IH

μA

mA

pF

4

I_IL

10

5

I_ILPU

Low Level Input Current Pull-Up

Three-State Leakage Current

Three-State Leakage Current Pull-Up

Supply Current (Internal)

Supply Current (Analog)

200

10

6, 7

I_OZH

6

I_OZL

10

7

I_OZLPU

200

800

10

8, 9

I_DD-INTYP

10

AI_DD

11, 12

C_IN

Input Capacitance

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 1.2V

4.7

1

Specifications subject to change without notice.

²Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

³See Output Drive Currents on Page 45 for typical drive current capabilities.

⁴Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

⁵Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

⁶Applies to three-statable pins: FLAG3–0.

⁷Applies to three-statable pins with 22.5 kΩ pull-ups: AD15-0, DAI_Px, SPICLK, EMU, MISO, MOSI.

⁸Typical internal current data reflects nominal operating conditions.

⁹See Engineer-to-Engineer Note (No. EE-277) for further information.

¹⁰Characterized, but not tested.

¹¹Applies to all signal pins.

¹²Guaranteed, but not tested.

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October 2005

ADSP-21364

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note (EE-277) for detailed thermal

and power information regarding maximum power dissipation.

For information on package thermal specifications, see Thermal

Characteristics on Page 46.

ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

1

Internal (Core) Supply Voltage (V_DDINT

)

–0.3 V to +1.5 V

–0.3 V to +4.6 V

+0.5 V

1

Analog (PLL) Supply Voltage (A_VDD

)

1

External (I/O) Supply Voltage (V_DDEXT

)

1

Input Voltage –0.5 V to V_DDEXT

Output Voltage Swing –0.5 V to V_DDEXT

Load Capacitance¹

+0.5 V

200 pF

Storage Temperature Range¹

Junction Temperature Under Bias¹

–65°C to +150°C

125°C

¹Stresses greater than those listed above may cause permanent damage to the device. These

are stress ratings only; functional operation of the device at these or any other conditions

greater than those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADSP-21364 features proprietary ESDprotectioncircuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0

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ADSP-21364

Table 9. Clock Periods

TIMING SPECIFICATIONS

The ADSP-21364’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, serial ports, and parallel port (as required for read/write

strobes in asynchronous access mode). During reset, program

the ratio between the processor’s internal clock frequency and

external (CLKIN) clock frequency with the CLKCFG1–0 pins.

To determine switching frequencies for the serial ports, divide

down the internal clock, using the programmable divider con-

trol of each port (DIVx for the serial ports).

Timing

Requirements

Description¹

CLKIN Clock Period

t_CK

t_CCLK

(Processor) Core Clock Period

t_PCLK

(Peripheral) Clock Period = 2 × t_CCLK

Serial Port Clock Period = (t_PCLK) × SR

SPI Clock Period = (t_PCLK) × SPIR

t_SCLK

t_SPICLK

¹where:

The ADSP-21364’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock (the

clock source for the parallel port logic and I/O pads).

SR = serial port-to-peripheral clock ratio (wide range, determined by

SPORT CLKDIV)

SPIR = SPI-to-peripheral clock ratio (wide range, determined by

SPIBAUD register)

DAI_Px = serial port clock

SPICLK = SPI clock

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Note the definitions of various clock periods that are a function

of CLKIN and the appropriate ratio control shown inTable 8.

Table 8. ADSP-21364 CLKOUT and CCLK Clock

Generation Operation

Timing

Requirements

Description

Input Clock

Core Clock

Calculation

1/t_CK

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

CLKIN

CCLK

1/t_CCLK

Figure 5 shows Core to CLKIN ratios of 6:1, 16:1, and 32:1 with

external oscillator or crystal. Note that more ratios are possible

and can be set through software using the power management

control register (PMCTL). For more information, see the

ADSP-2136x SHARC Processor Programming Reference.

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 38 on Page 45 under Test Conditions for voltage refer-

ence levels.

PLLICLK

CLKOUT

CLKIN

XTAL

OSC

INDIV

÷1, 2

DIVEN

÷2, 4, 8, 16

CCLK

(CORE CLOCK)

PLLM

XTAL

PCLK, MCLK

(PERIPHERAL CLOCK,

MASTER CLOCK)

CLK-CFG [1:0]

(6:1, 16:1, 32:1)

Figure 5. Core Clock and System Clock Relationship to CLKIN

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October 2005

ADSP-21364

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 10.

Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

RESET Low Before V_DDINT/V_DDEXTOn

V_DDINTOn Before V_DDEXT

0

ns

t_IVDDEVDD

–50

0

10²

200

ms

μs

1

t_CLKVDD

CLKIN Valid After V_DDINT/V_DDEXTValid

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

t_CLKRST

t_PLLRST

20

μs

Switching Characteristic

, 34

t_CORERST

Core Reset Deasserted After RESET Deasserted

4096t_CK+ 2 t_CCLK

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for startup time.

Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁴The 4096 cycle count depends on t_SRSTspecification in Table 12. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

RESET

t_RSTVDD

V

DDINT

t_IVDDEVDD

t_CLKVDD

V

DDEXT

CLKIN

t_CLKRST

CLK_CFG1-0

t_CORERST

t_PLLRST

RSTOUT

Figure 6. Power-Up Sequencing

Rev. 0

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October 2005

ADSP-21364

Clock Input

Table 11. Clock Input

333 MHz

Max

Parameter

Unit

Min

Timing Requirements

t_CK

CLKIN Period

18¹

100

ns

ps

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low

7.5¹

CLKIN Width High

CLKIN Rise/Fall (0.4 V–2.0 V)

CCLK Period

3

3.0¹

10

2

3,4

t_CKJ

CLKIN Jitter Tolerance

–250

+250

¹Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

²Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_CCLK

³Actual input jitter should be combined with ac specifications for accurate timing analysis.

⁴Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

.

t_CKJ

t_CK

CLKIN

t_CKH

t_CKL

Figure 7. Clock Input

Clock Signals

The ADSP-21364 can use an external clock or a crystal. See the

CLKIN pin description in Table 3 on Page 11. The user applica-

tion program can configure the ADSP-21364 to use its internal

clock generator by connecting the necessary components to the

CLKIN and XTAL pins. Figure 8 shows the component connec-

tions used for a fundamental frequency crystal operating in

parallel mode.

Note that the clock rate is achieved using a 16.67 MHz crystal

and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock

speed of 266.72 MHz). To achieve the full core clock rate, pro-

grams need to configure the multiplier bits in the PMCTL

register.

CLKIN

XTAL

1M⍀

C1

C2

X1

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL

SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

Figure 8. 333 MHz Operation (Fundamental Mode Crystal)

Rev. 0

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October 2005

ADSP-21364

Reset

Table 12. Reset

Parameter

Min

Max

Unit

Timing Requirements

1

t_WRST

t_SRST

RESET Pulse Width Low

RESET Setup Before CLKIN Low

4t_CK

8

ns

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_SRST

t_WRST

RESET

Figure 9. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1 pins

when configured as interrupts.

Table 13. Interrupts

Parameter

Min

2 × t_PCLK+ 2

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

ns

DAI_P20-1

FLAG2-0

(IRQ2-0)

t

IPW

Figure 10. Interrupts

Rev. 0

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October 2005

ADSP-21364

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Table 14. Core Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_WCTIM

CTIMER Pulse Width

2 × t_PCLK– 1

ns

t_WCTIM

FLAG3

(CTIMER)

Figure 11. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse-width modulation) mode.

Timer signals are routed to the DAI_P20–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 15. Timer PWM_OUT Timing

Parameter

Min

2 t_PCLK– 2

Max

2(2³¹– 1) t_PCLK

Unit

Switching Characteristic

t_PWMO

Timer Pulse Width Output

ns

t_PWMO

DAI_P20-1

(TIMER2-0)

Figure 12. Timer PWM_OUT Timing

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October 2005

ADSP-21364

Timer WDTH_CAP Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in WDTH_CAP (pulse width count and capture)

mode. Timer signals are routed to the DAI_P20–1 pins through

the SRU. Therefore, the timing specifications provided below

are valid at the DAI_P20–1 pins.

Table 16. Timer Width Capture Timing

Parameter

Min

2 t_PCLK

Max

Unit

Timing Requirement

t_PWI

Timer Pulse Width

2(2³¹– 1) t_PCLK

ns

t_PWI

DAI_P20-1

(TIMER2-0)

Figure 13. Timer Width Capture Timing

DAI Pin to Pin Direct Routing

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 17. DAI Pin to Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI Pin Input Valid to DAI Output Valid

1.5

10

ns

DAI_Pn

DAI_Pm

t_DPIO

Figure 14. DAI Pin to Pin Direct Routing

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October 2005

ADSP-21364

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is not timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 18. Precision Clock Generator (Direct Pin Routing)

K and B Grade

W Grade

Parameter

Min

Max

Unit

Timing Requirements

t_PCGIP

t_STRIG

Input Clock Period

20

ns

PCG Trigger Setup Before Falling 4.5

Edge of PCG Input Clock

t_HTRIG

PCGTriggerHoldAfterFallingEdge 3

of PCG Input Clock

ns

Switching Characteristics

t_DPCGIOPCG Output Clock and Frame Sync

Active Edge Delay After PCG Input 2.5

Clock

10

ns

t_DTRIGCLKPCG Output Clock Delay After PCG 2.5 + ((2.5 + D) × t_PCGIP

Trigger

)

10 + ((2.5 + D) × t_PCGIP

)

12 + ((2.5 + D) × t_PCGIP)

t_DTRIGFS

PCG Frame Sync Delay After PCG 2.5 + ((2.5 + D – PH) × t_PCGIP) 10 + ((2.5 + D – PH) × t_PCGIP) 12 + ((2.5 + D – PH) × t_PCGIP) ns

Trigger

1

t_PCGOP

Output Clock Period

2 × t_PCGIP

ns

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Generators”

chapter.

¹In normal mode, t_PCGOP(min) = 2 x t_PCGIP

.

t_STRIG

t_HTRIG

DAI_Pn

PCG_TRIGx_I

t_PCGIP

DAI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

DAI_Py

PCG_CLKx_O

t_DTRIGCLK

t_DPCGIO

t_PCGOP

DAI_Pz

PCG_FSx_O

t_DTRIGFS

Figure 15. Precision Clock Generator (Direct Pin Routing)

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October 2005

ADSP-21364

Flags

The timing specifications provided below apply to the FLAG3–0

and DAI_P20–1 pins, the parallel port and the serial peripheral

interface (SPI). See Table 3, “Pin Descriptions,” on Page 11 for

more information on flag use.

Table 19. Flags

Parameter

Min

Max

Unit

Timing Requirement

t_FIPW

FLAG3–0 IN Pulse Width

2 × t_PCLK+ 3

ns

Switching Characteristic

t_FOPWFLAG3–0 OUT Pulse Width

2 × t_PCLK– 2

ns

DAI_P20-1

(FLAG3-0_IN

)

(DATA31-0)

t_FIPW

DAI_P20-1

(FLAG3-0_OUT

(DATA31-0)

)

t_FOPW

Figure 16. Flags

Rev. 0

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October 2005

ADSP-21364

Memory Read—Parallel Port

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) when the ADSP-21364

is accessing external memory space.

Table 20. 8-Bit Memory Read Cycle

K and B Grade

Max

W Grade

Max

Parameter

Min

Unit

Timing Requirements

1

t_DRS

t_DRH

t_DAD

AD7–0 Data Setup Before RD High

AD7–0 Data Hold After RD High

AD15–8 Address to AD7–0 Data Valid

3.3

0

4.5

0

ns

1

D + t_PCLK– 5.0

D + t_PCLK– 5.0 ns

Switching Characteristics

t_ALEWALE Pulse Width

AD15–0 Address Setup Before ALE Deasserted t_PCLK– 2.5

2 × t_PCLK– 2.0

t_PCLK– 2.5

ns

2

t_ADAS

t_RRH

Delay Between RD Rising Edge to Next

Falling Edge

H + t_PCLK– 1.4

t_ALERW

ALE Deasserted to Read Asserted

Read Deasserted to ALE Asserted

AD15–0 Address Hold After ALE Deasserted

ALE Deasserted to AD7–0 Address in High Z

RD Pulse Width

2 × t_PCLK– 3.8

F + H + 0.5

t_PCLK– 2.3

t_PCLK

2 × t_PCLK– 3.8

F + H + 0.5

t_PCLK– 2.3

t_PCLK

ns

t_RWALE

2

t_ADAH

2

t_ALEHZ

t_RW

t_PCLK+ 3.0

t_PCLK+ 3.8

ns

D – 2.0

t_RDDRV

t_ADRH

t_DAWH

AD7–0 ALE Address Drive After Read High

AD15–8 Address Hold After RD High

AD15–8 Address to RD High

F + H + t_PCLK– 2.3

H

F + H + t_PCLK– 2.3

H

D + t_PCLK– 4.0

D = (data cycle duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t_PCLK

H = t_PCLK(if a hold cycle is specified, else H = 0)

F = 7 x t_PCLK(if FLASH_MODE is set, else F = 0)

t

_PCLK= (peripheral) clock period = 2 × t_CCLK

¹The timing specified here is sufficient to satisfy either t_DADor t_DRSas they are independent.

²On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

t_RWALE

t_ALERW

t_ALEW

ALE

t_RRH

RD

t_RW

t_RDDRV

WR

t_DAWH

t_ADRH

t_ADAS

t_ADAH

VALID

ADDRESS

AD15-8

VALID ADDRESS

t_DRSt_DRH

t_DAD

VALID

ADDRESS

VALID

DATA

VALID

DATA

VALID ADDRESS

AD7-0

t_ALEHZ

NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR

BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY

READS IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION.

Figure 17. Read Cycle for 8-Bit Memory Timing

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October 2005

ADSP-21364

Table 21. 16-Bit Memory Read Cycle

K and B Grade

Max

W Grade

Max

Parameter

Min

Unit

Timing Requirements

t_DRS

t_DRH

AD15–0 Data Setup Before RD High

AD15–0 Data Hold After RD High

3.3

0

4.5

0

ns

Switching Characteristics

t_ALEWALE Pulse Width

AD15–0 Address Setup Before ALE Deasserted t_PCLK– 2.5

ns

2 × t_PCLK– 2.0

t_PCLK– 2.5

1

t_ADAS

t_ALERW

ALE Deasserted to Read Asserted

2 × t_PCLK– 3.8

H + t_PCLK– 1.4

2 × t_PCLK– 3.8

H + t_PCLK– 1.4

2

t_RRH

Delay Between RD Rising Edge to Next Falling

Edge

t_RWALE

Read Deasserted to ALE Asserted

F + H + 0.5

ns

t_RDDRV

ALE Address Drive After Read High

AD15–0 Address Hold After ALE Deasserted

F + H + t_PCLK– 2.3

t_PCLK– 2.3

F + H + t_PCLK– 2.3

t_PCLK– 2.3

1

t_ADAH

1

t_ALEHZ

t_RW

ALE Deasserted to Address/Data15–0 in High Z t_PCLK

RD Pulse Width D – 2.0

t_PCLK+ 3.0 t_PCLK

D – 2.0

t_PCLK+ 3.8 ns

ns

D = (data cycle duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t_PCLK

H = t_PCLK(if a hold cycle is specified, else H = 0)

F = 7 x t_PCLK(if FLASH_MODE is set, else F = 0)

t

_PCLK= (peripheral) clock period = 2 × t_CCLK

¹On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

²This parameter is only available when in EMPP = 0 mode.

t_RWALE

t_ALERW

t_ALEW

ALE

t_RRH

RD

t_RW

WR

t_RDDRV

t_ALEHZ

t_ADAH

t_DRS

t_DRH

t_ADAS

VALID

ADDRESS

AD15-0

VALID DATA

VALID ADDRESS

NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP ꢀ 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.

WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,

SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.

Figure 18. Read Cycle for 16-Bit Memory Timing

Rev. 0

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October 2005

ADSP-21364

Memory Write—Parallel Port

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) when the

ADSP-21364 is accessing external memory space.

Table 22. 8-Bit Memory Write Cycle

K and B Grade

Max

W Grade

Parameter

Min

Max

Unit

Switching Characteristics:

t_ALEW

ALE Pulse Width

2 × t_PCLK– 2.0

t_PCLK– 2.8

2 × t_PCLK– 3.8

H + 0.5

2 × t_PCLK– 2.0

t_PCLK– 2.8

2 × t_PCLK– 3.8

H + 0.5

ns

1

t_ADAS

t_ALERW

t_RWALE

t_WRH

AD15–0 Address Setup Before ALE Deasserted

ALE Deasserted to Write Asserted

Write Deasserted to ALE Asserted

Delay Between WR Rising Edge to Next WR Falling Edge

AD15–0 Address Hold After ALE Deasserted

WR Pulse Width

F + H + t_PCLK– 2.3

t_PCLK– 0.5

D – F – 2.0

t_PCLK– 2.8

H

F + H + t_PCLK– 2.3

t_PCLK– 0.5

D – F – 2.0

t_PCLK– 3.5

H

1

t_ADAH

t_WW

t_ADWL

t_ADWH

t_DWS

AD15–8 Address to WR Low

AD15–8 Address Hold After WR High

AD7–0 Data Setup Before WR High

AD7–0 Data Hold After WR High

AD15–8 Address to WR High

D – F + t_PCLK– 4.0

H

D – F + t_PCLK– 4.0

H

t_DWH

t_DAWH

D – F + t_PCLK– 4.0

D = (data cycle duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t_PCLK

H = t_PCLK(if a hold cycle is specified, else H = 0)

.

F = 7 x t_PCLK(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 x t_PCLK

_PCLK= (peripheral) clock period = 2 × t_CCLK

.

t

¹On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

t_ALERW

t_ALEW

ALE

t_RWALE

t_WW

WR

t_WRH

t_ADWL

t_DAWH

RD

t_ADAS

t_ADAH

t_ADWH

VALID

ADDRESS

AD15-8

VALID ADDRESS

t_DWH

t_DWS

VALID

ADDRESS

VALID DATA

AD7-0

NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR

BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY

WRITES IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION.

Figure 19. Write Cycle for 8-Bit Memory Timing

Rev. 0

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October 2005

ADSP-21364

Table 23. 16-Bit Memory Write Cycle

K and B Grade

Min

W Grade

Parameter

Min

Unit

Switching Characteristics

t_ALEW

ALE Pulse Width

2 × t_PCLK– 2.0

t_PCLK– 2.5

2 × t_PCLK– 2.0

t_PCLK– 2.5

ns

1

t_ADAS

AD15–0 Address Setup Before ALE Deasserted

ALE Deasserted to Write Asserted

Write Deasserted to ALE Asserted

Delay Between WR Rising Edge to Next WR Falling Edge

AD15–0 Address Hold After ALE Deasserted

WR Pulse Width

t_ALERW

2 × t_PCLK– 3.8

H + 0.5

2 × t_PCLK– 3.8

H + 0.5

t_RWALE

2

t_WRH

F + H + t_PCLK– 2.3

t_PCLK– 2.3

F + H + t_PCLK– 2.3

t_PCLK– 2.3

1

t_ADAH

t_WW

D – F – 2.0

D – F + t_PCLK– 4.0

H

D – F – 2.0

D – F + t_PCLK– 4.0

H

t_DWS

t_DWH

AD15–0 Data Setup Before WR High

AD15–0 Data Hold After WR High

D = (data cycle duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t_PCLK

H = t_PCLK(if a hold cycle is specified, else H = 0)

.

F = 7 x t_PCLK(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 x t_PCLK

_PCLK= (peripheral) clock period = 2 × t_CCLK

.

t

¹On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

²This parameter is only available when in EMPP = 0 mode.

t_ALEW

t_ALERW

ALE

WR

RD

t_RWALE

t_WW

t_WRH

t_DWH

t_ADAS

t_ADAH

VALID

ADDRESS

VALID

ADDRESS

AD15-0

VALID DATA

t_DWS

VALID DATA

NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP Þ 0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES.

WHEN EMPP = 0, MULTIPLE WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,

SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.

Figure 20. Write Cycle for 16-Bit Memory Timing

Rev. 0

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October 2005

ADSP-21364

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals (SCLK, FS, data channel A, data channel B)

are routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 24. Serial Ports—External Clock

K and B Grade

W Grade

Max

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSE

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

2.5

ns

1

t_HFSE

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

2.5

12

ns

1

t_SDRE

Receive Data Setup Before Receive SCLK

Receive Data Hold After SCLK

SCLK Width

1

t_HDRE

t_SCLKW

t_SCLK

SCLK Period

24

Switching Characteristics

2

t_DFSE

FS Delay After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)

9.5

11

ns

2

t_HOFSE

FS Hold After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)

2

ns

2

t_DDTE

Transmit Data Delay After Transmit SCLK

Transmit Data Hold After Transmit SCLK

2

t_HDTE

¹Referenced to sample edge.

²Referenced to drive edge.

Table 25. Serial Ports—Internal Clock

K and B Grade

Max

W Grade

Max

Parameter

Min

Unit

Timing Requirements

1

t_SFSI

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

7

ns

1

t_HFSI

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

2.5

7

ns

1

t_SDRI

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

1

t_HDRI

2.5

Switching Characteristics

2

t_DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode)

3

8

3

3.5

9.5

4.0

ns

2

t_HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode)

FS Delay After SCLK (Internally Generated FS in Receive Mode)

FS Hold After SCLK (Internally Generated FS in Receive Mode)

Transmit Data Delay After SCLK

–1.0

2

t_DFSIR

2

t_HOFSIR

2

t_DDTI

2

t_HDTI

Transmit Data Hold After SCLK

t_SCLKIW

Transmit or Receive SCLK Width

0.5t_SCLK– 2 0.5t_SCLK+ 2 0.5t_SCLK+ 2

¹Referenced to the sample edge.

²Referenced to drive edge.

Rev. 0

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October 2005

ADSP-21364

Table 26. Serial Ports—Enable and Three-State

K and B Grade

Max

W Grade

Parameter

Min

2

Max

Unit

Switching Characteristics

1

t_DDTEN

Data Enable from External Transmit SCLK

Data Disable from External Transmit SCLK

Data Enable from Internal Transmit SCLK

ns

1

t_DDTTE

7

8.5

1

t_DDTIN

–1

¹Referenced to drive edge.

Table 27. Serial Ports—External Late Frame Sync

K and B Grade

Max

W Grade

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DDTLFSE

Data Delay from Late External Transmit FS or

External Receive FS with MCE = 1, MFD = 0

9

10.5

ns

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DAI_P20-1

(SCLK)

t_SFSE/I

t_HFSE/I

DAI_P20-1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20-1

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE

SAMPLE

DRIVE

t_HFSE/I

DAI_P20-1

(SCLK)

t_SFSE/I

DAI_P20-1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20-1

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.

Figure 21. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified sample pair mode.

Rev. 0

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ADSP-21364

Table 26. Serial Ports—Enable and Three-State

K and B Grade

Max

W Grade

Parameter

Min

2

Max

Unit

Switching Characteristics

1

t_DDTEN

Data Enable from External Transmit SCLK

Data Disable from External Transmit SCLK

Data Enable from Internal Transmit SCLK

ns

1

t_DDTTE

7

8.5

1

t_DDTIN

–1

¹Referenced to drive edge.

Table 27. Serial Ports—External Late Frame Sync

K and B Grade

Max

W Grade

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DDTLFSE

Data Delay from Late External Transmit FS or

External Receive FS with MCE = 1, MFD = 0

9

10.5

ns

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DAI_P20-1

(SCLK)

t_SFSE/I

t_HFSE/I

DAI_P20-1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20-1

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE

SAMPLE

DRIVE

t_HFSE/I

DAI_P20-1

(SCLK)

t_SFSE/I

DAI_P20-1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20-1

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.

Figure 21. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified sample pair mode.

Rev. 0

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October 2005

ADSP-21364

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20-1

(SCLK)

DAI_P20-1

(SCLK)

t_DFSI

t_DFSE

t_HFSE

t_HFSI

t_SFSI

t_SFSE

t_HOFSI

t_HOFSE

DAI_P20-1

(FS)

DAI_P20-1

(FS)

t_HDRE

t_SDRI

t_HDRI

t_SDRE

DAI_P20-1

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20-1

(SCLK)

DAI_P20-1

(SCLK)

t_DFSI

t_DFSE

t_HFSI

t_HOFSI

t_SFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20-1

(FS)

DAI_P20-1

(FS)

t_DDTE

t_DDTI

t_HDTE

t_HDTI

DAI_P20-1

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

DAI_P20-1

SCLK

SCLK (EXT)

t_DDTEN

t_DDTTE

DAI_P20-1

(DATA CHANNEL A/B)

DRIVE EDGE

DAI_P20-1

SCLK (INT)

t_DDTIN

DAI_P20-1

(DATA CHANNEL A/B)

Figure 22. Serial Ports

Rev. 0

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October 2005

ADSP-21364

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 28. IDP

Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 28. IDP

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SData Setup Before SCLK Rising Edge

SData Hold After SCLK Rising Edge

Clock Width

3

ns

1

t_SIHFS

3

1

t_SISD

3

1

t_SIHD

t_IDPCLKW

t_IDPCLK

3

9

Clock Period

24

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_IPDCLK

t_IPDCLKW

DAI_P20-1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20-1

(FS)

t_SISD

t_SIHD

DAI_P20-1

(SDATA)

Figure 23. IDP Master Timing

Rev. 0

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October 2005

ADSP-21364

ence . Note that the most significant 16 bits of external PDAP

data can be provided through either the parallel port AD15–0 or

the DAI_P20–5 pins. The remaining 4 bits can only be sourced

through DAI_P4–1. The timing below is valid at the

DAI_P20–1 pins or at the AD15–0 pins.

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 29. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the IDP, see the IDP

chapter of the ADSP-2136x SHARC Processor Hardware Refer-

Table 29. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge

PDAP_CLKEN Hold After PDAP_CLK Sample Edge

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

Clock Width

2.5

3.0

2.5

7.0

24

ns

1

t_HPCLKEN

1

t_PDSD

1

t_PDHD

t_PDCLKW

t_PDCLK

Clock Period

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRBPDAP Strobe Pulse Width

2 × t_PCLK– 1

ns

2 × t_PCLK– 1.5

1

Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20-1

(PDAP_CLK)

t_SPCLKEN

t_HPCLKEN

DAI_P20-1

(PDAP_CLKEN)

t_PDSD

t_PDHD

DATA

DAI_P20-1

(PDAP_STROBE)

t_PDSTRB

t_PDHLDD

Figure 24. PDAP Timing

Rev. 0

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October 2005

ADSP-21364

Pulse-Width Modulation Generators

Table 30. PWM Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_PWMW

t_PWMP

PWM Output Pulse Width

PWM Output Period

t_PCLK– 2

(2¹⁶– 2) × t_PCLK– 2

(2¹⁶– 1) × t_PCLK

ns

2 × t_PCLK– 1.5

t_PWMW

PWM

OUTPUTS

t_PWMP

Figure 25. PWM Timing

Sample Rate Converter—Serial Input Port

The SRC input signals (SCLK, FS, and SDATA) are routed from

the DAI_P20–1 pins using the SRU. Therefore, the timing spec-

ifications provided in Table 31 are valid at the DAI_P20–1 pins.

Table 31. SRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SData Setup Before SCLK Rising Edge

SData Hold After SCLK Rising Edge

Clock Width

3

ns

1

t_SRCHFS

3

1

t_SRCSD

3

1

t_SRCHD

t_SRCCLKW

t_SRCCLK

3

36

80

Clock Period

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

t_SRCCLKW

DAI_P20-1

(SCLK)

t_SRCSFS

t_SRCHFS

DAI_P20-1

(FS)

t_SRCSD

t_SRCHD

DAI_P20-1

(SDATA)

Figure 26. SRC Serial Input Port Timing

Rev. 0

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Page 35 of 56

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October 2005

ADSP-21364

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and should

meet setup and hold times with regard to SCLK on the output

port. The serial data output, SDATA, has a hold time and delay

specification with regard to SCLK. Note that SCLK rising edge is

the sampling edge and the falling edge is the drive edge.

Table 32. SRC, Serial Output Port

K and B Grade

Max

W Grade

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

3

ns

1

t_SRCHFS

Switching Characteristics

1

t_SRCTDD

Transmit Data Delay After SCLK Falling Edge

Transmit Data Hold After SCLK Falling Edge

10.5

12.5

ns

1

t_SRCTDH

2

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

t_SRCCLKW

DAI_P20-1

(SCLK)

t_SRCSFS

t_SRCHFS

DAI_P20-1

(FS)

t_SRCTDD

DAI_P20-1

(SDATA)

t_SRCTDH

Figure 27. SRC Serial Output Port Timing

Rev. 0

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Page 36 of 56

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October 2005

ADSP-21364

SPDIF Transmitter

Serial data input to the SPDIF transmitter can be formatted as

left-justified, I²S, or right-justified with word widths of 16, 18,

20, or 24 bits. The following sections provide timing for the

transmitter.

SPDIF Transmitter—Serial Input Waveforms

Figure 28 shows the right-justified mode. LRCLK is HI for the

left channel and LO for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are 64

SCLK periods per LRCLK period, the LSB of the data will be

right-justified to the next LRCLK transition.

LRCLK

RIGHT CHANNEL

LEFT CHANNEL

SCLK

SDATA

LSB

MSB MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB MSB-1 MSB-2

LSB+2 LSB+1

LSB

Figure 28. Right -Justified Mode

Figure 29 shows the default I2S-justified mode. LRCLK is LO

for the left channel and HI for the right channel. Data is valid on

the rising edge of SCLK. The MSB is left-justified to an LRCLK

transition but with a single SCLK period delay.

RIGHT CHANNEL

LRCLK

LEFT CHANNEL

SCLK

MSB MSB-1 MSB-2

LSB+2 LSB+1 LSB

MSB

MSB-1 MSB-2

LSB+2 LSB+1 LSB

MSB

SDATA

Figure 29. I²S-Justified Mode

Figure 30 shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising

edge of SCLK. The MSB is left-justified to an LRCLK transition

with no MSB delay.

LRCLK

RIGHT CHANNEL

LEFT CHANNEL

SCLK

SDATA

LSB+2 LSB+1 LSB

MSB

MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB

MSB-1 MSB-2

MSB MSB+1

Figure 30. Left-Justified Mode

Rev. 0

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Page 37 of 56

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October 2005

ADSP-21364

SPDIF Transmitter Input Data Timing

The timing requirements for the input port are given in

Table 33. Input signals (SCLK, FS, SDATA) are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

Table 33. SPDIF Transmitter Input Data Timing

K and B Grade

Min

W Grade

Max

Parameter

Min

Unit

Timing Requirements

1

t_SISFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SData Setup Before SCLK Rising Edge

SData Hold After SCLK Rising Edge

Clock Width

3

ns

1

t_SIHFS

3

1

t_SISD

3

1

t_SIHD

t_SISCLKW

t_SISCLK

t_SITXCLKW

t_SITXCLK

3

36

80

9

36

80

9.5

20

Clock Period

Transmit Clock Width

Transmit Clock Period

20

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

t_SITXCLKW

t_SITXCLK

SAMPLE EDGE

DAI_P20-1

(TXCLK)

t_SISCLKW

DAI_P20-1

(SCLK)

t_SIHFS

t_SISFS

DAI_P20-1

(FS)

t_SISD

t_SIHD

DAI_P20-1

(SDATA)

Figure 31. SPDIF Transmitter Input Timing

Oversampling Clock (TXCLK) Switching Characteristics

The SPDIF Transmitter has an oversampling clock. This

TXCLK input is divided down to generate the biphase clock.

Table 34. Oversampling Clock (TXCLK) Switching Characteristics

Parameter

Min

Max

147.5

98.4

Unit

MHz

kHz

TXCLK Frequency for TXCLK = 768 × FS

TXCLK Frequency for TXCLK = 512 × FS

TXCLK Frequency for TXCLK = 384 × FS

TXCLK Frequency for TXCLK = 256 × FS

Frame Rate

73.8

49.2

192.0

Rev. 0

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Page 38 of 56

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October 2005

ADSP-21364

SPDIF Receiver

The following section describes timing as it relates to the SPDIF

receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × Fs clock.

Table 35. SPDIF Receiver Output Timing (Internal Digital PLL Mode)

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

LRCLK Delay After SCLK

LRCLK Hold After SCLK

Transmit Data Delay After SCLK

Transmit Data Hold After SCLK

Transmit SCLK Width

5

ns

t_HOFSI

t_DDTI

t_HDTI

–2

38

1

t_SCLKIW

t_CCLK

Core Clock Period

5

¹SCLK frequency is 64 × FS where FS = the frequency of LRCLK.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

DAI_P20-1

(SCLK)

t_DFSI

t_HOFSI

DAI_P20-1

(FS)

t_DDTI

t_HDTI

DAI_P20-1

(DATA CHANNEL A/B)

Figure 32. SPDIF Receiver Internal Digital PLL Mode Timing

Rev. 0

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Page 39 of 56

|

October 2005

ADSP-21364

SPI Interface—Master

The ADSP-21364 contains two SPI ports. The primary has dedi-

cated pins and the secondary is available through the DAI. The

timing provided in Table 36 and Table 37 applies to both.

Table 36. SPI Interface Protocol—Master Switching and Timing Specifications

K and B Grade

W Grade

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Data Input Valid to SPICLK Edge (Data Input

Setup Time)

5.2

8.2

2

6.2

9.5

2

ns

Data Input Valid to SPICLK Edge (Data Input

Setup Time) (SPI2)

SPICLK Last Sampling Edge to Data

Input Not Valid

Switching Characteristics

t_SPICLKM

t_SPICHM

t_SPICLM

Serial Clock Cycle

8 × t_PCLK– 2

4 × t_PCLK– 2

8 × t_PCLK– 2

4 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

t_DDSPIDM

SPICLK Edge to Data Out Valid

(Data Out Delay Time)

3.0

8.0

3.0

9.5

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

SPICLK Edge to Data Out Valid

(Data Out Delay Time) (SPI2)

ns

SPICLK Edge to Data Out Not Valid

(Data Out Hold Time)

2

FLAG3–0IN (SPI Device Select) Low to First

SPICLK Edge

4 × t_PCLK– 2.5

4 × t_PCLK– 3.0

t_SDSCIM

FLAG3–0IN (SPI Device Select) Low to First

SPICLK Edge (SPI2)

t_HDSM

Last SPICLK Edge to FLAG3–0IN High

Sequential Transfer Delay

4 × t_PCLK– 2

4 × t_PCLK– 1

4 × t_PCLK– 2

4 × t_PCLK– 1

ns

t_SPITDM

Rev. 0

|

Page 40 of 56

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October 2005

ADSP-21364

FLAG3-0

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICHM

t_{D DSPIDM}

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0)

(OUTPUT)

t_SPICLM

SPICLK

(CP = 1)

(OUTPUT)

t_HDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

MSB

LSB

(INPUT)

VALID

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

t_HSPIDM

CPHASE = 0

MSB

VALID

LSB

VALID

MISO

(INPUT)

Figure 33. SPI Master Timing

Rev. 0

|

Page 41 of 56

|

October 2005

ADSP-21364

SPI Interface—Slave

Table 37. SPI Interface Protocol—Slave Switching and Timing Specifications

K and B Grade

Max

W Grade

Max

Parameter

Min

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

Serial Clock Cycle

4 × t_PCLK– 2

2 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × t_PCLK

t_HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE = 0)

2 × t_PCLK

ns

t_SSPIDS

t_HSPIDS

t_SDPPW

2

2 × t_PCLK

Switching Characteristics

t_DSOESPIDS Assertion to Data Out Active

0

5

ns

1

t_DSOE

t_DSDHI

SPIDS Assertion to Data Out Active (SPI2)

8

9

SPIDS Deassertion to Data High Impedance

SPIDS Deassertion to Data High Impedance (SPI2)

SPICLK Edge to Data Out Valid (Data Out Delay Time)

5

5.5

10

11.0

1

t_DSDHI

8.6

9.5

t_DDSPIDS

t_HDSPIDS

t_DSOV

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t_PCLK

SPIDS Assertion to Data Out Valid (CPHASE = 0)

5 × t_PCLK

¹The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-2136x SHARC Processor Hardware

Reference , “Serial Peripheral Interface Port” chapter.

Rev. 0

|

Page 42 of 56

|

October 2005

ADSP-21364

SPIDS

(INPUT)

t_{SPIC HS}

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0)

(INPUT)

t_SPICLS

t_SDSCO

t_SPICHS

SPICLK

(CP = 1)

(INPUT)

t_DSDHI

t_HDSPIDS

t_DDSPIDS

t_DSOE

t_DDSPIDS

MISO

(OUTPUT)

MSB

LSB

t_HSPIDS

CPHASE = 1

t_SSPIDS

MOSI

(INPUT)

MSB VALID

LSB VALID

t_DSOV

t_{DSO E}

t_HDSPIDS

t_DDSPIDS

t_DSDHI

MISO

(OUTPUT)

LSB

MSB

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

MSB VALID

LSB VALID

(INPUT)

Figure 34. SPI Slave Timing

Rev. 0

|

Page 43 of 56

|

October 2005

ADSP-21364

JTAG Test Access Port and Emulation

Table 38. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

t_CK

5

ns

t_STAP

t_HTAP

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High

System Inputs Hold After TCK High

TRST Pulse Width

6

1

t_SSYS

7

1

t_HSYS

t_TRSTW

18

4t_CK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

System Outputs Delay After TCK Low

7

ns

2

t_DSYS

t_CK÷ 2 + 7

¹System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

²System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 35. IEEE 1149.1 JTAG Test Access Port

Rev. 0

|

Page 44 of 56

|

October 2005

ADSP-21364

OUTPUT DRIVE CURRENTS

CAPACITIVE LOADING

Figure 36 shows typical I-V characteristics for the output driv-

ers of the ADSP-21364. The curves represent the current drive

capability of the output drivers as a function of output voltage.

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 37). Figure 41 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 39, Figure 40, and Figure 41 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% to 80%, V =

Min) vs. Load Capacitance.

40

V

OH

30

20

3.3V, 25°C

3.47V, -45°C

12

10

0

3.11V, 125°C

RISE

y = 0.0467x + 1.6323

FALL

-10

8

3.11V, 125°C

-20

3.3V, 25°C

3.5

6

V

-30

-40

OL

3.47V, -45°C

4

y = 0.045x + 1.524

0

0.5

1

1.5

2

2.5

3

SWEEP (V

) VOLTAGE (V)

DDEXT

2

0

Figure 36. ADSP-21364 Typical Drive

50

100

150

200

250

0

TEST CONDITIONS

LOAD CAPACITANCE (pF)

The ac signal specifications (timing parameters) appear in

Table 12 on Page 20 through Table 38 on Page 44. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 37.

Figure 39. Typical Output Rise/Fall Time (20% to 80%,

_DDEXT= Max)

V

12

10

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 38 on Page 45. All delays (in nanoseconds)

are measured between the point that the first signal reaches

1.5 V and the point that the second signal reaches 1.5 V.

RISE

y = 0.049x + 1.5105

FALL

8

6

50⍀

TO

y = 0.0482x + 1.4604

1.5V

OUTPUT

4

2

30pF

0

50

100

150

200

250

Figure 37. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

LOAD CAPACITANCE (pF)

Figure 40. Typical Output Fall Time (20% to 80%,

V_DDEXT= Min)

INPUT

OR

1.5V

OUTPUT

Figure 38. Voltage Reference Levels for AC Measurements

Rev. 0

|

Page 45 of 56

|

October 2005

ADSP-21364

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heat sink is required.

10

8

Table 39. Thermal Characteristics for BGA (No thermal vias

in PCB)¹

Y = 0.0488X - 1.5923

6

4

Parameter

θ_JA

Condition

Typical

25.40

21.90

20.90

5.07

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

2

0

θ_JMA

θ_JC

-2

-4

Ψ_JT

Ψ_JMT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.140

0.330

0.410

0

50

100

150

200

LOAD CAPACITANCE (pF)

Table 40. Thermal Characteristics for BGA (Thermal vias in

PCB)¹

Figure 41. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

Parameter

θ_JA

θ_JMA

θ_JC

Ψ_JT

Ψ_JMT

Condition

Typical

23.40

20.00

19.20

5.00

Unit

°C/W

THERMAL CHARACTERISTICS

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

The ADSP-21364 processor is rated for performance over the

temperature range specified in Recommended Operating Con-

ditions on Page 15.

Table 39 through Table 42 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. Test board and

thermal via design comply with JEDEC standards JESD51-9

(BGA) and JESD51-5 (integrated heat sink LQFP). The junc-

tion-to-case measurement complies with MIL-STD-883. All

measurements use a 2S2P JEDEC test board.

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.130

0.300

0.360

Table 41. Thermal Characteristics for LQFP (With heat slug

not soldered to PCB)

Industrial applications using the BGA package require thermal

vias, to an embedded ground plane, in the PCB. Refer to JEDEC

standard JESD51-9 for printed circuit board thermal ball land

and thermal via design information. Industrial applications

using the LQFP package require thermal trace squares and ther-

mal vias, to an embedded ground plane, in the PCB. The bottom

side heat slug must be soldered to the thermal trace squares.

Refer to JEDEC standard JESD51-5 for more information.

Parameter

θ_JA

θ_JMA

θ_JC

Ψ_JT

Ψ_JMT

Condition

Typical

26.08

24.59

23.77

6.83

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.236

0.427

0.441

To determine the junction temperature of the device while on

the application PCB, use:

Table 42. Thermal Characteristics for LQFP (With heat slug

soldered to PCB)

T = T_T+ (Ψ × P )

J

JT

D

Parameter

θ_JA

Condition

Typical

16.50

15.14

14.35

6.83

Unit

°C/W

where:

T_J= junction temperature °C

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

θ_JMA

θ_JC

T_T= case temperature (°C) measured at the top center of the

package

Ψ_JT= junction-to-top (of package) characterization parameter

is the Typical value from Table 39 and Table 41.

Ψ_JT

Ψ_JMT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.129

0.255

0.261

P

_D= power dissipation (see EE Note #EE-277)

Values of θ_JAare provided for package comparison and PCB

design considerations.

Rev. 0

|

Page 46 of 56

|

October 2005

ADSP-21364

136-BALL BGA PIN CONFIGURATIONS

The following table shows the ADSP-21364’s pin names and

their default function after reset (in parentheses).

Table 43. BGA Pin Assignments

Ball Name

CLKCFG0

XTAL

TMS

Ball No. Ball Name

Ball No.

D01

D02

D04

D05

D06

D09

D10

D11

D13

D14

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

E01

E02

E04

E05

E06

E09

E10

E11

E13

E14

CLKCFG1

GND

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

F01

F02

F04

F05

F06

F09

F10

F11

F13

F14

BOOTCFG1

BOOTCFG0

GND

C01

C02

C03

C12

C13

C14

V_DDINT

GND

V_DDINT

V_DDEXT

CLKIN

TRST

TCK

GND

TDI

GND

CLKOUT

TDO

A_VSS

V_DDINT

A_VDD

EMU

V_DDEXT

SPICLK

RESET

V_DDINT

GND

MOSI

MISO

SPIDS

V_DDINT

GND

V_DDINT

GND

FLAG1

FLAG0

GND

AD7

G01

G02

G13

G14

AD6

H01

H02

V_DDINT

V_DDEXT

GND

V_DDEXT

DAI_P18 (SD5B)

DAI_P17 (SD5A)

H13

H14

GND

DAI_P19 (SCLK45)

GND

FLAG2

DAI_P20 (SFS45)

FLAG3

Rev. 0

|

Page 47 of 56

|

October 2005

ADSP-21364

Table 43. BGA Pin Assignments (Continued)

Ball Name

AD5

Ball No. Ball Name

Ball No.

M01

J01

AD3

K01

K02

K04

K05

K06

K09

K10

K11

K13

K14

P01

P02

P03

P04

P05

P06

P07

P08

P09

P10

P11

P12

P13

P14

AD2

L01

L02

L04

L05

L06

L09

L10

L11

L13

L14

AD0

AD4

J02

V_DDINT

AD1

WR

M02

GND

J04

GND

M03

GND

J05

GND

M12

GND

J06

GND

DAI_P12 (SD3B)

DAI_P13 (SCLK23)

M13

GND

J09

GND

M14

GND

J10

GND

J11

GND

V_DDINT

J13

GND

DAI_P16 (SD4B)

AD15

J14

DAI_P15 (SD4A)

AD14

DAI_P14 (SFS23)

N01

N02

N03

N04

N05

N06

N07

N08

N09

N10

N11

N12

N13

N14

ALE

AD13

RD

AD12

V_DDINT

AD11

V_DDEXT

AD8

AD10

AD9

V_DDINT

DAI_P1 (SD0A)

DAI_P3 (SCLK0)

DAI_P5 (SD1A)

DAI_P6 (SD1B)

DAI_P7 (SCLK1)

DAI_P8 (SFS1)

DAI_P9 (SD2A)

DAI_P11 (SD3A)

DAI_P2 (SD0B)

V_DDEXT

DAI_P4 (SFS0)

V_DDINT

GND

DAI_P10 (SD2B)

Rev. 0

|

Page 48 of 56

|

October 2005

ADSP-21364

14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

KEY

V_DDINT

V_DDEXT

A_VDD

I/O SIGNALS

GND*

A_VSS

*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHWAYS TO YOUR PRINTED

CIRCUIT BOARD’S GROUND PLANE.

Figure 42. BGA Pin Assignments (Bottom View, Summary)

Rev. 0

|

Page 49 of 56

|

October 2005

ADSP-21364

144-LEAD LQFP PIN CONFIGURATIONS

The following table shows the ADSP-21364’s pin names and

their default function after reset (in parentheses).

Table 44. LQFP Pin Assignments

Pin Name

V_DDINT

CLKCFG0

CLKCFG1

BOOTCFG0

BOOTCFG1

GND

Pin No.

1

Pin Name

V_DDINT

GND

Pin No.

37

Pin Name

V_DDEXT

Pin No.

73

Pin Name

GND

Pin No.

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

2

38

GND

74

V_DDINT

GND

3

RD

39

V_DDINT

75

4

ALE

40

GND

76

V_DDINT

GND

5

AD15

AD14

AD13

GND

41

DAI_P10 (SD2B)

DAI_P11 (SD3A)

DAI_P12 (SD3B)

77

6

42

78

V_DDINT

GND

V_DDEXT

GND

7

43

79

8

44

DAI_P13 (SCLK23) 80

V_DDEXT

GND

V_DDINT

GND

9

V_DDEXT

AD12

V_DDINT

GND

45

DAI_P14 (SFS23)

DAI_P15 (SD4A)

V_DDINT

81

82

83

84

85

86

87

88

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

46

V_DDINT

GND

V_DDINT

GND

47

48

GND

V_DDINT

RESET

SPIDS

GND

V_DDINT

GND

AD11

AD10

AD9

49

GND

50

DAI_P16 (SD4B)

DAI_P17 (SD5A)

DAI_P18 (SD5B)

FLAG0

FLAG1

AD7

51

AD8

52

V_DDINT

SPICLK

MISO

MOSI

GND

DAI_P1 (SD0A) 53

DAI_P19 (SCLK45) 89

GND

V_DDINT

GND

54

55

V_DDINT

GND

90

V_DDINT

GND

91

DAI_P2 (SD0B) 56

DAI_P3 (SCLK0) 57

GND

92

V_DDEXT

GND

V_DDEXT

DAI_P20 (SFS45)

GND

93

V_DDINT

V_DDEXT

A_VDD

GND

58

59

60

61

94

V_DDINT

AD6

V_DDEXT

V_DDINT

GND

95

V_DDINT

FLAG2

FLAG3

V_DDINT

GND

96

A_VSS

AD5

97

GND

AD4

DAI_P4 (SFS0) 62

DAI_P5 (SD1A) 63

DAI_P6 (SD1B) 64

DAI_P7 (SCLK1) 65

98

CLKOUT

EMU

V_DDINT

GND

99

100

101

102

103

104

105

106

107

108

TDO

AD3

V_DDINT

GND

TDI

AD2

V_DDINT

GND

66

67

68

69

TRST

V_DDEXT

GND

V_DDINT

GND

TCK

V_DDINT

GND

TMS

AD1

V_DDINT

GND

AD0

DAI_P8 (SFS1) 70

DAI_P9 (SD2A) 71

CLKIN

XTAL

V_DDEXT

WR

V_DDINT

72

Rev. 0

|

Page 50 of 56

|

October 2005

ADSP-21364

OUTLINE DIMENSIONS

The ADSP-21364 is available in a 144-lead integrated heat sink

LQFP package and a 136-ball BGA package.

22.00BSC SQ

20.00 BSC SQ

0.27

0.22 TYP

0.17

144

10 9

1

108

0.50

BSC

TYP

PIN 1 INDI CA TOR

(LEAD

PI TCH)

SEATING

PLANE

13.71

0. 08 MAX (LEAD

COPLANARITY)

13.21 DIA

12.71

0.15

0.05

1. 45

1. 40

1. 35

0.75

0.60TYP

0.45

1.60 MAX

36

72

37

DE TAIL A

DETAIL A

HEAT SLUG ON BOTTOM

(NOTE 4)

NOTES:

TOP VIEW (PINS DOWN)

1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH

JEDEC STANDARD MS-026-BFB-HD.

2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS

IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.

3. CENTER DIMENSIONS ARE NOMINAL.

4. HEAT SLUG IS COINCIDENT WITH BOTTOM SURFACE AND DOES

NOT PROTRUDE BEYOND IT.

Figure 43. 144-Lead Low Profile Quad Flat Package, with Integrated Heatsink [LQFP_INT_HS] (SQ-144-3)

Rev. 0

|

Page 51 of 56

|

October 2005

ADSP-21364

10.40 BSC SQ

12.00 BSC SQ

0.80

BSC

TYP

A

B

C

D

E

F

PIN A1 INDICATOR

G

H

J

K

L

M

N

P

0.80

BSC

TYP

14 13 12 11 10 9 8

7 6 5 4 3 2 1

BOTTOM VIEW

TOP VIEW

1.70

MAX

DETAIL A

0.25

MIN

SEATING

PLANE

0.50

0.45

1. DIMENSIONS ARE IN MILIMETERS (MM).

2. THE ACTUAL POSITION OF THE BALL GRID IS

WITHIN 0.15 MM OF ITS IDEAL POSITION RELATIVE

TO THE PACKAGE EDGES.

3. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR

THE BALL DIAMETER.

0.40

0.12 MAX (BALL

COPLANARITY)

(BALL

DIAMETER)

4. CENTER DIMENSIONS ARE NOMINAL.

DETAIL A

Figure 44. 136-Lead Chip Scale Package Ball Grid Array [CSP_BGA](BC-136-2)

SURFACE MOUNT DESIGN

The following table is provided as an aide to PCB design. The

numbers listed in the table are for reference purposes and

should not supersede the PCB design rules. Please reference

IPC-7351, Surface Mount Design and Land Pattern Standard,

for PCB design recommendations.

Solder Mask

Package

Ball Attach Type

Opening

Ball Pad Size

136-Lead Ball Grid

Array (BC-136-2)

Solder Mask

Defined (SMD)

0.40

0.53

Rev. 0

|

Page 52 of 56

|

October 2005

ADSP-21364

ORDERING GUIDE

Analog Devices offers a wide variety of audio algorithms and

combinations to run on the ADSP-21364 processor. These

products are sold as part of a chip set, bundled with necessary

application software under special part numbers. For a complete

list, visit our website at www.analog.com/SHARC.

These products also may contain third party IPs that may

require users to have authorization from the respective IP hold-

ers to receive them. Royalty for use of the third party IPs may

also be payable by users.

Table 45. ADSP-21364 Ordering Guide

Operating

Temperature Instruction On-Chip

Voltage

Package

Model

Range ¹

Rate

SRAM

3M Bit

ROM

Internal/External Package Description Option

ADSP-21364KBC–1AA

0 to 70°C

333 MHz

4M Bit

1.2 V/3.3 V

1.0 V/3.3 V

136-ball CSP-BGA

BC-136-2

ADSP-21364KBCZ–1AA²0 to 70°C

ADSP-21364KSQZ–1AA²0 to 70°C

144-lead LQFP_INT_HS SQ-144-3

ADSP-21364BBC–1AA

–40 to +85°C 333 MHz

136-ball CSP-BGA

BC-136-2

ADSP-21364BBCZ–1AA²–40 to +85°C 333 MHz

ADSP-21364BSQZ–1AA²–40 to +85°C 333 MHz

ADSP-21364WSQZ–2AA²–40 to +105°C 200 MHz

144-lead LQFP_INT_HS SQ-144-3

¹Referenced temperature is ambient temperature.

²Z = Pb-free part.

Rev. 0

|

Page 53 of 56

|

October 2005

ADSP-21364

Rev. 0

|

Page 54 of 56

|

October 2005

ADSP-21364

Rev. 0

|

Page 55 of 56

|

October 2005

ADSP-21364

©

registered trademarks are the property of their respective owners.

D04624-0-10/05(0)

Rev. 0

| Page 56 of 56 | October 2005


型号：	ADSP-21364WSQZ-2AA
厂家：	ADI
描述：	IC 16-BIT, OTHER DSP, PQFP144, LEAD FREE, MS-026BFB-HD, LQFP-144, Digital Signal Processor 外围集成电路
文件：	总56页 (文件大小：2810K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21364WSQZ-2AA [ADI]

相关型号：

ADSP-21364WYSWZ-2A

ADSP-21364YSWZ-2AA

ADSP-21365

ADSP-21365BBC-1AA

ADSP-21365BSQZ-1AA

ADSP-21365KBC-1AA

ADSP-21365KBC-1AX

ADSP-21365KBCZ-1AA

ADSP-21365KBCZ-1AX

ADSP-21365KSQZ-1AA

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