ADSP-2141LKS-N1_技术文档

R

a

DSP

ADSP-2141L

APPLICATIONS

SECURE KERNEL CONTROL

Security Coprocessor for High Speed Networking Prod-

ucts (Routers, Switches, Hubs)

Cryptographic Core for Firewalls, Hardware Encryptors,

and More

Tamper-Resistant Isolation of Cryptographic Functions

Enforces Security Perimeter Around Crypto Functions

and Crypto Storage Locations

Anticloning Protection

Crypto Peripheral for Implementing Secure NIC Adapt-

ers (10/100 Ethernet, Token Ring, ISDN)

Secure Modem-on-a-Chip (V.34, ADSL)

Secure Algorithm Download

SafeNet CGX LIBRARY

On-Chip SafeNet CGX Crypto Library with Flexible CGX

API

FEATURES

DES CRYPTO BLOCK

Includes Chained and Parallel Execution Commands

Such as Hash-and-Encrypt

Embodied as 32K Words (32K

؋

24) Kernel Program

Mask-Programmed into On-Chip ROM

On-Chip Protected 4K

؋

16 Security Scratchpad RAM

640 Mbps Sustained Performance—Single DES

214 Mbps Sustained Performance—Triple DES

Supports All Modes: ECB; CBC; 64-Bit OFB; and 1-, 8-,

64-Bit CFB. Includes Automatic Padding

Implements IPsec ESP Transforms Autonomously at

OC-3 (155 Mbps) Rates (3-DES, SHA-1)

RANDOM NUMBER GENERATOR

Hardware-Based Nondeterministic Random Number

Generator

HASH BLOCK

Hardware-Based SHA-1 and MD-5 Hashing

253 Mbps Sustained Performance—SHA-1

315 Mbps Sustained Performance—MD-5

Implements IPsec AH and HMAC Transforms

Generates Internal Session Keys That Are Never

Exposed Outside of the SafeNet DSP

Redundant Fail-Safe Design

Up to 1.3 Mbits of Random Data Available per Second

FUNCTIONAL BLOCK DIAGRAM

KERNEL

MODE

CONTROL

BUS_MODE

IDMA MODE

PCI MODE

16

32

16

32

16-

OR

32-BIT

BUS

IDMA

BUS

INTERFACE

INTERRUPTS

FLAGS

ADSP-218x

DSP CORE

DMA-32

CONTROLLER

PCI OR

CARDBUS

INTERFACE

KERNEL ROM

32K

؋

24

PROTECTED

SPORT 0

HASH

ENCRYPT

BLOCK

(DES, 3-DES)

KERNEL

RAM

PUBLIC KEY

ACCELERATOR

RNG

BLOCK

(MD-5, SHA-1)

SERIAL

PORTS

(4K

؋

16)

PROG ROM

16K

؋

24

BUS_MODE

BUS_SEL

EMI BUS

SPORT 1

DATA ROM

16K

؋

16

EXTERNAL

MEMORY

INTERFACE

LASER

VARIABLE

STORE

SERIAL

EEPROM

INTERFACE

INTERRUPT

CONTROLLER

APPLICATION

REGISTERS

TIMER

26-BITS

ADDR

32-BITS

DATA

PF7/INT_H

RAM/ROM

SafeNet is a registered trademark of Information Resource Engineering (IRE).

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Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADSP-2141L

GENERAL DESCRIPTION

PUBLIC KEY ACCELERATOR

The ADSP-2141L SafeNet DSP is a highly integrated embedded

security processor that incorporates a sophisticated, general

purpose DSP, along with a number of high performance Cryp-

tographic function blocks, as well as PCI, DMA and Serial

EEPROM interfaces. It is fabricated in 0.35 µ CMOS triple-

layer metal technology and uses a 3.3 V power supply. It is

available in a 208-lead MQFP package with a commercial (0°C

to 70°C) temperature range.

Accelerator for Math-Intensive Public Key Operations

Diffie-Hellman Negotiate: <29 ms (1024-Bit Modulus,

180-Bit Exponent)

RSA 1024-Bit Sign: <29 ms; RSA 1024-Bit Verify: 6 ms

DSA Sign: <39 ms; DSA Verify: <66 ms

KEY MANAGEMENT BLOCK

Laser-Programmed Unique Triple-DES Cryptovariable

Protects Off-Chip Storage

Support for Secure Storage of Both Secret Keys and

Public/Private Key Pairs

Trust-Model Rules Enforcement

Only Encrypted Keys May Be Exported Off the Chip

Internal Key Cache for 15 Keys—Can Be Expanded to

700 Keys On-Chip

Keys May Also Be Securely Stored Off-Chip, Allowing

Unlimited Storage

DSP Core

The DSP is a standard Analog Devices ADSP-218x core with

full ADSP-2100 family compatibility. The ADSP-218x Core

combines the base DSP components from the ADSP-2100

family with the addition of two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities, and on-chip program and data

memory. The external memory interface of the 218x core has

been extended to support up to 64M-words addressing for both

program and data memory. Some core enhancements have been

added in the ADSP-2141L, including on-chip security ROM

and interrupt functions. Refer to the Analog Devices ADSP-2183

data sheet for further information.

DSP CORE

40 MIPS Sustained Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

Zero-Overhead Looping

Low Power Dissipation

SafeNet CGX Library–Secure Kernel

The SafeNet CGX Library is a crypto library embodied as firm-

ware (a secure kernel) that is mask-programmed into ROM within

the DSP. This solution protects the library from tampering. The

CGX Library provides the Application Programming Interface

(API) to applications that require security services from the

ADSP-2141L. Those applications may be software executing in

user mode on the DSP, or they may be external host software

accessing the ADSP-2141L via a PCI bus. Approximately 40

Crypto commands—called CGX (CryptoGraphic eXtensions)—

are provided at the API and a simple control block structure is

used to pass arguments into the secure kernel and return status.

The CGX library includes integrated drivers for the various

hardware crypto blocks on the chip. This allows the program-

mer to ignore those details and concentrate on other product

design issues.

16K Words (16K

؋

24) On-Chip Program RAM

16K Words (16K

؋

16) On-Chip Data RAM

64M Words Off-Chip Program and Data Memory

Programmable 16-Bit Interval Timer with Prescale

PCI BUS/CARDBUS INTERFACE

32-Bit 3.3 V Bus Interface

33 MHz or 40 MHz* Bus Speed

Bus Master and Target Modes

Can Directly DMA Between Crypto Functions and Other

PCI Bus Agents

*66 MHz speed pending chip characterization.

The CGX library firmware runs under a protected mode state

of the DSP as described in the Kernel Mode Control section

following. This guarantees the security integrity of the system

during the execution of CGX processes and, for example, prevents

disclosure of cryptographic key data or tampering with a

security operation.

Kernel Mode Control

The Kernel Mode Control subsystem is responsible for enforcing

the security perimeter around the cryptographic functions of

the ADSP-2141L. The device may operate in either user mode

(kernel space is not accessible) or kernel mode (kernel space is

accessible) at a given time. When in kernel mode, the kernel RAM

and certain protected crypto registers and functions (kernel

space) are accessible only to the CGX library firmware. The

CGX Library executes host-requested macro-level functions

and then returns control to the calling application. The kernel

mode control subsystem resets the DSP should any security

violation occur, such as attempting to access a protected

memory location while in user mode.

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ADSP-2141L

PCI/Cardbus Interface

Protected Kernel RAM

A full 40 MHz/33 MHz PCI bus interface has been added to the

core DSP functions. The 32-bit PCI interface supports both bus

master and target modes. The ADSP-2141L is capable of using

DMA to directly access data on other PCI entities and pass that

data through its encryption/hash engines.

The 4K × 16 kernel RAM provides a secure storage area on the

ADSP-2141L for sensitive data such as keys or intermediate

calculations during public key operations. The Kernel Mode

Control subsystem (above) enforces the protection by allowing

only internal secure kernel mode access to this RAM. A public

keyset and a cache of up to 15 secret keys may be stored in kernel

RAM. Secure key storage may be expanded to 700 secret keys

by assigning segments of the DSP’s internal data RAM to be

protected. Furthermore, a virtually unlimited number of data

encryption keys may be stored in an encrypted form in off-chip

memory.

32-Bit DMA Controller

The ADSP-2141L incorporates a high performance 32-bit DMA

controller which can be set up to move data efficiently between

Host PCI memory, the hash/encrypt blocks, and/or external

memory. The DMA controller can be used with the PCI bus in

master mode, thus autonomously moving 32-bit data with mini-

mal DSP intervention. Up to 255 long words (1020 bytes) can

be moved in a burst at up to 160 Mbytes per second.

Encrypt Block

The encrypt block performs high speed DES and Triple-DES

encrypt/decrypt operations. All four standard modes of DES are

supported: Electronic Code Book (ECB), Cipher Block Chaining

(CBC), 64-bit Output Feedback (OFB) and 1-bit, 8-bit and 64-

bit Cipher Feedback (CFB). The DES encrypt/decrypt operations

are highly pipelined and execute full 16-round DES in only four

clock cycles. Hardware support for padding insertion, verification

and removal further accelerates the encryption operation. Con-

text switching is provided to minimize the overhead of changing

crypto keys and Initialization Vectors (IVs) to nearly zero.

Application Registers

The application registers are a set of memory-mapped registers

that facilitate communications between the ADSP-2141L and a

host processor via the PCI bus. One of the registers is a mailbox

that is 44 bytes long and set up to hold the CGX command

structure passed between the host and DSP processors. The

application registers also provide the mechanism that allows the

DSP and the external host to negotiate ownership of the hash/

encrypt block.

Hash Block

Serial EEPROM Interface

The secure hash block is tightly coupled with the encrypt block

and provides hardware accelerated one-way hash functions.

Both the MD-5 and SHA-1 algorithms are supported. Combined

operations that chain both hashing and encrypt/decrypt functions

are provided in order to significantly reduce the processing time

for data that needs both operations applied. For hash-then-encrypt

and hash-then-decrypt operations, the ADSP-2141L can perform

parallel execution of both functions from the same source and

destination buffers. For encrypt-then-hash and decrypt-then-hash

operations, the processing must be sequential, but minimum

latency is still provided through the pipeline chaining design. An

offset may be specified between the start of hashing and the

start of encryption to support certain protocols such as IPsec. A

‘mutable bit handler’ is also provided on the hash engine to

facilitate IPsec AH processing.

The serial EEPROM interface allows an external nonvolatile

memory to be connected to the ADSP-2141L for storing PCI

configuration information (Plug and Play), as well as general-

purpose nonvolatile storage. For example, encrypted (black)

keys could be stored into EEPROM for fast recovery after a

power outage.

Interrupt Controller

The DSP core provides support for 14 interrupt sources, includ-

ing six external and eight internal. All interrupts are prioritized

into 12 levels and interrupt nesting may be enabled or disabled

under software control. The security block interrupt controller

provides enhancements to the DSP interrupt functions.

Primarily, the interrupt controller provides a new interrupt

generation capability to the DSP or to an external host processor.

Under programmable configuration control, a crypto interrupt

may be generated due to completion of certain operations such

as encrypt complete, hash complete. The interrupt may either

be directed at the DSP core (on IRQ2), or provided on an out-

put line (PF7/INT_H) to a host subsystem.

Random Number Generator (RNG) Block

The hardware random number generator provides a true, non-

deterministic noise source for the purpose of generating keys,

Initialization Vectors (IVs), and other random number require-

ments. Random numbers are provided as 16-bit words to the

kernel. The CGX kernel requests random numbers as needed to

perform requested CGX commands such as CGX_Gen_Key,

and can also directly supply from 1 to 65,535 random bytes to a

host application via the CGX_Random command.

Laser Variable Storage

The laser variable storage consists of 256 bits of tamper-proof

factory-programmed data that is only accessible to the internal

function blocks and the security kernel. Included in these laser

variable bits are:

Public Key Accelerator

•

Local Storage Variable (master key-encryption key)

Randomizer Seed (to supplement the true entropy fed into

the RNG)

The public key accelerator module works in concert with the

CGX kernel firmware to provide full public key services to the

host application. The kernel provides macro-level functions to

perform Diffie-Hellman key agreement, RSA encrypt or decrypt,

DSA compute and verify digital signatures. The hardware accel-

erator block speeds computation-intensive operations such as

large vector multiply, add, subtract, square.

•

Program Control Data (enables/disables various features and

configures the ADSP-2141L)

CRC of the Laser Data (to verify laser data integrity).

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ADSP-2141L

The Program Control Data Bits (PCDBs) include configuration

for permitted key lengths, algorithm enables, Red KEK loading.

Most of the PCDB settings may be overridden with a digitally

signed token which may be loaded into the ADSP-2141L when

it boots. These tokens are created by IRE and each is targeted to

a specific ADSP-2141L using a hash of its unique identity.

ARCHITECTURE OVERVIEW

This section provides an architecture-level description of the

unique function blocks within the ADSP-2141L.

Memory Map

The ADSP-2141L memory map is very similar to that of the

ADSP-2183 DSP, except that it includes significantly more off-

chip memory addressing, and has additional crypto registers

which are accessible to the user.

Downloadable Secure Code

The ADSP-2141L allows additional security functions to be added

to the device through a secure download feature. Up to 16K

words of code may be downloaded into internal memory within

the DSP and this code can be given the security privileges of the

CGX kernel firmware. All downloaded firmware is authenticated

with a digital signature and verified with an on-chip public key.

Additional functions could include new encryption, hash or

public key algorithms such as IDEA, RC-4, RIPEMD, elliptic

curve, or any other application that needs direct control over the

protected cryptographic hardware.

DSP Core

The DSP core is architecturally identical to the ADSP-218x

with a few exceptions.

•

The memory map includes additional external memory

addressing through the PMOVLAY and DMOVLAY mecha-

nisms. For more information, see the Memory Map section.

•

Additional memory-mapped crypto registers are available in

the kernel data RAM space.

The PF7/INT_H flag pin may be reassigned to be the host

interrupt output.

0x3FFF

8K KERNEL TOP

KERNEL MODE

(PMOVLAYL = C)

(PMOVLAYH = 000)

8K KERNEL BASE

KERNEL MODE

(PMOVLAYL = F)

8K INTERNAL

PAGE

(PMOVLAYL = 0)

8K EXTERNAL

PAGE = 0

(PMOVLAYL = 1)

8K EXTERNAL

PAGE 1

(PMOVLAYL = 2)

8K KERNEL

PAGE 8191

(PMOVLAYL = 2)

(PMOVLAYH = FFF)

(PMOVLAYH = 000) (PMOVLAYH = 000) (PMOVLAYH = 000) (PMOVLAYH = 000)

0x2000

0x1FFF

UP TO 64 MEGAWORDS

8K INTERNAL

PMOVLAYL = LS NIBBLE OF PMOVLAY

PMOVLAYH = MS 3 NIBBLES OF PMOVLAY

EXTERNAL PROGRAM MEMORY

(COMMON BANK)

(PMOVLAYL ALTERNATES 2, 1, 2, 1...)

0x0000

SHADED = KERNEL SPACE

Figure 1. Program Memory (MMAP = 0)

0x3FFF

8K KERNEL TOP

KERNEL MODE

(PMOVLAYL = C)

8K KERNEL

KERNEL MODE

(PMOVLAYL = D)

8K KERNEL

KERNEL MODE

(PMOVLAYL = E)

8K KERNEL

KERNEL MODE

(PMOVLAYL = F)

8K INTERNAL

(PMOVLAYL = 0)

(PMOVLAYH = 000)

(PMOVLAYH = 000) (PMOVLAYH = 000) (PMOVLAYH = 000) (PMOVLAYH = 000)

0x2000

0x1FFF

PMOVLAYL = LS NIBBLE OF PMOVLAY

PMOVLAYH = MS 3 NIBBLES OF PMOVLAY

8K EXTERNAL

SHADED = KERNEL SPACE

0x0000

Figure 2. Program Memory (MMAP = 1)

0x3FFF

32

MEMORY-MAPPED

REGISTERS

0x3FE0

0x3FDF

UP TO 64 MEGAWORDS

EXTERNAL DATA MEMORY

(DMOVLAYL ALTERNATES 2, 1, 2, 1...)

8160 WORDS

INTERNAL

0x2000

0x1FFF

0x1800

0x17FF

0x1000

0x0FFF

MEMORY-MAPPED

REGISTERS

PROTECTED

4K KERNEL RAM

(DMOVLAY = 000F)

8K EXTERNAL

PAGE = 0

(DMOVLAYL = 1)

(DMOVLAYH = 000) (DMOVLAYH = 000)

8K EXTERNAL

PAGE 1

(DMOVLAYL = 2)

8K KERNEL

PAGE 8191

(DMOVLAYL = 2)

(DMOVLAYH = FFF)

8K INTERNAL

(DMOVLAYL = 0)

(DMOVLAYH = 000)

KERNEL MODE

0x0000

SHADED = KERNEL SPACE

Figure 3. Data Memory

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ADSP-2141L

•

IRQ2 now can include interrupt sources from the crypto

subsystem, depending on interrupt mask registers.

A new read register has been added to indicate the state of

interrupt enable and interrupt masks.

The kernel mode control subsystem has been added to super-

vise the protected mode of operation of the DSP core.

Internal RAM protection logic has been added to allow the

kernel to seize increments of 1K word of internal PRAM and

DRAM.

Bus mode configuration (218x vs. PCI) pins have been added.

32K words of kernel program ROM have been added to the

DSP memory space. (See the Memory Map section.)

set to 0x000F. Once in kernel mode, any branch to nonkernel

space program memory causes the DSP to return to user mode.

(Note: For security reasons when in kernel mode, the DSP does

not respond to Emulator bus requests.)

The kernel mode can be interrupted during execution; however,

during certain periods where sensitive data is being moved, all

interrupts are disabled. Within the interrupt service routine,

another call to the kernel (CGX call) may be made if desired,

although there are limitations on which CGX commands may

preempt another. (For information, see the ADSP-2141L CGX

Interface Programmer’s Guide http://www.ire-ma.com/proddoc.htm.)

Only one level of kernel mode nesting is permitted. An interrupt

to a user mode vector location while in nested kernel mode will

also trigger the violation reset logic.

•

Kernel Mode Control

The kernel mode control subsystem provides the following

functions which serve to enforce the security integrity of the

ADSP-2141L:

Once the interrupt service routine is finished, the return-from-

interrupt must return control back to the kernel at the address/

overlay that was originally interrupted, otherwise the protection

logic will issue a chip reset.

•

Provide a means to securely enter the kernel mode.

Provide a means to properly exit the kernel mode.

Prevent user mode access to protected memory and register

locations.

Hash and Encrypt Block Overview

The encrypt block is tightly coupled to the hash block in the

ADSP-2141L and therefore the two are discussed together.

Refer to Figure 4, Hash/Encrypt Functional Block Diagram, for

the following description.

•

Manage interrupts during kernel mode executions.

Manage the reset function to ensure that sensitive variables

in DSP registers are erased.

The algorithms implemented in the combined hash and encryp-

tion block are: DES, Triple DES, MD-5 and SHA-1. Data can

be transferred to and from the module once to perform both

hashing and encryption on the same data stream. The DES

encrypt/decrypt operations are highly paralleled and pipelined,

and execute full 16-round DES in only four clock cycles. The

internal data flow and buffering allows parallel execution of

hashing and encryption where possible, and allows processing of

data concurrently with I/O of previous and subsequent blocks.

Most of the kernel mode control functions are implemented in

the hardware of the ADSP-2141L and are not directly visible to

nonkernel applications (user mode). Any attempt by a user

mode application program running on the DSP to access a

kernel space addresses (PRAM 0x2001 – 0x3FFF, PMOVLAY

000C – 000F; or DRAM 0x0000 – 0x17FF, DMOVLAY 000F)

results in an immediate chip reset and all sensitive registers and

memory locations are erased. Kernel mode may only be entered

via a call, jump or increment to address 0x2000 with PMOVLAY

7

REGISTER

ADDRESS

RD

WR

PAD

CONSUME

PAD

INSERTION

AND VERIFY

512-BIT

FIFO

DSP

OR

PCI

ENCRYPT/

DECRYPT

BLOCK

DSP

OR

PCI

READ

CONTEXT

WRITE

CONTEXT

STORAGE (0/1)

16-/32-BIT

OUTPUT

BUS

512-BIT

FIFO

HASH

DIGEST

16-/32-BIT

INPUT

BUS

HASH

BLOCK

PAD

INSERTION

MUTABLE BIT

PROCESSING

(ENCRYPT-THEN-HASH)

(DECRYPT-THEN-HASH)

Figure 4. Hash/Encrypt Functional Block Diagram

–5–

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ADSP-2141L

with trailing pad length and next header byte (for IPsec), or

fixed character padding. Note that for the IPsec and PKCS#7

pad protocols, there are cases where the padding not only fills

out the last 8-byte block, but also causes an additional 8-byte

block of padding to be added.

Context switching is optimized to minimize the overhead of

changing cryptographic keys to near zero.

The software interface to the module consists of a set of

memory-mapped registers, all of which are visible to the DSP and

most of which can be enabled for host access via the PCI bus. A

set of five, 16-bit registers define the operation to be performed,

the length of the data buffer to be processed, in bytes, the offset

between the start of hashing and encryption (or vice versa), and

the padding operation. If the data length is unknown at the time

the encrypt/decrypt operation is started, the data length register

may be set to zero, which specifies special handling. In this case,

data may be passed to the hash/encrypt block indefinitely until

the end of data is encountered. At that time, the operation is

terminated by writing a new control word to the hash/encrypt

control register (either to process the next packet or to invoke

the idle state if there is no further work to do). This will close

out the processing for the packet, including the addition of the

selected crypto padding.

For the hash operations, padding is automatically added as

specified in the MD-5 and SHA-1 standards. When the hash

final command is issued indicating the last of the input data, the

algorithm-specified padding and data count bits are added to the

end of the hash input buffer prior to computing the hash.

Data Offsets

Certain security protocols, including IPsec, require portions of a

data packet to be hashed while the remainder of the data is both

hashed and encrypted. The ADSP-2141L supports this require-

ment through the OFFSET register, which allows specifying the

number of 32-bit dwords of offset between the hash and encrypt/

decrypt operations.

Black Key Loads

A set of seven status registers provides information on when a

new operation can be started, when there is space available to

accept new data, when there is data available to be read out, and

the results from the padding operation.

The cryptographic keys loaded as part of a crypto-context can

be stored off-chip in a black, or encrypted, form. If the appropri-

ate control bit is set (HECNTL Bit 15), the DES or 3-DES key

will be decrypted immediately after it is written into the context

register. The hardware handles this decryption automatically.

The Key Encryption Key (KEK) that covers the black keys

is loaded in a dedicated write-only KEK register within the

ADSP-2141L. The IV for decrypting the black secret key is

called ‘salt’ and must be stored along with the black key (as part

of the context). Note that 3-DES CBC mode is used for pro-

tecting 3-DES black keys and single DES CBC is used for

single DES black keys.

Crypto Contexts

There are two sets of crypto-context registers. Each context

contains a DES or triple DES key, initialization vector, and

precomputed hashes (inner and outer) of the authentication key

for HMAC operations. The contexts also contain registers to

reload the byte count from a previous operation (which is part

of the hashing context), as well as an IV (also called salt) for

decrypting a black key, if necessary.

When black keys are used, the key-decrypt operation adds a

6-cycle overhead (0.15 µs @ 40 MHz) for DES keys or 36-cycle

overhead (0.9 µs @ 40 MHz) for triple DES keys each time a

new crypto-context is loaded. (Note that if the same context is

used for more than one packet operation, the key decryption does

not need to be performed again.) Depending on the sequencing

of operations, this key decryption may in fact be hidden (from a

performance impact perspective) if other operations are underway.

This is because the black key decryption process only requires

that the DES hardware be available. For example, if the DSP is

reading the previous hash result from the output FIFO, the

black key decryption can be going on in parallel. Also note that

the data driver firmware does NOT have to wait for the key to

be decrypted before writing data to the input FIFO. The hard-

ware automatically waits for the key to be decrypted before

beginning to process data for a given packet. So, with efficient

pipeline programming, it is possible to make the impact of black

key essentially zero.

Once a crypto-context has been loaded and the operation

defined, data is processed by writing it to a data input FIFO. At

the I/O interface, data is always written to, or read from, the

same address. Internally, the hash and encryption functions

have separate 512-bit FIFOs, each with their own FIFO man-

agement pointers. Incoming data is automatically routed to one

or both of these FIFOs, depending on the operation in progress.

Output from the encryption block is read from the data output

FIFO. In encrypt-hash or decrypt-hash operations, the data is

also automatically passed to the hashing data input FIFO. Output

from the hash function is always read from the digest register of

the appropriate crypto-context.

The initialization vector to be used for a crypto operation can be

loaded as part of a crypto-context. When an operation is complete,

the same context will contain the resulting IV produced at the

end, which can be saved away and restored later to continue the

operation with more data.

In certain packet-based applications such as IPsec, a feature is

available that avoids the need for the control software to generate

and load random IVs for outgoing (encrypted) packets. Effec-

tively, the IV register can be configured to be automatically

updated with new random numbers for each encrypted packet,

with almost no software intervention.

The KEK for key decryption is loaded via the secure kernel

firmware using one of the CGX key manipulation commands.

(For more information, see the Command Summary section.)

This KEK is typically the same for all black keys, since it is usually

protecting local storage only. It is designated the DKEK in the

CGX API.

Padding

One of the laser-programmed configuration bits specifies whether

red (plaintext) keys are allowed to be loaded into the ADSP-

2141L from a host. If the AllowRedKeyLoad laser bit is not set,

keys may only be loaded in their black form. This is useful in

systems where export restrictions limit the key length that may

be used or where the external storage environment is untrusted.

When the input data is not a multiple of eight bytes (a 64-bit

DES block), the encrypt module can be configured to automati-

cally append pad bytes. There are several options for how the

padding is constructed, which are specified using the pad control

word of the operation description. Options include zero padding,

pad-length character padding (PKCS#7), incrementing count,

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ADSP-2141L

If the AllowRedKeyLoad bit is set, keys may be loaded either in

their black form, or in the red or unencrypted form. Note that

the laser configuration bit may be overridden with a signed

enabler token. (For more information, see the Laser Variable

Storage section.)

result, as well as specifying the length and operation type. Once

the operation type field is written, the processor polls the opera-

tion complete status while the calculation is carried out.

The PKAC utilizes the protected kernel RAM for input, output

and intermediate variable storage. It may only be accessed from

the secure kernel mode. Since public key computations typically

take many milliseconds to complete, they may be preempted

using a DSP interrupt.

Depending on the definition of the security module boundary in

a given application, FIPS 140-1 may require the use of black

keys to protect key material. In other words, if the security

boundary does not enclose the database where keys are stored,

those keys must be protected from compromise. Black key is a

satisfactory way to meet this FIPS requirement.

Most application interaction with the public key accelerator will

occur via the CGX software interface (see the Command Inter-

face section). Both high level public key operations such as RSA

Sign or Create Diffie-Hellman Key, as well as primitive operations

such as Multiply Vector, Add Long Vector, etc., are presented

via the CGX interface.

Random Number Generator (RNG) Block

The random number generator is designed to provide highly

random, nondeterministic binary numbers at a high delivery rate

with little software intervention. The random numbers are acces-

sible to the kernel firmware in a 16-bit register that may be read

by the DSP in kernel mode. Once the register is read, the RNG

immediately generates a new 16-bit value that is available within

12 microseconds.

PCI/Cardbus Interface

The ADSP-2141L appears as a target on the PCI Bus as a single

contiguous memory space of 128k bytes. In this memory space,

the host can access the following:

•

The unprotected internal crypto registers of the ADSP-2141L

IDMA access to the DSP’s internal program memory (PM)

and data memory (DM)

All application-level access to random numbers should occur

through the Kernels CGX_RANDOM command (see the

Command Summary section).

•

Paged access to external memory connected to the

ADSP-2141L

The Kernel RAM (KRAM) if it has been unprotected by an

extended mode program

The random number generator is designed using a “shot noise”

true entropy source which is sampled by the master 40 MHz

clock of the ADSP-2141L. The entropy source then feeds a

complex nonlinear combinatorial circuit that produces the final

RNG output based on the interaction of the entropy source and

the 40 MHz system clock. Over 200 stages of Linear Feedback

Shift Register (LFSR) are incorporated into the RNG design.

As a PCI Master, the ADSP-2141L can transfer data between:

•

The unprotected internal crypto registers and FIFOs of the

ADSP-2141L and PCI Host memory

•

External memory and PCI Host memory

In order to facilitate FIPS 140-1 compliance, an option may be

selected during CGX kernel initialization to enable an ANSI

X9.17 Annex C post-randomizer to be applied to the output of

the RNG. This randomizer applies the DES ECB algorithm

multiple times to further disperse and whiten the random source.

Although this is not necessary to ensure the quality of the random

numbers, it meets the criteria for a NIST-approved random num-

ber generation algorithm.

A 32-bit DMA engine within the ADSP-2141L facilitates these

transfers and permits full PCI bandwidth use.

Serial EEPROM Interface

The serial EEPROM interface allows the ADSP-2141L to auto-

matically read the PCI configuration parameters at chip power-up.

IRE can provide the data content for the EEPROM to properly

set the chip device vendor ID, type and properties for full com-

pliance with the PCI Plug and Play standards.

Public Key Accelerator (PKAC)

The public key arithmetic coprocessor (otherwise known as a

BigNum processor) is designed to support long vector calcula-

tions of the kind needed to perform RSA, Diffie-Hellman and

Elliptic Curve operations.

In addition to being used for storage of host bus parameters, any

extra space in the EEPROM may be accessed by the DSP, either

in user mode or kernel mode. Support for this function is not

included in the standard CGX command set. Refer to the

ADSP-2141 User’s Manual for the information on the data

contents of the EEPROM. Refer to http://www.analog.com/

industry/dsp/ire.html.

The PKAC can perform multiplication, squaring, addition and

subtraction on arbitrary length bit vectors. The CGX software is

responsible for setting the address register for the operands and

Table I. Interrupt Sources

Internal Interrupt Sources

External Interrupt Sources

Interrupt Notes

Interrupt

Notes

Reset

or Power-Up (PUCR = 1)

IRQ2

IRQL1

IRQL0

IRQE

IRQ1

Edge- or Level-Sensitive

Level-Sensitive

Edge-Sensitive

Edge- or Level-Sensitive

Power-Down

SPORT0 Transmit

SPORT0 Receive

BDMA Interrupt

SPORT1 Transmit Mixed with IRQ1

IRQ0

SPORT1 Receive

Mixed with IRQ0

Timer

REV. 0

–7–

ADSP-2141L

Interrupt Controller

•

48-Bit Program Control Data (enables/disables various fea-

tures and configures the ADSP-2141L)

CRC of the Laser Data (to verify integrity of the laser bits)

The DSP core of the ADSP-2141L provides a powerful set of

interrupt sources. A total of 14 interrupt sources are available,

although two pairs are multiplexed, yielding 12 simultaneous

sources. Refer to Table I.

The LSV is a unique triple DES master key-encrypting key that

allows the ADSP-2141L to securely store data (primarily other keys)

off-chip for later reloading. This is necessary if more storage space

is needed than is available with on-chip RAM, or if keys need to

be saved and restored after a power outage. Each ADSP-2141L

produced is programmed with a unique, randomly generated

local storage variable.

The ADSP-2141L enhances the existing interrupt controller

within the ADSP-218x DSP Core with some additional func-

tions related to the crypto functional blocks and the external

host bus interfaces. Two additional interrupt controller sub-

systems have been added to the basic interrupt controller as

shown in Figure 5.

The internal seed variable is used to randomly initialize the

RNG circuits before the entropy is mixed in. Each ADSP-2141L

produced is programmed with a unique, randomly generated

internal seed variable which is loaded into the RNG at chip boot

time and cannot ever be read by software.

The DSP interrupt controller allows programming between one

and nine sources for the IRQ2 interrupt to the DSP. The

DIMASK register provides the mask to select which interrupt

source is enabled. A pair of status registers, DUMSTAT and

DMSTAT, allow the DSP firmware to read the status of any

interrupt source either before or after the mask is applied.

The 48 Program Control Data Bits (PCDBs) include configura-

tion for permitted key lengths, algorithm enables, red KEK

loading, internal IC pulse timing characteristics. The PCDBs

provide configuration data that falls into three categories:

The host interrupt controller allows programming between one

and five sources for the PF7/INT_H interrupt output signal

(which may be connected to the interrupt input of the host

system). The HMASK register provides the mask to select which

interrupt source is enabled. A pair of status registers, HUMSTAT

and HMSTAT, allow the host firmware to read the status of any

interrupt source either before or after the mask is applied.

• Internal IC pulse-timing characteristics

• ADSP-2141L hardware version number field

• ADSP-2141L feature enables

The first two categories consist of data that cannot be altered

once the ADSP-2141L has been fabricated.

Laser Variable Storage

The laser variables are configured through 256 Fuses in the

ADSP-2141L, which are programmed during IC manufacture.

Each ADSP-2141L produced is programmed with a unique set

of Laser Variables.

The feature enables can be overridden using a factory token

enabler which may be passed to the CGX kernel as part of the

CGX_INIT command. This token is digitally signed with an

IRE private key and verified internal to the ADSP-2141L with

its public key. The CGX_INIT command is documented in the

ADSP-2141 CGX Interface Programmer’s Guide (available from

http://www.ire-ma.com/proddoc.htm).

•

Local Storage Variable (LSV—the Master Key-Encryption-Key)

Internal Seed Variable

DSP

DSP INTERRUPT CONTROLLER

HOST INTERRUPT CONTROLLER

DICFG

DICLR

HICFG

HICLR

DIFRC

HIFRC

INTERNAL

DIMASK

HIMASK

ADSP-2183

INTERRUPT

CONTROLLER

INTERRUPTS

DSP

HOST

RESET

POWER DOWN

SPORT0 Tx

SPORT0 Rx

BDMA INT

TIMER INT

SPORT1 Tx

SPORT1 Rx

INTERRUPT

H/E CONTEXT1

DONE

ICNTL

IMASK

IFC

H/E CONTEXT1

DONE

H/E CONTEXT0

DONE

HOST

WROTE CMD

H/E CONTEXT0

DONE

DMA xFER

DONE

INTH

TO HOST

IRQ2

DSP

WROTE

CMD

DMA xFER

QUEUED

EXT MEM

CONFLICT

EXTERNAL

HASH/ENC

ERROR

INTERRUPTS

HASH/ENC

ERROR

IRQE

IRQL0

IRQL1

IRQ0

IRQ2

IRQ1

IRQ2

CRYPTO INTERRUPT

SUBSYSTEM BOUNDRY

Figure 5. Interrupt Controller Block Diagram

–8–

REV. 0

ADSP-2141L

PIN FUNCTIONS

I/O Descriptions

This section describes the physical I/O hardware on the ADSP-2141L.

PIN FUNCTION DESCRIPTIONS–I/O Hardware

Input/

# of

Pins

Pin Name

Output

Function

External Memory Bus

Address [25:0]

26

32

O

Address Output Pins for Program, Data, Byte and I/O Spaces (13 Bits 2183, 13 Bits

from Overlay Register) Note: A0 not used for 32-bit memory.

Data I/O Pins for Program and Data Memory Spaces

D31:0 are used for wide-bus data memory.

D23:0 are used for DSP Program RAM.

Data [31:0]

I/O

D23:8 are used for I/O Space.

D23:8 are used for DSP Data RAM.

D15:8 are used for byte memory.

D23:16 are also used as Byte Space Addresses

Interrupts

IRQ2

IRQL0

IRQL1

IRQE

1

I

Edge- or Level-Sensitive Interrupt Request

Level-Sensitive Interrupt Requests

Edge-Sensitive Interrupt Request

Bus Signals

BR

BG

BGH

PMS

DMSL

DMSH

BMS

1

I

Bus Request Input

Bus Grant Output

Bus Grant Hung Output

Program Memory Select Output

Data Memory Select Output (Lower 16 Bits for 32-Bit DM)

Upper Memory Select Output (Upper 16 Bits for 32-Bit DM, Not Used for 16-Bit DM)

Byte Memory Select Output

I/O Space Memory Select Output

Combined Memory Select Output (PMS, DMS*, IOMS, BMS)

Memory Read Enable Output

O

IOMS

CMS

RD

WR

Memory Write Enable Output

Miscellaneous

MMAP

BMODE

CLKIN, XTAL

CLKOUT

1

2

1

I

O

Memory Map Select Input (1 = Overlay External at 0x0000)

Boot Option Control Input (0 = BDMA, 1 = IDMA)

Clock or Quartz Crystal Input (1/2 of the ADSP-2141 Clock)

Processor Clock Output

Serial Ports

SPORT0

SCLK0

DR0

RFS0

DT0

1

I/O

I

I/O

O

Serial Port 0 Clock

Serial Port 0 Receive Data Input

Serial Port 0 Receive Frame Sync

Serial Port 0 Transmit Data Output

Serial Port 0 Transmit Frame Sync

TFS0

I/O

SPORT1

Port Configuration

(System Control Reg) –>

SCLK1

DR1

RFS1

1 = Serial Port

Serial Port 1

Serial Port 1 Receive Data Input

Serial Port 1 Receive Frame Sync

Serial Port 1 Transmit Data Output

Serial Port 1 Transmit Frame Sync

0 = Other

Clock

Flag In

IRQ0

Flag Out

IRQ1

1

I/O

I

I/O

O

I/O

DT1

TFS1

Power-Down

PWD

PWDACK

1

I

O

Power-Down Initiate Control

Power-Down Acknowledge

REV. 0

–9–

ADSP-2141L

# of

Pins

Input/

Output

Pin Name

Function

Flags

PF6:0

PF7/INT_H

7

1

I/O

Programmable I/O Pins

Programmable I/O Pin–or–Interrupt Output (Host Mode)

Emulator

EE

EBR

EBG

ERESET

EMS

EINT

ECLK

ELIN

1

(Emulator Only)

ELOUT

Serial EEPROM Interface

EE_DI

EE_DO

EE_CS

EE_SK

1

O

I

O

Serial EEPROM Data In

Serial EEPROM Data Out

Serial EEPROM Chip Select

Serial EEPROM Clock

Bus Select

BUS_MODE

BUS_SEL

1

I

Processor Bus Select

Bus Select

PCI Bus (Dedicated Pins)

PCI_CLK

PCI_PAR

PCI_IRDY

PCI_STOP

1

I

PCI Clock

PCI Parity Bit

PCI Initiator Ready

PCI Abort Transfer

I/O

*When DMS is enabled for generation of CMS, the CMS is activated for DSP access to external memory only, NOT for DMA controller accesses.

Bus Mode Descriptions

The Pin Function Descriptions, Bus Mode table, shows the multiplexed pins in 2183 and PCI mode. For more information on the

PCI pins MPLX1–MPLX12, see the Pin Functions Description–PCI Mode Multiplex Bus table on the following page.

PIN FUNCTION DESCRIPTIONS—Bus Mode

# of

Pins

Input/

Output

2183 Mode

(bus_mode = 0, bus_sel = 0)

PCI Mode

(bus_mode = 1, bus_sel = 0)

Bus Mode

MPLX_RESET

MPLX1

MPLX2

MPLX3

MPLX4

MPLX5

MPLX6

MPLX7

MPLX8

1

32

I

RESET_1

Pci_rst

I/O

I

Pci_cbe3

Pci_cbe2

Pci_cbe1

Pci_cbe0

Pci_idsel

Pci_gnt

Pci_frame

Pci_devsel

Pci_trdy

Pci_perr

Pci_serr

IRD

IWR

IS

IAL

IACK

FL0

FL1

FL2

I

I/O

O

MPLX9

MPLX10

MPLX11

MPLX12

MPLX_BUS[31:0]

Pci_req

Pci_ad15:0

I/O

IAD15:0

N/C 31:16

Pci_ad31:16

Power

GND

VDD

24

22

–

Ground Pins

Power Supply Pins (3.3 V)

Total:

208

Includes the pins from this table and the I/O Hardware Pin Function Description table.

REV. 0

–10–

ADSP-2141L

IDMA Mode Multiplex Bus Pin Definition

IDMA Port (218x Mode)

PIN FUNCTION DESCRIPTIONS—IDMA Mode Multiplex Bus

Pin Name

IDMA Name

Pins

I/O

Description

MPLX5

MPLX6

MPLX7

IRD

IWR

IS

1

I

IDMA Port Read Input

IDMA Port Write Input

IDMA Port Select

MPLX8

MPLX9

MPLX10

MPLX11

MPLX12

MPLX_BUS

IAL

IACK

FL0

FL1

FL2

IAD

1

16

I

IDMA Port Address Latch

IDMA Port Access Ready Acknowledge

Output Flags

O

I/O

IDMA Data I/O

PCI Port

PIN FUNCTION DESCRIPTIONS—PCI Mode Multiplex Bus

Pin Name

PCI Name

Pins

I/O

Description

MPLX1

MPLX2

MPLX3

MPLX4

MPLX5

MPLX6

MPLX7

MPLX8

MPLX9

MPLX10

MPLX11

MPLX12

MPLX_BUS

Pci_cbe3

Pci_cbe2

Pci_cbe1

Pci_cbe0

Pci_idsel

Pci_gnt

Pci_frame

Pci_devsel

Pci_trdy

Pci_perr

Pci_serr

1

I/O

I

Bus Command / Byte Enable 3

Bus Command / Byte Enable 2

Bus Command / Byte Enable 1

Bus Command / Byte Enable 0

Initialization Device Select

Bus Grant

Cycle Frame

Device Select

Target Ready

Parity Error

I

I/O

O

System Error

PCI Bus Request

Pci_req

Pci_ad15:0

Pci_ad31:16

Pci_intA

32

1

I/O

O

PCI Address/Data Bus

PCI Interrupt A Request

PF7/INT_H

SYSTEM INTERFACE

specifying only the starting address of the block. This increases

throughput as the address does not have to be sent for each

memory access.

The ADSP-2141L may be integrated into a wide variety of sys-

tems, including those that already have a microprocessor and

those that will use the ADSP-2141L as the main processor. The

device can be configured into one of two Host Bus modes:

IDMA or PCI.

The IDMA port access occurs in two phases. The first is the

IDMA address latch cycle. When the acknowledge is asserted, a

14-bit address and 1-bit destination type can be driven onto the

bus by an external device. The address specifies an on-chip

memory location; the destination type specifies whether it is a

DM or PM access. The falling edge of the address latch signal

latches this value to the IDMAA register.

IDMA Bus Mode

The IDMA bus mode operates the same as in a native ADSP-

218x device, as described in this section.

The IDMA port provides an efficient means of communication

between a host system and the ADSP-2141L. The port is used

to access the on-chip program memory and data memory of the

DSP with only one DSP cycle per word overhead. The IDMA

port cannot, however, be used to write to the DSP’s memory-

mapped control registers.

Once the address is stored, data can either be read from or

written to the ADSP-2141L’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD and

IWR respectively) signals the ADSP-2141L that a particular

transaction is required. In either case, there is a one-processor-

cycle delay for synchronization. The memory access consumes

an additional processor cycle.

The IDMA port has a 16-bit multiplexed address and data bus,

and supports reading or writing 16-bit data (DM) or 24-bit

program memory (PM). The IDMA port is completely asyn-

chronous and can be written to while the ADSP-2141L is oper-

ating at full speed.

Once an access has occurred, the latched address is automati-

cally incremented and another access can occur.

Through the IDMAA register, the ADSP-2141L can also

specify the starting address and data format for DMA operation.

The DSP memory address is latched and then automatically

incremented after each IDMA transaction. An external device can

therefore access a block of sequentially addressed memory by

Figure 6 illustrates a typical system configuration for the

IDMA mode.

REV. 0

–11–

ADSP-2141L

EXTERNAL

MEMORY BUS

ADSP-2141

26

A13–0

CLKOUT

ADDR25–0

A0-A21

D23–16

D15–8

1/2X CLOCK

OR

CRYSTAL

CLKIN

XTAL

BYTE

MEMORY

(BOOT

32

DATA 31–0

DATA

LOADER)

FL0–2

PF0–7

BMS

CS

IRQ2

A10–0

D23–8

IRQE

IRQL0

IRQL1

INTERRUPT

SOURCES

ADDR

16-BIT

I/O SPACE

2048

DATA

LOCATIONS

IOMS

CS

SPORT1

SCLK1

A25–0

D23–0

PROGRAM

OVERLAY

MEMORY

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

ADDR

DATA

SERIAL

DEVICE

8192

8K

؋

24

PMS

PM SEGMENTS

CMS

(OPTIONAL)

SPORT0

SCLK0

RFS0

A25–0*

SERIAL

DEVICE

D15–0

DATA

TFS0

OVERLAY

MEMORY

DT0

DR0

D31–16

8192

DMSH

DMSL

8K

؋

16

IDMA PORT

SEGMENTS

IRD

IWR

IS

IAL

IACK

SYSTEM

INTERFACE

OR

UP TO 32M

؋

32

BR

BG

BUS

ARBITER

␮CONTROLLER

16

BGH

IAD15–0

PWD

MPLX31–16

NC

PWDACK

RESET

VDD

BUS_MODE

BUS_SEL

PCI_CLK

PCI_PAR

PCI_IRDY

PCI_STOP

NC

MMAP

VDD OR GND

BMODE

EE_DI

EEPROM

*ADDR0 FROM THE ADSP-2141

IS NO CONNECT FOR 32-BIT MEMORY.

ADSP-2141 ADDR1 IS WIRED TO RAM A0.

EE_DO

EE_CS

EE_SK

NC

Figure 6. ADSP-2141L IDMA System Configuration

REV. 0

–12–

ADSP-2141L

PCI Bus Mode

Figure 7 illustrates a typical system configuration for the

PCI mode.

EXTERNAL

MEMORY BUS

ADSP-2141

26

A13–0

CLKOUT

ADDR25-0

A0-A21

D23–16

D15–8

1/2X CLOCK

OR

CRYSTAL

CLKIN

XTAL

BYTE

MEMORY

(BOOT

32

DATA 31-0

DATA

LOADER)

PF0–6

BMS

CS

IRQ2

A10–0

D23–8

IRQE

IRQL0

IRQL1

INTERRUPT

SOURCES

ADDR

16-BIT

I/O SPACE

2048

DATA

LOCATIONS

IOMS

CS

SPORT1

SCLK1

A25–0

D23–0

PROGRAM

OVERLAY

MEMORY

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

ADDR

DATA

SERIAL

DEVICE

8192

8K

؋

24

PMS

PM SEGMENTS

CMS

(OPTIONAL)

SPORT0

SCLK0

RFS0

A25–0*

SERIAL

DEVICE

D15–0

TFS0

DATA

OVERLAY

MEMORY

DT0

DR0

D31–16

8192

DMSH

DMSL

8K

؋

16

PCI PORT

PCI_CBE3-0

PCI_IDSEL

PCI_REQ

4

SEGMENTS

UP TO 32M

؋

32

PCI_GNT

BR

BG

PCI_FRAME

PCI_DEVSEL

PCI_TRDY

PCI_PERR

PCI_SERR

BUS

ARBITER

BGH

PCI

BUS

PWD

PWDACK

32

VDD

PCI_AD31–0

PCI_RST

PCI_CLK

BUS_MODE

BUS_SEL

*ADDR0 FROM THE ADSP-2141

IS NO CONNECT FOR 32-BIT MEMORY.

ADSP-2141 ADDR1 IS WIRED TO RAM A0.

PCI_PAR

PCI_IRDY

PCI_STOP

PF7/INT_H

MMAP

VDD OR GND

BMODE

INTA

EE_DI

EEPROM

EE_DO

EE_CS

EE_SK

SERIAL

EEPROM

Figure 7. ADSP-2141L PCI System Configuration

REV. 0

–13–

ADSP-2141L

Table III. Boot Mode Selection

DEVICE OPERATION

OPERATIONAL MODES

Boot Mode Pins

BMODE

MMAP

Security Modes

The ADSP-2141L operates in one of two security modes: kernel

mode or user mode. The mode switching is performed on the fly

as program execution proceeds. Kernel mode is entered via a

jump or call to address 0x2000 with PMOVLAY set to 0x000F.

Kernel mode will exit on its own once it has completed a requested

operation (or terminates due to an error).

Byte-Wide (BDMA) Boot Mode

Host Bus (IDMA) Boot Mode

External Program Boot Mode

0

1

0

1

The hardware pin states are not relevant after the ADSP-2141L

comes out of power-up reset. Refer to the ADSP-2141L User’s

Manual (available from IRE) for information on BDMA, IDMA

and external program boot modes.

Special interrupt handling is performed if the DSP is executing

in kernel mode. While executing a CGX command in kernel

mode, it is possible to interrupt to a nonprotected vector loca-

tion and then invoke the kernel again during the interrupt han-

dler. The [IF CONDITION] RTI instruction must be used to

return to the kernel from the interrupt handler. The return

address and PMOVLAY page must match the interrupted ad-

dress and PMOVLAY page. If not, the violation reset logic will

be triggered. Only one level of kernel mode nesting is permitted.

An interrupt to a nonprotected vector location while in nested

kernel mode will also trigger the violation reset logic.

COMMAND INTERFACE

This section provides a general overview of the software com-

mand interface to the crypto functions in the ADSP-2141L.

Refer to the ADSP-2141 CGX Interface Programmer’s Guide

(available from http://www.ire-ma.com/proddoc.htm) for more

details.

Overview

The ADSP-2141L provides an embedded crypto library that

provides a command interface API (Application Programming

Interface) to outside applications. These commands are referred

to as CGX (CryptoGraphic eXtensions).

While in kernel mode, it is possible to interrupt to a protected

vector location. In this case, the processor remains in kernel

mode. The [IF CONDITION] RTI instruction must be used to

return the processor from the interrupt handler. There is no

imposed limit on the number of nested interrupts to a protected

vector location.

The CGX API simultaneously enforces certain security policies

within the ADSP-2141L and insulates applications from the

details of many complex cryptographic operations. The security

policy built into the ADSP-2141L has some of the following

rules:

Bus Modes

The ADSP-2141L Host Bus may be configured for one of two

personalities: IDMA Mode or PCI Bus Mode. The selection of

mode is made with two hardware control inputs BUS_MODE

and BUS_SEL at boot time.

•

Unencrypted (red) keys may never be retrieved from the

ADSP-2141L.

Keys within the ADSP-2141L are marked with an attributes

field that specifies key type and trust level.

Table II. Bus Mode Selection

A key’s type field must match the use in a requested opera-

tion (i.e., cannot use a KEK to encrypt traffic).

Bus Mode Pins

BUS_MODE

BUS_SEL

Keys generated internal to the ADSP-2141L (i.e., from RNG)

are marked as trusted.

IDMA Mode

PCI Bus Mode

0

1

0

Keys that are negotiated or imported from outside systems are

marked untrusted (although they may still be quite secure).

This selection may not be changed after the ADSP-2141L

comes out of power-up reset. It is typically expected that the bus

mode signals are tied to ground or VDD on the PC Board.

Separate trusted and untrusted key hierarchies may be main-

tained and customer applications may choose which trust

level is required for a given command.

Boot Modes

The ADSP-2141L may be bootstrap-loaded from one of three

sources: byte-wide memory, host processor bus, or external

program memory. The selection of mode is made with two

hardware control inputs BMODE and MMAP. When the host

processor boot mode is selected, any one of the two bus modes

may be used.

For most key management operations, the CGX interface must

be used. However, for certain high performance encryption/

hashing applications, the CGX interface may be bypassed and

either the DSP or a host processor may exercise direct control

over the hash/encrypt block.

REV. 0

–14–

ADSP-2141L

COMMAND SUMMARY

Approximately 40 CGX Commands are supported in the API to the ADSP-2141L.

General Utilities

INIT

Initializes Secure Kernel and Allow Reconfiguration of the ADSP-2141L

Restores Factory Default Settings

Generates Random Numbers (between 1K and 64K bytes)

Returns ADSP-2141L System Information

Runs a suite of self-tests on the hardware and CGX

DEFAULT

RANDOM

GET CHIPINFO

SELF TEST

Symmetrical Key Management

UNCOVER KEY

GEN KEY

GEN KEK

GEN RKEK

Loads and Decrypts a Secret Key

Generates a Secret Key

Generates an Internal Key Encryption Key

Generates a Key Recovery Key Encryption Key

Saves a key protected by the Recovery Key (RKEK)

Imports a Red (plaintext) User Secret Key

Derives a Secret Key from a Pass Phrase

Transforms a Secret Key using IPsec

Removes Secret Key from the KCR

Exports an IRE-format Secret Key

SAVE KEY

LOAD KEY

DERIVE KEY

TRANSFORM KEY

DESTROY KEY

EXPORT KEY

IMPORT KEY

Imports an IRE-format Secret Key

Symmetrical Encryption

ENCRYPT

Encrypts Data

DECRYPT

Decrypts Data

LOAD KG

Loads Secret Key into HW/SW Key Generator

Hash

HASH INIT

Initializes the Hash Operator

Hash Customer Data

Hash and Encrypt Customer Data

HASH DATA

HASH ENCRYPT

HASH DECRYPT

Hash and Decrypt Customer Data

PRF Functions

MERGE KEY

Combines two secret keys into one key

MERGE LONG KEY

EXTRACT LONG KEY

PRF DATA

Combines two secret keys into a data string (long key)

Creates a secret key from a data string (long key)

Hash multiple data items using HMAC

PRF KEY

Completes the above HMAC and create secret key

Asymmetrical Key Management

GEN PUBKEY

GEN NEWPUBKEY

GEN NEGKEY

Generates a Public Keyset (Public and Private Parts)

Generates a part of a Public Keyset

Generates a Diffie-Hellman Derived Secret Key

EXPORT PUBKEY

IMPORT PUBKEY

Exports an IRE-format Public Key

Imports an IRE-format Public Key

Asymmetrical Encryption

PUBKEY ENCRYPT

PUBKEY DECRYPT

Encrypts Data using RSA Public Key

Decrypts Data using RSA Public Key

Digital Signatures

SIGN

VERIFY

Digitally Signs a Message

Verifies a Digital Signature

Math Utilities

ADD VECTOR

SUB VECTOR

MULT VECTOR

EXP VECTOR

SHIFT VECTOR

Performs a Vector Add Operation

Performs a Vector Subtract Operation

Performs a Vector Multiply Operation

Performs a Vector Exponentiate Operation

Performs a Vector Right or Left Shift Operation

Extended Mode

LOAD EXTENDED

EXECUTE EXTENDED

Loads/Enables Extended (Downloaded) Algorithm Block

Executes Extended (Downloaded) Algorithm Block

REV. 0

–15–

ADSP-2141L

ABSOLUTE MAXIMUM RATINGS

Frequency Dependency For Timing Specifications

t_CKis defined as 0.5t_CKI. The ADSP-2141L uses an input clock

with a frequency equal to half the instruction rate: a 20.0 MHz

input clock (which is equivalent to 50 ns) yields a 25 ns processor

cycle (equivalent to 40 MHz). t_CKvalues within the range of 0.5t_CKI

period should be substituted for all relevant timing parameters to

obtain the specification value.

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Operating Temperature Range (Ambient) . . . . . 0°C to 70°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) MQFP . . . . . . . . . . . . . . . . . 280°C

Example: t_CKH= 0.5t_CK– 7 ns = 0.5 (25 ns) – 7 ns = 8 ns

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADSP-2141L features proprietary ESD protection circuitry, permanent damage

may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–16–

ADSP-2141L

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

Parameter

Min

Max

Unit

V_DD

T_AMB

Supply Voltage

Ambient Operating Temperature

3.0

0

3.6

70

V

°C

ELECTRICAL CHARACTERISTICS

DC SPECIFICATIONS

K Grade

Typ

Parameter

Test Conditions

Min

Max

Unit

V_IH

V_IL

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN/Reset Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= max

@ V_DD= min

2.0

2.4

V

0.4

V_OH

I

_OH= –0.5 mA

2.4

V

@ V_DD= min

I_OH= –100 µA⁶

@ V_DD= min

V_DD– 0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

I

_OL= 2 mA

@ V_DD= max

_IN= V_DDmax

0.4

10

8

V

µA

I_IL

Lo-Level Input Current³

3 @ V_DD= max

V_IN= 0 V

I_OZH

I_OZL

I_DD

Three-State Leakage Current⁷

Three-State Leakage Current⁹

Supply Current (Idle)^{10, 11}

@ V_DD= max

V

_IN= V_DDmax⁸

@ V_DD= max

V

_IN= 0 V⁹

@ V_DD= 3.3

T_AMB= 25°C

t

_CK= 25 ns¹²

_CK= 30 ns¹²

16

15

mA

I_DD

Supply Current (Dynamic)^{11, 13}

@ V_DD= 3.3

_AMB= 25°C

T

t

_CK= 25 ns¹²

195

165

mA

t_CK= 30 ns¹²

C_I

Input Pin Capacitance^{3, 6, 14}

@ V_IN= 2.5 V

f

_IN= 1.0 MHz

T_AMB= 25°C

@ V_IN= 2.5 V

f

8

pF

C_O

Output Pin Capacitance^{6, 7, 14, 15}

_IN= 1.0 MHz

T_AMB= 25°C

NOTES

¹Bidirectional pins: D0–D31, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0–15, PF0–PF7.

²Input only pins: IRQ2, BR, MMAP, BMODE, BUS MODE, BUS SEL, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.

³Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, BMODE, BUS MODE, BUS SEL, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.

⁴Output pins: BG, BGH, PMS, DMSL, DMSH, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0–A25, DT0, DT1, CLKOUT, FL2–0.

⁵Although specified for TTL outputs, all ADSP-2141L outputs are CMOS-compatible and will drive to V_DDand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷Output pins: BG, BGH, PMS, DMSL, BMS, IOMS, DMSH, CMS, RD, WR, IACK, PWDACK, A0–A25, DT0, DT1, CLKOUT, FL2–0, EE_DI, EE_CS, EE_SK.

⁸0 V on BR. CLKIN active (to force three-state condition).

⁹Three-statable pins: A0–A25, D0–D31, PMS, DMSL, DMSH, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCKL0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0–

IAD15, PF0–PF7.

¹⁰Idle refers to ADSP-2141L state of operation during execution of IDLE Instruction. Deasserted pins are driven to either V_DDor GND.

¹¹Current reflects device operating with no output loads.

12

V

= 0.4 V and 2.4 V. For typical supply currents, refer to Power Dissipation section.

measurement taken with 93% of instructions executing from internal memory and 7% from external memory. H/E operations are executing from internal

IN

13

I

DD

memory concurrently with PCI transactions. Initialization operations are executed from external memory.

¹⁴Applies to MQFP package type.

¹⁵Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

REV. 0

–17–

ADSP-2141L

DC SPECIFICATIONS– PCI Bus Pins

K Grade

Parameter

Test Conditions

Min

Max

Unit

V_IH

V_IL

V_OH

V_OL

I_IH

Hi-Level Input Voltage^{1, 2}

Lo-Level Input Voltage^{1, 2}

Hi-Level Output Voltage^{1, 3}

Lo-Level Output Voltage^{1, 3}

Hi-Level Input Current²

Lo-Level Input Current²

Three-State Leakage Current⁴

Three-State Leakage Current¹

Input Pin Capacitance

0.5 V_DD

–0.5

0.9 V_DD

V_DD+ 0.5

0.3 V_DD

V

µA

pF

nH

I_OUT= –500 µA

I_OUT= 1500 µA

0 < V_IN< V_DD

T_AMB= 25°C

0.1 V_DD

10

12

8

20

I_IL

I_OZH

I_OZL

C_I

C_CLK

C_IDSEL

L_PIN

PCI CLK Pin Capacitance

PCI IDSEL Pin Capacitance⁵

Pin Inductance

5

NOTES

¹Bidirectional pins: MPLX_BUS [31:0}, MPLX1–4, MPLX7–10, MPLX12

²Input only pins: MPLX_RESET, MPLX5, MPLX6, PCI_CLK, PCI_PAR, PCI_IRDY, PCI_STOP

³Output only pins: MPLX11

⁴Leakage currents include High-Z output leakage for bidirectional buffers with three-state outputs.

⁵Lower capacitance of IDSEL (MPLX_5) input-only pin allows for nonresistive connection to Address/Data bus.

TIMING PARAMETERS

PCI Clock (Guaranteed Over Operating Temperature and Digital Supply Range)

The ADSP-2141L is targeted for use in PCI add-on I/O slave card designs. It provides a glueless interface to the PCI bus. All bus

drivers are compliant with PCI interface electrical switching and drive capability specifications.

The ADSP-2141L does not implement the following signals: LOCK, INTB, INTC, INTD, SBO, SDONE, CLKRUN, AD[64:32],

C/BE[7:4], REQ64, ACK64, PAR64.

Parameter

Min

Max

Unit

Timing Requirements:

t_CYC

CLK Cycle Time

25

11

1

100

ns

V/ns

mV/ns

t_HIGH

t_LOW

CLK High Time

CLK Low Time

CLK Slew Rate¹

RST Slew Rate²

4

50

NOTES

¹Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the waveform as

shown in Figure 8.

²The minimum RST slew rate applies only to the rising (deassertion) edge of the reset signal, and ensures that system noise cannot render an otherwise monotonic

signal to appear to bounce in the switching range.

t_CYC

t_HIGH

0.6V

CC

t_LOW

0.5V

CC

2V p-p

MINIMUM)

0.4V

CC

(

0.3V

CC

0.2V

CC

Figure 8. Clock Waveform

REV. 0

–18–

ADSP-2141L

Parameter

Min

Max

Unit

PCI Bus Interface

Timing Requirements:

t_VAL

t_ON

t_OFF

t_SU

CLK to Signal Valid

2

11

28

ns

CLK to Low-Z Delay

CLK to High-Z Delay

Input Setup to CLK

7

1

t_H

t_RST-OFF

Input Hold After CLK

RST Active to Outputs High-Z

40

CLK

V

TEST

t_VAL

OUTPUT

DELAY

V

(3.3V SIGNALING)

STEP

OUTPUT CURRENT Յ LEAKAGE CURRENT

THREE-STATE

OUTPUT

t_ON

t_OFF

V

TH

CLK

V

TL

t_SU

t_H

V

TH

INPUTS

VALID

V

INPUT

MAX

V

V_TEST

TEST

V

TL

Figure 9. Output (Top) and Input Timing Measurement Conditions

REV. 0

–19–

ADSP-2141L

Parameter

Min

Max

Unit

Clock Signals and Reset

Timing Requirements:

t_CKI

CLKIN Period

50

15

100

ns

t_CKIL

t_CKIH

CLKIN Width Low

CLKIN Width High

Switching Characteristics:

t_CKL

CLKOUT Width Low

0.5t_CK– 7

0

ns

t_CKH

t_CKOH

CLKOUT Width High

CLKIN High to CLKOUT High

20

Control Signals

Timing Requirement:

t_RSP

RESET Width Low¹

5t_CK

ns

NOTE

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

Figure 10. Clock Signals and Reset

REV. 0

–20–

ADSP-2141L

Parameter

Min

Max

Unit

Interrupts and Flags

Timing Requirements:

t_IFS

t_IFH

IRQx, FI, or PFx Setup Before CLKOUT Low^{1, 2, 3, 4}

IRQx, FI, or PFx Hold After CLKOUT High^{1, 2, 3, 4}

0.25t_CK+ 15

0.25t_CK

ns

Switching Characteristics:

t_FOH

Flag Output Hold After CLKOUT Low⁵

t_FOD

Flag Output Delay from CLKOUT Low⁵

0.5t_CK– 7

ns

0.5t_CK+ 5

NOTES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to the Interrupt Controller Operation section in the Program Control chapter of the ADSP-2100 Family User’s Manual for further informa-

tion on interrupt servicing.)

²Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

⁴PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

⁵Flag Outputs = PFx, FL0, FL1, FL2, Flag_out.

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

PFx

t_IFS

Figure 11. Interrupts and Flags

REV. 0

–21–

ADSP-2141L

Parameter

Min

Max

Unit

Bus Request/Bus Grant

Timing Requirements:

t_BH

t_BS

BR Hold After CLKOUT High¹

BR Setup Before CLKOUT Low¹

0.25t_CK+ 2

0.25t_CK+ 17

ns

Switching Characteristics:

t_SD

CLKOUT High to xMS, RD, WR Disable

0.25t_CK+ 10 ns

t_SDB

t_SE

t_SEC

t_SDBH

t_SEH

xMS, RD, WR Disable to BG Low

BG High to xMS, RD, WR Enable

xMS, RD, WR Enable to CLKOUT High

xMS, RD, WR Disable to BGH Low²

BGH High to xMS, RD, WR Enable²

0

ns

0.25t_CK– 6

0

NOTES

xMS = PMS, DMSL, DMSH, CMS, IOMS, BMS.

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise, the signal will be recognized

on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

²BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMSL,

BMS, RD, WR

t_SD

t_SEC

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 12. Bus Request/Bus Grant

REV. 0

–22–

ADSP-2141L

Parameter

Min

Max

Unit

External Memory Write: ADSP-2141L DMA Initiated

Switching Characteristics:

t_A

Clock to Address and DMSx

5

9

ns

t_DW

t_DH

t_WP

Data Setup Before Write Deasserted

Data Hold After Write Deasserted

Write Pulsewidth

0.5t_CK– 2 + w

0.5t_CK– 8

0.5t_CK– 5 + w

–5

1

0

6

0.5t_CK– 2 + w

2

0.5t_CK– 7

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

t_AH

t_WRA

Write Low to Data Enabled

Address, DMSx Setup Before Write Low

Data Disable Before Write/Read Low

Clock High to Write Low

Address, DMSx Setup Before Write High

Address and DMSx Hold After Clock

Address, DMSx Hold After Write High

Write High to Read/Write Low

12

t_WWR

0.5t_CK– 3

1. If wait-state(s) added, then referenced to last wait-state clock interval.

2. w = DMA wait states × t_CK

.

25ns (REF @ 40MHz)

DSP CLOCK

OUT

t_ASW

t_AH

EXT. ADDR

(A25–0)

t_A

t_AW

t_WRA

EXT. DMSH

EXT. DMSL

t_CWR

t_WP

t_WWR

EXT. WR

t_WDE

t_DW

t_DH

t_DDR

EXT. DATA

(D31–0)

Figure 13. External Memory Write: ADSP-2141L DMA Initiated

REV. 0

–23–

ADSP-2141L

Parameter

Min

Max

Unit

External Memory Read—ADSP-2141L DMA Initiated

Timing Requirements:

t_RDD

t_AA

t_SUR

t_RDH

Read Low to Data Valid

0.5t_CK– 8 + w

0.5t_CK– 3 + w

ns

Address, DMSx Valid to Data Valid

Data Valid Before Read Deasserted

Data Hold After Read Deasserted

4

1

Switching Characteristics:

t_A

t_ASR

t_AH

t_RDA

t_CRD

t_RP

Clock to Address and DMSx Active

5

2

9

ns

Address, DMSx Setup Before Read Low

Address and DMSx Hold After Clock

Address, DMSx Hold After Read High

Clock High to RD Low

0.5t_CK– 7

8

0.5t_CK– 5 + w

0.5t_CK– 3

12

Read Pulsewidth

t_RWR

RD High to Read or Write Low

1. If wait-state(s) added, then referenced to last wait-state clock interval.

2. w = DMA wait states × t_CK

.

25ns (REF @ 40MHz)

DSP CLOCK

OUT

t_A

t_AH

EXT. ADDR

(A25–0)

t_AA

t_RDA

t_ASR

EXT. DMSH

EXT. DMSL

t_RWR

t_RP

t_CRD

EXT. RD

t_RDD

t_SUR

t_RDH

EXT. DATA

(D31–0)

Figure 14. External Memory Read – ADSP-2141L DMA Initiated

REV. 0

–24–

ADSP-2141L

Parameter

Min

Max

Unit

External Memory Write: ADSP-2141L DSP Initiated

Switching Characteristics:

t_A

Clock to Address, xMS

1

6

ns

t_DW

t_DH

t_WP

Data Setup Before Write Deasserted

Data Hold After Write Deasserted

Write Pulsewidth

0.5t_CK– 7 + w

0.25t_CK– 3.5

0.5t_CK– 5 + w

0

0.25t_CK– 4

0.25t_CK

0.75t_CK– 6 + w

1

0.25t_CK– 4

0.5t_CK– 5

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

t_AH

t_WRA

t_WWR

Write Low to Data Enabled

Address, xMS Setup Before Write Low

Data Disable Before Write/Read Low

Clock High to Write Low

Address, xMS Setup Before Write High

Address, xMS Hold After Clock

Address, xMS Hold After Write High

Write High to Read/Write Low

0.5t_CK+ 9

1. If wait-state(s) added, then referenced to last wait-state clock interval.

2. w = DSP wait states × t_{CK .}

25ns (REF @ 40MHz)

DSP CLOCK

OUT

t_ASW

t_AH

EXT. ADDR

(A13–0)

t_A

t_AW

t_WRA

PMS, DMSx,

BMS, IOMS,

CMS

t_WP

t_WWR

t_CWR

EXT. WR

t_WDE

t_DW

t_DH

t_DDR

EXT. DATA

(D23–0)

Figure 15. External Memory Write: ADSP-2141L DSP Initiated

REV. 0

–25–

ADSP-2141L

Parameter

Min

Max

Unit

External Memory Read—ADSP-2141L DSP Initiated

Timing Requirements:

t_RDD

t_AA

t_SUR

t_RDH

Read Low to Data Valid

0.5t_CK– 10 + w

0.75t_CK– 11.5 + w ns

ns

Address, xMS Valid to Data Valid

Data Valid Before Read Deasserted

Data Hold After Read Deasserted

9

0

ns

Switching Characteristics:

t_A

t_ASR

t_AH

t_RDA

t_CRD

t_RP

Clock to Address, xMS Active

1

6

ns

Address, xMS Setup Before Read Low

Address, xMS Hold After Clock

Address, xMS Hold After Read High

Clock High to RD Low

0.25t_CK– 4

1

0.25t_CK– 3

0.25t_CK– 2

0.5t_CK– 5 + w

0.5t_CK–5

0.25t_CK+ 7

Read Pulsewidth

t_RWR

RD High to RD or WR Low

1. If wait-state(s) added, then referenced to last wait-state clock interval.

2. w = DSP wait state × t_CK

.

25ns (REF @ 40MHz)

DSP CLOCK

OUT

t_A

t_AH

EXT. ADDR

(A13–0)

t_AA

t_RDA

t_ASR

PMS, DMSx,

BMS, IOMS,

CMS

t_RWR

t_CRD

t_RP

EXT. RD

t_RDD

t_SUR

t_RDH

EXT. DATA

(D23–0)

Figure 16. External Memory Read – ADSP-2141L DSP Initiated

REV. 0

–26–

ADSP-2141L

Parameter

Min

Max

Unit

Serial Ports

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

50

4

7

ns

DR/TFS/RFS Setup Before SCLK Low

DR/TFS/RFS Hold After SCLK Low

SCLK_INWidth

15

Switching Characteristics:

t_CC

CLKOUT High to SCLKOUT

0.25t_CK

0

0.25t_CK+ 10

ns

t_SCDE

t_SCDV

t_RH

SCLK High to DT Enable

SCLK High to DT Valid

TFS/RFS_OUTHold After SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold After SCLK High

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

15

0

t_RD

t_SCDH

t_TDE

t_TDV

t_SCDD

t_RDV

0

14

15

CLKOUT

t_CC

t_SCK

SCLK

t_SCS

t_SCH

t_SCP

DR

TFS

IN

RFS

IN

t_RD

t_RH

RFS

OUT

TFS

t_SCDV

t_SCDE

t_SCDD

t_SCDH

DT

t_TDE

t_TDV

TFS

OUT

ALTERNATE

FRAME MODE

t_RDV

RFS

OUT

MULTICHANNEL MODE

FRAME DELAY 0

(MFD = 0)

t_TDE

t_TDV

TFS

IN

ALTERNATE

FRAME MODE

t_RDV

RFS

IN

MULTICHANNEL MODE

FRAME DELAY 0

(MFD = 0)

Figure 17. Serial Ports

REV. 0

–27–

ADSP-2141L

Parameter

Min

Max

Unit

IDMA Address Latch (IDMA Mode Multiplex Bus)

Timing Requirements:

t_IALP

t_IASU

t_IAH

Duration of Address Latch^{1, 2}

10

5

3

0

4

ns

MPLX_BUS Address Setup Before Address Latch End²

MPLX_BUS Address Hold After Address Latch End²

MPLX9 Low Before Start of Address Latch^{2, 3}

Start of Write or Read After Address Latch End^{2, 3}

t_IKA

t_IALS

NOTES

¹Start of Address Latch = MPLX7 Low and MPLX8 High.

²Start of Write or Read = MPLX7 Low and MPLX6 Low or MPLX5 Low.

³End of Address Latch = MPLX7 High or MPLX8 Low.

MPLX9 IACK

/

t_IKA

MPLX8 IAL

/

t_IALP

MPLX7 IS

/

t_IASU

t_IAH

MPLX_BUS IAD15–0

/

t_IALS

MPLX5 OR MPLX6 IRD OR IWR

/

Figure 18. IDMA Address Latch (IDMA Mode Multiplex Bus)

REV. 0

–28–

ADSP-2141L

Parameter

Min

Max

Unit

IDMA Write, Short Write Cycle (IDMA Mode, Multiplex Bus)

Timing Requirements:

t_IKW

t_IWP

t_IDSU

t_IDH

MPLX9 Low Before Start of Write¹

Duration of Write^{1, 2}

0

15

5

ns

MPLX_BUS Data Setup Before End of Write^{2, 3, 4}

MPLX_BUS Hold After End of Write^{2, 3, 4}

3

Switching Characteristic:

t_IKHW

Start of Write to MPLX9 High

15

ns

NOTES

¹Start of Write = MPLX7 Low and MPLX6 Low.

²End of Write = MPLX7 High or MPLX6 High.

³If Write Pulse ends before MPLX9 Low, use specifications t_IDSU, t_IDH

⁴If Write Pulse ends after MPLX9 Low, use specifications t_IKSU, t_IKH.

.

t_IKW

MPLX9 IACK

/

t_IKHW

MPLX7 IS

/

t_IWP

MPLX6 IWR

/

t_IDH

t_IDSU

DATA

MPLX_BUS IAD15–0

/

Figure 19. IDMA Write, Short Write Cycle (IDMA Mode, Multiplex Bus)

REV. 0

–29–

ADSP-2141L

Parameter

Min

Max

Unit

IDMA Write, Long Write Cycle (IDMA Mode, Multiplex Bus)

Timing Requirements:

t_IKW

t_IKSU

t_IKH

MPLX9 Low Before Start of Write¹

0

ns

MPLX_BUS Data Setup Before MPLX9 Low^{2, 3, 4}

MPLX_BUS Data Hold After MPLX9 Low^{2, 3, 4}

0.5t_CK+ 10

2

Switching Characteristics:

t_IKLW

Start of Write to MPLX9 Low⁴

t_IKHWStart of Write to MPLX9 High

1.5t_CK

ns

15

NOTES

¹Start of Write = MPLX7 Low and MPLX6 Low.

²If Write Pulse ends before MPLX9 Low, use specifications t_IDSU, t_IDH.

³If Write Pulse ends after MPLX9 Low, use specifications t_IKSU, t_IKH.

⁴This is the earliest time for MPLX9 Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.

t_IKW

MPLX9 IACK

/

t_IKHW

t_IKLW

MPLX7 IS

/

MPLX6 IWR

/

t_IKH

t_IKSU

MPLX_BUS IAD15–0

DATA

/

Figure 20. IDMA Write, Long Write Cycle (IDMA Mode, Multiplex Bus)

REV. 0

–30–

ADSP-2141L

Parameter

Min

Max

Unit

IDMA Read, Long Read Cycle (IDMA Mode, Multiplex Bus)

Timing Requirements:

t_IKR

t_IRP

MPLX9 Low Before Start of Read¹

Duration of Read¹

0

15

ns

Switching Characteristics:

t_IKHR

t_IKDS

t_IKDH

t_IKDD

t_IRDE

t_IRDV

t_IRDH1

t_IRDH2

MPLX9 High After Start of Read¹

15

ns

MPLX_BUS Data Setup Before MPLX9 Low

0.5t_CK– 7

0

MPLX_BUS Data Hold After End of Read²

MPLX_BUS Data Disabled After End of Read²

14

15

MPLX_BUS Previous Data Enabled After Start of Read

MPLX_BUS Previous Data Valid After Start of Read

MPLX_BUS Previous Data Hold After Start of Read (DM/PM1)³

MPLX_BUS Previous Data Hold After Start of Read (PM2)⁴

0

2t_CK– 5

t_CK– 5

NOTES

¹Start of Read = MPLX7 Low and MPLX5 Low.

²End of Read = MPLX7 High or MPLX5 High.

³DM read or first half of PM read.

⁴Second half of PM read.

MPLX9 IACK

/

t_IKHR

t_IKR

MPLX7 IS

/

t_IRP

MPLX6 IRD

/

t_IRDE

t_IKDH

t_IKDS

MPLX_BUS IAD15–0

READ DATA

/

t_IRDV

t_IKDD

t_IRDH

Figure 21. IDMA Read, Long Read Cycle (IDMA Mode, Multiplex Bus)

REV. 0

–31–

ADSP-2141L

Parameter

Min

Max

Unit

IDMA Read, Short Read Cycle (IDMA Mode, Multiplex Bus)

Timing Requirements:

t_IKR

t_IRP

MPLX9 Low Before Start of Read¹

Duration of Read

0

15

ns

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

MPLX9 High After Start of Read¹

15

14

15

ns

MPLX_BUS Data Hold After End of Read²

0

MPLX_BUS Data Disabled After End of Read²

MPLX_BUS Previous Data Enabled After Start of Read

MPLX_BUS Previous Data Valid After Start of Read

NOTES

¹Start of Read = MPLX7 Low and MPLX5 Low.

²End of Read = MPLX7 High or MPLX5 High.

MPLX9/IACK

t_IKR

t_IKHR

MPLX7/IS

t_IRP

MPLX6/IRD

t_IRDE

t_IKDH

MPLX_BUS/IAD15–0

t_IRDV

t_IKDD

Figure 22. IDMA Read, Short Read Cycle (IDMA Mode, Multiplex Bus)

REV. 0

–32–

ADSP-2141L

CAPACITIVE LOADING

Figures 23 and 24 show the capacitive loading characteristics of

the ADSP-2141L.

is calculated. If multiple pins (such as the data bus) are disabled,

the measurement value is that of the last pin to stop driving.

INPUT

18

1.5V

OR

T = +70؇C

OUTPUT

16

14

12

V

= 3.0V

DD

Figure 25. Voltage Reference Levels for AC Measure-

ments (Except Output Enable/Disable)

Output Enable Time

10

8

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to when they start

driving. The output enable time (t_ENA) is the interval from when

a reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram. If multiple pins (such as

the data bus) are enabled, the measurement value is that of the

first pin to start driving.

6

4

2

0

50

100

150

– pF

200

250

300

C

L

REFERENCE

SIGNAL

Figure 23. Typical Output Rise Time vs. Load Capacitance,

C_L(at Maximum Ambient Operating Temperature)

t_MEASURED

t_DIS

t_ENA

18

16

14

12

10

8

V

OH

(MEASURED)

OH

(MEASURED)

V

(MEASURED) – 0.5V

(MEASURED) +0.5V

2.0V

1.0V

OH

OUTPUT

OL

V

OL

t_DECAY

(MEASURED)

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

6

4

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

2

NOMINAL

–2

Figure 26. Output Enable/Disable

–4

I

OL

0

50

100

150

200

250

C

– pF

L

Figure 24. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maximum Ambient Operating

Temperature)

TO

OUTPUT

+1.5V

50pF

TEST CONDITIONS

Output Disable Time

I

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured

output high or low voltage to a high impedance state. The out-

put disable time (t_DIS) is the difference of t_MEASUREDand t_DECAY

OH

Figure 27. Equivalent Device Loading for AC Measure-

ments (Including All Fixtures)

,

as shown in the Output Enable/Disable diagram. The time is the

interval from when a reference signal reaches a high or low

voltage level to when the output voltages have changed by 0.5 V

from the measured output high or low voltage. The decay time,

t_DECAY, is dependent on the capacitive load, C_L, and the current

load, i_L, on the output pin. It can be approximated by the fol-

lowing equation:

C_L• 0.5V

t_DECAY

=

i_L

from which

t_DIS= t_MEASURED– t_DECAY

REV. 0

–33–

ADSP-2141L

Table IV. Thermal Ratings: MQFP Package

Rating Description

Symbol

Value (MQFP Still Air)

Value (MQFP 9500 fpm)

Thermal Resistance (Case to Ambient)

Thermal Resistance (Junction to Ambient)

Thermal Resistance (Junction to Case)

θ_CA

θ_JA

θ_JC

30.7°C/W

35°C/W

4.3°C/W

16.7°C/W

21°C/W

4.3°C/W

ENVIRONMENTAL CONDITIONS

POWER DISSIPATION

The following figures assume a four-layer JEDEC printed circuit

board:

Total power dissipation has two components: one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation depends on the sequence in

which instructions execute and the data operands involved. See

I_DDINcalculation in Electrical Characteristics section. Internal

power dissipation is calculated this way:

T

_AMB= T_CASE– (PD × θ_CA

_CASE= Case Temperature in °C

)

OUTPUT DRIVE CURRENTS

Figures 28 and 29 show typical I-V characteristics for the

output drivers of the ADSP-2141L. The curves represent the

current drive capability of the output drivers as a function of

output voltage.

P

_INT= I_DDIN× V_DD

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

– the number of output pins that switch during each cycle (O)

– the maximum frequency at which the pins can switch (f)

– the load capacitance of the pins (C)

100

V

= 3.3V @ +25؇C

DD

80

60

– the voltage swing of the pins (V_DD).

V

= 3.6V @ 0؇C

DD

The external component is calculated using:

40

2

P

_EXT= O × C × V_DD× f

20

V

= 3.0V @ +70؇C

DD

The load capacitance should include the processor’s package

capacitance (C_IN). The frequency f includes driving the load

high and then back low.

0

V

= 3.0V @ +70؇C

DD

–20

–40

–60

V

= 3.3V @ +25؇C

DD

V

= 3.6V @ 0؇C

DD

–80

–100

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE – V

Figure 28. Typical Drive Currents (PCI Pins)

80

V

= 3.3V @ +25؇C

DD

60

40

V

OH

V

= 3.6V @ 0؇C

DD

20

V

= 3.0V @ +70؇C

DD

0

V

= 3.0V @ +70؇C

DD

–20

–40

–60

–80

V

= 3.3V @ +25؇C

DD

V

OL

V

= 3.6V @ 0؇C

DD

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE – V

Figure 29. Typical Drive Currents (Addr/Dbus/rd/wr Pins)

REV. 0

–34–

ADSP-2141L

POWER, INTERNAL

Example:

940

840

740

640

540

440

340

In an application where external data memory is used and no

other outputs are active, power dissipation is calculated as

follows:

823mW

V

= 3.6V

DD

Assumptions:

•

External data memory is accessed every cycle with 50% of the

address pins switching.

706mW

554mW

649mW

509mW

V

= 3.3V

= 3.0V

DD

External data memory writes occur every other cycle with

50% of the data pins switching.

V

DD

•

Each address and data pin has a 10 pF total load at the pin.

The application operates at V_DD= 3.3 V and t_CK= 25 ns.

431mW

33

2

Total Power Dissipation = P_INT+ (C × V_DD× f )

32

34

35

36

37

38

39

40

41

42

P_INT= internal power dissipation from Power vs. Frequency

FREQUENCY – MHz

graphs (Figures 30 and 31).

Figure 30. Power vs. Frequency

2

(C × V_DD× f ) is calculated for each output:

POWER, IDLE

80

75

70

65

60

55

50

45

40

# of

Pins × C

2

× V_DD

× f

74mW

V

= 3.6V

DD

Address, DMS

Data Output, WR

RD

8

9

1

× 10 pF × 3.3²V × 40 MHz

× 10 pF × 3.3²V × 20 MHz

× 10 pF × 3.3²V × 40 MHz

× 10 pF × 3.3²V × 20 MHz

=

34.8 mW

19.6 mW

2.2 mW

4.4 mW

61.0 mW

68mW

CLKOUT

Total power dissipation for this example is P_INT+61 mW.

V

= 3.3V

53mW

DD

51mW

V

= 3.0V

36

DD

43mW

41

41mW

33

32

34

35

37

38

39

40

42

FREQUENCY – MHz

Figure 31. Power vs. Frequency

REV. 0

–35–

ADSP-2141L

Pin Configurations

For all multiplexed pins the active sense is determined by the mode selected.

Pin # Pin Name

1

2

3

4

5

6

7

8

EMS

EE

GND

ECLK

ELOUT

ELIN

EINT

EBR

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

PCI_CLK

GND

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

VDD

GND

MPLX6

MPLX5

MPLX_BUS[15]

MPLX_BUS[14]

MPLX_BUS[13]

MPLX_BUS[12]

VDD

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

166

167

168

GND

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

GND

ADDR[0]

ADDR[1]

ADDR[2]

ADDR[3]

VDD

ADDR[4]

ADDR[5]

ADDR[6]

ADDR[7]

ADDR[8]

ADDR[9]

ADDR[10]

ADDR[11]

ADDR[12]

ADDR[13]

GND

ADDR[14]

ADDR[15]

ADDR[16]

ADDR[17]

ADDR[18]

ADDR[19]

VDD

ADDR[20]

ADDR[21]

ADDR[22]

ADDR[23]

ADDR[24]

ADDR[25]

DT0

DATA[0]

DATA[1]

DATA[2]

DATA[3]

VDD

MPLX_BUS[30]

MPLX_BUS[29]

MPLX_BUS[28]

MPLX_BUS[27]

VDD

GND

DATA[4]

DATA[5]

DATA[6]

DATA[7]

DATA[8]

DATA[9]

DATA[10]

DATA[11]

DATA[12]

DATA[13]

DATA[14]

DATA[15]

VDD

9

EBG

MPLX_BUS[26]

MPLX_BUS[25]

MPLX_BUS[24]

MPLX1

MPLX_BUS[23]

MPLX_BUS[22]

VDD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

MMAP

BMODE

BUS_MODE

BUS_SEL

EE_SK

EE_CS

EE_DI

EE_DO

VDD

GND

PF[7]/INT_H

PF[6]

PF[5]

PF[4]

PF[3]

PF[2]

PF[1]

PF[0]

PWD

PWDACK

BR

BG

BGH

GND

MPLX_BUS[11]

MPLX_BUS[10]

MPLX_BUS[9]

MPLX_BUS[8]

VDD

GND

MPLX4

MPLX_BUS[21]

MPLX_BUS[20]

MPLX_BUS[19]

MPLX_BUS[18]

GND

VDD

GND

MPLX_BUS[17]

MPLX_BUS[16]

MPLX2

PCI_IRDY

VDD

GND

PCI_STOP

MPLX10

MPLX11

PCI_PAR

VDD

GND

MPLX3

MPLX7

MPLX9

MPLX8

GND

MPLX_BUS[7]

MPLX_BUS[6]

MPLX_BUS[5]

MPLX_BUS[4]

VDD

GND

DATA[16]

DATA[17]

DATA[18]

DATA[19]

DATA[20]

DATA[21]

VDD

GND

MPLX_BUS[3]

MPLX_BUS[2]

MPLX_BUS[1]

MPLX_BUS[0]

GND

CLKOUT

VDD

GND

WR

RD

DMSH

DMSL

PMS

BMS

CMS

IOMS

VDD

CLKIN

XTAL

GND

DATA[22]

DATA[23]

DATA[24]

DATA[25]

DATA[26]

DATA[27]

DATA[28]

DATA[29]

DATA[30]

DATA[31]

ERESET

TFS0

RFS0

DR0

SCLK0

DT1

TFS1

RFS1

DR1

IRQE

IRQL0

IRQL1

IRQ2

VDD

GND

MPLX_RESET

MPLX12

MPLX_BUS[31] 83

VDD 84

SCLK1

GND

VDD

REV. 0

–36–

ADSP-2141L

PINOUT

PCI Mode

1

2

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

ADDR[25]

ADDR[24]

ADDR[23]

ADDR[22]

ADDR[21]

ADDR[20]

VDD

ADDR[19]

ADDR[18]

ADDR[17]

ADDR[16]

ADDR[15]

ADDR[14]

GND

ADDR[13]

ADDR[12]

ADDR[11]

ADDR[10]

ADDR[9]

ADDR[8]

ADDR[7]

ADDR[6]

ADDR[5]

ADDR[4]

VDD

ADDR[3]

ADDR[2]

ADDR[1]

ADDR[0]

GND

XTAL

CLKIN

VDD

IOMS

CMS

BMS

PMS

DMSL

DMSH

RD

WR

GND

VDD

CLKOUT

GND

MPLX_BUS/Pci_ad[0]

MPLX_BUS/Pci_ad[1]

MPLX_BUS/Pci_ad[2]

MPLX_BUS/Pci_ad[3]

GND

EMS

EE

GND

ECLK

ELOUT

ELIN

PIN 1

IDENTIFIER

3

4

5

6

7

EINT

EBR

EBG

8

9

10

11

MMAP

BMODE

BUS_MODE

BUS_SEL

EE_SK

EE_CS

EE_DI

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

EE_DO

VDD

GND

PF[7]/INT_H

PF[6]

PF[5]

PF[4]

PF[3]

PF[2]

PF[1]

PF[0]

ADSPO-2O141L

TOP VIEW

(Not to Scale)

PWD

PWDACK

BR

BG

BGH

IRQE

IRQL0

IRQL1

IRQ2

PCI MODE

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

VDD

GND

MPLX_RESET/Pci_rst

MPLX12/Pci_req

MPLX_BUS/Pci_ad[31]

VDD

PCI_CLK

GND

MPLX_BUS/Pci_ad[30]

MPLX_BUS/Pci_ad[29] 46

47

MPLX_BUS/Pci_ad[28]

MPLX_BUS/Pci_ad[27]

48

49

50

VDD

GND

MPLX_BUS/Pci_ad[26] 51

MPLX_BUS/Pci_ad[25] 52

VDD

MPLX_BUS/Pci_ad[4]

REV. 0

–37–

ADSP-2141L

PINOUT

2183-Mode

1

156 ADDR[25]

155 ADDR[24]

154 ADDR[23]

EMS

EE

GND

ECLK

ELOUT

ELIN

EINT

EBR

2

3

4

5

6

7

PIN 1

IDENTIFIER

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

ADDR[22]

ADDR[21]

ADDR[20]

VDD

ADDR[19]

ADDR[18]

ADDR[17]

ADDR[16]

ADDR[15]

ADDR[14]

GND

8

9

EBG

MMAP

10

11

12

13

14

15

16

BMODE

BUS_MODE

BUS_SEL

EE_SK

EE_CS

EE_DI

ADDR[13]

ADDR[12]

ADDR[11

17

18

19

20

21

22

23

24

EE_DO

VDD

GND

]

ADDR[10]

ADDR[9

]

PF[7]/INT_H

PF[6]

ADDR[8]

ADDR[7]

ADDR[6]

ADDR[5]

ADDR[4]

VDD

ADDR[3]

ADDR[2]

ADDR[1]

ADDR[0]

GND

PF[5]

PF[4]

PF[3]

PF[2] 25

PF[1] 26

OO

TOP VIEW

(Not to Scale)

ADSP-2141L

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

PF[0]

PWD

PWDACK

2183 MODE

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

BR

BG

BGH

IRQE

IRQL0

IRQL1

IRQ2

VDD

GND

XTAL

CLKIN

VDD

IOMS

CMS

BMS

PMS

DMSL

DMSH

RD

WR

GND

VDD

CLKOUT

GND

MPLX_BUS/IAD[0]

MPLX_BUS/IAD[1

MPLX_RESET/RESET_1

MPLX12/FL2

MPLX_BUS/NC[31]

VDD

PCI_CLK

GND

MPLX_BUS/NC[30]

MPLX_BUS/NC[29]

MPLX_BUS/NC[28]

]

MPLX_BUS/NC[27] 48

MPLX_BUS/IAD[2]

49

50

51

52

VDD

GND

MPLX_BUS/IAD[3]

GND

VDD

MPLX_BUS/NC[26]

MPLX_BUS/NC[25]

MPLX_BUS/IAD[4]

REV. 0

–38–

ADSP-2141L

PACKAGE DESCRIPTION

Package Details

The package shown below is a 208-lead metric quad flatpack. Measurements are listed in English and (metric). Because this package

is designed as a metric package, Analog Devices recommends that you use these measurements for any PCB layout.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

208-Lead Metric Plastic Quad Flatpack (MQFP)

(Nonhermetic)

1.256 (31.40)

0.164 (4.10)

1.248 (31.20) SQ

MAX

1.240 (31.00)

0.041 (1.03)

0.035 (0.88)

0.031 (0.78)

208

157

156

10

TYP

1

SEATING

PLANE

1.124 (28.10)

1.120 (28.00) SQ

1.116 (27.90)

TOP VIEW

(PINS DOWN)

0.003 (0.08)

MAX LEAD

COPLANARITY

105

104

52

53

0.020 (0.50)

0.010 (0.25)

0.011 (0.27)

0.009 (0.22)

0.007 (0.17)

LEAD WIDTH

0.020 (0.50)

BSC

0.144 (3.59)

0.136 (3.39)

LEAD PITCH

NOTE:

THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.003 (0.08) FROM ITS IDEAL

POSITION WHEN MEASURED IN THE LATERAL DIRECTION.

CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.

THE 208 LEAD MQFP IS A METRIC PACKAGE. ENGLISH DIMENSIONS PROVIDED

ARE APPROXIMATE AND MUST NOT BE USED FOR BOARD DESIGN PURPOSES

ORDERING GUIDE

Part Number

Ambient Temperature Range

Instruction Rate

Package Description

Package Option

ADSP-2141LKS-N1¹

0°C to +70°C

40 MHz

208-Lead MQFP

S-208

ADSP-2141LKS-E1²

NOTES

¹The ADSP-2141LKS-N1 is an electrically equivalent, full function, production (non x-grade) version of the product described in this data sheet. (Full function =

Triple DES enabled, full 168-bit key length, full 2048-bit public key lengths, red keys allowed.)

²The ADSP-2141LKS-E1 is an electrically equivalent, full function, production (non x-grade) version of the product described in this data sheet except for the following:

Encryption: DES only, with maximum 56-bit key length. Triple DES is disabled.

Public Key Algorithms: Public Key Algorithms limited to 1024-bit max modulus. Red keys not allowed in hardware crypto context.

REV. 0

–39–


型号：	ADSP-2141LKS-N1
厂家：	ADI
描述：	DSP DSP 电信集成电路电信加密电路电信电路
文件：	总39页 (文件大小：259K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-2141LKS-N1 [ADI]

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