ADSP-2184LBST-160_技术文档

a

DSP Microcomputer

ADSP-2184L

FUNCTIONAL BLOCK DIAGRAM

FEATURES

PERFORMANCE

25 ns Instruction Cycle Time 40 MIPS Sustained

Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

POWER-DOWN

CONTROL

FULL MEMORY

MODE

MEMORY

PROGRAMMABLE

DATA ADDRESS

GENERATORS

I/O

AND

FLAGS

EXTERNAL

ADDRESS

BUS

4K

؋

24

PROGRAM

MEMORY

4K

؋

16

DATA

MEMORY

PROGRAM

SEQUENCER

DAG 1 DAG 2

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

EXTERNAL

DATA

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

BYTE DMA

CONTROLLER

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 400 Cycle Recovery from

Power-Down Condition

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

Low Power Dissipation in Idle Mode

ARITHMETIC UNITS

SHIFTER

SERIAL PORTS

SPORT 0 SPORT 1

TIMER

INTERNAL

DMA

PORT

ALU MAC

INTEGRATION

ADSP-2100 BASE

ARCHITECTURE

ADSP-2100 Family Code Compatible, with Instruction

Set Extensions

HOST MODE

20K Bytes of On-Chip RAM, Configured as

4K Words On-Chip Program Memory RAM and

4K Words On-Chip Data Memory RAM

Dual Purpose Program Memory for Both Instruction

and Data Storage

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

Signaling

UART Emulation through Software SPORT Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging

in Final Systems

Independent ALU, Multiplier/Accumulator and Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides

Zero Overhead Looping Conditional Instruction

Execution

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP

GENERAL DESCRIPTION

The ADSP-2184L is a single-chip microcomputer optimized for

digital signal processing (DSP) and other high speed numeric

processing applications.

The ADSP-2184L combines the ADSP-2100 family base archi-

tecture (three computational units, data address generators and

a program sequencer) with two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities and on-chip program and data

memory.

SYSTEM INTERFACE

16-Bit Internal DMA Port for High Speed Access to

On-Chip Memory (Mode Selectable)

4 MByte Byte Memory Interface for Storage of Data

Tables and Program Overlays

The ADSP-2184L integrates 20K bytes of on-chip memory

configured as 4K words (24-bit) of program RAM and 4K

words (16-bit) of data RAM. Power-down circuitry is also pro-

vided to meet the low power needs of battery operated portable

equipment. The ADSP-2184L is available in a 100-lead LQFP

package.

8-Bit DMA to Byte Memory for Transparent Program

and Data Memory Transfers (Mode Selectable)

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals (Mode Selectable)

Programmable Memory Strobe and Separate I/O Memory

Space Permits “Glueless” System Design

(Mode Selectable)

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

In addition, the ADSP-2184L supports instructions that include

bit manipulations—bit set, bit clear, bit toggle, bit test—ALU

constants, multiplication instruction (x squared), biased round-

ing, result free ALU operations, I/O memory transfers and

global interrupt masking for increased flexibility.

ICE-Port is a trademark of Analog Devices, Inc.

All other trademarks are the property of their respective holders.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADSP-2184L

The EZ-ICE performs a full range of functions, including:

Fabricated in a high speed, double metal, low power, CMOS

process, the ADSP-2184L operates with a 25 ns instruction cycle

time. Every instruction can execute in a single processor cycle.

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

The ADSP-21xx family DSPs contain a shadow bank register

that is useful for single cycle context switching of the processor.

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

The ADSP-2184L’s flexible architecture and comprehensive

instruction set allow the processor to perform multiple opera-

tions in parallel. In one processor cycle the ADSP-2184L can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

See Designing An EZ-ICE-Compatible Target System in the

ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as

well as the Target Board Connector for EZ-ICE Probe section

of this data sheet, for the exact specifications of the EZ-ICE

target board connector.

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive or transmit data through the internal DMA port

• Receive or transmit data through the byte DMA port

• Decrement timer

Additional Information

This data sheet provides a general overview of ADSP-2184L

functionality. For additional information on the architecture and

instruction set of the processor, refer to the ADSP-2100 Family

User’s Manual, Third Edition. For more information about the

development tools, refer to the ADSP-2100 Family Development

Tools Data Sheet.

Development System

The ADSP-2100 Family Development Software, a complete set

of tools for software and hardware system development, sup-

ports the ADSP-2184L. The System Builder provides a high

level method for defining the architecture of systems under

development. The Assembler has an algebraic syntax that is easy

to program and debug. The Linker combines object files into an

executable file. The Simulator provides an interactive instruction-

level simulation with a reconfigurable user interface to display

different portions of the hardware environment. A PROM

Splitter generates PROM programmer compatible files. The

C Compiler, based on the Free Software Foundation’s GNU

C Compiler, generates ADSP-2184L assembly source code.

The source code debugger allows programs to be corrected in

the C environment. The Runtime Library includes over 100

ANSI-standard mathematical and DSP-specific functions.

ARCHITECTURE OVERVIEW

The ADSP-2184L instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single pro-

cessor cycle. The ADSP-2184L assembly language uses an alge-

braic syntax for ease of coding and readability. A comprehensive

set of development tools supports program development.

POWER-DOWN

CONTROL

FULL MEMORY

MODE

MEMORY

PROGRAMMABLE

DATA ADDRESS

GENERATORS

I/O

AND

FLAGS

EXTERNAL

ADDRESS

BUS

4K

؋

24

PROGRAM

MEMORY

4K

؋

16

DATA

PROGRAM

SEQUENCER

DAG 2

DAG 1

MEMORY

EXTERNAL

DATA

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

The EZ-KIT Lite is a hardware/software kit offering a complete

development environment for the entire ADSP-21xx family: an

ADSP-218x based evaluation board with PC monitor software

plus Assembler, Linker, Simulator and PROM Splitter software.

The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware

platform on which you can quickly get started with your DSP soft-

ware design. The EZ-KIT Lite includes the following features:

BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

ARITHMETIC UNITS

MAC SHIFTER

SERIAL PORTS

SPORT 0 SPORT 1

TIMER

INTERNAL

DMA

PORT

ALU

• 33 MHz ADSP-2181

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

• Full 16-bit Stereo Audio I/O with AD1847 SoundPort^®Codec

• RS-232 Interface to PC with Windows^®3.1 Control Software

• EZ-ICE^®Connector for Emulator Control

• DSP Demo Programs

Figure 1. Block Diagram

Figure 1 is an overall block diagram of the ADSP-2184L. The

processor contains three independent computational units: the

ALU, the multiplier/accumulator (MAC) and the shifter. The

computational units process 16-bit data directly and have provi-

sions to support multiprecision computations. The ALU per-

forms a standard set of arithmetic and logic operations; division

primitives are also supported. The MAC performs single-cycle

multiply, multiply/add and multiply/subtract operations with

40 bits of accumulation. The shifter performs logical and arith-

metic shifts, normalization, denormalization and derive expo-

nent operations.

• Code compatible with all 218x products

The ADSP-218x EZ-ICE Emulator aids in the hardware debug-

ging of an ADSP-2184L system. The emulator consists of hard-

ware, host computer resident software, and the target board

connector. The ADSP-2184L integrates on-chip emulation

support with a 14-pin ICE-Port interface. This interface provides a

simpler target board connection that requires fewer mechanical

clearance considerations than other ADSP-2100 Family EZ-ICEs.

The ADSP-2184L device need not be removed from the target

system when using the EZ-ICE, nor are any adapters needed. Due

to the small footprint of the EZ-ICE connector, emulation can

be supported in final board designs.

The shifter can be used to efficiently implement numeric

format control including multiword and block floating-point

representations.

SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc.

Windows is a registered trademark of Microsoft Corporation.

REV. 0

–2–

ADSP-2184L

The internal result (R) bus connects the computational units so

the output of any unit may be the input of any unit on the next

cycle.

variety of framed or frameless data transmit and receive modes

of operation.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these compu-

tational units. The sequencer supports conditional jumps, sub-

routine calls and returns in a single cycle. With internal loop

counters and loop stacks, the ADSP-2184L executes looped

code with zero overhead; no explicit jump instructions are re-

quired to maintain loops.

The ADSP-2184L provides up to 13 general-purpose flag pins.

The data input and output pins on SPORT1 can be alternatively

configured as an input flag and an output flag. In addition, eight

flags are programmable as inputs or outputs, and three flags are

always outputs.

A programmable interval timer generates periodic interrupts. A

16-bit count register (TCOUNT) decrements every n processor

cycles, where n is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches from data memory and pro-

gram memory. Each DAG maintains and updates four address

pointers. Whenever the pointer is used to access data (indirect

addressing), it is post-modified by the value of one of four pos-

sible modify registers. A length value may be associated with

each pointer to implement automatic modulo addressing for

circular buffers.

Serial Ports

The ADSP-2184L incorporates two complete synchronous

serial ports (SPORT0 and SPORT1) for serial communications

and multiprocessor communication.

Efficient data transfer is achieved with the use of five internal

buses:

Here is a brief list of the capabilities of the ADSP-2184L SPORTs.

For additional information on Serial Ports, refer to the ADSP-

2100 Family User’s Manual, Third Edition.

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

• SPORTs are bidirectional and have a separate, double-buff-

ered transmit and receive section.

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

• SPORTs can use an external serial clock or generate their own

serial clock internally.

• SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulsewidths and timings.

Program memory can store both instructions and data, permit-

ting the ADSP-2184L to fetch two operands in a single cycle,

one from program memory and one from data memory. The

ADSP-2184L can fetch an operand from program memory and

the next instruction in the same cycle.

• SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCITT recommendation G.711.

When configured in host mode, the ADSP-2184L has a 16-bit

Internal DMA port (IDMA port) for connection to external

systems. The IDMA port is made up of 16 data/address pins

and five control pins. The IDMA port provides transparent,

direct access to the DSPs on-chip program and data RAM.

• SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt

is generated after a data buffer transfer.

An interface to low cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

• SPORT0 has a multichannel interface to selectively receive

and transmit a 24- or 32-word, time-division multiplexed,

serial bitstream.

• SPORT1 can be configured to have two external interrupts

(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this

configuration.

The byte memory and I/O memory space interface supports

slow memories and I/O memory-mapped peripherals with

programmable wait state generation. External devices can

gain control of external buses with bus request/grant signals

(BR, BGH and BG). One execution mode (Go Mode) allows

the ADSP-2184L to continue running from on-chip memory.

Normal execution mode requires the processor to halt while

buses are granted.

PIN DESCRIPTIONS

The ADSP-2184L is available in a 100-lead LQFP package. In

order to maintain maximum functionality and reduce package

size and pin count, some serial port, programmable flag, inter-

rupt and external bus pins have dual, multiplexed functionality.

The external bus pins are configured during RESET only, while

serial port pins are software configurable during program execu-

tion. Flag and interrupt functionality is retained concurrently

on multiplexed pins. In cases where pin functionality is

reconfigurable, the default state is shown in plain text; alternate

functionality is shown in italics.

The ADSP-2184L can respond to 13 interrupts. There are up to

six external interrupts (one edge-sensitive, two level-sensitive and

three configurable) and seven internal interrupts generated by

the timer, the serial ports (SPORTs), the Byte DMA port and

the power-down circuitry. There is also a master RESET inter-

rupt. The two serial ports provide a complete synchronous serial

interface with optional companding in hardware and a wide

REV. 0

–3–

ADSP-2184L

Common-Mode Pins

Memory Interface Pins

The ADSP-2184L processor can be used in one of two modes:

Full Memory Mode, which allows BDMA operation with full

external overlay memory and I/O capability, or Host Mode, which

allows IDMA operation with limited external addressing capabili-

ties. The operating mode is determined by the state of the Mode C

pin during reset and cannot be changed while the processor is

running. (See Table VI for complete mode operation descriptions.)

#

of

Input/

Out-

Name(s)

Pins put

Function

RESET

BR

1

I

Processor Reset Input

Bus Request Input

Bus Grant Output

BG

O

I/O

O

I

BGH

DMS

PMS

IOMS

BMS

CMS

RD

Bus Grant Hung Output

Data Memory Select Output

Program Memory Select Output

Memory Select Output

Byte Memory Select Output

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

Full Memory Mode Pins (Mode C = 0)

#

of

Input/

Pin Name Pins

Output Function

A13:0

14

O

Address Output Pins for Pro-

gram, Data, Byte and I/O Spaces

D23:0

24

I/O

Data I/O Pins for Program,

Data, Byte and I/O Spaces

(8 MSBs Are Also Used as

Byte Memory Addresses)

WR

IRQ2/

Edge- or Level-Sensitive

Interrupt Request¹

PF7

IRQL0/

PF5

IRQL1/

PF6

IRQE/

PF4

PF3

I/O

I

I/O

I

I/O

I

I/O

I

Programmable I/O Pin

Host Mode Pins (Mode C = 1)

1

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

#

of

Input/

Output Function

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Edge-Sensitive Interrupt Requests¹

Programmable I/O Pin

Mode Select Input—Checked

only During RESET

Pin Name Pins

IAD15:0

A0

16

1

I/O

O

IDMA Port Address/Data Bus

Address Pin for External I/O,

Program, Data or Byte Access

Data I/O Pins for Program,

Data Byte and I/O Spaces

1

D23:8

16

I/O

Mode C/

PF2

I/O

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked

only During RESET

IWR

IRD

IAL

IS

1

I

IDMA Write Enable

IDMA Read Enable

IDMA Address Latch Pin

IDMA Select

Mode B/

1

I

PF1

I/O

IACK

O

IDMA Port Acknowledge

Mode A/

I

In Host Mode, external peripheral addresses can be decoded using the A0,

BMS, CMS, PMS, DMS and IOMS signals.

PF0

I/O

Programmable I/O Pin During

Normal Operation

Clock or Quartz Crystal Input

Processor Clock Output

Serial Port I/O Pins

Setting Memory Mode

Memory Mode selection for the ADSP-2184L is made during

chip reset through the use of the Mode C pin. This pin is multi-

plexed with the DSP’s PF2 pin, so care must be taken in how

the mode selection is made. The two methods for selecting the

value of Mode C are passive and active.

CLKIN, XTAL 2

CLKOUT

SPORT0

SPORT1

IRQ1:0/

FI, FO

I

O

I/O

1

5

Serial Port I/O Pins

Passive configuration involves the use of a pull-up or pull-down

resistor connected to the Mode C pin. To minimize power

consumption, or if the PF2 pin is to be used as an output in the

DSP application, a weak pull-up or pull-down, on the order of

100 kΩ, can be used. This value should be sufficient to pull the

pin to the desired level and still allow the pin to operate as a

programmable flag output without undue strain on the processor’s

output driver. For minimum power consumption during

power-down, reconfigure PF2 to be an input, as the pull-up or

pull-down will hold the pin in a known state, and will not switch.

Edge- or Level-Sensitive Interrupts,

Flag In, Flag Out²

PWD

1

I

Power-Down Control Input

Power-Down Control Output

Output Flags

Power and Ground

For Emulation Use³

PWDACK

O

I

FL0, FL1, FL2 3

_DDand GND 16

V

EZ-Port

9

I/O

NOTES

¹Interrupt/Flag pins retain both functions concurrently. If IMASK is set to

enable the corresponding interrupts, the DSP will vector to the appropriate

interrupt vector address when the pin is asserted, either by external devices or

set as a programmable flag.

Active configuration involves the use of a three-stateable exter-

nal driver connected to the Mode C pin. A driver’s output en-

able should be connected to the DSP’s RESET signal such that

it only drives the PF2 pin when RESET is active (low). After

RESET is deasserted, the driver should three-state, thus allow-

ing full use of the PF2 pin as either an input or output.

²SPORT configuration determined by the DSP System Control Register. Soft-

ware configurable.

³See Designing an EZ-ICE-Compatible System in this data sheet for complete

information.

REV. 0

–4–

ADSP-2184L

To minimize power consumption during power-down, configure

the programmable flag as an output when connected to a three-

stated buffer. This ensures that the pin will be held at a constant

level and not oscillate should the three-state driver’s level hover

around the logic switching point.

The IFC register is a write-only register used to force and clear

interrupts.

On-chip stacks preserve the processor status and are automati-

cally maintained during interrupt handling. The stacks are twelve

levels deep to allow interrupt, loop and subroutine nesting.

Interrupts

The following instructions allow global enable or disable servic-

ing of the interrupts (including power-down), regardless of the

state of IMASK. Disabling the interrupts does not affect serial

port autobuffering or DMA.

The interrupt controller allows the processor to respond to the

thirteen possible interrupts (eleven of which can be enabled

at any one time), and RESET with minimum overhead. The

ADSP-2184L provides four dedicated external interrupt input

pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the PF7:4

pins). In addition, SPORT1 may be reconfigured for IRQ0,

IRQ1, FLAG_IN and FLAG_OUT, for a total of six external

interrupts. The ADSP-2184L also supports internal interrupts

from the timer, the byte DMA port, the two serial ports, soft-

ware and the power-down control circuit. The interrupt levels

are internally prioritized and individually maskable (except

power-down and RESET). The IRQ2, IRQ0 and IRQ1 input

pins can be programmed to be either level- or edge-sensitive.

IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive.

The priorities and vector addresses of all interrupts are shown in

Table I.

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2184L has three low power modes that significantly

reduce the power dissipation when the device operates under

standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external

power dissipation.

Table I. Interrupt Priority and Interrupt Vector Addresses

Source Of Interrupt

Interrupt Vector Address (Hex)

Power-Down

The ADSP-2184L processor has a low power feature that lets

the processor enter a very low power dormant state through

hardware or software control. Following is a brief list of power-

down features. Refer to the ADSP-2100 Family User’s Manual,

Third Edition, “System Interface” chapter, for detailed informa-

tion about the power-down feature.

RESET (or Power-Up with

PUCR = 1)

Power-Down (Nonmaskable) 002C

IRQ2

0000 (Highest Priority)

0004

0008

000C

0010

0014

0018

001C

IRQL1

IRQL0

•

Quick recovery from power-down. The processor begins

executing instructions in as few as 400 CLKIN cycles.

SPORT0 Transmit

SPORT0 Receive

IRQE

•

Support for an externally generated TTL or CMOS proces-

sor clock. The external clock can continue running during

power-down without affecting the lowest power rating and

400 CLKIN cycle recovery.

BDMA Interrupt

SPORT1 Transmit or IRQ1 0020

•

Support for crystal operation includes disabling the oscillator

to save power (the processor automatically waits approxi-

mately 4096 CLKIN cycles for the crystal oscillator to start

or stabilize), and letting the oscillator run to allow 400 CLKIN

cycle start-up.

SPORT1 Receive or IRQ0

Timer

0024

0028 (Lowest Priority)

Interrupt routines can either be nested, with higher priority

interrupts taking precedence, or processed sequentially. Inter-

rupts can be masked or unmasked with the IMASK register.

Individual interrupt requests are logically ANDed with the bits

in IMASK; the highest priority unmasked interrupt is then

selected. The power-down interrupt is nonmaskable.

•

Power-down is initiated by either the power-down pin (PWD)

or the software power-down force bit.

Interrupt support allows an unlimited number of instructions

to be executed before optionally powering down. The power-

down interrupt also can be used as a nonmaskable, edge-

sensitive interrupt.

The ADSP-2184L masks all interrupts for one instruction cycle

following the execution of an instruction that modifies the

IMASK register. This does not affect serial port autobuffering

or DMA transfers.

•

Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving the

power-down state.

The interrupt control register, ICNTL, controls interrupt nest-

ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to

be either edge- or level-sensitive. The IRQE pin is an external

edge-sensitive interrupt and can be forced and cleared. The

IRQL0 and IRQL1 pins are external level-sensitive interrupts.

•

The RESET pin also can be used to terminate power-down.

Power-down acknowledge (PWDACK) pin indicates when

the processor has entered power-down.

REV. 0

–5–

ADSP-2184L

Idle

FULL MEMORY MODE

When the ADSP-2184L is in the Idle Mode, the processor waits

indefinitely in a low power state until an interrupt occurs. When

an unmasked interrupt occurs, it is serviced; execution then

continues with the instruction following the IDLE instruction.

In Idle mode IDMA, BDMA and autobuffer cycle steals still

occur.

ADSP-2184L

CLKIN

A

D

13-0

1/2x CLOCK

OR

CRYSTAL

14

ADDR13-0

XTAL

A0-A21

23-16

FL0-2

BYTE

MEMORY

D

15-8

24

PF3

DATA

DATA23-0

IRQ2/PF7

CS

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

BMS

A

10-0

Slow Idle

WR

RD

ADDR

DATA

D

23-8

MODE C/PF2

MODE B/PF1

MODE A/PF0

I/O SPACE

The IDLE instruction is enhanced on the ADSP-2184L to let

the processor’s internal clock signal be slowed, further reducing

power consumption. The reduced clock frequency, a program-

mable fraction of the normal clock rate, is specified by a select-

able divisor given in the IDLE instruction. The format of the

instruction is:

(PERIPHERALS)

2048 LOCATIONS

CS

IOMS

A

13-0

ADDR

DATA

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

OVERLAY

MEMORY

D

23-0

SERIAL

DEVICE

TWO 8K

PMS

DMS

CMS

PM SEGMENTS

TWO 8K

IDLE (n)

SPORT0

SCLK0

RFS0

TFS0

DT0

DM SEGMENTS

BR

BG

BGH

SERIAL

DEVICE

where n = 16, 32, 64 or 128. This instruction keeps the proces-

sor fully functional, but operating at the slower clock rate. While

it is in this state, the processor’s other internal clock signals such

as SCLK, CLKOUT and timer clock, are reduced by the same

ratio. The default form of the instruction, when no clock divisor

is given, is the standard IDLE instruction.

PWD

DR0

PWDACK

HOST MEMORY MODE

ADSP-2184L

CLKIN

1/2x CLOCK

OR

CRYSTAL

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to in-

coming interrupts. The one-cycle response time of the standard

idle state is increased by n, the clock divisor. When an enabled

interrupt is received, the ADSP-2184L will remain in the idle

state for up to a maximum of n processor cycles (n = 16, 32, 64

or 128) before resuming normal operation.

1

A0

XTAL

FL0-2

PF3

16

DATA23-8

IRQ2/PF7

IRQE/PF4

BMS

IRQL0/PF5

IRQL1/PF6

WR

MODE C/PF2

MODE B/PF1

MODE A/PF0

RD

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster rate than can be serviced due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

IOMS

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

SERIAL

DEVICE

PMS

DMS

CMS

SPORT0

SCLK0

RFS0

TFS0

DT0

SERIAL

DEVICE

BR

BG

BGH

DR0

IDMA PORT

PWD

PWDACK

SYSTEM INTERFACE

IRD/D6

IWR/D7

IS/D4

IAL/D5

IACK/D3

SYSTEM

INTERFACE

OR

Figure 2 shows typical basic system configurations with the

ADSP-2184L, two serial devices, a byte-wide EPROM and op-

tional external program and data overlay memories (mode select-

able). Programmable wait state generation allows the processor

to connect easily to slow peripheral devices. The ADSP-2184L

also provides four external interrupts and two serial ports or six

external interrupts and one serial port. Host Memory Mode

allows access to the full external data bus, but limits addressing

to a single address bit (A0). Additional system peripherals can

be added in this mode through the use of external hardware to

generate and latch address signals.

␮CONTROLLER

16

IAD15-0

Figure 2. Basic System Configuration

REV. 0

–6–

ADSP-2184L

Clock Signals

The master RESET sets all internal stack pointers to the empty

stack condition, masks all interrupts and clears the MSTAT

register. When RESET is released, if there is no pending bus

request and the chip is configured for booting, the boot-loading

sequence is performed. The first instruction is fetched from

on-chip program memory location 0x0000 once boot loading

completes. In an EZ-ICE-compatible system RESET and

ERESET have the same functionality. For complete information,

see Designing an EZ-ICE-Compatible System section.

The ADSP-2184L can be clocked by either a crystal or a

TTL-compatible clock signal.

The CLKIN input cannot be halted, changed during operation

or operated below the specified frequency during normal opera-

tion. The only exception is while the processor is in the power-

down state. For additional information on the power-down

feature, refer to the ADSP-2100 Family User’s Manual, Third

Edition.

If an external clock is used, it should be a TTL-compatible

signal running at half the instruction rate. The signal is con-

nected to the processor’s CLKIN input. When an external clock

is used, the XTAL input must be left unconnected.

MEMORY ARCHITECTURE

The ADSP-2184L provides a variety of memory and peripheral

interface options. The key functional groups are Program Memory,

Data Memory, Byte Memory and I/O.

The ADSP-2184L uses an input clock with a frequency equal to

half the instruction rate; a 20 MHz input clock yields a 25 ns

processor cycle (which is equivalent to 40 MHz). Normally,

instructions are executed in a single processor cycle. All device

timing is relative to the internal instruction clock rate, which is

indicated by the CLKOUT signal when enabled.

Program Memory (Full Memory Mode) is a 24-bit-wide space

for storing both instruction opcodes and data. The ADSP-2184L

has 4K words of Program Memory RAM on chip, and the capabil-

ity of accessing up to two 8K external memory overlay spaces using

the external data bus. Both an instruction opcode and a data value

can be read from on-chip program memory in a single cycle.

Because the ADSP-2184L includes an on-chip oscillator circuit,

an external crystal may be used. The crystal should be con-

nected across the CLKIN and XTAL pins, with two capacitors

connected as shown in Figure 3. Capacitor values are dependent

on crystal type and should be specified by the crystal manufac-

turer. A parallel-resonant, fundamental frequency, microproces-

sor-grade crystal should be used.

Data Memory (Full Memory Mode) is a 16-bit-wide space

used for the storage of data variables and for memory-mapped

control registers. The ADSP-2184L has 4K words on Data

Memory RAM on chip, consisting of 4K user-accessible

locations and 32 memory-mapped registers. Support also exists

for up to two 8K external memory overlay spaces through the

external data bus.

A clock output (CLKOUT) signal is generated by the proces-

sor at the processor’s cycle rate. This can be enabled and

disabled by the CLKODIS bit in the SPORT0 Autobuffer

Control Register.

Byte Memory (Full Memory Mode) provides access to an

8-bit wide memory space through the Byte DMA (BDMA) port.

The Byte Memory interface provides access to 4 MBytes of

memory by utilizing eight data lines as additional address lines.

This gives the BDMA Port an effective 22-bit address range. On

power-up, the DSP can automatically load bootstrap code from

byte memory.

I/O Space (Full Memory Mode) allows access to 2048 loca-

tions of 16-bit-wide data. It is intended to be used to communi-

cate with parallel peripheral devices such as data converters and

external registers or latches.

CLKIN

CLKOUT

XTAL

DSP

Program Memory

The ADSP-2184L contains 4K × 24 of on-chip program RAM.

The on-chip program memory is designed to allow up to two

accesses each cycle so that all operations can complete in a

single cycle. In addition, the ADSP-2184L allows the use of 8K

external memory overlays.

Figure 3. External Crystal Connections

Reset

The RESET signal initiates a master reset of the ADSP-2184L.

The RESET signal must be asserted during the power-up

sequence to assure proper initialization. RESET during initial

power-up must be held long enough to allow the internal clock

to stabilize. If RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

The program memory space organization is controlled by the

Mode B pin and the PMOVLAY register. Normally, the ADSP-

2184L is configured with Mode B = 0 and program memory

organized as shown in Figure 4.

The power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid V_DDis

applied to the processor, and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum of

2000 CLKIN cycles ensures that the PLL has locked, but does

not include the crystal oscillator start-up time. During this

power-up sequence the RESET signal should be held low. On

any subsequent resets, the RESET signal must meet the mini-

PROGRAM MEMORY ADDRESS

0x3FFF

EXTERNAL 8K

(PMOVLAY = 1 or 2,

MODE B = 0)

0x2000

0x1FFF

RESERVED MEMORY

RANGE

0x1000

0x0FFF

4K INTERNAL

mum pulsewidth specification, t_RSP

.

0x0000

The RESET input contains some hysteresis; however, if an RC

circuit is used to generate the RESET signal, an external Schmidt

trigger is recommended.

Figure 4. Program Memory (Mode B = 0)

REV. 0

–7–

ADSP-2184L

When PMOVLAY is set to 1 or 2, external accesses occur at

addresses 0x2000 through 0x3FFF. The external address is

generated as shown in Table II.

DATA MEMORY

ADDRESS

0x3FFF

32 MEMORY–

MAPPED REGISTERS

0x3FEO

0x3FDF

4064 RESERVED WORDS

Table II.

0x3000

0x2FFF

INTERNAL

4K

PMOVLAY Memory A13

A12:0

0x2000

0x1FFF

0

1

Internal

External

Not Applicable Not Applicable

13 LSBs of Address

EXTERNAL 8K

(DMOVLAY = 1, 2)

Overlay 1

0

Between 0x2000

and 0x3FFF

0x0000

2

External

Overlay 2

13 LSBs of Address

Between 0x2000

and 0x3FFF

Figure 6. Data Memory

1

There are 4K words of memory accessible internally when the

DMOVLAY register is set to 0. When DMOVLAY is set to 1 or

2, external accesses occur at addresses 0x0000 through 0x1FFF.

The external address is generated as shown in Table III.

Table III.

NOTE: Addresses 0x2000 through 0x3FFF should not be accessed when

PMOVLAY = 0.

This organization provides for two external 8K overlay segments

using only the normal 14 address bits, which allows for simple

program overlays using one of the two external segments in

place of the on-chip memory. Care must be taken in using this

overlay space in that the processor core (i.e., the sequencer)

does not take into account the PMOVLAY register value. For

example, if a loop operation is occurring on one of the external

overlays and the program changes to another external overlay or

internal memory, an incorrect loop operation could occur. In

addition, care must be taken in interrupt service routines as the

overlay registers are not automatically saved and restored on the

processor mode stack.

DMOVLAY Memory A13

A12:0

0

1

Internal

External

Not Applicable Not Applicable

13 LSBs of Address

Overlay 1

0

Between 0x0000

and 0x1FFF

2

External

Overlay 2

13 LSBs of Address

Between 0x0000

and 0x1FFF

1

This organization allows for two external 8K overlays using only

the normal 14 address bits. All internal accesses complete in one

cycle. Accesses to external memory are timed using the wait

states specified by the DWAIT register.

When Mode B = 1, booting is disabled and overlay memory is

disabled. Figure 5 shows the memory map in this configuration.

The 4K internal pin cannot be accessed with Mode B = 1.

I/O Space (Full Memory Mode)

PROGRAM MEMORY

ADDRESS

0x3FFF

The ADSP-2184L supports an additional external memory

space called I/O space. This space is designed to support simple

connections to peripherals or to bus interface ASIC data regis-

ters. I/O space supports 2048 locations. The lower eleven bits

of the external address bus are used; the upper three bits are

undefined. Two instructions were added to the core ADSP-

2100 Family instruction set to read from and write to I/O

memory space. The I/O space also has four dedicated three-bit

wait state registers, IOWAIT0-3, that specify up to seven wait

states to be automatically generated for each of four regions.

The wait states act on address ranges as shown in Table IV.

RESERVED

0x2000

0x1FFF

8K EXTERNAL

0x0000

Figure 5. Program Memory (Mode B = 1)

Data Memory

The ADSP-2184L has 4K 16-bit words of internal data memory.

In addition, the ADSP-2184L allows the use of 8K external

memory overlays. Figure 6 shows the organization of the data

memory.

Table IV.

Address Range

Wait State Register

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

IOWAIT0

IOWAIT1

IOWAIT2

IOWAIT3

REV. 0

–8–

ADSP-2184L

external memory have priority over BDMA byte memory

accesses.

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. The byte memory space

consists of 256 16K × 8 pages.

The BDMA Context Reset bit (BCR) controls whether the

processor is held off while the BDMA accesses are occurring.

Setting the BCR bit to 0 allows the processor to continue opera-

tions. Setting the BCR bit to 1 causes the processor to stop

execution while the BDMA accesses are occurring, to clear the

context of the processor and start execution at address 0 when

the BDMA accesses have completed.

The byte memory space on the ADSP-2184L supports read and

write operations as well as four different data formats. The byte

memory uses data bits 15:8 for data. The byte memory uses

data bits 23:16 and address bits 13:0 to create a 22-bit address.

This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be

used without glue logic. All byte memory accesses are timed by

the BMWAIT register.

Composite Memory Select (CMS)

The ADSP-2184L has a programmable memory select signal

that is useful for generating memory select signals for memories

mapped to more than one space. The CMS signal is generated

to have the same timing as each of the individual memory select

signals (PMS, DMS, BMS, IOMS), but can combine their

functionality.

Byte Memory DMA (BDMA, Full Memory Mode)

The Byte memory DMA controller allows loading and storing of

program instructions and data using the byte memory space.

The BDMA circuit is able to access the byte memory space

while the processor is operating normally and steals only one

DSP cycle per 8-, 16- or 24-bit word transferred.

Each bit in the CMSSEL register, when set, causes the CMS

signal to be asserted when the selected memory select is as-

serted. For example, to use a 32K word memory to act as both

program and data memory, set the PMS and DMS bits in the

CMSSEL register and use the CMS pin to drive the chip select

of the memory and use either DMS or PMS as the additional

address bit.

The BDMA circuit supports four different data formats, that are

selected by the BTYPE register field. The appropriate number

of 8-bit accesses is determined from the byte memory space to

build the word size selected. Table V shows the data formats sup-

ported by the BDMA circuit.

Table V.

The CMS pin functions as the other memory select signal, with

the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

selected memory select signal. All enable bits, except the BMS

bit, default to 1 at reset.

Internal

BTYPE

Memory Space

Word Size

Alignment

00

01

10

11

Program Memory

Data Memory

24

16

8

Full Word

MSBs

Internal Memory DMA Port (IDMA Port; Host Memory Mode)

The IDMA Port provides an efficient means of communication

between a host system and the ADSP-2184L. The port is used

to access the on-chip program memory and data memory of the

DSP with only one DSP cycle per word overhead. The IDMA

port cannot, however, be used to write directly to the DSP’s

memory-mapped control registers.

8

LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.

The BIAD register field is used to specify the starting address for

the on-chip memory involved with the transfer. The 14-bit BEAD

register specifies the starting address for the external byte memory

space. The 8-bit BMPAGE register specifies the starting page for

the external byte memory space. The BDIR register field selects

the direction of the transfer. Finally the 14-bit BWCOUNT

register specifies the number of DSP words to transfer and

initiates the BDMA circuit transfers.

The IDMA port has a 16-bit multiplexed address and data bus

and supports 24-bit program memory. The IDMA port is com-

pletely asynchronous and can be written to while the ADSP-

2184L is operating at full speed.

The DSP memory address is latched and then automatically

incremented after each IDMA transaction. An external device

can therefore access a block of sequentially addressed memory

by specifying only the starting address of the block. This in-

creases throughput as the address does not have to be sent for

each memory access.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers specified by the BWCOUNT register.

The BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches

zero, the transfers have finished and a BDMA interrupt is gener-

ated. The BMPAGE and BEAD registers must not be accessed

by the DSP during BDMA operations.

IDMA Port access occurs in two phases. The first is the IDMA

Address Latch cycle. When the acknowledge is asserted, a 14-bit

address and 1-bit destination type can be driven onto the bus by

an external device. The address specifies an on-chip memory

location, the destination type specifies whether it is a DM or

PM access. The falling edge of the IDMA address latch signal

(IAL) or the missing edge of the IDMA select signal (IS) latches

this value into the IDMAA register.

The source or destination of a BDMA transfer will always be

on-chip program or data memory, regardless of the values of

Mode B, PMOVLAY or DMOVLAY.

When the BWCOUNT register is written with a nonzero value,

the BDMA circuit starts executing byte memory accesses with

wait states set by BMWAIT. These accesses continue until the

count reaches zero. When enough accesses have occurred to

create a destination word, it is transferred to or from on-chip

memory. The transfer takes one DSP cycle. DSP accesses to

Once the address is stored, data can then either be read from or

written to the ADSP-2184L’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD and

IWR respectively) signals the ADSP-2184L that a particular

REV. 0

–9–

ADSP-2184L

transaction is required. In either case, there is a one-processor-

cycle delay for synchronization. The memory access consumes

one additional processor cycle.

The BDMA interface is set up during reset to the following de-

faults when BDMA booting is specified: the BDIR, BMPAGE,

BIAD and BEAD registers are set to 0; the BTYPE register is

set to 0 to specify program memory 24-bit words; and the

BWCOUNT register is set to 32. This causes 32 words of on-

chip program memory to be loaded from byte memory. These

32 words are used to set up the BDMA to load in the remaining

program code. The BCR bit is also set to 1, which causes program

execution to be held off until all 32 words are loaded into on-chip

program memory. Execution then begins at address 0.

Once an access has occurred, the latched address is automati-

cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the

starting address and data format for DMA operation.

Bootstrap Loading (Booting)

The ADSP-2184L has two mechanisms to allow automatic

loading of the internal program memory after reset. The method

for booting is controlled by the Mode A, B and C configuration

bits as shown in Table VI. These four states can be compressed

into two-state bits by allowing an IDMA boot with Mode C = 1.

However, three bits are used to ensure future compatibility with

parts containing internal program memory ROM.

The IDLE instruction can also be used to allow the processor to

hold off execution while booting continues through the BDMA

interface. For BDMA accesses while in Host Mode, the ad-

dresses to boot memory must be constructed externally to the

ADSP-2184L. The only memory address bit provided by the

processor is A0.

BDMA Booting

When the MODE pins specify BDMA booting, the ADSP-2184L

initiates a BDMA boot sequence when RESET is released.

IDMA Booting

The ADSP-2184L can also boot programs through its Internal

DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the

ADSP-2184L boots from the IDMA port. The IDMA feature

can load as much on-chip memory as desired. Program execu-

tion is held off until on-chip program memory location 0 is

written to.

Table VI. Boot Summary Table

MODE C MODE B MODE A Booting Method

0

1

0

BDMA feature is used to load

the first 32 program memory

words from the byte memory

space. Program execution is

held off until all 32 words

have been loaded. Chip is

configured in Full Memory

Mode.

Bus Request and Bus Grant

The ADSP-2184L can relinquish control of the data and ad-

dress buses to an external device. When the external device

requires access to memory, it asserts the bus request (BR) sig-

nal. If the ADSP-2184L is not performing an external memory

access, it responds to the active BR input in the following pro-

cessor cycle by:

• Three-stating the data and address buses and the PMS, DMS,

BMS, CMS, IOMS, RD, WR output drivers,

0

No Automatic boot opera-

tions occur. Program execu-

tion starts at external memory

location 0. Chip is config-

ured in Full Memory Mode.

BDMA can still be used but

the processor does not auto-

matically use or wait for these

operations.

• Asserting the bus grant (BG) signal, and

• Halting program execution.

If Go Mode is enabled, the ADSP-2184L will not halt program

execution until it encounters an instruction that requires an

external memory access.

If the ADSP-2184L is performing an external memory access

when the external device asserts the BR signal, it will not three-

state the memory interfaces or assert the BG signal until the

processor cycle after the access completes. The instruction does

not need to be completed when the bus is granted. If a single

instruction requires two external memory accesses, the bus will

be granted between the two accesses.

1

0

BDMA feature is used to load

the first 32 program memory

words from the byte memory

space. Program execution is

held off until all 32 words

have been loaded. Chip is

configured in Host Mode.

Additional interface hardware

is required.

When the BR signal is released, the processor releases the BG

signal, reenables the output drivers and continues program

execution from the point at which it stopped.

The bus request feature operates at all times, including when

1

0

1

IDMA feature is used to load

any internal memory as de-

sired. Program execution is

held off until internal pro-

gram memory location 0 is

written to. Chip is configured

in Host Mode.

the processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-2184L is ready to

execute an instruction but is stopped because the external bus is

already granted to another device. The other device can release

the bus by deasserting bus request. Once the bus is released, the

ADSP-2184L deasserts BG and BGH and executes the external

memory access.

REV. 0

–10–

ADSP-2184L

Flag I/O Pins

If using a passive method of maintaining mode information (as

discussed in Setting Memory Modes), it does not matter that

the mode information is latched by an emulator reset. However,

if using the RESET pin as a method of setting the value of the

mode pins, the effects of an emulator reset must be taken into

consideration.

The ADSP-2184L has eight general purpose programmable input/

output flag pins. They are controlled by two memory mapped

registers. The PFTYPE register determines the direction,

1 = output and 0 = input. The PFDATA register is used to read

and write the values on the pins. Data being read from a pin

configured as an input is synchronized to the ADSP-2184L’s

clock. Bits that are programmed as outputs will read the value

being output. The PF pins default to input during reset.

One method of ensuring that the values located on the mode

pins are the desired values is to construct a circuit like the one

shown in Figure 7. This circuit forces the value located on the

Mode A pin to logic low, regardless if it latched via the RESET

or ERESET pin.

In addition to the programmable flags, the ADSP-2184L has

five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and

FL2. FL0-FL2 are dedicated output flags. FLAG_IN and

FLAG_OUT are available as an alternate configuration of

SPORT1.

Note: Pins PF0, PF1 and PF2 are also used for device configu-

ration during reset.

ERESET

RESET

ADSP-2184L

1k⍀

MODE A/PF0

INSTRUCTION SET DESCRIPTION

The ADSP-2184L assembly language instruction set has an

algebraic syntax that was designed for ease of coding and

readability. The assembly language, which takes full advantage

of the processor’s unique architecture, offers the following benefits:

• The algebraic syntax eliminates the need to remember cryptic

assembler mnemonics. For example, a typical arithmetic add

instruction, such as AR = AX0 + AY0, resembles a simple

equation.

• Every instruction assembles into a single, 24-bit word that

can execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly lan-

guage and is completely source and object code compatible

with other family members. Programs may need to be relo-

cated to utilize on-chip memory and conform to the ADSP-

2184L’s interrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional jump,

call, return or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

• Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches or one write to

processor memory space during a single instruction cycle.

PROGRAMMABLE I/O

Figure 7. Boot Mode Circuit

See the ADSP-2100 Family EZ-Tools data sheet for complete

information on ICE products.

The ICE-Port interface consists of the following ADSP-2184L

pins:

EBR

EMS

ELIN

EBG

EINT

ELOUT

ERESET

ECLK

EE

These ADSP-2184L pins are usually connected only to the

EZ-ICE connector in the target system. These pins have no

function except during emulation, and do not require pull-up

or pull-down resistors. The traces for these signals between

the ADSP-2184L and the connector must be kept as short as

possible, no longer than three inches.

The following pins are also used by the EZ-ICE:

BR

BG

RESET

GND

The EZ-ICE uses the EE (emulator enable) signal to take con-

trol of the ADSP-2184L in the target system. This causes the

processor to use its ERESET, EBR and EBG pins instead of

the RESET, BR and BG pins. The BG output is three-stated.

These signals do not need to be jumper-isolated in your system.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2184L has on-chip emulation support and an

ICE-Port, a special set of pins that interface to the EZ-ICE. These

features allow in-circuit emulation without replacing the target

system processor by using only a 14-pin connection from the

target system to the EZ-ICE. Target systems must have a 14-pin

connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.

The EZ-ICE connects to your target system via a ribbon cable

and a 14-pin female plug. The female plug is plugged onto the

14-pin connector (a pin strip header) on the target board.

Issuing the chip reset command during emulation causes the

DSP to perform a full chip reset, including a reset of its memory

mode. Therefore, it is vital that the mode pins are set correctly

PRIOR to issuing a chip reset command from the emulator user

interface.

REV. 0

–11–

ADSP-2184L

Note: If your target does not meet the worst case chip specifica-

tions for memory access parameters, you may not be able to

emulate your circuitry at the desired CLKIN frequency. Depend-

ing on the severity of the specification violation, you may have

trouble manufacturing your system as DSP components statisti-

cally vary in switching characteristics and timing requirements

within published limits.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in

Figure 8. You must add this connector to your target board

design if you intend to use the EZ-ICE. Be sure to allow

enough room in your system to fit the EZ-ICE probe onto the

14-pin connector.

1

3

2

Restriction: All memory strobe signals on the ADSP-2184L

(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your

target system must have 10 kΩ pull-up resistors connected when

the EZ-ICE is being used. The pull-up resistors are necessary

because there are no internal pull-ups to guarantee their state

during prolonged three-state conditions resulting from typical

EZ-ICE debugging sessions. These resistors may be removed at

your option when the EZ-ICE is not being used.

GND

BG

4

EBG

BR

5

6

8

EBR

KEY (NO PIN)

ELOUT

EINT

ELIN

ECLK

EMS

7

9

10

12

14

Target System Interface Signals

When the EZ-ICE board is installed, the performance of some

system signals change. Design your system to be compatible

with the following system interface signal changes introduced by

the EZ-ICE board:

11

13

EE

RESET

ERESET

• EZ-ICE emulation introduces an 8 ns propagation delay be-

TOP VIEW

tween your target circuitry and the DSP on the RESET signal.

Figure 8. Target Board Connector for EZ-ICE

• EZ-ICE emulation introduces an 8 ns propagation delay be-

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-

tion—you must remove Pin 7 from the header. The pins must

be 0.025 inch square and at least 0.20 inch in length. Pin spac-

ing should be 0.1 × 0.1 inches. The pin strip header must have

at least 0.15-inch clearance on all sides to accept the EZ-ICE

probe plug. Pin strip headers are available from vendors such as

3M, McKenzie and Samtec.

tween your target circuitry and the DSP on the BR signal.

• EZ-ICE emulation ignores RESET and BR when single-

stepping.

• EZ-ICE emulation ignores RESET and BR when in Emulator

Space (DSP halted).

• EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the

DSP’s external memory bus only if bus grant (BG) is asserted

by the EZ-ICE board’s DSP.

Target Memory Interface

For your target system to be compatible with the EZ-ICEemu-

lator, it must comply with the memory interface guidelines listed

below.

PM, DM, BM, IOM, and CM

Design Program Memory (PM), Data Memory (DM), Byte

Memory (BM), I/O Memory (IOM) and Composite Memory

(CM) external interfaces to comply with worst case device tim-

ing requirements and switching characteristics as specified in

this DSP’s data sheet. The performance of the EZ-ICE may ap-

proach published worst case specification for some memory

access timing requirements and switching characteristics.

REV. 0

–12–

ADSP-2184L

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

B Grade

Parameter

Min

Max

Unit

V_DD

T_AMB

3.0

–40

3.6

+85

V

°C

ELECTRICAL CHARACTERISTICS

B Grade

Typ

Parameter

Test Conditions

Min

Max

Unit

V_IH

V_IL

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= max

@ V_DD= min

I_OH= –0.5 mA

@ V_DD= min

I_OH= –100 µA⁶

@ V_DD= min

I_OL= 2 mA

@ V_DD= max

V_IN= V_DDmax

@ V_DD= max

V_IN= 0 V

@ V_DD= max

V_IN= V_DDmax⁸

@ V_DD= max

V_IN= 0 V⁸

@ V_DD= 3.3

T_AMB= +25°C

t_CK= 25 ns

2.0

2.2

V

0.8

V_OH

2.4

V

V_DD– 0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

0.4

10

V

µA

I_IL

Lo-Level Input Current³

I_OZH

I_OZL

Three-State Leakage Current⁷

µA

mA

I_DD

Supply Current (Idle)⁹

8.6

42

Supply Current (Dynamic)^{10, 11}

mA

pF

C_I

Input Pin Capacitance^{3, 6, 12}

@ V_IN= 2.5 V,

f_IN= 1.0 MHz,

T_AMB= +25°C

@ V_IN= 2.5 V,

f_IN= 1.0 MHz,

T_AMB= +25°C

8

C_O

Output Pin Capacitance^{6, 7, 12, 13}

pF

NOTES

¹Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

²Input only pins: RESET, BR, DR0, DR1, PWD.

³Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

⁴Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.

⁵Although specified for TTL outputs, all ADSP-2184L outputs are CMOS-compatible and will drive to V_DDand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.

⁸0 V on BR.

⁹Idle refers to ADSP-2184L state of operation during execution of IDLE instruction. Deasserted pins are driven to either V_DDor GND.

10

I

measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2

DD

and type 6, and 20% are idle instructions.

11

V

= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

IN

¹²Applies to LQFP package type.

¹³Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

REV. 0

–13–

ADSP-2184L

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Operating Temperature Range (Ambient) . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . +280°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. These are stress ratings only; functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADSP-2184L features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

MEMORY TIMING SPECIFICATIONS

ADSP-2184L TIMING PARAMETERS

The table below shows common memory device specifications

and the corresponding ADSP-2184L timing parameters, for

your convenience.

GENERAL NOTES

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add up parameters to derive longer times.

Memory

Device

ADSP-2184L Timing

Timing

Parameter

Specification

Parameter

Definition

Address Setup to

Write Start

t_ASW

A0–A13, xMS Setup

before WR Low

TIMING NOTES

Address Setup to

Write End

t_AW

A0–A13, xMS Setup

before WR Deasserted

Switching characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

Address Hold Time t_WRA

A0–A13, xMS Hold

before WR Low

Data Setup Time

Data Hold Time

OE to Data Valid

t_DW

t_DH

Data Setup before WR

High

Data Hold after WR

High

Timing requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input for a

read operation. Timing requirements must be met to guarantee

that the processor operates correctly with other devices.

t_RDD

RD Low to Data Valid

Address Access Time t_AA

A0–A13, xMS to Data

Valid

xMS = PMS, DMS, BMS, CMS, IOMS.

FREQUENCY DEPENDENCY FOR TIMING

SPECIFICATIONS

t_CKis defined as 0.5 t_CKI. The ADSP-2184L uses an input clock

with a frequency equal to half the instruction rate: a 20 MHz

input clock (which is equivalent to 50 ns) yields a 25 ns proces-

sor cycle (equivalent to 40 MHz). t_CKvalues within the range of

0.5 t_CKIperiod should be substituted for all relevant timing para-

meters to obtain the specification value.

Example: t_CKH= 0.5 t_CK– 7 ns = 0.5 (25 ns) – 7 ns = 5.5 ns

REV. 0

–14–

ADSP-2184L

TIMING PARAMETERS

Parameter

Min

Max

Unit

Clock Signals and Reset

Timing Requirements:

t_CKI

CLKIN Period

CLKIN Width Low

CLKIN Width High

50

20

150

ns

t_CKIL

t_CKIH

Switching Characteristics:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

0.5 t_CK– 7

0

ns

CLKIN High to CLKOUT High

20

Control Signals

Timing Requirements:

t_RSP

t_MS

t_MH

RESET Width Low¹

5 t_CK

2

5

ns

Mode Setup before RESET High

Mode Setup after RESET High

NOTE

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

PF(2:0)

*

t_MH

t_MS

RESET

t_RSP

*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 9. Clock Signals

REV. 0

–15–

ADSP-2184L

TIMING PARAMETERS

Parameter

Min

Max

Unit

Interrupts and Flag

Timing Requirements:

t_IFS

t_IFH

IRQx, FI, or PFx Setup before CLKOUT Low^{1, 2, 3, 4}

IRQx, FI, or PFx Hold after CLKOUT High^{1, 2, 3, 4}

0.25 t_CK+ 15

0.25 t_CK

ns

Switching Characteristics:

t_FOH

Flag Output Hold after CLKOUT Low⁵

t_FOD

Flag Output Delay from CLKOUT Low⁵

0.25 t_CK– 7

ns

0.5 t_CK+ 6

NOTES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further

information on interrupt servicing.)

²Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

⁴PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

⁵Flag outputs = PFx, FL0, FL1, FL2, Flag_out.

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

PFx

t_IFS

Figure 10. Interrupts and Flags

REV. 0

–16–

ADSP-2184L

Parameter

Min

Max

Unit

Bus Request–Bus Grant

Timing Requirements:

t_BH

t_BS

BR Hold after CLKOUT High¹

BR Setup before CLKOUT Low¹

0.25 t_CK+ 2

0.25 t_CK+ 17

ns

Switching Characteristics:

t_SD

CLKOUT High to xMS, RD, WR Disable

0.25 t_CK+ 10

ns

t_SDB

t_SE

xMS, RD, WR Disable to BG Low

BG High to xMS, RD, WR Enable

xMS, RD, WR Enable to CLKOUT High

xMS, RD, WR Disable to BGH Low²

BGH High to xMS, RD, WR Enable²

0

t_SEC

t_SDBH

t_SEH

0.25 t_CK– 7

0

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS.

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on

the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.

²BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

WR

t_SD

t_SEC

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 11. Bus Request–Bus Grant

REV. 0

–17–

ADSP-2184L

TIMING PARAMETERS

Parameter

Min

Max

Unit

Memory Read

Timing Requirements:

t_RDD

t_AA

RD Low to Data Valid

A0–A13, xMS to Data Valid

Data Hold from RD High

0.5 t_CK– 9 + w

0.75 t_CK– 12.5 + w

ns

t_RDH

1

Switching Characteristics:

t_RP

RD Pulsewidth

CLKOUT High to RD Low

0.5 t_CK– 5 + w

0.25 t_CK– 5

0.25 t_CK– 6

0.25 t_CK– 3

0.5 t_CK– 5

ns

t_CRD

t_ASR

t_RDA

t_RWR

0.25 t_CK+ 7

A0–A13, xMS Setup before RD Low

A0–A13, xMS Hold after RD Deasserted

RD High to RD or WR Low

w = wait states × t_CK

.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, IOMS,

CMS

t_RDA

RD

t_ASR

t_CRD

t_RP

t_RWR

D0–D23

t_RDD

t_RDH

t_AA

WR

Figure 12. Memory Read

REV. 0

–18–

ADSP-2184L

Parameter

Min

Max

Unit

Memory Write

Switching Characteristics:

t_DW

t_DH

Data Setup before WR High

Data Hold after WR High

0.5 t_CK– 7 + w

0.25 t_CK– 2

0.5 t_CK– 5 + w

0

0.25 t_CK– 6

0.25 t_CK– 7

0.25 t_CK– 5

0.75 t_CK– 9 + w

0.25 t_CK– 3

0.5 t_CK– 5

ns

t_WP

WR Pulsewidth

WR Low to Data Enabled

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

t_WRA

t_WWR

A0–A13, xMS Setup before WR Low

Data Disable before WR or RD Low

CLKOUT High to WR Low

A0–A13, xMS, Setup before WR Deasserted

A0–A13, xMS Hold after WR Deasserted

WR High to RD or WR Low

0.25 t_CK+ 7

w = wait states × t_CK

.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

IOMS

t_WRA

WR

t_WWR

t_ASW

t_WP

t_AW

t_DH

t_DDR

t_CWR

D0–D23

t_DW

t_WDE

RD

Figure 13. Memory Write

REV. 0

–19–

ADSP-2184L

TIMING PARAMETERS

Parameter

Min

Max

Unit

Serial Ports

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

50

4

8

ns

DR/TFS/RFS Setup before SCLK Low

DR/TFS/RFS Hold after SCLK Low

SCLK_INWidth

20

Switching Characteristics:

t_CC

CLKOUT High to SCLK_OUT

SCLK High to DT Enable

SCLK High to DT Valid

TFS/RFS_OUTHold after SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

0.25 t_CK

0

0.25 t_CK+ 10

ns

t_SCDE

t_SCDV

t_RH

15

0

t_RD

t_SCDH

t_TDE

t_TDV

t_SCDD

t_RDV

0

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

14

15

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCS

t_SCH

DR

TFS

RFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

OUT

ALTERNATE

FRAME MODE

t_RDV

RFS

OUT

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

t_TDE

t_TDV

TFS

IN

ALTERNATE

FRAME MODE

t_RDV

RFS

IN

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

Figure 14. Serial Ports

REV. 0

–20–

ADSP-2184L

Parameter

Min

Max

Unit

IDMA Address Latch

Timing Requirements:

t_IALP

t_IASU

t_IAH

Duration of Address Latch^{1, 2}

10

5

3

0

3

ns

IAD15–0 Address Setup before Address Latch End²

IAD15–0 Address Hold after Address Latch End²

IACK Low before Start of Address Latch^{2, 3}

t_IKA

t_IALS

Start of Write or Read after Address Latch End^{2, 3}

NOTES

¹Start of Address Latch = IS Low and IAL High.

²End of Address Latch = IS High or IAL Low.

³Start of Write or Read = IS Low and IWR Low or IRD Low.

IACK

t_IKA

IAL

t_IALP

IS

t_IASU

t_IAH

IAD15–0

t_IALS

IRD OR

IWR

Figure 15. IDMA Address Latch

REV. 0

–21–

ADSP-2184L

TIMING PARAMETERS

Parameter

Min

Max

Unit

IDMA Write, Short Write Cycle

Timing Requirements:

t_IKW

t_IWP

t_IDSU

t_IDH

IACK Low before Start of Write¹

0

15

5

ns

Duration of Write^{1, 2}

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

2

Switching Characteristic:

t_IKHW

Start of Write to IACK High

17

ns

NOTES

¹Start of Write = IS Low and IWR Low.

²End of Write = IS High or IWR High.

³If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

⁴If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

t_IKW

IACK

t_IKHW

IS

t_IWP

IWR

t_IDH

t_IDSU

DATA

IAD15–0

Figure 16. IDMA Write, Short Write Cycle

REV. 0

–22–

ADSP-2184L

Parameter

Min

Max

Unit

IDMA Write, Long Write Cycle

Timing Requirements:

t_IKW

t_IKSU

t_IKH

IACK Low before Start of Write¹

0

ns

IAD15–0 Data Setup before IACK Low^{2, 3, 4}

IAD15–0 Data Hold after IACK Low^{2, 3, 4}

0.5 t_CK+ 10

2

Switching Characteristics:

t_IKLW

Start of Write to IACK Low⁴

t_IKHWStart of Write to IACK High

1.5 t_CK

ns

17

NOTES

¹Start of Write = IS Low and IWR Low.

²If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

³If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

⁴This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition.

t_IKW

IACK

t_IKHW

t_IKLW

IS

IWR

t_IKSU

t_IKH

DATA

IAD15–0

Figure 17. IDMA Write, Long Write Cycle

REV. 0

–23–

ADSP-2184L

TIMING PARAMETERS

Parameter

Min

Max

Unit

IDMA Read, Long Read Cycle

Timing Requirements:

t_IKR

t_IRK

IACK Low before Start of Read¹

0

2

ns

End of Read after IACK Low

Switching Characteristics:

t_IKHR

t_IKDS

t_IKDH

t_IKDD

t_IRDE

t_IRDV

t_IRDH1

t_IRDH2

IACK High after Start of Read¹

17

ns

IAD15–0 Data Setup before IACK Low

0.5 t_CK– 10

0

IAD15–0 Data Hold after End of Read²

IAD15–0 Data Disabled after End of Read²

10

15

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

IAD15–0 Previous Data Hold after Start of Read (DM/PM1)³

IAD15–0 Previous Data Hold after Start of Read (PM2)⁴

0

2 t_CK– 5

t_CK– 5

NOTES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

³DM read or first half of PM read.

⁴Second half of PM read.

IACK

IS

t_IKHR

t_IKR

t_IRK

IRD

t_IKDS

t_IKDH

t_IRDE

READ

DATA

IAD15–0

t_IRDV

t_IKDD

t_IRDH

Figure 18. IDMA Read, Long Read Cycle

REV. 0

–24–

ADSP-2184L

Parameter

Min

Max

Unit

IDMA Read, Short Read Cycle

Timing Requirements:

t_IKR

t_IRP

IACK Low before Start of Read¹

0

15

ns

Duration of Read

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High after Start of Read¹

15

10

15

ns

IAD15–0 Data Hold after End of Read²

0

IAD15–0 Data Disabled after End of Read²

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

NOTES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

IACK

IS

t_IKR

t_IKHR

t_IRP

IRD

t_IKDH

t_IRDE

IAD15–0

t_IKDD

t_IRDV

Figure 19. IDMA Read, Short Read Cycle

REV. 0

–25–

ADSP-2184L

1, 2, 3

POWER DISSIPATION

2184L POWER, INTERNAL

180

170

160

150

140

130

120

110

100

To determine total power dissipation in a specific application,

the following equation should be applied for each output:

169mW

V

= 3.6V

DD

C × V_DD²× f

139mW

C = load capacitance, f = output switching frequency.

126mW

V

= 3.3V

= 3.0V

Example

DD

In an application where external data memory is used and no

other outputs are active, power dissipation is calculated as follows:

102mW

83mW

V

DD

113mW

40

Assumptions

90

80

• External data memory is accessed every cycle with 50% of the

address pins switching.

30

32

34

36

38

42

1/t – MHz

CK

• External data memory writes occur every other cycle with

50% of the data pins switching.

1, 2, 4

POWER, IDLE

36

34

32

30

28

26

24

22

20

35mW

• Each address and data pin has a 10 pF total load at the pin.

• The application operates at V_DD= 3.3 V and t_CK= 30 ns.

V

= 3.6V

DD

2

Total Power Dissipation = P_INT+ (C × V_DD× f)

27mW

22mW

17mW

28mW

22mW

P

_INT= internal power dissipation from Power vs. Frequency

V

= 3.3V

= 3.0V

DD

graph (Figure 21).

2

(C × V_DD× f ) is calculated for each output:

DD

# of

Pins × C

2

18

16

× V_DD

× f

Address, DMS

Data Output, WR

RD

8

9

1

× 10 pF × 3.3²

V

× 33.3 MHz

× 16.67 MHz

× 33.3 MHz

=

29.0 mW

16.3 mW

1.8 mW

30

34

36

38

40

42

1/t – MHz

CK

2

POWER, IDLE n MODES

30

28

26

24

22

20

CLKOUT

3.6 mW

IDLE

28mW

50.7 mW

22mW

Total power dissipation for this example is PINT + 50.7 mW.

Output Drive Currents

n

Figure 20 shows typical I-V characteristics for the output drivers

of the ADSP-2184L. The curves represent the current drive

capability of the output drivers as a function of output voltage.

18

16

14

12

10

IDLE (16)

IDLE (128)

13mW

12mW

10mW

9mW

8

6

80

V

= 3.3V @ +25؇C

DD

V

= 3.6V @ –40؇C

30

34

36

1/t – MHz

38

40

42

DD

60

40

CK

V

OH

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2

3

TYPICAL POWER DISSIPATION AT 3.3V V AND T = 25؇C EXCEPT WHERE SPECIFIED.

DD

A

20

I

MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL

DD

V

= 3.0V @ +85؇C

DD

MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14)

30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

0

V

= 3.0V @ +85؇C

DD

4

IDLE REFERS TO ADSP-2184L STATE OF OPERATION DURING EXECUTION OF IDLE

–20

–40

–60

–80

INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.

DD

V

= 3.3V @ +25؇C

OL

DD

Figure 21. Power vs. Frequency

V

= 3.6V @ –40؇C

DD

0

0.5

1

1.5

2

2.5

3

3.5

SOURCE VOLTAGE – V

Figure 20. Typical Output Driver Characteristics

REV. 0

–26–

ADSP-2184L

CAPACITIVE LOADING

Figures 22 and 23 show the capacitive loading characteristics of

the ADSP-2184L.

the current load, i_L, on the output pin. It can be approximated

by the following equation:

C_L× 0.5V

t_DECAY

=

i_L

25

from which

V

= 3.0V

DD

20

15

10

5

T = ؉85؇C

t

_DIS= t_MEASURED– t_DECAY

is calculated. If multiple pins (such as the data bus) are dis-

abled, the measurement value is that of the last pin to stop

driving.

INPUT

OR

OUTPUT

1.5V

Figure 24. Voltage Reference Levels for AC Measure-

ments (Except Output Enable/Disable)

0

20

40

60

80

100 120 140 160 180 200

– pF

Output Enable Time

C

L

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to when they start

driving. The output enable time (t_ENA) is the interval from when

a reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram. If multiple pins (such as

the data bus) are enabled, the measurement value is that of the

first pin to start driving.

Figure 22. Typical Output Rise Time vs. Load Capacitance,

C_L(at Maximum Ambient Operating Temperature)

18

16

V

= 3.0V

DD

14

12

10

T = +85؇C

8

6

4

REFERENCE

SIGNAL

t_MEASURED

t_DIS

t_ENA

V

2

OH

(MEASURED)

NOMINAL

V

(MEASURED) – 0.5V

(MEASURED) +0.5V

2.0V

1.0V

OH

–2

–4

–6

OUTPUT

OL

V

OL

t_DECAY

(MEASURED)

0

50

100

150

– pF

200

250

C

L

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

Figure 23. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maximum Ambient Operating

Temperature)

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

Figure 25. Output Enable/Disable

TEST CONDITIONS

Output Disable Time

I

OL

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured

output high or low voltage to a high impedance state. The out-

put disable time (t_DIS) is the difference between t_MEASUREDand

t_DECAY, as shown in the Output Enable/Disable diagram. The

time is the interval from when a reference signal reaches a high

or low voltage level to when the output voltages have changed

by 0.5 V from the measured output high or low voltage. The

decay time, t_DECAY, is dependent on the capacitive load, C_L, and

TO

OUTPUT

+1.5V

50pF

I

OH

Figure 26. Equivalent Device Loading for AC Measure-

ments (Including All Fixtures)

REV. 0

–27–

ADSP-2184L

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

10000

1000

100

10

T_AMB

T_CASE

PD

θ_CA

θ_JA

=

T_CASE– (PD × θ_CA)

Case Temperature in °C

Power Dissipation in W

Thermal Resistance (Case-to-Ambient)

Thermal Resistance (Junction-to-Ambient)

Thermal Resistance (Junction-to-Case)

3.6V

3.3V

θ_JC

Package

␪

CA

JA

JC

LQFP

50°C/W

2°C/W

48°C/W

1

0

25

55

85

TEMPERATURE – ؇C

Figure 27. Rev 2.0 Power-Down Graph

REV. 0

–28–

ADSP-2184L

100-Lead LQFP Package Pinout

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

1

2

D15

D14

D13

D12

GND

D11

D10

D9

A4/IAD3

A5/IAD4

GND

PIN 1

IDENTIFIER

3

4

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

5

6

7

8

9

VDD

GND

D8

10

11

12

13

14

15

16

17

18

19

D7/IWR

ADSP-2184L

TOP VIEW

D6/IRD

CLKIN

D5/IAL

XTAL

(Not to Scale)

D4/IS

VDD

GND

CLKOUT

GND

VDD

D3/IACK

VDD

D2/IAD15

D1/IAD14

WR

RD 20

21

22

23

24

25

55 D0/IAD13

BMS

DMS

PMS

IOMS

CMS

BG

54

53

52

51

EBG

BR

EBR

REV. 0

–29–

ADSP-2184L

The ADSP-2184L package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when

Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in

brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

LQFP Pin Configurations

LQFP

Number

Name

LQFP

Number

Name

LQFP

Number

Name

LQFP

Number

Name

1

2

3

4

5

6

7

8

A4/IAD3

A5/IAD4

GND

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

IRQE + PF4

IRQL0 + PF5

GND

IRQL1 + PF6

IRQ2 + PF7

DT0

TFS0

RFS0

DR0

SCLK0

VDD

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

EBR

BR

EBG

BG

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

D16

D17

D18

D19

GND

D20

D21

D22

D23

FL2

FL1

FL0

PF3

PF2 [Mode C]

VDD

PWD

GND

PF1 [Mode B]

PF0 [Mode A]

BGH

PWDACK

A0

A1/IAD0

A2/IAD1

A3/IAD2

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

CLKIN

XTAL

VDD

CLKOUT

GND

VDD

WR

RD

BMS

DMS

PMS

IOMS

CMS

D0/IAD13

D1/IAD14

D2/IAD15

D3/IACK

VDD

GND

D4/IS

D5/IAL

D6/IRD

D7/IWR

D8

GND

VDD

D9

D10

D11

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

DT1

TFS1

RFS1

DR1

GND

SCLK1

ERESET

RESET

EMS

EE

GND

D12

D13

D14

D15

ECLK

ELOUT

ELIN

EINT

REV. 0

–30–

ADSP-2184L

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

100-Lead Metric Thin Plastic Quad Flatpack (LQFP)

(ST-100)

0.640 (16.25)

TYP SQ

0.630 (16.00)

0.620 (15.75)

0.553 (14.05)

0.551 (14.00)

0.549 (13.95)

0.063 (1.60) MAX

0.472 (12.00) BSC

0.030 (0.75)

0.024 (0.60) TYP

0.020 (0.50)

100

1

76

75

12°

TYP

SEATING

PLANE

TOP VIEW

(PINS DOWN)

0.004

(0.102)

MAX LEAD

COPLANARITY

25

26

51

50

6° ± 4°

0° – 7°

0.020 (0.50)

BSC

0.007 (0.177)

0.011 (0.27)

0.005 (0.127) TYP

0.003 (0.077)

0.009 (0.22) TYP

0.007 (0.17)

LEAD PITCH

LEAD WIDTH

NOTE:

THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)

0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE

LATERAL DIRECTION.

CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED

ORDERING GUIDE

Instruction

Ambient

Temperature

Range

Rate

(MHz)

Package

Description

Package

Option*

Part Number

ADSP-2184LBST-160

–40°C to +85°C

40

100-Lead LQFP

ST-100

*ST = Plastic Thin Quad Flatpack (LQFP).

REV. 0

–31–


型号：	ADSP-2184LBST-160
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 微控制器和处理器外围集成电路数字信号处理器装置电脑
文件：	总31页 (文件大小：218K)
中文：	中文翻译
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ADSP-2184LBST-160 [ADI]

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