ADSP-21992YST_技术文档

PRELIMINARY TECHNICAL DATA

a

Mixed Signal DSP Controller With CAN

ADSP-21992

8-Channel, 20 MSPS, 14-bit Analog to Digital Converter

System

Preliminary Technical Data

MIXED SIGNAL DSP CONTROLLER FEATURES

ADSP-219x, 16-bit, Fixed Point DSP Core with up to 160

MIPS sustained performance

48K Words of On chip RAM, Configured as 32K Words

On chip 24-bit Program RAM and 16K Words On chip

16-bit Data RAM

Three Phase 16-bit Center Based PWM Generation Unit

with 12.5 ns resolution

Dedicated 32-bit Encoder Interface Unit with

Companion Encoder Event Timer

External Memory Interface

Dual 16-bit Auxiliary PWM Outputs

16 General Purpose Flag I/O Pins

Three Programmable 32-bit Interval Timers

SPI Communications Port with Master or Slave

Operation

Synchronous Serial Communications Port (SPORT)

Capable of Software UART Emulation

Controller Area Network (CAN) Module Fully Compliant

with V2.0B Standard

Dedicated Memory DMA Controller for Data/Instruction

Transfer between Internal/External Memory

Programmable PLL and Flexible Clock Generation

Circuitry Enables Full speed Operation from Low

speed Input Clocks

IEEE JTAG Standard 1149.1 Test Access Port Supports

On chip Emulation and System Debugging

FUNCTIONAL BLOCK DIAGRAM

CLOCK

GENERATOR / PLL

16K X 16

DMRAM

(BLOCK 1)

4K X 24

PMROM

(BLOCK 2)

160 MHZ

ADSP-219X

DSP

32K X 24

PM RAM

(BLOCK 0)

JTAG

TEST &

EMULATION

ADDRESS

EXTERNAL

MEMORY

INTERFACE

(EMI)

DATA

I/O

BUS

PM ADDRESS/DATA

CONTROL

DM ADDRESS/DATA

I/O REGISTERS

CONTROLLER

AREA

NETWORK

(CAN)

SPI

SPORT

MEMORY DMA

CONTROLLER

TIMER 0

TIMER 1

TIMER 2

INTERRUPT

CONTROLLER

(ICNTL)

PWM

GENERATION

UNIT

ENCODER

INTERFACE

UNIT

(AND EET)

AUXILIARY

PWM

UNIT

PIPELINE

FLASH ADC

ADC

CONTROL

WATCHDOG

TIMER

FLAG

I/O

VREF

POR

REV. PrA

This information applies to a product under development. Its characteristics and specifi- One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

cations are subject to change without notice. Analog Devices assumes no obligation Tel:781/329-4700 www.analog.com

regarding future manufacturing unless otherwise agreed to in writing. Fax:781/326-8703 ©Analog Devices,Inc., 2002

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

August 2002

Integrated Watchdog Timer

Fabricated in a high speed, low power, CMOS process, the

ADSP-21992 operates with a 6.25 ns instruction cycle time

(160 MIPS). All instructions, except two multiword

instructions, execute in a single DSP cycle.

Dedicated Peripheral Interrupt Controller with Software

Priority Control

Multiple Boot Modes

Precision 1.0V Voltage Reference

Integrated Power-On-Reset (POR) Generator

Flexible Power Management with Selectable Powerdown

and Idle Modes

The ADSP-21992’s flexible architecture and comprehen-

sive instruction set support multiple operations in parallel.

For example, in one processor cycle, the ADSP-21992 can:

2.5V Internal Operation with 3.3V I/O

Operating Temperature Range of –40ºC to +115ºC

176 pin LQFP package

• Generate an address for the next instruction fetch

• Fetch the next instruction

• Perform one or two data moves

TARGET APPLICATIONS

Industrial Motor Drives

• Update one or two data address pointers

• Perform a computational operation

Un-Interruptible Power Supplies

Optical Networking Control

Data Acquisition Systems

Test and Measurement Systems

Portable Instrumentation

These operations take place while the processor

continues to:

• Receive and transmit data through the serial port

• Receive or transmit data over the SPI port

GENERAL NOTE

• Access external memory through the external memory

This data sheet provides preliminary information for the

ADSP-21992 Mixed Signal Digital Signal Processor.

interface

• Decrement the timers

• Operate the embedded control peripherals (ADC, PWM,

GENERAL DESCRIPTION

The ADSP-21992 is a mixed signal DSP controller based

on the ADSP-219x DSP Core, suitable for a variety of high

performance Industrial Motor Control and Signal Process-

ing applications that require the combination of a high

performance DSP and the mixed signal integration of

embedded control peripherals such as analog to digital con-

version with communications interfaces such as CAN.

EIU, etc.)

DSP Core Architecture

• 6.25 ns instruction cycle time (internal), for up to 160

MIPS sustained performance

• ADSP-218x family code compatible with the same easy

to use algebraic syntax

• Single cycle instruction execution

The ADSP-21992 integrates the 160 MIPS, fixed point

ADSP-219x family base architecture with a serial port, an

SPI compatible port, a DMA controller, three programma-

ble timers, general purpose Programmable Flag pins,

extensive interrupt capabilities, on chip program and data

memory spaces, and a complete set of embedded control

peripherals that permits fast motor control and signal pro-

cessing in a highly integrated environment.

• Up to 1 Mwords of addressable memory space with

twenty four bits of addressing width

• Dual purpose program memory for both instruction and

data storage

• Fully transparent Instruction Cache allows dual operand

fetches in every instruction cycle

• Unified memory space permits flexible address genera-

tion, using two independent DAG units

The ADSP-21992 architecture is code compatible with

previousADSP-217xbasedADMCxxxproducts. Although

the architectures are compatible, the ADSP-21992, with

ADSP-219x architecture, has a number of enhancements

over earlier architectures. The enhancements to computa-

tional units, data address generators, and program

• Independent ALU, Multiplier/Accumulator, and barrel

Shifter computational units with dual 40-bit

accumulators

• Single cycle context switch between two sets of computa-

sequencer make the ADSP-21992 more flexible and easier

to program than the previous ADSP-21xx embedded DSPs.

tional and DAG registers

• Parallel execution of computation and memory

instructions

Indirect addressing options provide addressing flexibility—

premodify with no update, pre- and post-modify by an

immediate 8-bit, two’s complement value and base address

registers for easier implementation of circular buffering.

• Pipelined architecture supports efficient code execution

at speeds up to 160 MIPS

• Register file computations with all non-conditional,

The ADSP-21992 integrates 48K words of on chip memory

configured as 32K words (24-bit) of program RAM, and

16K words (16-bit) of data RAM.

non-parallel computational instructions

• Powerful Program Sequencer provides zero overhead

looping and conditional instruction execution

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

2

REV. PrA

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

INTERNAL SRAM

INTERRUPT CONTROLLER/

TIMERS/FLAGS

ADSP-219X

DSP CORE

JTAG

TWO INDEPENDENT BLOCKS

TEST &

EMULATION

CACHE

64 X 24-BIT

ADDRESS

DATA

DAG1

4 X 4 X 16

DAG2

4 X 4 X 16

PROGRAM

SEQUENCER

EXTERNAL PORT

PM ADDRESS BUS

ADDR BUS

MUX

DMA

ADDRESS

DMA

DATA

DM ADDRESS BUS

EXTERNAL MEMORY

INTERFACE

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

DATA BUS

MUX

AHB CORE

INTERFACE

DATA

REGISTER

FILE

INPUT

REGISTERS

EMBEDDED

CONTROL

PERIPHERALS AND

COMMUNICATIONS

PORTS

I/O REGISTERS

(MEMORY MAPPED)

RESULT

REGISTERS

DMA

CONTROLLER

CONTROL

STATUS

BUFFERS

BARREL

SHIFTER

16 X 16-BIT

MULT

ALU

I/O PROCESSOR

Figure 1. ADSP-21992 DSP Block Diagram

• Architectural enhancements for compiled C code

efficiency

The block diagram Figure 1 shows the architecture of the

embedded ADSP-219x core. It contains three independent

computational units: the ALU, the multiplier/accumulator

(MAC), and the shifter. The computational units process

16-bit data from the register file and have provisions to

support multiprecision computations. The ALU performs

a standard set of arithmetic and logic operations; division

primitives are also supported. The MAC performs single

cycle multiply, multiply/add, and multiply/subtract opera-

tions. The MAC has two 40-bit accumulators, which help

with overflow. The shifter performs logical and arithmetic

shifts,normalization,denormalization,andderiveexponent

operations. The shifter can be used to efficiently implement

numeric format control, including multiword and block

floating point representations.

• Architecture enhancements beyond ADSP-218x family

are supported with instruction set extensions for added

registers, ports, and peripherals.

The clock generator module of the ADSP-21992 includes

ClockControllogic that allowsthe user to select and change

themainclockfrequency. Themodulegeneratestwooutput

clocks; the DSP core clock, CCLK, and the peripheral

clock, HCLK. CCLK can sustain clock values of up to 160

MHz, while HCLK can be equal to CCLK or CCLK/2 for

values up to a maximum 80MHz peripheral clock.

The ADSP-21992 instruction set provides flexible data

moves and multifunction (one or two data moves with a

computation) instructions. Every single word instruction

can be executed in a single processor cycle. The

ADSP-21992 assembly language uses an algebraic syntax

for ease of coding and readability. A comprehensive set of

development tools supports program development.

Register usage rules influence placement of input and

resultswithinthecomputationalunits. Formostoperations,

the computational units’ data registers act as a data register

file, permitting any input or result register to provide input

to any unit for a computation. For feedback operations, the

computational units let the output (result) of any unit be

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

3

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

August 2002

input to any unit on the next cycle. For conditional or mul-

tifunction instructions, there are restrictions on which data

registers may provide inputs or receive results from each

computational unit. For more information, see the

ADSP-219x DSP Instruction Set Reference.

memory boot ROM (that is reserved by ADI for boot load

routines). The memory map of the ADSP-21992 is illus-

trated in Figure 2.

As shown in Figure 2, the twointernalmemoryRAM blocks

reside in memory page 0. The entire DSP memory map

consists of 256 pages (pages 0 to 255), and each page is 64

kWords long. External memory space consists of four

memory banks (banks 0-3) and supports a wide variety of

memory devices. Each bank is selectable using unique

memoryselectlines(MS3-MS0)andhasconfigurablepage

boundaries,waitstates,andwaitstatemodes.The4Kwords

of on chip boot ROM populates the top of page 255, while

the remaining 254 pages are addressable off chip. I/O

memory pages differ from external memory in that they are

1K word long, and the external I/O pages have their own

select pin (IOMS). Pages 0-31 of I/O memory space reside

on chip and contain the configuration registers for the

peripherals. Both the ADSP_219x core and DMA capable

peripherals can access the DSP’s entire memory map.

A powerful program sequencer controls the flow of instruc-

tion execution. The sequencer supports conditional jumps,

subroutine calls, and low interrupt overhead. With internal

loop counters and loop stacks, the ADSP-21992 executes

looped code with zero overhead; no explicit jump instruc-

tions are required to maintain loops.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

16-bit address pointers. Whenever the pointer is used to

access data (indirect addressing), it is pre- or post-modified

bythevalueofoneoffourpossiblemodifyregisters.Alength

value and base address may be associated with each pointer

to implement automatic modulo addressing for circular

buffers.PageregistersintheDAGsallowcircularaddressing

within 64K word boundaries of each of the 256 memory

pages, but these buffers may not cross page boundaries.

Secondary registers duplicatealltheprimaryregistersin the

DAGs; switching between primary and secondary registers

provides a fast context switch.

0x000000

BLOCK 0: 32K X 24-BIT RAM

PAGE 0 (64K) ON-CHIP

0x00 7FFF

(0 WAIT STATE)

0x00 8000

BLOCK 1: 16K X 16-BIT RAM

RESERVED (16K)

0x00 BFFF

0x00 C000

Efficient data transfer in the core is achieved with the use of

internal buses:

0x00 FFFF

0x01 0000

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Direct Memory Access Address Bus

• Direct Memory Access Data Bus

PAGES 1 TO 63

BANK 0 (OFF-CHIP)

EXTERNAL MEMORY

(4M - 64K)

MS0

0x40 0000

0x80 0000

EXTERNAL MEMORY

PAGES 64 TO 127

BANK 1 (OFF-CHIP)

MS1

MS2

MS3

PAGES 128 TO 191

BANK 2 (OFF-CHIP)

0xC0 0000

PAGES 192 TO 254

BANK 0 (OFF-CHIP)

EXTERNAL MEMORY

(4M - 64K)

The two address buses (PMA and DMA) share a single

external address bus, allowing memory to be expanded off

chip, and the two data buses (PMD and DMD) share a

single external data bus. Boot memory space and I/O

memory space also share the external buses.

0xFF 0000

BLOCK 2: 4K X 24-BIT

PM ROM

PAGE 255

(ON-CHIP

0xFF 0FFF

0xFF 1000

UNUSED ON-CHIP

MEMORY (60K)

0xFF FFFF

Program memory can store both instructions and data, per-

mitting the ADSP-21992 to fetch two operands in a single

cycle, one from program memory and one from data

memory. The DSP’s dual memory buses also let the

embedded ADSP-219x core fetch an operand from data

memory and the next instruction from program memory in

a single cycle.

Figure 2. ADSP-21992 DSP Core Memory Map at Reset

NOTE:Thephysicalexternalmemoryaddressesarelimited

by 20 address lines, and are determined by the external data

width and packing of the external memory space. The

Strobe signals (MS3 - 0) can be programmed to allow the

user to change starting page addresses at run time.

Memory Architecture

The ADSP-21992 provides 48K words of on chip SRAM

memory. This memory is divided into two blocks; a 32K x

24-bit (block 0) and a 16K x 16-bit (block 1). In addition,

the ADSP-21992 provides a 4k x 24-bit block of program

Internal (On chip) Memory

The ADSP-21992’s unified program and data memory

space consists of 16M locations that are accessible through

two 24-bit address buses, the PMA and DMA buses. The

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

4

REV. PrA

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

External Memory Space

DSP uses slightly different mechanisms to generate a 24-bit

address for each bus. The DSP has three functions that

support access to the full memory map.

External memory space consists of four memory banks.

These banks can contain a configurable number of 64 k

Word pages. At reset, the page boundaries for external

memory have Bank0 containing pages 1 to 63, Bank1 con-

tainingpages64to 127, Bank2 containingpages 128to 191,

and Bank3 containing pages 192 to 254. The MS3-MS0

memory bank pins select Banks 3-0, respectively. Both the

ADSP-219x core and DMA capable peripherals can access

the DSP’s external memory space.

• TheDAGsgenerate24-bitaddressesfordatafetchesfrom

the entire DSP memory address range. Because DAG

index (address) registers are 16 bits wide and hold the

lower 16 bits of the address, each of the DAGs has its own

8-bit page register (DMPGx) to hold the most significant

eight address bits. Before a DAG generates an address,

the program must set the DAG’s DMPGx register to the

appropriate memory page. The DMPG1 register is also

used as a page register when accessing external memory.

The program must set DMPG1 accordingly, when

accessing data variables in external memory. A 'C'

program macro is provided for setting this register.

All accesses to external memory are managed by the

External Memory Interface Unit (EMI).

I/O Memory Space

The ADSP-21992 supports an additional external memory

called I/O memory space. The IO space consists of 256

pages, each containing 1024 addresses. This space is

designedtosupportsimpleconnectionstoperipherals(such

as data converters and external registers) or to bus interface

ASIC data registers. The first 32K addresses (IO pages 0 to

31) are reserved for on chip peripherals. The upper 224k

addresses (IO pages 32 to 255) are available for external

peripheral devices. External I/O pages have their own select

pin (IOMS). The DSP instruction set provides instructions

for accessing I/O space.

• The Program Sequencer generates the addresses for

instruction fetches. For relative addressing instructions,

theprogramsequencerbasesaddressesforrelativejumps,

calls, and loops on the 24-bit Program Counter (PC). In

direct addressing instructions (two word instructions),

the instruction provides an immediate 24-bit address

value. The PC allows linear addressing of the full 24-bit

address range.

• For indirect jumps and calls that use a 16-bit DAG

address register for part of the branch address, the

Program Sequencer relies on an 8-bit Indirect Jump page

(IJPG) register to supply the most significant eight

addressbits. Beforeacross pagejumpor call, theprogram

must set the program sequencer’s IJPG register to the

appropriate memory page.

0X00::0X000

ON-CHIP

PAGES 0 TO 31

PERIPHERALS

16-BITS

1024 WORDS/PAGE

2 PERIPHERALS/PAGE

The ADSP-21992 has 4K word of on chip ROM that holds

boot routines. The DSP starts executing instructions from

the on chip boot ROM, which starts the boot process. For

more information, see Booting Modes on page 14. The on

chip boot ROM is located on Page 255 in the DSP’s

memory space map, starting at address 0xFF0000.

0X1F::0X3FF

0X20::0X000

OFF-CHIP

PERIPHERALS

16-BITS

PAGES 32 TO 255

1024 WORDS/PAGE

External (Off Chip) Memory

0XFF::0X3FF

Each of the ADSP-21992’s off chip memory spaces has a

separate control register, so applications can configure

unique access parameters for each space. The access param-

eters include read and write wait counts, wait state

completion mode, I/O clock divide ratio, write hold time

extension, strobe polarity, and data bus width. The core

clock and peripheral clock ratios influence the external

memory access strobe widths. For more information, see

Clock Signals on page 13. The off chip memory spaces are:

Figure 3. ADSP-21992 I/O Memory Map

Boot Memory Space

Boot memory space consists of one off chip bank with 254

pages. The BMS memory bank pin selects boot memory

space. Both the ADSP-219x core and DMA capable periph-

• External memory space (MS3–0 pins)

• I/O memory space (IOMS pin)

• Boot memory space (BMS pin)

All of these off chip memory spaces are accessible through

the External Port, which can be configured for 8-bit or

16-bit data widths.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

5

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

August 2002

DMA Controller

eralscanaccesstheDSP’soffchipbootmemoryspace.After

reset, the DSP always starts executing instructions from the

on chip boot ROM.

The ADSP-21992 has a DMA controller that supports

automated data transfers with minimal overhead for the

DSP core. Cycle stealing DMA transfers can occur between

the ADSP-21992’s internal memory and any of its DMA

capable peripherals. Additionally, DMA transfers can be

accomplished between any of the DMA capable peripherals

and external devices connected to the external memory

interface. DMA capable peripherals include the SPORT

and SPI ports, and ADC Control module. Each individual

DMA capable peripheral has a dedicated DMA channel. To

describe each DMA sequence, the DMA controller uses a

set of parameters—called a DMA descriptor. When succes-

sive DMA sequences are needed, these DMA descriptors

can be linked or chained together, so the completion of one

DMA sequence auto initiates and starts the next sequence.

DMAsequencesdonotcontendforbusaccesswiththeDSP

core, instead DMAs “steal” cycles to access memory.

0x01 0000

OFF-CHIP

BOOT MEMORY

PAGES 1 TO 254

16-BITS

64K WORDS/PAGE

0xFE 0000

Figure 4. ADSP-21992 Boot Memory Map

Bus Request and Bus Grant

The ADSP-21992 can relinquish control of the data and

address buses to an external device. When the external

device requires access to the bus, it asserts the bus request

(BR) signal. The (BR) signal is arbitrated with core and

peripheral requests. External Bus requests have the lowest

priority. If no other internal request is pending, the external

bus request will be granted. Due to synchronizer and arbi-

tration delays, bus grants will be provided with a minimum

of three peripheral clock delays. The ADSP-21992 will

respond to the bus grant by:

All DMA transfers use the DMA bus shown in Figure 1 on

page 3. Because all of the peripherals use the same bus,

arbitration for DMA bus access is needed. The arbitration

for DMA bus access appears in Table 1.

Table 1. I/O Bus Arbitration Priority

DMA Bus Master

Arbitration Priority

SPORT Receive DMA

SPORT Transmit DMA

ADC Control DMA

SPI0 Receive/Transmit DMA

Memory DMA

0—Highest

1

2

3

• Three stating the data and address buses and the MS3–0,

BMS, IOMS, RD, and WR output drivers.

• Asserting the bus grant (BG) signal.

4—Lowest

The ADSP-21992 will halt program execution if the bus is

granted to an external device and an instruction fetch or

data read/write request is made to external general purpose

or peripheral memory spaces. If an instruction requires two

external memory read accesses, the bus will not be granted

between the two accesses. If an instruction requires an

externalmemoryreadandanexternalmemorywriteaccess,

the bus may be granted between the two accesses. The

external memory interface can be configured so that the

core will have exclusive use of the interface. DMA and Bus

Requests will be granted. When the external device releases

BR, the DSP releases BG and continues program execution

from the point at which it stopped.

DSP Peripherals Architecture

The ADSP-21992 contains a number of special purpose,

embedded control peripherals, which can be seen in the

Functional Block diagram on page 1. The ADSP-21992

contains a high performance, 8-channel, 14-bit ADC

system with dual channel simultaneous sampling ability

across 4 pairs of inputs. An internal precision voltage

reference is also available as part of the ADC system. In

addition, a three phase, 16-bit, center based PWM genera-

tionunitcanbeusedtoproducehighaccuracyPWMsignals

with minimal processor overhead. The ADSP-21992 also

contains a flexible incremental encoder interface unit for

positionsensorfeedback;twoadjustablefrequencyauxiliary

PWM outputs, 16 lines of digital I/O; a 16-bit watchdog

timer; three general purpose timers and an interrupt con-

troller that manages all peripheral interrupts. Finally, the

ADSP-21992containsanintegratedpower-on-reset(POR)

circuit that can be used to generate the required reset signal

for the device on power-on.

The bus request feature operates at all times, even while the

DSP is booting and RESET is active.

The ADSP-21992 asserts the BGH pin when it is ready to

start another external port access, but is held off because

the bus was previously granted. This mechanism can be

extended to define more complex arbitration protocols for

implementing more elaborate multimaster systems.

The ADSP-21992 has an external memory interface that is

shared by the DSP’s core, the DMA controller, and DMA

capable peripherals, which include the ADC, SPORT, and

SPI communication ports. The external port consists of a

16-bit data bus, a 20-bit address bus, and control signals.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

6

REV. PrA

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

The data bus is configurable to provide an 8 or 16 bit

interface to external memory. Support for word packing lets

the DSP access 16- or 24-bit words from external memory

regardless of the external data bus width.

In master mode, the DSP’s core performs the following

sequence to set up and initiate SPI transfers:

1. Enables and configures the SPI port operation (data

size, and transfer format).

The memory DMA controller lets the ADSP-21992 move

data and instructions from between memory spaces: inter-

nal-to-external, internal-to-internal, and external-to-

external. On chip peripherals can also use this controller for

DMA transfers.

2. Selects the target SPI slave with the SPISELx output

pin (reconfigured Programmable Flag pin).

3. Defines one or more DMA descriptors in Page 0 of I/O

memory space (optional in DMA mode only).

4. Enables the SPI DMA engine and specifies transfer

direction (optional in DMA mode only).

The embedded ADSP-219x core can respond to up to

seventeen interrupts at any given time: three internal (stack,

emulator kernel, and power down), two external (emulator

and reset), and twelve user defined (peripherals) interrupts.

Programmers assign each of the 32 peripheral interrupt

requests to one of the 12 user defined interrupts. These

assignments determine the priority of each peripheral for

interrupt service.

5. In non DMA mode only, reads or writes the SPI port

receive or transmit data buffer.

The SCK line generates the programmed clock pulses for

simultaneously shifting data out on MOSI and shifting

data in on MISO. In DMA mode only, transfers continue

until the SPI DMA word count transitions from 1 to 0.

In slave mode, the DSP core performs the following

sequence to set up the SPI port to receive data from a master

transmitter:

The following sections provide a functional overview of the

ADSP-21992 peripherals.

Serial Peripheral Interface (SPI) Port

1. Enables and configures the SPI slave port to match the

operation parameters set up on the master (data size

and transfer format) SPI transmitter.

The Serial Peripheral Interface (SPI) Port provides func-

tionality for a generic configurable serial port interface

based on the SPI standard, which enables the DSP to com-

municate with multiple SPI compatible devices. Key

features of the SPI port are:

2. Defines and generates a receive DMA descriptor in

Page 0 of memory space to interrupt at the end of the

data transfer (optional in DMA mode only).

• Interface to host microcontroller or serial EEPROM

3. Enables the SPI DMA engine for a receive access

(optional in DMA mode only).

• Master or slave operation (3 Wire Interface MISO,

MOSI, SCK)

4. Starts receiving the data on the appropriate SCK edges

after receiving an SPI chip select on the SPISS0 input

pin (reconfigured Programmable Flag pin)

from a master

• Data rates to 20 Mbaud (16-bit baud rate selector)

• 8 or 16-bit transfer

• Programmable clock phase & polarity

• Broadcast Mode - 1 master, multiple slaves

• DMA capability & Dedicated interrupts

• PF0 can be used as Slave Select Input Line

• PF1-PF7 can be used as external Slave Select output

In DMA mode only, reception continues until the SPI

DMA word count transitions from 1 to 0. The DSP core

could continue, by queuing up the next DMA descriptor.

A slave mode transmit operation is similar, except the DSP

core specifies the data buffer in memory space from which

to transmit data, generates and relinquishes control of the

transmit DMA descriptor, and begins filling the SPI port

data buffer. If the SPI controller is not ready on time to

transmit, it can transmit a “zero” word.

SPI is a 3 wire interface consisting of 2 data pins (MOSI

and MISO), one clock pin (SCK), and a single Slave Select

input (SPISS0) that is multiplexed with the PF0 Flag IO

line and seven Slave Select outputs (SPISEL1 to SPISEL7)

that are multiplexed with the PF1 to PF7 Flag IO lines. The

SPISS0 input is used to select the ADSP-21992 as a slave

to an external master. The SPISEL1 to SPISEL7 outputs

can be used by the ADSP-21992 (acting as a master) to

select/enable up to seven external slaves in an multi device

SPI configuration. In a multimaster or a multi device con-

figuration, all MOSI pins are tied together, all MISO pins

are tied together, and all SCK pins are tied together.

DSP Serial Port (SPORT)

The ADSP-21992 incorporates a complete synchronous

serial port (SPORT) for serial and multiprocessor commu-

nications. The SPORT supports the following features:

• Bidirectional: the SPORT has independent transmit and

receive sections.

• Double buffered: the SPORT section (both receive and

transmit) has a data register for transferring data words

to and from other parts of the processor and a register for

shifting data in or out. The double buffering provides

additional time to service the SPORT.

Duringtransfers, theSPIportsimultaneouslytransmitsand

receives by serially shifting data in and out on the serial data

line. The serial clock line synchronizes the shifting and

sampling of data on the serial data line.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

7

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

August 2002

• Clocking: the SPORT can use an external serial clock or

generate its own in a wide range of frequencies down to 0

Hz. Maximum clock value is 40 MHz for internally

generated clock.

• Error Status and Warning registers

• Transmit Priority by Identifier

• Universal Counter Module

• Readable Receive and Transmit Counters

• Word length: each SPORT section supports serial data

word lengths from three to sixteen bits that can be trans-

ferred either MSB first or LSB first.

The CAN Module is a low baud rate serial interface

intended for use in applications where baud rates are

typicallyunder1Mbit/sec. TheCANprotocolincorporates

a data CRC check, message error tracking and fault node

confinement as means to improve network reliability to the

level required for control applications.

• Framing: each SPORT section (receive and transmit) can

operate with or without frame synchronization signals for

each data word; with internally generated or externally

generated frame signals; with active high or active low

frame signals; with either of two pulse widths and frame

signal timing.

The CAN module architecture is based around a 16-entry

mailbox RAM. The mailbox is accessed sequentially by the

CAN serial interface or the host CPU. Each mailbox

consists of eight 16-bit data words. The data is divided into

fields, which includes a message identifier, a time stamp, a

byte count, up to 8 bytes of data, and several control bits.

Each node monitors the messages being passed on the

network. If the identifier in the transmitted message

matches an identifier in one of it's mailboxes, then the

module knows that the message was meant for it, passes the

data into it's appropriate mailbox, and signals the host of its

arrival with an interrupt.

• Companding in hardware: each SPORT section can

perform A law and µ law companding according to

CCITT recommendation G.711.

• Direct Memory Access with single cycle overhead: using

the built in DMA master, the SPORT can automatically

receive and/or transmit multiple memory buffers of data

with an overhead of only one DSP cycle per data word.

The on chip DSP via a linked list of memory space

resident DMA descriptor blocks can configure transfers

betweentheSPORTandmemoryspace. Thischainedlist

can be dynamically allocated and updated.

The CAN network itself is a single, differential pair line. All

nodescontinuouslymonitorthisline.Thereisnoclockwire.

Messages are passed in one of 4 standard message types or

frames. Synchronization is achieved by an elaborate sync

scheme performed in each CAN receiver. Message arbitra-

tion is accomplished 1 bit at a time. A dominant polarity is

established for the network. All nodes are allowed to start

transmitting at the same time following a frame sync pulse.

• Interrupts: each SPORT section (receive and transmit)

generates an interrupt upon completing a data word

transfer, or after transferring an entire buffer or buffers if

DMA is used.

• Multi channel capability: The SPORT can receive and

transmit data selectively from channels of a serial bit

stream that is time division multiplexed into up to 128

channels. This is especially useful for T1 interfaces or as

a network communication scheme for multiple proces-

sors. The SPORTs also support T1 and E1 carrier

systems.

As each node transmits a bit, it checks to see if the bus is the

same state that it transmitted. If it is, it continues to

transmit. If not, then another node has transmitted a

dominant bit so the first node knows it has lost the arbitra-

tion and it stops transmitting. The arbitration continues, bit

by bit until only 1 node is left transmitting.

• Each SPORT channel (TX and RX) supports a DMA

buffer of up to 8, 16-bit transfers.

The electrical characteristics of each network connection

are very stringent so the CAN interface is typically divided

into 2 parts: a controller and a transceiver. This allows a

single controller to support different drivers and CAN

networks. The ADSP-21992 CAN module represents only

the controller part of the interface. This module's network

I/O is a single transmit line and a single receive line, which

communicate to a line transceiver.

• The SPORT operates at a frequency of up to ½ the clock

frequency of the HCLK

• The SPORT is capable of UART software emulation.

Controller Area Network (CAN) Module

The ADSP-21992 contains a Controller Area Network

(CAN) Module. Key features of the CAN Module are:

• Conforms to the CAN V2.0B standard.

Analog To Digital Conversion System

• Supports both standard (11-bit) and extended (29-bit)

Identifiers

The ADSP-21992 contains a fast, high accuracy, multiple

input analog to digital conversion system with simultaneous

sampling capabilities. This A/D conversion system permits

• Supports Data Rates of up to 1Mbit/sec (and higher)

• 16 Configurable Mailboxes (All receive or transmit)

• Dedicated Acceptance Mask for each Mailbox

• Data Filtering (first 2 bytes) can be used for Acceptance

Filtering

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

8

REV. PrA

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

the fast, accurate conversion of analog signals needed in

high performance embedded systems. Key features of the

ADC system are:

• Programmable Dead Time and Switching Frequency

• Two's Complement Implementation permits smooth

transition into full ON and full OFF states

• 14-bit Pipeline (6-Stage Pipeline) Flash Analog to Digital

Converter.

• Possibility to synchronize the PWM Generation to an

External Synchronization

• 8 Dedicated Analog Inputs.

• Special Provisions for BDCM Operation (Crossover and

Output Enable Functions)

• Dual Channel Simultaneous Sampling Capability.

• Wide Variety of Special Switched Reluctance (SR)

• Programmable ADC Clock Rate to Maximum of 20

Operating Modes

MSPS.

• Output Polarity and Clock Gating Control

• FirstChannelADCDataValidapproximately400nsafter

CONVST (at 20 MSPS).

• Dedicated Asynchronous PWM Shutdown Signal

• Multiple shut down sources, independently for each unit

• All 8 Inputs Converted in approximately 800 ns (at 20

MSPS).

The ADSP-21992 integrates a flexible and programmable,

three phase PWM waveform generator that can be pro-

grammed to generate the required switching patterns to

drive a three phase voltage source inverter for ac induction

(ACIM) or permanent magnet synchronous (PMSM)

motor control. In addition, the PWM block contains special

functions that considerably simplify the generation of the

required PWM switching patterns for control of the elec-

tronically commutated motor (ECM) or brushless dcmotor

(BDCM). Tying a dedicated pin, PWMSR, to GND,

enables a special mode, for switched reluctance motors

(SRM).

• 2.0 V peak to peak Input Voltage Range.

• Multiple Convert Start Sources.

• Internal or External Voltage Reference.

• Out of Range Detection.

• DMA capable transfers from ADC to memory.

The ADC system is based on a pipeline flash converter core,

and contains dual input Sample and Hold amplifiers so that

simultaneous sampling of two input signals is supported.

The ADC system provides an analog input voltage range of

2.0Vpp and provides 14-bit performance with a clock rate

of up to 20 MHz. The ADC system can be programmed to

operate at a clock rate that is programmable from HCLK⁄4

to HCLK⁄30, to a maximum of 20 MHz.

The six PWM output signals consist of three high side drive

pins (AH, BH and CH) and three low side drive signals pins

(AL, BL and CL). The polarity of the generated PWM

signals may be set via hardware by the PWMPOL input pin,

so that either active HI or active LO PWM patterns can be

produced.

The ADC input structure supports 8 independent analog

inputs; 4 of which are multiplexed into one sample and hold

amplifier (A_SHA) and 4 of which are multiplexed into the

other sample and hold amplifier (B_SHA).

The switching frequency of the generated PWM patterns is

programmable using the 16-bit PWMTM register. The

PWM generator is capable of operating in two distinct

modes, single update mode or double update mode. In

single update mode the duty cycle values are programmable

only once per PWM period, so that the resultant PWM

patterns are symmetrical about the midpoint of the PWM

period. In the double update mode, a second updating of

the PWM registers is implemented at the midpoint of the

PWM period. In this mode, it is possible to produce asym-

metrical PWM patterns. that produce lower harmonic

distortion in three phase PWM inverters.

At the 20 MHz HCLK rate, the first data value is valid

approximately 400 ns after the Convert Start command. All

8 channels are converted in approximately 800 ns.

The core of theADSP-21992 provides 14-bit data such that

the stored data values in the ADC data registers are 14-bits

wide.

Voltage Reference

The ADSP-21992 contains an onboard band gap reference

that can be used to provide a precise 1.0V output for use by

the A/D system and externally on the VREF pin for biasing

and level shifting functions. Additionally, the ADSP-21992

may be configured to operate with an external reference

applied to the VREF pin, if required.

Auxiliary PWM Generation Unit

Key features of the Auxiliary PWM Generation Unit are:

• 16-bit, programmable frequency, programmable duty

cycle PWM outputs

PWM Generation Unit

Key features of the three phase PWM Generation Unit are:

• Independent or offset operating modes

• 16-bit, center based PWM Generation Unit

• Double buffered control of duty cycle and period registers

• Programmable PWM Pulsewidth, with resolutions to

12.5 ns (at 80 MHz)

• Single/Double Update Modes

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

9

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

August 2002

• Separate auxiliary PWM synchronization signal and asso-

ciated interrupt (can be used to trigger ADC Convert

Start).

and EIS pins. These events may be programmed to be either

rising edge only (latch event) or rising edge if the encoder is

moving in the forward direction and falling edge if the

encoder is moving in the reverse direction (software latched

north marker functionality).

• Separate Auxiliary PWM shutdown signal (AUXTRIP).

The ADSP-21992 integrates a two channel, 16-bit,

auxiliary PWM output unit that can be programmed with

variable frequency, variable duty cycle values and may

operate in two different modes, independent mode or offset

mode. In independent mode, the two auxiliary PWM gen-

erators are completely independent and separate switching

frequencies and duty cycles may be programmed for each

auxiliary PWM output. In offset mode the switching

frequency of the two signals on the AUX0 and AUX1 pins

is identical. Bit 4 of the AUXCTRL register places the

auxiliary PWM channel pair in independent or offset mode

The encoder interface unit incorporates programmable

noisefilteringonthefourencoderinputstopreventspurious

noise pulses from adversely affecting the operation of the

quadrature counter. The encoder interface unit operates at

a clock frequency equal to the HCLK rate. The encoder

interface unit operates correctly with encoder signals at fre-

quencies ofup to 13.25 MHz, corresponding to a maximum

quadrature frequency of 53 MHz (assuming an ideal

quadrature relationship between the input EIA and EIB

signals).

The EIU may be programmed to use the north marker on

EIZ to reset the quadrature encoder in hardware, if

required.

The Auxiliary PWM Generation unit provides two chip

output pins, AUX0 and AUX1 (on which the switching

signals appear) and one chip input pin, AUXTRIP, which

can be used to shutdown the switching signals, for example

in a fault condition.

Alternatively, the north marker can be ignored, and the

encoder quadrature counter is reset according to the

contents of a maximum count register, EIUMAXCNT.

There is also a “single north marker” mode available in

which the encoder quadrature counter is reset only on the

first north marker pulse.

Encoder Interface Unit

The ADSP-21992 incorporates a powerful encoder

interface block to incremental shaft encoders that are often

used for position feedback in high performance motion

control systems.

The encoder interface unit can also be made to implement

some error checking functions. If an encoder count error is

detected (due to a disconnected encoder line, for example),

astatusbitintheEIUSTATregisterisset, andanEIUcount

error interrupt is generated.

• Quadrature rates to 53 MHz (at 80 MHz peripheral

clock).

• Programmable filtering of all encoder input signals

• 32-bit encoder counter

The encoder interface unit of the ADSP-21992 contains a

16-bit loop timer that consists of a timer register, period

register and scale register so that it can be programmed to

time out and reload at appropriate intervals. When this loop

timer times out, an EIU loop timer timeout interrupt is

generated. This interrupt could be used to control the

timing of speed and position control loops in high perfor-

mance drives.

• Variety of hardware and software reset modes

• Two registration inputs to latch EIU count value with

corresponding registration interrupt

• Status of A/B signals latched with reading of EIU count

value.

• Alternative frequency & direction mode

• Single north marker mode

Theencoderinterfaceunitalsoincludesahighperformance

encoder event timer (EET) block that permits the accurate

timing of successive events of the encoder inputs. The EET

can be programmed to time the duration between up to 255

encoder pulses and can be used to enhance velocity estima-

tion, particularly at low speeds of rotation.

• Count error monitor function with dedicated error

interrupt

• Dedicated 16-bit loop timer with dedicated interrupt

• Companion encoder event (1⁄T) timer unit.

The encoder interface unit (EIU) includes a 32-bit quadra-

ture up/down counter, programmable input noise filtering

of the encoder input signals and the zero markers, and has

four dedicated chip pins. The quadrature encoder signals

are applied at the EIA and EIB pins. Alternatively, a

frequency and direction set of inputs may be applied to the

EIA and EIB pins. In addition, two north marker/strobe

inputs are provided on pins EIZ and EIS. These inputs may

be used to latch the contents of the encoder quadrature

counter into dedicated registers, EIZLATCH and

Flag I/O (FIO) Peripheral Unit

The FIO module is a generic parallel I/O interface that

supportssixteenbidirectionalmultifunctionflagsorgeneral

purpose digital I/O signals (PF15-PF0).

All sixteen FLAG bits can be individually configured as an

input or output based on the content of the direction (DIR)

register, and can also be used as an interrupt source for one

of two FIO interrupts. When configured as input, the input

EISLATCH,ontheoccurrenceofexternaleventsattheEIZ

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

10

REV. PrA

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

signal can be programmed to set the FLAG on either a level

(level sensitive input/interrupt) or an edge (edge sensitive

input/interrupt).

peripheral interrupts. The Peripheral Interrupt Controller

is used to assign the various peripheral interrupts to the 12

user assignable interrupts of the DSP core.

The FIO module can also be used to generate an asynchro-

nous unregistered wake up signal FIO_WAKEUP for DSP

core wake up after power down.

Table 2. Interrupt Priorities/Addresses

IMASK/

Interrupt

IRPTL

Vector Address

TheFIOLines,PF7-PF1canalsobeconfiguredasexternal

slaveselectoutputsfortheSPICommunicationsPort, while

PF0 can be configured to act as a Slave select input.

Emulator (NMI)

—Highest Priority

Reset (NMI)

Power Down (NMI)

Loop and PC Stack

Emulation Kernel

User Assigned Interrupt

(USR0)

User Assigned Interrupt

(USR1)

User Assigned Interrupt

(USR2)

User Assigned Interrupt

(USR3)

User Assigned Interrupt

(USR4)

User Assigned Interrupt

(USR5)

User Assigned Interrupt

(USR6)

NA

0

1

2

3

4

0x00 0000

0x00 0020

0x00 0040

0x00 0060

0x00 0080

TheFIOLinescanbeconfiguredtoactasaPWMshutdown

source for the three phase PWM generation unit of the

ADSP-21992.

Watchdog Timer

The ADSP-21992 integrates a watchdog timer that can be

used as a protection mechanism against unintentional

software events. It can be used to cause a complete DSP and

peripheral reset in such an event. The watchdog timer

consists of a 16-bit timer that is clocked at the external clock

rate (CLKIN or crystal input frequency).

5

0x00 00A0

0x00 00C0

0x00 00E0

0x00 0100

0x00 0120

0x00 0140

0x00 0160

0x00 0180

0x00 01A0

0x00 01C0

0x00 01E0

6

7

In order to prevent an unwanted timeout or reset, it is

necessary to periodically write to the watchdog timer

register. During abnormal system operation, the watchdog

count will eventually decrement to 0 and a watchdog

timeout will occur. In the system, the watchdog timeout will

cause a full reset of the DSP core and peripherals.

8

9

10

11

12

13

14

15

General Purpose Timers

User Assigned Interrupt

(USR7)

User Assigned Interrupt

(USR8)

User Assigned Interrupt

(USR9)

User Assigned Interrupt

(USR10)

The ADSP-21992 contains a general purpose timer unit

that contains three identical 32-bit timers. The three pro-

grammable interval timers (Timer0, Timer1 and Timer2)

generate periodic interrupts. Each timer can be indepen-

dently set to operate in one of three modes:

• Pulse Waveform Generation (PWM_OUT) mode

• Pulse Width Count/Capture (WDTH_CAP) mode

• External Event Watchdog (EXT_CLK) mode

User Assigned Interrupt

(USR11)

Each Timer has one bidirectional chip pin, TMR2-TMR0.

For each timer, the associated pin is configured as an output

pin in PWM_OUT Mode and as input pin in WDTH_CAP

and EXT_CLK Modes.

—Lowest Priority

There is no assigned priority for the peripheral interrupts

after reset. To assign the peripheral interrupts a different

priority, applications write the new priority to their corre-

sponding control bits (determined by their ID) in the

Interrupt Priority Control register.

Interrupts

The interrupt controller lets the DSP respond to 17 inter-

rupts with minimum overhead. The DSP core implements

an interrupt priority scheme as shown in Table 2. Applica-

tions can use the unassigned slots for software and

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially.

Interrupts can be masked or unmasked with the IMASK

register. Individual interrupt requests are logically ANDed

with the bits in IMASK; the highest priority unmasked

interrupt is then selected. The emulation, power down, and

reset interrupts are nonmaskable with the IMASK register,

but software can use the DIS INT instruction to mask the

power down interrupt.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

11

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

August 2002

The Interrupt Control (ICNTL) register controls interrupt

nesting and enables or disables interrupts globally.

This scheme permits the user to assign the number of

specific interrupts that are unique to their application to the

interruptschemeoftheADSP-219xcore. Theusercanthen

use the existing interrupt priority control scheme to dynam-

ically control the priorities of the 12 core interrupts.

The IRPTL register is used to force and clear interrupts.

On chip stacks preserve the processor status and are auto-

maticallymaintained during interrupt handling. To support

interrupt, loop, and subroutine nesting, the PC stack is

33 levels deep, the loop stack is eight levels deep, and the

status stack is 16 levels deep. To prevent stack overflow, the

PC stack can generate a stack level interrupt if the PC stack

falls below three locations full or rises above 28

locations full.

Low Power Operation

The ADSP-21992 has four low power options that signifi-

cantly reduce the power dissipation when the device

operates under standby conditions. To enter any of these

modes, the DSP executes an IDLE instruction. The

ADSP-21992 uses the configuration of the PD, STCK, and

STALL bits in the PLLCTL register to select between the

lowpowermodesastheDSPexecutestheIDLEinstruction.

Depending on the mode, an IDLE shuts off clocks to

different parts of the DSP in the different modes. The low

power modes are:

The following instructions globally enable or disable

interrupt servicing, regardless of the state of IMASK.

ENA INT;

DIS INT;

At reset, interrupt servicing is disabled.

• Idle

For quick servicing of interrupts, a secondary set of DAG

and computational registers exist. Switching between the

primary and secondary registers lets programs quickly

service interrupts, while preserving the state of the DSP.

• Power Down Core

• Power Down Core/Peripherals

• Power Down All

Peripheral Interrupt Controller

Idle Mode

The Peripheral Interrupt Controller is a dedicated periph-

eral unit of the ADSP-21992 (accessed via IO mapped

registers). The function of the peripheral interrupt control-

ler is to manage the connection of up to 32 peripheral

interrupt requests to the DSP core.

When the ADSP-21992 is in Idle mode, the DSP core stops

executing instructions, retains the contents of the instruc-

tion pipeline, and waits for an interrupt. The core clock and

peripheral clock continue running.

To enter Idle mode, the DSP can execute the IDLE instruc-

tion anywhere in code. To exit Idle mode, the DSP responds

to an interrupt and (after two cycles of latency) resumes

executing instructions.

For each peripheral interrupt source, there is a unique 4-bit

code that allows the user to assign the particular peripheral

interrupt to any one of the 12 user assignable interrupts of

the embedded ADSP-219x core. Therefore, the peripheral

interrupt controller of the ADSP-21992 contains 8, 16-bit

Interrupt Priority Registers (Interrupt Priority Register 0

(IPR0) to Interrupt Priority Register 7 (IPR7)).

Power down Core Mode

When the ADSP-21992 is in Power Down Core mode, the

DSP core clock is off, but the DSP retains the contents of

the pipeline and keeps the PLL running. The peripheral bus

keeps running, letting the peripherals receive data.

Each Interrupt Priority Registercontains a four 4-bit codes;

one specifically assigned to each peripheral interrupt. The

user may write a value between 0x0 and 0xB to each 4-bit

location in order to effectively connect the particular

interrupt source to the corresponding user assignable

interrupt of the ADSP-219x core.

To exit Power Down Core mode, the DSP responds to an

interruptand(aftertwocyclesoflatency)resumesexecuting

instructions.

Power Down Core/Peripherals Mode

Writing a value of 0x0 connects the peripheral interrupt to

the USR0 user assignable interrupt of the ADSP-219x core

while writing a value of 0xB connects the peripheral

interrupt to the USR11 user assignable interrupt. The core

interrupt USR0 is the highest priority user interrupt, while

USR11 is the lowest priority. Writing a value between 0xC

and 0xF effectively disables the peripheral interrupt by not

connecting it to any ADSP-219x core interrupt input. The

user may assign more than one peripheral interrupt to any

given ADSP-219x core interrupt. In that case, the onus is

on the user software in the interrupt vector table to

determine the exact interrupt source through reading status

bits etc.

When the ADSP-21992 is in Power Down Core/Peripherals

mode, the DSP core clock and peripheral bus clock are off,

but the DSP keeps the PLL running. The DSP does not

retain the contents of the instruction pipeline.The periph-

eral bus is stopped, so the peripherals cannot receive data.

To exit Power Down Core/Peripherals mode, the DSP

responds to an interrupt and (after five to six cycles of

latency) resumes executing instructions.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

12

REV. PrA

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Power Down All Mode

core clock is 160 MHz, and the maximum peripheral clock

is 80 MHz—the combination of the input clock and

core/peripheral clock ratios may not exceed these limits.

When the ADSP-21992 is in Power Down All mode, the

DSP core clock, the peripheral clock, and the PLL are all

stopped. The DSP does not retain the contents of the

instruction pipeline. The peripheral bus is stopped, so the

peripherals cannot receive data.

To exit Power Down Core/Peripherals mode, the DSP

responds to an interrupt and (after 500 cycles to re-stabilize

the PLL) resumes executing instructions.

50MHZ

XTAL

CLKIN

Clock Signals

ADSP-2199X

The ADSP-21992 can be clocked by a crystal oscillator or

a buffered, shaped clock derived from an external clock

oscillator. If a crystal oscillator is used, the crystal should be

connected across the CLKIN and XTAL pins, with two

capacitors connected as shown in Figure 5. Capacitor

values are dependenton crystaltype and should be specified

by the crystal manufacturer. A parallel resonant, fundamen-

tal frequency, microprocessor grade crystal should be used

for this configuration.

Figure 5. External Crystal Connections

Reset and Power On Reset (POR)

The RESET pin initiates a complete hardware reset of the

ADSP-21992 when pulled low. The RESET signal must be

asserted when the device is powered up to assure proper

initialization. The ADSP-21992 contains an integrated

power on reset (POR) circuit that provides an output reset

signal, POR, from the ADSP-21992 on power up and if the

power supply voltage falls below the threshold level. The

ADSP-21992 may be reset from an external source using

the RESET signal or alternatively the internal power on

reset circuit may be used by connecting the POR pin to the

RESET pin. During power up the RESET line must be

activated for long enough to allow the DSP core's internal

clock to stabilize. The power up sequence is defined as the

total time required for the crystal oscillator to stabilize after

a valid VDD is applied to the processor and for the internal

phase locked loop (PLL) to lock onto the specific crystal

frequency. A minimum of 2000 cycles will ensure that the

PLL has locked (this does not include the crystal oscillator

start up time).

If a buffered, shaped clock is used, this external clock

connects to the DSP’s CLKIN pin. CLKIN input cannot

be halted, changed, or operated below the specified

frequency during normal operation. This clock signal

should be a TTL compatible signal. When an external clock

is used, the XTAL input must be left unconnected.

The DSP provides a user programmable 1

؋

to 32

؋

multi-

plication of the input clock, including some fractional

values, to support 128 external to internal (DSP core) clock

ratios. The BYPASS pin, and MSEL6–0 and DF bits, in the

PLL configuration register, decide the PLL multiplication

factor at reset. At runtime, the multiplication factor can be

controlled in software. To support input clocks greater that

100 MHz, the PLL uses an additional bit (DF). If the input

clock is greater than 100 MHz, DF must be set. If the input

clock is less than 100 MHz, DF must be cleared. For clock

multiplier settings, see the ADSP-21992 DSP Hardware

Reference Manual.

The peripheral clock is supplied to the CLKOUT pin.

The RESET input contains some hysteresis. If using an RC

circuit to generate your RESET signal, the circuit should

use an external Schmidt trigger.

All on chip peripherals for the ADSP-21992 operate at the

rate set by the peripheral clock. The peripheral clock

(HCLK) is either equal to the core clock rate or one half the

DSP core clock rate (CCLK). This selection is controlled

by the IOSEL bit in the PLLCTL register. The maximum

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts, and resets all registers

to their default values (where applicable). When RESET is

released, if there is no pending bus request, program control

jumps to the location of the on chip boot ROM (0xFF0000)

and the booting sequence is performed.

Power Supplies

The ADSP-21992 has separate power supply connections

for the internal (V_DDINT) and external (V_DDEXT) power

supplies. The internal supply must meet the 2.5 V require-

ment. The external supply must be connected to a 3.3 V

supply. All external supply pins must be connected to the

same supply.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

13

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

August 2002

Booting Modes

pin, or a software initiated reset, via writing to the Software

Reset register Following either a hardware or a software

reset, execution always startsfrom the boot ROM at address

0xFF0000, irrespective of the settings of the BMODE2,

BMODE1 and BMODE0 pins. The dedicated BMODE2,

BMODE1 and BMODE0 pins are sampled during

hardware reset.

The ADSP-21992 supports a number of different boot

modes that are controlled by the three dedicated hardware

boot mode control pins (BMODE2, BMODE1 and

BMODE0). The use of 3 boot mode control pins means

that up to 8 different boot modes are possible. Of these only

5 modes are valid on the ADSP-21992. The ADSP-21992

exposes the boot mechanism to software control by

providing a nonmaskable boot interrupt that vectors to the

start of the on chip ROM memory block (at address

0xFF0000). A boot interrupt is automatically initiated

following either a hardware initiated reset, via the RESET

The particular boot mode for the ADSP-21992 associated

with the settings of the BMODE2, BMODE1, BMODE0

pins is defined in Table 1.

Table 3. Summary of Boot Modes for ADSP-21992

Boot Mode BMODE2 BMODE1 BMODE0 Function

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Illegal – Reserved

Boot from External 8-bit Memory over EMI

Execute from External 8-bit Memory

Execute from External 16-bit Memory

Boot from SPI0 ≤ 4 kbits

Boot from SPI0 > 4kbits

Illegal – Reserved

Instruction Set Description

DEVELOPMENT TOOLS

The ADSP-21992 assembly language instruction set has an

algebraic syntax that was designed for ease of coding and

readability. The assembly language, which takes full

advantage of the processor’s unique architecture, offers the

following benefits:

The ADSP-21992 is supported with a complete set of

softwareandhardwaredevelopmenttools,includingAnalog

Devices’ emulators and VisualDSP® development environ-

ment. The same emulator hardware that supports other

ADSP-219x DSPs, also fully emulates the ADSP-21992.

• ADSP-219xassemblylanguagesyntaxisasupersetofand

source code compatible (except for two data registers and

DAG base address registers) with ADSP-21xx family

syntax. It may be necessary to restructure ADSP-21xx

programs to accommodate the ADSP-21992’s unified

memory space and to conform to its interrupt vector map.

The VisualDSP project management environment lets pro-

grammers develop and debug an application. This

environmentincludesaneasy-to-useassemblerthatisbased

on an algebraic syntax; an archiver (librarian/library

builder); a linker; a loader; a cycle-accurate, instruc-

tion-level simulator; a C/C++ compiler; and a C/C++

run-time library that includes DSP and mathematical func-

tions. Two key points for these tools are:

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical

arithmetic add instruction, such as AR = AX0 + AY0,

resembles a simple equation.

• Compiled ADSP-219x C/C++ code efficiency—the

compiler has been developed for efficient translation of

C/C++ code to ADSP-219x assembly. The DSP has

architectural features that improve the efficiency of

compiled C/C++ code.

• Every instruction, but two, assembles into a single, 24-bit

word that can execute in a single instruction cycle. The

exceptions are two dual word instructions. One writes 16-

or 24-bit immediate data to memory, and the other is an

absolute jump/call with the 24-bit address specified in the

instruction.

• ADSP-218x family code compatibility—The assembler

has legacy features to ease the conversion of existing

ADSP-218x applications to the ADSP-219x.

• Multifunction instructions allow parallel execution of an

arithmetic, MAC, or shift instruction with up to two

fetches or one write to processor memory space during a

single instruction cycle.

Debugging both C/C++ and assembly programs with the

VisualDSP debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved

source and object information)

• Program flow instructions support a wider variety of con-

ditional and unconditional jumps/calls and a larger set of

conditions on which to base execution of conditional

instructions.

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

14

REV. PrA

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

• Trace instruction execution

• Profile program execution

• Fill and dump memory

with a minimum post length of 0.235". Pin 3 is the key

position used to prevent the pod from being inserted back-

wards. This pin must be clipped on the target board.

Also, the clearance (length, width, and height) around the

header must be considered. Leave a clearance of at least

0.15” and 0.10” around the length and width of the header,

and reserve a height clearance to attach and detach the pod

connector. For more information, see Layout Require-

ments on page 17.

• Source level debugging

• Create custom debugger windows

The VisualDSP IDE lets programmers define and manage

DSP software development. Its dialog boxes and property

pages let programmers configure and manage all of the

ADSP-219x development tools, including the syntax high-

lighting in the VisualDSP editor. This capability permits:

1

3

5

2

4

6

• Control how the development tools process inputs and

generate outputs.

EMU

GND

• Maintain a one-to-one correspondence with the tool’s

command line switches.

KEY (NO PIN)

GND

TMS

BTMS

Analog Devices DSP emulators use the IEEE 1149.1 JTAG

test access port of the ADSP-21992 processor to monitor

and control the target board processor during emulation.

The emulator provides full-speed emulation, allowing

inspection and modification of memory, registers, and

processor stacks. Nonintrusive in-circuit emulation is

assured by the use of the processor’s JTAG interface—the

emulator does not affect target system loading or timing.

7

9

8

BTCK

TCK

10

12

BTRST

TRST

9

11

BTDI

GND

TDI

13

14

TDO

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the ADSP-219x processor family.

Hardware tools include ADSP-219x PC plug-in cards.

Third Party software tools include DSP libraries, real-time

operating systems, and block diagram design tools.

TOP VIEW

Figure 6. JTAG Target Board Connector for JTAG

Equiped Analog Devices DSP (Jumpers in

Place)

Designing an Emulator Compatible DSP Board (Target)

The White Mountain DSP (Product Line of Analog

Devices, Inc.) family of emulators are tools that every DSP

developer needs to test and debug their hardware and

software system. Analog Devices has supplied an IEEE

1149.1 JTAG Test Access Port (TAP) on each JTAG DSP.

The emulator uses the TAP to access the internals of the

DSP, allowing the developer to load code, set breakpoints,

observe variables, observe memory, examine registers, etc.

The DSP must be halted to send data and commands, but

once an operation is completed by the emulator, the DSP

system is set running at full speed with no impact on system

timing.

As can be seen in Figure 6, there are two sets of signals on

the header. There are the standard JTAG signals TMS,

TCK, TDI, TDO, TRST and , EMU used for emulation

purposes (via an emulator). There arealso secondary JTAG

signals BTMS, BTCK, BTDI, and BTRST that are option-

ally used for board-level (boundary scan) testing. The "B"

signals would be connected to a separate on-board JTAG

boundaryscancontrollerifused. Mostcustomerswillnever

use the "B" signals. If they will not be used, tie all of them

to ground as shown in figure 2.

Note: BTCK can alternately be pulled up (for some older

silicon) to VDD (+5V, +3.3V, or +2.5V) using a 4.7K⍀

resistor, as described in previous documents. Tying the

signal to ground is universal and will work for all silicon.

To use these emulators, the target’s design must include the

interface between an Analog Devices JTAG DSP and the

emulation header on a custom DSP target board. The

followingsectionsprovidetheguidelinesfordesignthathelp

eliminate possible JTAG emulation port problems.

When the emulator is not connected to this header, place

jumpers across BTMS, BTCK, BTRST, and BTDI as

shown in Figure 7. This holds the JTAG signals in the

correct state to allow the DSP to run free. Remove all the

jumpers when connecting the emulator to the JTAG header.

Target Board Connector

The emulator interface to an ADI JTAG DSP is a 14-pin

header, as shown in Figure 6. The customer must supply

this header on their target board in order to communicate

with the emulator. The interface consists of a standard dual

row 0.025" square post header, set on 0.1" x 0.1" spacing,

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

15

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

August 2002

VDD

DSP

JTAG

PORT

1

3

5

2

4

6

EMU

GND

TMS

GND

JTAG

CONNECTOR

1

3

5

2

4

6

EMU

GND

TMS

GND

KEY (NO PIN)

BTMS

EMU

KEY (NO PIN)

BTMS

7

9

8

BTCK

TCK

TMS

7

9

8

10

12

BTRST

TRST

BTCK

TCK

9

10

12

11

BTRST

TRST

BTDI

GND

TDI

TRST

9

11

13

14

BTDI

GND

TDI

TDO

TDI

13

14

TDO

TOP VIEW

TDO

6 INCHES OR LESS

TOP VIEW

Figure 7. JTAG Target Board Connector With No Local

Boundary Scan

Figure 8. Single-DSP JTAG-Connections, Unbuffered

The state of each standard JTAG signal can be found in

Table 4.

Should your design use more than one DSP (or other JTAG

device in the scan chain), or if your JTAG header is more

than 6 inches from the DSP, use a buffered connection

scheme as shown in Figure 9 (no local boundary scan mode

shown). To keep signal skew to a minimum, be sure the

buffers are all in the same physical package (typical chips

have 6, 8, or 16 drivers). Using a buffer that has built in

series resistors such as the 74ABT2244 family can help

reduce ringing on the JTAG signal lines. For low voltage

applications (3.3V, 2.5V, and 1.8V I/O), the 74ALVT, and

74AVC logic families are a good starting point. Also, note

the position of the pull-up resistor on EMU. This is

required since the EMU line is an open drain signal.

Table 4. State of Standard JTAG Signals¹

Signal

Description

Emulator

DSP

TMS

TCK

TRST

TDI

TDO

EMU

Test Mode Select

Test Clock (10 MHz)

Test Reset

Test Data In

Test Data Out

Emulation Pin

O

I

O

O, o/d

I

¹O = Output, I = Input, o/d = Open Drain

Important: If you have more than one DSP (or JTAG

device) on your target (in the scan chain), it is imperative

that you buffer the JTAG header. This will keep the signals

cleanandavoidnoise problems thatoccur withlonger signal

traces (ultimately resulting in reliable emulator operation).

The DSP CLKIN signal is the clock signal line (typically 30

MHz or greater) that connects an oscillator to all DSPs in

multiple DSP systems requiring synchronization. For syn-

chronous DSP operations to work correctly the CLKIN

signal on all the DSPs must be the same signal and the skew

between them must be minimal (use clock drivers, or other

means) – see the DSP users guide for more details on

CLKIN.

Although the theoretical number of devices that can be

supported (by the software) in one JTAG scan chain is quite

large (50 devices or more) it is not recommended that you

use more than eight physical devices in one scan chain. (A

physical device could however contain many JTAG devices

such as inside a multi-chip module). The recommendation

of not more than eight physical devices is mostly due to the

transmission line effects that appear in long signal traces,

and based on some field-collected empirical data. The best

approach for large numbers of physical devices is to break

the chain into several smallerindependent chains, each with

their own JTAG header and buffer. If this is not possible,

at least add some jumpers that can reduce the number of

devices in one chain for debug purposes, and pay special

attention in the layout stage for transmission line effects.

Note that the CLKIN signal is not used by the emulator and

can cause noise problems if connected to the JTAG header.

Legacy documents show it connected to pin 4 of the JTAG

header. Pin-4 should be tied to ground on the 14-pin JTAG

header (do not connect the JTAG header pin to the DSP

CLKIN signal). If you have already connected it to the

JTAG header pin, and are experiencing noise from this

signal, simply clip this pin on the 14-pin JTAG header.

The final connections between a single DSP target and the

emulation header (within 6 inches) are shown in Figure 8.

A 4.7K⍀ pull-up resistor has been added on TCK, TDI

and TMS chain for increased noise resistance.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

16

REV. PrA

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

DSP

P0

DSP

P1

DSP

P#

VDD

TDI

TDO

TDI

TDO

TDI

TDO

JTAG

CONNECTOR

1

3

5

2

4

6

EMU

GND

TMS

GND

KEY (NO PIN)

BTMS

7

9

8

BTCK

TCK

10

12

BTRST

TRST

9

11

BTDI

GND

TDI

13

14

TDO

BUFFERS

TOP VIEW

Figure 9. Multiple-DSP JTAG-Connections, Buffered

Layout Requirements

software takes control. Removal of power should be the

reverse: Turn off power to the target board then to the

emulator.

All JTAG signals (TCK, TMS, TDI, TDO, EMU, and

TRST) should be treated as critical route signals. This

means pay special attention when routing these signals.

Specify a controlled impedance requirement for each route

(value depends on your circuit board - typically 50-75⍀).

Keep crosstalk and inductance to a minimum on these lines

by using a good ground plane and by routing away from

other high noise signals such as clock lines. Keep these

routes as short and clean as possible, and keep the bused

signals(TMS, TCK, TRSTand, EMU)asclosetothesame

length as possible.

Emulator Model Specifics

The following sections contain design details on various

emulator pod designs by White Mountain DSP. The

emulator pod is the device that connects directly to the DSP

target board 14-pin JTAG header. Check our web site for

updates to this document that will contain new emulator

design details.

White Mountain DSP JTAG Pod Connector

This section applies to the Mountain ICE, Summit-ICE,

Trek-ICE, Mountain-ICE/WS, Apex-ICE.

Note: The JTAG TAP relies on the state of the TMS line

and the TCKclock signal. If these signals haveglitches (due

to ground bounce, crosstalk, etc.) unreliable emulator

operation will result. If you are experiencing emulator

problems, look at these signals using a high-speed digital

oscilloscope. These lines must be clean, and may require

special termination schemes. If you are buffering the JTAG

header (most customers will) you must provide signal ter-

mination appropriate for your target board (series, parallel,

R/C, etc.).

Figure 10detailsthedimensionsoftheJTAGpodconnector

at the 14-pin target end. Figure 11 displays the keep-out

area for a target board header. The keep-out area allows the

podconnectortoproperlyseatontothetargetboardheader.

This board area should contain no components (chips,

resistors, capacitors, etc.). The dimensions are referenced

to the center of the 0.25” square post pin.

White Mountain DSP 3.3V Pod Logic

This section applies to Mountain ICE, Summit-ICE,

Trek-ICE, Mountain-ICE/WS, Apex-ICE.

Power Sequence

The power-on sequence for your target and emulation

system is as follows: Apply power to the emulator first, then

to the target board. This ensures that the JTAG signals are

in the correct state for the DSP to run free. Upon power-on,

the emulator drives the TRST signal low, keeping the DSP

TAP in the test-logic-reset state, until the emulation

A portion of the White Mountain DSP 3.3V emulator pod

interface is shown in Figure 12. This figure describes the

driver circuitry of the emulator pod. As can be seen, TMS,

TCK and TDI are driven with a 33⍀ series resistor. TRST

is driven with a 100⍀ series resistor. TDO and CLKIN are

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

17

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

August 2002

order to use the terminators on the TDO line (CLKIN is

not used), you MUST have a buffer on your target board

JTAGheader. TheDSPisnotcapableofdrivingtheparallel

terminator load directly with TDO. Assuming you have the

proper buffers, you may use the optional parallel termina-

tors simply by placing a jumper on J2.

White Mountain DSP 2.5V Pod Logic

This section applies to Mountain ICE, Summit-ICE,

Trek-ICE, Mountain-ICE/WS.

A portion of the White Mountain DSP 2.5V emulator pod

interface is shown in Figure 13. This figure describes the

driver circuitry of the emulator pod. As can be seen, TMS,

TCK, and TDI are driven with a 33⍀ series resistor. TRST

is driven with a 100⍀ series resistor. TDO is pulled up with

a 4.7K⍀ resistor and terminated with an optional parallel

terminator that can be configured by the user. EMU is

pulled up with a 4.7K⍀ resistor.

Figure 10. JTAG Pod Connector Dimensions

The CLKIN signal is not used and not connected inside the

pod. The 74ALVT16244 chip drives the signals at 2.5V,

with a maximum current rating of 8mA.

Figure 11. JTAG Pod Connector Keep-Out Area

terminated with an optional 91/120⍀ parallel terminator.

EMU is pulled up with a 4.7K⍀ resistor. The 74LVT244

chip drives the signals at 3.3V, with a maximum current

rating of 32mA.

Figure 13. 2.5V JTAG Pod Driver Logic

You can terminate the TMS, TCK, TRST, and TDI lines

locally on your target board, if needed, as long as the termi-

nator’s current use does not exceed the driver’s maximum

current supply ( 8mA). In order to use the terminator on

theTDOline, youMUSThaveabufferonyourtargetboard

JTAG header. The DSP is not capable of driving a parallel

terminator load (typically 50-75⍀) directly with TDO.

Assuming you have the proper buffers, you may use the

optional parallel terminator by adding the appropriate

resistors and placing a jumper on J2.

Additional Information

Figure 12. 3.3V JTAG Pod Driver Logic

This data sheet provides a general overview of the

ADSP-21992 architecture and functionality. For detailed

information on the ADSP-21992 embedded DSP core

YoucanparallelterminatetheTMS,TCK,TRST,andTDI

lines locally on your target board, if needed, since they are

driven by the pod with sufficient current drive ( 32mA). In

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

18

REV. PrA

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

architecture, instruction set, communications ports and

embedded control peripherals, refer to the ADSP-21992

Mixed Signal DSP Controller Hardware Reference Manual.

TDI, PWMPOL, PWMSR, and RESET)—these pins can

be left floating. These pins have a logic level hold circuit that

prevents input from floating internally. PWMTRIP has an

internal pulldown, but should not be left floating to avoid

unnecessary PWM shutdowns.

PIN DESCRIPTIONS

ADSP-21992 pin definitions are listed in Table 5. All

ADSP-21992 inputs are asynchronous and can be asserted

asynchronously to CLKIN (or to TCK for TRST).

The following symbols appear in the Type column of

Table 5: G = Ground, I = Input, O = Output, P = Power

Supply, B = Bidirectional, T = Three State, D = Digital,

A = Analog, CKG = Clock Generation pin, PU = Internal

Pull Up, PD = Internal Pull Down, and OD = Open Drain.

Unused inputs should be tied or pulled to V_DDEXTor GND,

except for ADDR21–0, DATA15–0, PF7-0, and inputs that

have internal pullup or pulldown resistors (TRST,

BMODE0, BMODE1, BMODE2, BYPASS, TCK, TMS,

Table 5. ADSP-21992 Pin Descriptions

Signal Name

Type

Description

A19 - A0

D15 - D0

RD

WR

ACK

BR

BG

BGH

MS0

MS1

MS2

MS3

IOMS

BMS

CLKIN

XTAL

CLKOUT

BYPASS

RESET

POR

D, OT

D, BT

D, OT

D, I

D, I, PU

D, O

D, OT

D,I,CKG

D,O,CKG

D, OT

D, I, PU

D, O

External Port Address Bus

External Port Data Bus

External Port Read Strobe

External Port Write Strobe

External Port Access Ready Acknowledge

External Port Bus Request

External Port Bus Grant

External Port Bus Grant Hang

External Port Memory Select Strobe 0

External Port Memory Select Strobe 1

External Port Memory Select Strobe 2

External Port Memory Select Strobe 3

External Port IO Space Select Strobe

External Port Boot Memory Select Strobe

Clock Input/Oscillator Input/ Crystal Connection 0

Oscillator Output/ Crystal Connection 1

Clock Output (HCLK)

PLL Bypass Mode Select

Processor Reset Input

Power on Reset Output

BMODE2

BMODE1

BMODE0

TCK

D, I, PU

D, I, PD

D, I, PU

D, I

Boot Mode Select Input 2

Boot Mode Select Input 1

Boot Mode Select Input 0

JTAG Test Clock

TMS

TDI

TDO

TRST

EMU

D, I, PU

D, OT

D, I, PU

D, OT, PU

A, I

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

JTAG Test Reset Input

Emulation Status

ADC Input 0

VIN0

VIN1

A, I

ADC Input 1

VIN2

A, I

ADC Input 2

VIN3

A, I

ADC Input 3

VIN4

A, I

ADC Input 4

VIN5

A, I

ADC Input 5

VIN6

A, I

ADC Input 6

VIN7

A, I

ADC Input 7

ASHAN

BSHAN

A, I

Inverting SHA_A Input

Inverting SHA_B Input

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

19

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Table 5. ADSP-21992 Pin Descriptions (Continued)

Signal Name

Type

Description

CAPT

CAPB

A, O

Noise Reduction Pin

VREF

SENSE

CML

A, I, O

A, I

A, O

Voltage Reference Pin (Mode Selected by State of SENSE)

Voltage Reference Select Pin

Common Mode Level Pin

CONVST

CANRX

CANTX

PF15

PF14

PF13

PF12

PF11

PF10

PF9

D, I

ADC Convert Start Input

Controller Area Network (CAN) Receive

Controller Area Network (CAN) Transmit

General Purpose IO15

General Purpose IO14

General Purpose IO13

General Purpose IO12

General Purpose IO11

General Purpose IO10

General Purpose IO9

D, O, OD

D, BT, PD

D, BT

PF8

General Purpose IO8

PF7/SPISEL7

PF6/SPISEL6

PF5/SPISEL5

PF4/SPISEL4

PF3/SPISEL3

PF2/SPISEL2

PF1/SPISEL1

PF0/SPISS0

SCK

General Purpose IO7 / SPI Slave Select Output 7

General Purpose IO6 / SPI Slave Select Output 6

General Purpose IO5 / SPI Slave Select Output 5

General Purpose IO4 / SPI Slave Select Output 4

General Purpose IO3 / SPI Slave Select Output 3

General Purpose IO2 / SPI Slave Select Output 2

General Purpose IO1 / SPI Slave Select Output 1

General Purpose IO0 / SPI Slave Select Input 0

SPI Clock

MISO

MOSI

DT

DR

D, BT

D, OT

D, I

SPI Master In Slave Out Data

SPI Master Out Slave In Data

SPORT Data Transmit

SPORT Data Receive

RFS

TFS

TCLK

RCLK

EIA

D, BT

SPORT Receive Frame Sync

SPORT Transmit Frame Sync

SPORT Transmit Clock

SPORT Receive Clock

Encoder A Channel Input

D, I

EIB

D, I

Encoder B Channel Input

EIZ

D, I

Encoder Z Channel Input

EIS

D, I

Encoder S Channel Input

AUX0

AUX1

D, O

D, I, PD

D, BT

D, O

Auxiliary PWM Channel 0 Output

Auxiliary PWM Channel 1 Output

Auxiliary PWM Shutdown Pin

Timer 0 Input/Output Pin

Timer 1 Input/Output Pin

Timer 2 Input/Output Pin

PWM Channel A HI PWM

PWM Channel A LO PWM

PWM Channel B HI PWM

AUXTRIP

TMR2

TMR1

TMR0

AH

AL

BH

BL

CH

CL

PWMSYNC

PWMPOL

PWMTRIP

D, O

D, BT

D, I, PU

D, I, PD

PWM Channel B LO PWM

PWM Channel C HI PWM

PWM Channel C LO PWM

PWM Synchronization

PWM Polarity

PWM Trip

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

20

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Table 5. ADSP-21992 Pin Descriptions (Continued)

Signal Name

Type

Description

PWMSR

D, I, PU

A, P

A, G

D, P

PWM SR Mode Select

Analog Supply Voltage

Analog Ground

Digital Internal Supply

Digital External Supply

Digital Ground

AVDD (2 pins)

AVSS (2 pins)

VDDINT (6 pins)

VDDEXT (10 pins)

GND (16 pins)

D, G

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

21

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

ADSP-21992—SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter Description¹

Min

Max

Unit

V_DDINT

V_DDEXT

V_IH1

Internal (Core) Supply Voltage

2.37

TBD

2.0

2.63

3.6

V

External (I/O) Supply Voltage

High Level Input Voltage², @ V_DDINT= max

High Level Input Voltage³, @ V_DDINT= max

Low Level Input Voltage^{1, 2}, @ V_DDINT= min

Ambient Operating Temperature

V_DDEXT

0.6

V

V_IH2

2.2

V

V_IL

–0.3

–40ºC

V

T_AMB

+85ºC

ºC

¹Specifications subject to change without notice.

²Applies to input and bidirectional pins: DATA15–0, HAD15–0, HA16, HALE, HACK, HACK_P, BYPASS, HRD, HWR, ACK, PF7–0, HCMS,

HCIOMS, BR, TFS, TFS1, TFS2/MOSI0, RFS, RFS1, RFS2/MOSI1, BMODE2, BMODE1–0, TMS, TDI, TCK, DT2/MISO0, DR, DR1,

DR2/MISO1, TCLK, TCLK1, TCLK2/SCK0, RCLK, RCLK1, RCLK2/SCK1.

³Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS

Parameter¹

Description

Test Conditions

Min

Max

Unit

V_OH

High Level Output Voltage²@ V_DDEXT= min,

I_OH= –0.5 mA

2.4

V

V_OL

Low Level Output Voltage²

@ V_DDEXT= min,

I_OL= 2.0 mA

0.4

V

I_IH

High Level Input Current^{3, 4}@ V_DDEXT= max,

V_IN= V_DDmax

TBD

µA

mA

pF

I_IL

Low Level Input Current²

@ V_DDINT= max,

V_IN= 0 V

@ V_DDINT= max,

V_IN= 0 V

I_ILP

Low Level Input Current³

I_OZH

Three State Leakage Current⁵@ V_DDINT= max,

V_IN= V_DDmax

I_OZL

Three State Leakage Current⁴@ V_DDINT= max,

V_IN= 0 V

I_OZHP

I_OZLS

Three State Leakage Current⁶@ V_DDINT= max,

V_IN= V_DDmax

Three State Leakage Current⁵@ V_DDINT= max,

V_IN= 0 V

I_{IDD TYPICAL}

I_{IDD IDLE}

I_{IDD PWRDWN}

C_IN

Supply Current (Internal)

Input Capacitance^{7, 8}

@ t_CK= TBD ns,

V_DDINT= max

@ t_CK= TBD ns,

V_DDINT= max

@ t_CK= TBD ns,

V_DDINT= max

f_IN= 1 MHz,

T_CASE= 25°C,

V_IN= 2.5 V

¹Specifications subject to change without notice.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

22

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

²Applies to output and bidirectional pins: DATA15–0, ADDR21–0, HAD15–0, MS3–0, IOMS, RD, WR, CLKOUT, HACK, PF7–0, TMR2–0, BGH,

BG, DT, DT1, DT2/MISO0, TCLK, TCLK1, TCLK2/SCK0, RCLK, RCLK1, RCLK2/SCK1, TFS, TFS1, TFS2/MOSI0, RFS, RFS1, RFS2/MOSI1,

BMS, TDO, TXD, EMU.

³Applies to input pins: ACK, BR, HCMS, HCIOMS, BMODE2, BMODE1–0, HA16, HALE, HRD, HWR, CLKIN, RESET, TCK, TDI, TMS, TRST,

DR, DR1, BYPASS, RXD.

⁴Applies to input pins with internal pull ups: TRST, BMODE0, BMODE1, BMODE2, BYPASS, TCK, TMS, TDI, RESET.

⁵Applies to three statable pins: DATA15–0, ADDR21–0, MS3–0, RD, WR, PF7–0, BMS, IOMS, TFSx, RFSx, TDO, EMU.

⁶The test program used to measure I_DDINPEAKrepresents worst case processor operation and is not sustainable under normal application conditions. Actual

internal power measurements made using typical applications are less than specified. For more information, see Power Dissipation on page 42.

⁷Applies to all signal pins.

⁸Guaranteed, but not tested.

ABSOLUTE MAXIMUM RATINGS

V_DDINTInternal (Core) Supply Voltage^1,2. . . . . . –0.3 to 3.0 V

V

_DDEXTExternal (I/O) Supply Voltage . . . . . . . . –0.3 to 4.6 V

V_IL–V_IHInput Voltage . . . . . . . . . . . . . . . . . . –0.5 to +5.5 V³

V_OL–V_OHOutput Voltage Swing . . . . . . . . . . . –0.5 to +5.5 V³

C_LLoad Capacitance . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

t_CCLKCore Clock Period . . . . . . . . . . . . . . . . . . . . . . 6.25 ns

f_CCLKCore Clock Frequency . . . . . . . . . . . . . . . . . 160 MHz

t_HCLKPeripheral Clock Period . . . . . . . . . . . . . . . . . . . .10 ns

f_HCLKPeripheral Clock Frequency . . . . . . . . . . . . . . 80 MHz

T

_STOREStorage Temperature Range . . . . . . . . . .–65 to 150ºC

_LEADLead Temperature (5 seconds) . . . . . . . . . . . . . 185ºC

¹Specifications subject to change without notice.

²Stresses greater than those listed above may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or

any other conditions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

³Except CLKIN and analog pins.

ESD SENSITIVITY

CAUTION:

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-21992 features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high-energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid perfor-

mance degradation or loss of functionality.

TIMING SPECIFICATIONS

This section contains timing information for the DSP’s

external signals.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

23

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Clock In and Clock Out Cycle Timing

Table 6 and Figure 14 describe clock and reset operations. Per V_DDINTInternal (Core) Supply Voltage, –0.3 to 3.0 V on

page 23, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 160/100 MHz.

Table 6. Clock In and Clock Out Cycle Timing

Parameter

Description

Min

Max

Unit

Switching Characteristic

t_CKODCLKOUT delay from CLKIN

t_CKO

CLKOUT period¹

Timing Requirements

0

5.8

ns

10

t_CK

CLKIN period^2,3

6.25

200

ns

µs

ns

t_CKL

CLKIN low pulse

2.2

t_CKH

t_WRST

t_MSLS

t_MSLH

CLKIN high pulse

2.2

RESET asserted pulsewidth low

200t_CLKOUT

MSELx/BYPASS stable before RESET de-asserted setup 450

MSELx/BYPASS stable after RESET de-asserted hold 10t_CLKOUT

¹Figure 14 shows a

؋

2 ratio between CLKOUT = 2

؋

CLKIN (or t_HCLK= 2

؋

t_CCLK), but the ratio has many programmable options. For more information

see the System Design chapter of the ADSP-219x/2191 DSP Hardware Reference.

²In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), t_CK=t_CCLK

.

³In bypass mode, t_CK=t_CCLK

.

t_CK

CLKIN

RESET

t_CKL

t_CKH

t_WRST

t_MSLS

t_MSLH

MSEL6–0

BYPASS

t_CKOD

t_CKO

CLKOUT

Figure 14. Clock In and Clock Out Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

24

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Programmable Flags Cycle Timing

Table 7 and Figure 15 describe programmable flag operations.

Table 7. Programmable Flags Cycle Timing

Parameter Description

Min

Max

Unit

Switching Characteristic

t_DFO

t_HFO

Timing Requirement

t_HFIFlag input hold is asynchronous

Flag output delay with respect to HCLK

3

ns

Flag output hold after HCLK high

TBD

3

TBD

ns

HCLK

t_DFO

t_HFO

t_DFO

PF

(OUTPUT)

FLAG OUTPUT

t_HFI

PF

(INPUT)

FLAG INPUT

Figure 15. Programmable Flags Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

25

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Timer PWM_OUT Cycle Timing

Table 8 and Figure 16 describe timer expired operations. The input signal is asynchronous in “width capture mode” and

has an absolute maximum input frequency of 50 MHz.

Table 8. Timer PWM_OUT Cycle Timing

Parameter Description

Min

Max

Unit

Switching Characteristic

t_HTO

Timer pulsewidth output¹

6.25

(2³²–1) cycles

ns

¹The minimum time for t_HTOis one cycle, and the maximum time for t_HTOequals (2³²–1) cycles.

HCLK

t_HTO

PWM_OUT

Figure 16. Timer PWM_OUT Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

26

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

External Port Write Cycle Timing

Table 9 and Figure 17 describe external port write operations.

The external port lets systems extend read/write accesses in three ways: wait states, ACK input, and combined wait states

and ACK. To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP

to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see

the External Port chapter in the ADSP-219x/2191 DSP Hardware Reference

Table 9. External Port Write Cycle Timing

Parameter Description^{1, 2, 3}

Min

Max

Unit

Switching Characteristics

t_CWA

t_CSWS

t_AWS

t_AKS

EMI⁴clock low to WR asserted delay

2.8

6.5

7.0

ns

Chip select asserted to WR de-asserted delay

Address valid to WR setup and delay

ACK asserted to EMI clock high delay

WR de-asserted to chip select de-asserted

WR de-asserted to address invalid

4.3

4.9

6.0

t_WSCS

t_WSA

t_CWD

t_WW

4.8

7.0

6.6

2.7

4.5

EMI clock low to WR de-asserted delay

WR strobe pulsewidth

2.5

t_HCLK–0.5

1.5

t_CDA

t_CDD

t_DSW

t_DHW

WR to data enable access delay

4.1

WR to data disable access delay

3.3

7.4

Data valid to WR de-asserted setup

WR de-asserted to data invalid hold time; wt_hold=0

WR de-asserted to data invalid hold time; wt_hold=1

t_HCLK–1.4

3.4

t_HCLK+4.8

7.4

t_HCLK+3.4

t_HCLK+7.4

Timing Requirement

t_AKW

ACK strobe pulsewidth

10.0

ns

¹t_HCLKis the peripheral clock period.

²These are preliminary timing parameters that are based on worst case operating conditions.

³The pad loads for these timing parameters are 20 pF.

⁴EMI clock is the external port clock that is generated from the EMI clock ratio. This signal is not available on an external pin, but (roughly) corresponds

to HCLK (at similar clock ratios).

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

27

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

EMI CLOCK

t_CWA

t_CWD

t_WSCS

t_CSWS

t_AKS

MS3–0

IOMS

BMS

A21–0

WR

t_AWS

t_WW

t_WSA

t_AK

W

ACK

t_CD

t_DSW

t_DHW

A

D15–0

Figure 17. External Port Write Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

28

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

External Port Read Cycle Timing

Table 10 and Figure 18 describe external port read operations. For additional information on the ACK signal, see the

discussion on on page 27.

Table 10. External Port Read Cycle Timing

Parameter Description^{1, 2, 3}

Min

Max

Unit

Switching Characteristics

t_CRA

t_CSRS

t_ARS

t_AKS

t_CRD

t_RSCS

t_RW

EMI⁴clock low to RD asserted delay

2.8

6.5

7.0

ns

Chip select asserted to RD asserted delay

Address valid to RD setup and delay

ACK asserted to EMI clock high delay

EMI clock low to RD de-asserted delay

RD de-asserted to chip select de-asserted setup

RD strobe pulsewidth

4.3

4.9

6.0

2.5

2.7

7.0

4.8

t_HCLK–0.5

4.5

t_RSA

RD de-asserted to address invalid setup

6.6

Timing Requirements

t_AKW

t_CDA

t_RDA

t_ADA

t_SDA

t_SD

ACK strobe pulsewidth

10.0

0.0

ns

RD to data enable access delay

RD asserted to data access setup

Address valid to data access setup

Chip select asserted to data access setup

Data valid to RD de-asserted setup

RD de-asserted to data invalid hold

t_HCLK–5.5

t_HCLK–0.2

t_HCLK–0.6

1.8

0.0

t_HRD

¹t_HCLKis the peripheral clock period.

²These are preliminary timing parameters that are based on worst case operating conditions.

³The pad loads for these timing parameters are 20 pF.

⁴EMI clock is the external port clock that is generated from the EMI clock ratio. This signal is not available on an external pin, but (roughly) corresponds

to HCLK (at similar clock ratios).

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

29

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

EMI CLOCK

t_CRA

t_RSCS

t_CSRS

t_AKS

t_CRD

MS3–0

IOMS

BMS

A21–0

RD

t_ARS

t_RW

t_RSA

t_AKW

ACK

t_CDA

t_SD

t_HRD

D15–0

t_RDA

t_ADA

t_SDA

Figure 18. External Port Read Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

30

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

External Port Bus Request and Grant Cycle Timing

Table 11 and Figure 19 describe external port bus request and bus grant operations.

Table 11. External Port Bus Request and Grant Cycle Timing

Parameter Description^{1, 2, 3}

Min

Max

Unit

Switching Characteristics

t_SD

CLKOUT high to xMS, address, and RD/WR disable

4.3

4.0

2.2

2.4

ns

t_SE

CLKOUT low to xMS, address, and RD/WR enable

CLKOUT high to BG asserted setup

t_DBG

t_EBG

t_DBH

t_EBH

CLKOUT high to BG de-asserted hold time

CLKOUT high to BGH asserted setup

CLKOUT high to BGH de-asserted hold time

Timing Requirements

t_BS

BR asserted to CLKOUT high setup

CLKOUT high to BR de-asserted hold time

4.6

0.0

ns

t_BH

¹t_HCLKis the peripheral clock period.

²These are preliminary timing parameters that are based on worst case operating conditions.

³The pad loads for these timing parameters are 20 pF.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

31

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

CLKOUT

t_BS

t_BH

BR

t_SD

t_SE

MS3–0

IOMS

BMS

t_SD

t_SE

A21–0

t_SD

t_SE

WR

RD

t_DBG

t_EBG

BG

t_DBH

t_EBH

BGH

Figure 19. External Port Bus Request and Grant Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

32

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Serial Port (SPORT) Clocks and Data Timing

Table 12 and Figure 20 describe SPORT transmit and receive operations.

Table 12. Serial Port (SPORT) Clocks and Data Timing¹

Parameter Description

Min

Max

Unit

Switching Characteristics

t_HOFSE

t_DFSE

RFS Hold after RCLK (Internally Generated RFS)²

RFS Delay after RCLK (Internally Generated RFS)²

Transmit Data Delay after TCLK²

0

12.4

12.1

12.0

6.8

ns

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

Data Disable from External TCLK²

Data Enable from Internal TCLK²

Data Disable from Internal TCLK²

6.3

Timing Requirements

t_SCLKIWTCLK/RCLK Width

t_SFSI

20

ns

TFS/RFS Setup before TCLK/RCLK³

TFS/RFS Hold after TCLK/RCLK^{3, 4}

Receive Data Setup before RCLK³

Receive Data Hold after RCLK³

TCLK/RCLK Width

–0.6

–0.3

–2.3

1.9

t_HFSI

t_SDRI

t_HDRI

t_SCLKW

t_SFSE

20

TFS/RFS Setup before TCLK/RCLK³

TFS/RFS Hold after TCLK/RCLK^{3, 4}

Receive Data Setup before RCLK³

Receive Data Hold after RCLK³

–0.6

–2.2

1.8

t_HFSE

t_SDRE

t_HDRE

¹To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed:

1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.

²Referenced to drive edge.

³Referenced to sample edge.

⁴RFS hold after RCLK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCLK for late external TFS is 0 ns minimum from

drive edge.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

33

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

DATA RECEIVE— INTERNAL CLOCK

DATA RECEIVE— EXTERNAL CLOCK

SAMPLE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

t_SCLKIW

t_SCLKW

SCLK

TDFSE

t_DFSE

t_HOFSE

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

FS

t_SDRI

t_SDRE

t_HDRI

t_HDRE

DXA/DXB

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

SCLK

(EXT)

t_DDTEN

t_DDTTE

DXA/DXB

DRIVE EDGE

SCLK

(INT)

SCLK

t_DDTIN

t_DDTTI

DXA/DXB

Figure 20. Serial Port (SPORT) Clocks and Data

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

34

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Serial Port (SPORT) Frame Synch Timing

Table 13 and Figure 21 describe SPORT frame synch operations.

To determine whether communication is possible between two devices at clock speed n, the following specifications must

be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3)

R/TCLK width.

Table 13. Serial Port (SPORT) Frame Synch Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

t_HOFSE

RFS Hold after RCLK (Internally Generated RFS)¹

12.4

12.2

4.7

ns

t_HOFSI

TFS Hold after TCLK (Internally Generated TFS)¹

Data Enable from late FS or MCE = 1, MFD = 0²

t_DDTENFS

t_DDTLFSE

Data Delay from Late External TFS or External RFS with

MCE = 1, MFD = 0³

4.7

t_HDTE

t_HDTI

t_DDTE

t_DDTI

Transmit Data Hold after TCLK (external clk)¹

Transmit Data Hold after TCLK (internal clk)¹

Transmit Data Delay after TCLK (external clk)¹

Transmit Data Delay after TCLK (internal clk)¹

12.4

12.2

11.1

ns

0

Timing Requirements

t_SFSE

TFS/RFS Setup before TCLK/RCLK (external clk)³

t_SFSI

TFS/RFS Setup before TCLK/RCLK (internal clk)³

–0.6

TBD

ns

¹Referenced to drive edge.

²MCE = 1, TFS enable and TFS valid follow t_DDTLFSEand t_DDTENFS

³Referenced to sample edge.

.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

35

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

SAMPLE

DRIVE

SCLK

t_SFSE/I

t_HOFSE/I

FS

t_DDTE/I

t_DDTLFSE

t_HDTE/I

t_DDTENFS

DXA/DXB

FIRST BIT

SECOND BIT

LATE EXTERNAL TRANSMIT FS

DRIVE

SAMPLE

DRIVE

SCLK

t_SFSE/I

t_HOFSE/I

FS

t_DDTE/I

t_DDTLFSE

t_HDTE/I

t_DDTENFS

DXA/DXB

FIRST BIT

SECOND BIT

Figure 21. Serial Port (SPORT) Frame Synch

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

36

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Serial Peripheral Interface (SPI) Port—Master Timing

Table 14 and Figure 22 describe SPI port master operations.

Table 14. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

t_SDSCIM

t_SPICHM

t_SPICLM

t_SCK

SPISS low to first SCLK edge

Serial clock high period

2t_HCLK

4t_HCLK

2t_HCLK

0

ns

Serial clock low period

Serial clock period

t_HDSM

Last SCLK edge to SPISS high

Sequential transfer delay

t_SPITDM

t_DDSPID

t_HDSPID

SCLK edge to data out valid (data out delay)

SCLK edge to data out invalid (data out hold)

6

5

0

Timing Requirements

t_SSPIDData input valid to SCLK edge (data input setup)

t_HSPIDSCLK sampling edge to data input invalid

1.6

ns

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

37

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

SPISS

(OUTPUT)

t_HDSM

t_SPITDM

t_SPICHM

t_SPICLM

t_SPICLK

t_SDSCIM

SCLK

(CPOL = 0)

(OUTPUT)

t_SPICLM

t_SPICHM

SCLK

(CPOL = 1)

(OUTPUT)

t_DDS

-

t_HDSPID

PID

MOSI

(OUTPUT)

MSB

LSB

CPHA=1

THSPID

t_SSPID

t_HSPID

MISO

(INPUT)

MSB

VALID

LSB

VALID

t_DDS

-

t_HDSPID

PID

MOSI

(OUTPUT)

MSB

LSB

CPHA=0

THSPID

t_SSPID

MSB

LSB

MISO

VALID

(INPUT)

Figure 22. Serial Peripheral Interface (SPI) Port—Master

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

38

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 15 and Figure 23 describe SPI port slave operations.

Table 15. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

t_DSOE

SPISS assertion to data out active

0

6

5

ns

t_DSDHI

t_DDSPID

t_HDSPID

SPISS deassertion to data high impedance

SCLK edge to data out valid (data out delay)

SCLK edge to data out invalid (data out hold)

Timing Requirements

t_SPICHS

t_SPICLS

t_SCK

Serial clock high period

2t_HCLK

4t_HCLK

2t_HCLK

1.6

ns

Serial clock low period

Serial clock period

t_HDS

Last SCK edge to SPISS not asserted

Sequential Transfer Delay

t_SPITDS

t_SDSCI

t_SSPID

t_HSPID

SPISS assertion to first SCK edge

Data input valid to SCLK edge (data input setup)

SCLK sampling edge to data input invalid

1.6

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

39

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

SPISS

(INPUT)

TSPITD

S

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

SCLK

(CPOL = 0)

(INPUT)

t_SDSCI

t_SPICLS

t_SPICHS

SCLK

(CPOL = 1)

(INPUT)

t_DSOE

t_DDSPID

t_HDSPID

t_DDSPID

t_DSDHI

MISO

(OUTPUT)

MSB

LSB

CPHA=1

TSSPID

t_HSPID

t_SSPID

t_HSPID

MOSI

MSB

LSB

(INPUT)

VALID

t_DDSPID

t_DSOE

t_DSDHI

MISO

(OUTPUT)

LSB

MSB

CPHA=0

t_SSPID

t_HSPID

MSB

VALID

LSB

VALID

MOSI

(INPUT)

Figure 23. Serial Peripheral Interface (SPI) Port—Slave

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

40

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

JTAG Test And Emulation Port Timing

Table 16 and Figure 24 describe JTAG port operations.

Table 16. JTAG Port Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

t_DTDO

t_DSYS

TDO Delay from TCK Low

4

5

ns

System Outputs Delay After TCK Low¹

0

Timing Parameters

t_TCK

TCK Period

20

ns

t_STAP

t_HTAP

t_SSYS

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low²

System Inputs Hold After TCK Low²

TRST Pulsewidth³

4

5

t_HSYS

t_TRSTW

4

¹System Outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT, DT1, TCLK, TCLK1, RCLK, RCLK1,

TFS, TFS1, RFS, RFS1, BMS.

²System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR, DR1, TCLK, TCLK1, RCLK, RCLK1, TFS, TFS1, RFS, RFS1,

CLKIN, RESET.

³50 MHz max.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 24. JTAG Port Timing

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

41

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

120

100

Output Drive Currents

Figure 25 shows typical current and voltage characteristics

for the output drivers of the ADSP-21992. The curves

represent the current drive capability of the output drivers

as a function of output voltage.

80

60

40

20

Power Dissipation

0

TBD

Total power dissipation has two components, one due to

internal circuitry and one due to the switching of external

output drivers. Internal power dissipation is dependent on

the instruction execution sequence and the data operands

involved. Using the current specifications (I_DDINPEAK, I_DDINHIGH

I_DDINLOW, I_DDIDLE) from the Electrical Characteristics on

page 22 and the current versus operation information in

Table 17, designers can estimate the ADSP-21992’s

internal power supply (V_DDINT) input current for a specific

application, according to the formula in Figure 26.

–20

–40

–60

–80

–100

–120

,

0

0.5

1

1.5

2.0

2.5

3.0

3.5

SOURCE (V

) VOLTAGE – V

DDEXT

Figure 25. ADSP-21992 Typical Drive Currents

Table 17. ADSP-21992 Operation Types Versus Input Current

Operation

Typical Activity (I_{DD TYPICAL}

)

High Activity (I_{DD IDLE}

)

Low Activity (I_{DD PWRDWN})

Instruction Type

TBD

Instruction Fetch

Core Memory Access¹

Internal Memory DMA TBD

External Memory

DMA

TBD

Data bit pattern for core TBD

memory access and

DMA

TBD

¹These assume a 2:1 core clock ratio. For more information on ratios and clocks (t_CKand t_CCLK), see Clock Signals on page 13.

I_DDINT= (%Typical × I_DD-TYPICAL) + (%Idle × I_DD-IDLE) + (%Powerdown × I_DD-PWRDWN

)

Figure 26. I_DDINTCalculation

Theexternalcomponentoftotalpowerdissipationiscaused

by the switching of output pins. Its magnitude depends on:

1⁄(2t_CK). The write strobe can switch every cycle at a

frequency of 1⁄t_CK. Select pins switch at 1⁄(2t_CK), but selects

can switch on each cycle. For example, estimate P_EXTwith

the following assumptions:

• The number of output pins that switch during each cycle

(O)

• A system with one bank of external data memory—asyn-

chronous RAM (16-bit)

• The maximum frequency at which they can switch (f)

• Their load capacitance (C)

• Four 8K

؋

16 RAM chips are used, each with a load of 10

pF

• Their voltage swing (V_DD)

and is calculated by the formula in Figure 27.

• External data memory writes occur every other cycle, a

rate of 1⁄(4t_CK), with 50% of the pins switching

P_EXT= O × C × V_DD²× f

• The bus cycle time is 50 MHz (t_CK= 20 ns)

Figure 27. P_EXTCalculation

The load capacitance should include the processor’s

package capacitance (C_IN). The switching frequency

includes driving the load high and then back low. Address

and data pins can drive high and low at a maximum rate of

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

42

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

The P_EXTequation is calculated for each class of pins that

can drive as shown in Table 18.

Table 18. P_EXTCalculation

2

Pin Type

# of Pins

% Switching

؋

C

؋

f

؋

V_DD

= P_EXT

Address

MSx

WR

Data

CLKOUT

15

1

2

64

1

50

0

100

50

100

؋

44.7 pF

؋

44.7 pF

؋

44.7 pF

؋

14.7 pF

؋

4.7 pF

؋

12.5 MHz

؋

12.5 MHz

؋

25 MHz

؋

12.5 MHz

؋

25 MHz

؋

10.9 V

؋

10.9 V

؋

10.9 V

؋

10.9 V

؋

10.9 V

=0.046 W

=0.000 W

=0.024 W

=0.064 W

=0.001 W

P_EXT=0.135 W

A typical power consumption can now be calculated for

these conditions by adding a typical internal power dissipa-

tion with the formula in Figure 28.

REFERENCE

SIGNAL

P_TOTAL= P_EXT+ P_INT

t_MEASURED

t_ENA

2.0V

t_DIS

Figure 28. P_TOTAL(Typical) Calculation

V_OH(MEASURED)

V

_OH(MEASURED) – DV

Where:

V_OL(MEASURED) + DV

t_DECAY

1.0V

V_OL(MEASURED)

• P_EXTis from Table 18

• P_INTis I_DDINT

؋

2.5V, using the calculation I_DDINTlisted in

Power Dissipation on page 42

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

Note that the conditions causing a worst case P_EXTare

different from those causing a worst case P_INT. Maximum

P_INTcannot occur while 100% of the output pins are

switching from all ones to all zeros. Note also that it is not

common for an application to have 100% or even 50% of

the outputs switching simultaneously.

HIGH-IMPEDANCE STATE.

TEST CONDITIONS CAUSE THISVOLT-

AGE TO BE APPROXIMATELY 1.5V

Figure 30. Output Enable/Disable

Test Conditions

IOL

The DSP is tested for output enable, disable, and hold time.

Output Disable Time

Output pins are considered to be disabled when they stop

driving, go into a high impedance state, and start to decay

from their output high or low voltage. The time for the

voltage on the bus to decay by – V is dependent on the

capacitive load, C_Land the load current, I_L. This decay time

can be approximated by the equation in Figure 29.

TO

OUTPUT

+1.5V

50PF

IOH

C_L∆V

---------------

=

t_DECAY

I_L

Figure 31. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

Figure 29. Decay Time Calculation

The output disable time t_DISis the difference between

t_MEASUREDand t_DECAYas shown in Figure 30. The time t_MEASURED

is the interval from when the reference signal switches to

when the output voltage decays –V from the measured

output high or output low voltage. The t_DECAYis calculated

with test loads C_Land I_L, and with –V equal to 0.5 V.

INPUT

OR

OUTPUT

1.5V

Figure 32. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

43

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Output Enable Time

Output pins are considered to be enabled when they have

made a transition from a high impedance state to when they

startdriving. Theoutputenabletimet_ENAistheintervalfrom

when a reference signal reaches a high or low voltage level

to when the output has reached a specified high or low trip

point, as shown in the Output Enable/Disable diagram

(Figure 30). If multiple pins (such as the data bus) are

enabled, the measurement value is that of the first pin to

start driving.

3.5

3.0

2.5

2.0

TBD

1.5

1.0

Example System Hold Time Calculation

To determine the data output hold time in a particular

system, first calculate t_DECAYusing the equation given in

Figure 29. Choose –V to be the difference between the

ADSP-21992’s output voltage and the input threshold for

thedevicerequiringtheholdtime. Atypical–Vwillbe0.4 V.

C_Lis the total bus capacitance (per data line), and I_Lis the

total leakage or three state current (per data line). The hold

time will be t_DECAYplus the minimum disable time (i.e.,

t_DATRWHfor the write cycle).

0.5

0

20

40

60

80

100 120 140 160 180 200

LOAD CAPACITANCE–PF

Figure 34. Typical Output Rise Time (10%-90%,

V_DDEXT=Min) vs. Load Capacitance

Capacitive Loading

5

Output delays and holds are based on standard capacitive

loads: 50 pF on all pins (see Figure 35). The delay and hold

specifications given should be derated by a factor of

1.5 ns/50 pF for loads other than the nominal value of

50 pF. Figure 33 and Figure 34 show how output rise time

varies with capacitance. These figures also show graphically

how output delays and holds vary with load capacitance.

(Note that this graph or derating does not apply to output

disable delays; see Output Disable Time on page 43.) The

graphs in these figures may not be linear outside the ranges

shown.

4

3

2

TBD

1

NOMINAL

–

25

50

75

100

125

150

175

LOAD CAPACITANCE–PF

16.0

14.0

12.0

10.0

Figure 35. Typical Output Delay or Hold vs. Load

Capacitance (at Max Case Temperature)

Environmental Conditions

The thermal characteristics in which the DSP is operating

influence performance.

8.0

TBD

Thermal Characteristics

6.0

4.0

The ADSP-21992 comes in a 196-lead Ball Grid Array

(mini-BGA) package. The ADSP-21992 is specified for an

ambient temperature (T_AMB) as calculated using the formula

inFigure 36.ToensurethattheT_AMBdatasheetspecification

is not exceeded, a heatsink and/or an air flow source may be

used. A heatsink should be attached to the ground plane (as

close as possible to the thermal pathways) with a thermal

adhesive.

2.0

0

20

40

60

80

100 120 140 160 180 200

LOAD CAPACITANCE–PF

Figure 33. Typical Output Rise Time (10%–90%,

V_DDEXT=Max) vs. Load Capacitance

T_AMB= T_CASE– PD × θ_CA

Figure 36. T_CASECalculation

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

44

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Where:

• T_AMB= Ambient temperature (measured near top surface

of package)

• PD = Power dissipation in W (this value depends upon

the specific application; a method for calculating PD is

shown under Power Dissipation).

• θ_CA= Value from Table 19.

• θ_JB= TBD°C⁄W

There are some important things to note about these T_AMB

calculations and the values in Table 19:

• This represents thermal resistance at total power of

TBD W.

• For the mini-BGA package: θ_JC= 8.4°C⁄W

Table 19. θ_CAValues¹

Airflow

(Linear Ft.⁄Min.)

Airflow

(Meters⁄Second)

Mini-BGA:

θ_CA(°C⁄W)

0

100

0.5

24

200

1

400

2

600

3

0

26

22

20.9 19.8

¹These are preliminary estimates.

ADSP-21992 Pinout

Table 20 identifies the signal for each LQFP lead number.

Table 21 identifies the LQFP lead number for each signal

name.

Table 5 describes each signal.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

45

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Table 20. 176-lead LQFP

Signal By Lead Number

Lead # Signal

VDDEXT

1

N/C

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

VDDEXT

A4

89

N/C

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

2

N/C

90

N/C

PF11

3

4

5

6

7

8

9

VDDEXT

RCLK

SCK

MISO

MOSI

RD

WR

ACK

BR

A3

A2

A1

A0

D15

D14

D13

D12

91

92

93

94

95

96

97

98

VDDEXT

BYPASS

BMODE0

BMODE1

BMODE2

N/C

DGND

VDDINT

EMU

TRST

TDO

TDI

TMS

TCK

PF10

PF9

PF8

PF7/SPISEL7

PF6/SPISEL6

PF5/SPISEL5

PF4/SPISEL4

DGND

VDDEXT

PF3/SPISEL3

PF2/SPISEL2

PF1/SPISEL1

PF0/SPISS0

DGND

VDDINT

AVSS

AVDD

N/C

VREF

CML

CAPT

CAPB

SENSE

VIN3

VIN2

VIN1

VIN0

ASHAN

BSHAN

VIN4

VIN5

VIN6

VIN7

AVSS

AVDD

DT

DR

RFS

TFS

TCLK

DGND

N/C

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

D11

99

BG

DGND

VDDEXT

DGND

VDDINT

D10

D9

D8

D7

D6

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

BGH

IOMS

BMS

MS3

DGND

VDDEXT

MS2

MS1

MS0

DGND

VDDINT

A19

A18

A17

A16

A15

A14

A13

DGND

VDDEXT

A12

A11

A10

A9

A8

A7

A6

A5

DGND

N/C

POR

RESET

CLKIN

XTAL

CLKOUT

CONVST

TMR0

DGND

VDDEXT

TMR1

TMR2

EIS

DGND

VDDINT

EIZ

EIB

EIA

AUXTRIP

AUX1

AUX0

PF15

PF14

PF13

PF12

DGND

N/C

D5

DGND

VDDINT

D4

D3

D2

D1

D0

CANRX

DGND

VDDEXT

CL

CH

BL

BH

AL

AH

CANTX

N/C

PWMSYNC

PWMPOL

PWMSR

PWMTRIP

DGND

N/C

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

46

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

August 2002

ADSP-21992

Table 21. 176-lead LQFP

Lead Number by Signal

Signal

Lead # Signal

Lead #

A0

A1

A10

50

49

35

CAPB

CAPT

CH

156

155

77

EIS

EIZ

EMU

116

119

99

PWMTRIP

RCLK

RD

87

4

8

A11

A12

A13

A14

A15

A16

A17

A18

A19

A2

A3

A4

A5

A6

A7

A8

34

33

30

29

28

27

26

25

24

48

47

46

40

39

38

37

36

10

81

80

162

124

123

122

151

169

150

168

12

13

79

78

93

94

95

15

11

CL

76

IOMS

MISO

MOSI

MS0

MS1

MS2

MS3

N/C

PF0/SPISS0

PF1/SPISEL1

PF10

PF11

PF12

PF13

PF14

PF15

PF2/SPISEL2

PF3/SPISEL3

PF4/SPISEL4

PF5/SPISEL5

PF6/SPISEL6

PF7/SPISEL7

PF8

14

6

7

21

20

19

16

1

2

42

43

44

83

89

90

96

130

131

132

152

176

147

146

135

134

128

127

126

125

145

144

141

140

139

138

137

136

105

85

RESET

RFS

SCK

SENSE

TCK

TCLK

TDI

TDO

TFS

TMR0

TMR1

TMR2

TMS

106

172

5

CLKIN

CLKOUT

CML

CONVST

D0

D1

D10

D11

D12

D13

D14

D15

D2

D3

D4

D5

D6

107

109

154

110

72

71

60

55

54

53

52

51

70

69

68

65

64

63

62

61

17

22

31

41

56

58

66

74

88

157

104

174

102

101

173

111

114

115

103

100

3

18

32

45

57

75

91

113

133

143

23

TRST

VDDEXT

VDDINT

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

VREF

A9

ACK

AH

D7

D8

D9

AL

ASHAN

AUX0

AUX1

AUXTRIP

AVDD

AVSS

BG

DGND

DR

59

67

98

118

149

161

160

159

158

164

165

166

167

153

9

BGH

BH

BL

97

112

117

129

142

148

175

171

170

121

120

BMODE0

BMODE1

BMODE2

BMS

BR

BSHAN

BYPASS

CANRX

CANTX

PF9

POR

PWMPOL

PWMSR

PWMSYNC

163

92

73

DT

EIA

EIB

86

84

WR

XTAL

82

108

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

47

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at (781) 937-1799

OUTLINE DIMENSIONS

August 2002

ADSP-21992

Dimensionsintheoutlinediagramareshowninmillimeters.

176-LEAD LQFP (ST-176-1)

26.00 BSC SQ

24.00 BSC SQ

0.75

0.60

0.45

133

132

176

1

PIN 1

0.27

0.22 TYP

0.17

SEATING

PLANE

0.08 MAX LEAD

COPLANARITY

0.15

0.05

89

1.45

1.40

1.35

44

45

88

1.60 MAX

0.50 BSC

LEAD PITCH

DETAIL A

TOP VIEW (PINS DOWN)

NOTES:

1. DIMENSIONS IN MILLIMETERS.

2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS

IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.

3. CENTER DIMENSIONS ARE NOMINAL.

ORDERING GUIDE

Part Number

Ambient Temperature Range Instruction Rate Operating Voltage

–40ºC to +115ºC 160 MHz 2.5 Int./3.3 Ext. V

Package

176-lead LQFP

ADSP-21992YST

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

48


型号：	ADSP-21992YST
厂家：	ADI
描述：	Mixed Signal DSP Controller With CAN 混合信号DSP控制器， CAN 外围集成电路控制器时钟
文件：	总49页 (文件大小：602K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21992YST [ADI]

相关型号：

ADSP-21992_07

ADSP-21CSP01

ADSP-21MOD870

ADSP-21MOD870-000

ADSP-21MOD870-100

ADSP-21MOD870-110

ADSP-21MOD970

ADSP-21MOD970-000

ADSP-21MOD970-110

ADSP-21MOD970-510

ADSP-21MOD980

ADSP-21MOD980-000