ADSP-21MOD970-000_技术文档

Multiport Internet

Gateway Processor

a

ADSP-21mod970

FEATURES

PERFORMANCE

SYSTEM CONFIGURATION

16-Bit Internal DMA Port for High Speed Access to On-

Chip Memory (Mode Selectable)

Programmable Multichannel Serial Port Supports

24 Channels/32 Channels

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Separate RESET Pins for Each Internal Processor

Complete Single-Chip Multiport Internet Gateway

Processor (No External Memory Required)

Implements Six Modem Channels in One Package

Each Processor Can Implement V.34/V.90 Data/Fax

Modem (Includes Datapump and Controller)

312 MIPS Sustained Performance, 19 ns Instruction Time

@ 3.3 V

Open Architecture Extensible to Voice Over IP and Other

Applications

Low Power Dissipation, 100 mW (Typical) per Digital

Modem Processor

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation

GENERAL DESCRIPTION

The ADSP-21mod970 is a Multiport Internet Gateway Pro-

cessor optimized for implementation of a complete V.34/56K

modem. All data pump and controller functions can be imple-

mented on a single device, offering the lowest power consump-

tion and highest possible modem port density.

The ADSP-21mod970 combines the ADSP-2100 family base

architecture (three computational units, data address generators

and a program sequencer) with two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities and on-chip program and data

memory.

INTEGRATION

ADSP-2100 Family Code Compatible, with Instruction

Set Extensions

960K Bytes of On-Chip RAM, Configured as 576K Bytes

of Program Memory and 384K Bytes of Data Memory

Dual Purpose Program Memory for Both Instruction

and Data Storage

304-Ball PBGA with a 1.45 Square Inch (961 sq. mm)

Footprint

The ADSP-21mod970 integrates 960 bytes of on-chip memory,

configured as 192K words (24-bit) of program RAM, and 192K

words (16-bit) of data RAM. Power-down circuitry is also

provided to meet the low power needs of battery operated por-

table equipment. The ADSP-21mod970 is available in a

31 sq-mm., 304-lead PBGA package.

FUNCTIONAL BLOCK DIAGRAM

16

55

DATA<23:8>

CLKIN

GROUND

27

V

DD

16

4

IAD<15:0>

IDMA CNTL

MODEM

CHANNEL

2

MODEM

CHANNEL

3

MODEM

CHANNEL

4

MODEM

CHANNEL

5

MODEM

CHANNEL

6

4

8

4

SPORT0A

SPORT1

SPORT0B

EMULATOR

6

BR<5:0>

MODEM

CHANNEL

1

BG<5:0>

BGH<5:0>

FLAGS

ADSP-21mod970

6

66

6

IDMA CNTL = IAL, IRD, IWR, IACK

FLAGS = FL<0:2>, PF<0:7>

BUS CNTL = A0, BMS, PMS, DMS, CMS, IOMS, RD, WR

EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK,

ELOUT, ERESET

16

9

RESET<5:0>

DATA<23:8>_1

IAD<15:0>_1

6

CLKOUT<5:0>

EE<5:0>

6

CLKIN_1,

BUS CNTL_1

6

IS<5:0>

SPORT0A, SPORT0B = RFS0, DR0, DT0, SCLK0

SPORT1 = RFS1, DR1, SCLK1, TFS1

6

4

TFS0<5:0>

DT1<5:0>

IDMA CNTL_1

6

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADSP-21mod970

Fabricated in a high speed, low power, CMOS process, the

ADSP-21mod970 operates with a 19 ns instruction cycle time.

Every instruction can execute in a single processor cycle.

A PROM Splitter generates PROM programmer compatible

files. The C Compiler, based on the Free Software Foundation’s

GNU C Compiler, generates ADSP-21mod970 assembly source

code. The source code debugger allows programs to be cor-

rected in the C environment. The Runtime Library includes

over 100 ANSI-standard mathematical and DSP-specific

functions.

The ADSP-21mod970’s flexible architecture and comprehen-

sive instruction set allow the processor to perform multiple

operations in parallel. In one processor cycle, the ADSP-

21mod970 can:

The ADSP-218x EZ-ICE^®Emulator aids in the hardware de-

bugging of an ADSP-21mod970 system. The EZ-ICE, in con-

junction with the required processor selection hardware, lets you

independently debug code on individual modem processors.

The emulator consists of hardware, host computer resident

software, and the target board connector. The ADSP-21mod970

integrates on-chip emulation support with a 14-pin ICE-Port™

interface. The ADSP-21mod970 device need not be removed

from the target system when using the EZ-ICE, nor are any

adapters needed. Due to the small footprint of the EZ-ICE

connector, emulation can be supported in final board designs.

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the internal DMA port

• Receive and/or transmit data through the byte DMA port

• Decrement timer

Modem Software

The EZ-ICE performs a full range of functions, including:

The modem software executes general modem control, com-

mand sets, error correction and data compression, data

modulations (for example, V.90 and V.34), and host interface

functions. The host interface allows system access to modem

statistics such as call progress, connect speed, retrain count,

symbol rate and other modulation parameters.

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

The modem data pump and controller software reside in on-

chip SRAM and do not require additional memory. The user

can configure the ADSP-21mod970 dynamically by download-

ing software from the host through the 16-bit DMA interface.

This SRAM-based architecture provides a software upgrade

path to future standards and applications, such as voice over IP.

See “Designing An EZ-ICE-Compatible Target System” in the

ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as

well as the Designing an EZ-ICE Compatible System section of

this data sheet for the exact specifications of the EZ-ICE target

board connector.

The modem software is available as object code.

Additional Information

DEVELOPMENT SYSTEM

This data sheet provides a general overview of ADSP-21mod970

functionality. For specific information about the modem proces-

sors, refer to the ADSP-21mod870 data sheet. For additional

information on the architecture and instruction set of the mo-

dem processors, refer to the ADSP-2100 Family User’s Manual,

Third Edition. For more information about the development

tools, refer to the ADSP-2100 Family Development Tools Data

Sheet.

The ADSP-2100 Family Development Software, a complete set

of tools for software and hardware system development, supports

the ADSP-21mod970. The System Builder provides a high level

method for defining the architecture of systems under develop-

ment. The Assembler has an algebraic syntax that is easy to

program and debug. The Linker combines object files into an

executable file. The Simulator provides an interactive instruction-

level simulation with a reconfigurable user interface to display

different portions of the hardware environment.

EZ-ICE is a registered trademark of Analog Devices, Inc.

ICE-Port is a trademark of Analog Devices, Inc.

–2–

REV. 0

ADSP-21mod970

ARCHITECTURE OVERVIEW

INDIVDUAL

SIGNALS

BUSED

SIGNALS

MODEM PROCESSOR

Figure 1 is an overall block diagram of the ADSP-21mod970

modem pool. The modem pool contains six independent digital

modem processors.

PF7/IRQ2

PF6/IRQ1

PF5/IRQ0

PF4/IRQE

PF3/MODE D

PF2/MODE C

PF1/MODE B

PF0/MODE A

FL2

DATA 23:8

IAD 15:0

IAL

Each individual modem processor has a DSP core, 160K bytes

of RAM, two serial ports, and a DMA port. The signals for a

single processor are shown in Figure 2. The signals of each

modem processor are accessed through the external pins of the

ADSP-21mod970. Some signals are bused with the signals of

the other processors and are accessed through a single external

pin. Other signals remain separate and they are accessed through

separate external pins for each processor.

IRD

IRW

IACK

DATA 23:8

IAD 15:0

IAL

MODEM

PROCESSOR 1

FL1

IRD

IRW

FL0

EE

IACK

IS

EMS

EINT

TFS0

The arrangement of the six modem processors in the ADSP-

21mod970 makes two basic configurations possible: a master

configuration and a slave configuration. In both configurations,

the control and data pins of five of the six processors connect to

a single bus structure. The control and data pins of the one

modem processor (Modem Processor 1) are separate from the

other modem processors and accessed through external pins.

DT1

ELIN

BGH

BG

BR

EBR

EBG

ECLK

ELOUT

CLKOUT

RESET

A0

ERESET

RFS0

DR0

BMS

PMS

DT0

SCLK0

RFS1

DR1

MODEM

PROCESSOR 1

(ONLY)

DMS

In Slave Mode, all six modem processors have identical func-

tions and have equal status. Each modem processor is con-

nected to a common DMA bus and each modem processor is

configured to operate in the same mode (see the Slave Mode

and the Memory Mode descriptions in the Memory Architecture

CMS

IOMS

RD

TFS1

SCLK1

CLKIN

WR

Figure 2. Modem Processor Signals

ADSP-21mod970

16

DATA<23:8>

CLKIN

16

IAD<15:0>

4

IDMA CNTL

MODEM

CHANNEL

2

MODEM

CHANNEL

3

MODEM

CHANNEL

4

MODEM

CHANNEL

5

MODEM

CHANNEL

6

4

8

4

SPORT0B

SPORT0A

SPORT1

EMULATOR

IDMA CNTL = IAL, IRD, IWR, IACK

FLAGS = FL<0:2>, PF<0:7>

BUS CNTL = A0, BMS, PMS, DMS, CMS, IOMS, RD, WR

EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK, ELOUT, ERESET

SPORT0A, SPORT0B = RFS0, DR0, DT0, SCLK0

SPORT1 = RFS1, DR1, SCLK1, TFS1

MODEM

CHANNEL

1

16

9

DATA<23:8>

IAD<15:0>

THE FOLLOWING SIGNALS ARE ROUTED TO EACH ADSP-21mod970:

CLKIN_1,

BUS CNTL

6

BR<5:0>

BG<5:0>

4

IDMA CNTL

6

BGH<5:0>

66

6

NOTES:

IRQ FUNCTIONS ARE MULTIPLEXED

WITH PROGRAMMABLE FLAGS

FLAGS

RESET<5:0>

6

(SEE ADSP-21mod870 DATA SHEET)

CLKOUT<5:0>

EE<5:0>

6

IS<5:0>

55

GND

6

TFS0<5:0>

DT1<5:0>

27

V

6

DD

Figure 1. Modem Pool

REV. 0

–3–

ADSP-21mod970

section). The Slave Mode is considered to be the normal mode

of operation in a modem pool application. Figure 3 shows the

modem pool configured for slave mode operation.

mode, Processor 1 is treated as a master of the modem pool and

communicates with an external device such as a RAM, ROM or

a memory shared with a host processor. In this configuration,

the master processor performs some controlling function of the

remaining five modem processors. Figure 4 shows the modem

pool configured for Slave Mode operation.

The master mode of the ADSP-21mod970 configures five of the

modem processors with identical functions and isolates one of

the modem processors, Processor 1. In the Master Mode, Pro-

cessor 1 is not connected to the DMA bus as are the other five

modem processors. Processor 1 operates in a different mode

where external pins can be used for access to a 16-bit data bus,

a 14-bit address bus with associated bus control pins. In master

Since the memory bus of Processor 1 is accessible via external

pins in master mode, Processor 1 can be configured for one of

the several memory modes available on the ADSP-21xx family.

(See Full Memory, Host Mode Descriptions.)

6

CLKOUT

ADSP-21mod970

6

RESET

BR

SPORT0A BUS

4

SPORT0A

6

BG

SPORT0B BUS

4

6

SPORT0B

ICE

BGH

FLAGS

ICE BUS

14

42

ICE

MODEM

PROCESSOR

1

ICE

MODEM

ICE

MODEM

ICE

MODEM

ICE

MODEM

ICE

MODEM

SPORT0

MODE A

MODE B

MODE C

MODE D

MODE A

MODE B

MODE C

MODE D

HIGH/1

LOW/0

HIGH/1

LOW/0

HIGH/1

PROCESSOR

؋

5

2

3

4

5

6

(MASTER)

(SLAVE)

CNTL ADDR

D&CB IDMA

21

24

25

16

IDMA

DATA &

CONTROL BUS

DATA BUS

CLKIN

Figure 3. Configured for Slave Mode

6

CLKOUT

RESET

BR

ADSP-21mod970

6

SPORT0A BUS

4

SPORT0A

6

BG

SPORT0B BUS

4

SPORT0B

ICE

6

BGH

14

ICE BUS

42

FLAGS

SPORT0 ICE

MODE A

MODE B

MODE C

MODE D

MODE A

MODE B

MODE C

MODE D

HIGH/1

LOW/0

HIGH/1

LOW/0

MODEM

PROCESSOR

1

MODEM

PROCESSOR

2

MODEM

PROCESSOR

3

MODEM

PROCESSOR

4

MODEM

PROCESSOR

5

MODEM

PROCESSOR

6

؋

5

HIGH/1

(MASTER)

(SLAVE)

CNTL ADDR

D&CB IDMA

7

14

24

25

16

CONTROL

ADDRESS

IDMA

DATA BUS

CLKIN

MASTER

DATA

CLKIN

Figure 4. Configured for Master Mode

–4–

REV. 0

ADSP-21mod970

Serial Ports

Common-Mode Pins

#

The ADSP-21mod970 has a multichannel serial port (SPORT)

connected to each internal digital modem processor for serial

communications.

Input/

Out-

of

Name(s)

Pins put

Function

Following is a brief list of the capabilities of the ADSP-21mod970

SPORT. For additional information on the internal Serial Ports,

refer to the ADSP-2100 Family User’s Manual, Third Edition.

RESET

BR

6

1

I

Processor Reset Input

I

Bus Request Input

BG

O

I

Bus Grant Output

•

SPORT is bidirectional and has a separate, double-buffered

transmit and receive section.

SPORT can use an external serial clock or generate its own

serial clock internally.

SPORT has independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulsewidths and timings.

BGH

DMS

PMS

BMS

IOMS

CMS

RD

Bus Grant Hang Output

Data Memory Select Output

Program Memory Select Output

Byte Memory Select Output

I/O Memory Select Output

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

1

6

WR

•

SPORT supports serial data word lengths from 3 to 16 bits

and provides optional A-law and µ-law companding accord-

ing to CCITT recommendation G.711.

IRQ2/

Edge- or Level-Sensitive Interrupt

Request¹

PF7

I/O

Programmable I/O Pin

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Edge-Sensitive Interrupt Requests¹

Programmable I/O Pin

•

SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

SPORT can receive and transmit an entire circular buffer of

data with one overhead cycle per data word. An interrupt is

generated after a data buffer transfer.

IRQL1/

PF6

6

I

I/O

IRQL0/

PF5

IRQE/

PF4

I

I/O

I

I/O

•

A multichannel interface selectively receives and transmits a

24- or 32-word, time-division multiplexed, serial bitstream.

Mode D/

I

Mode Select Input—Checked Only

During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked Only

During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked Only

During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked Only

During RESET

PIN DESCRIPTIONS

PF3

I/O

The ADSP-21mod970 is available in a 304-lead PBGA package.

In order to maintain maximum functionality and reduce pack-

age size and pin count, some serial port, programmable flag,

interrupt and external bus pins have dual, multiplexed function-

ality. The external bus pins are configured during RESET only,

while serial port pins are software configurable during program

execution. Flag and interrupt functionality is retained concur-

rently on multiplexed pins. In cases where pin functionality is

reconfigurable, the default state is shown in plain text; alternate

functionality is shown in italics.

Mode C/

6

I

PF2

I/O

Mode B/

I

PF1

I/O

Mode A/

I

PF0

I/O

Programmable I/O Pin During

Normal Operation

CLKIN

2

I

Clock Input

CLKOUT

SPORT

6

O

Processor Clock Output

Serial Port I/O Pins²

Output Flags

24

I/O

O

FL0, FL1, FL2 18

V_DDand GND 82

I

Power and Ground

For Emulation Use

EZ-Port

14

I/O

NOTES

¹Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to

enable the corresponding interrupts, the modem pool will vector to the appro-

priate interrupt vector address when the pin is asserted, either by external

devices, or set as a programmable flag.

²SPORT configuration determined by the modem pool’s System Control Regis-

ter. Software configurable.

REV. 0

–5–

ADSP-21mod970

Memory Interface Pins

Table I. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

The ADSP-21mod970 modem pool can be used in one of two

modes, master mode or slave mode. In master mode, Modem

Processor 1 operates with full memory (BDMA operation with

full external overlay memory and I/O capability). In Slave Mode,

Modem Processor 1 operates in host configuration (IDMA

operation with limited external addressing capabilities). The

operating mode is determined by the state of the Mode C pin

during RESET and cannot be changed while the modem pool

is running. See the Memory Architecture section for more

information.

Source Of Interrupt

Address (Hex)

RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)

Power-Down (Nonmaskable)

IRQ2

002C

0004

IRQL1

0008

IRQL0

000C

SPORT0 Transmit

SPORT0 Receive

IRQE

0010

0014

0018

Full Memory Pins (Mode C = 0) Modem Processor 1 Only

BDMA Interrupt

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

001C

0020

0024

#

of

Input/

Name

Pins Output Function

0028 (Lowest Priority)

A13:0

D23:0

14

24

O

Address Output Pins for Program,

Data, Byte and I/O Spaces

When the modem pool is reset, interrupt servicing is disabled.

I/O

Data I/O Pins for Program, Data,

Byte and I/O Spaces (8 MSBs Are

Also Used as Byte Memory Addresses)

LOW POWER OPERATION

The ADSP-21mod970 has three low power modes that signifi-

cantly reduce the power dissipation when the device operates

under standby conditions. These modes are:

Host Pins (Mode C = 1)*

Modem Processor 1 and Modem Processors 2–6

• Power-Down

• Idle

• Slow Idle

#

Name

of

Input/

The CLKOUT pin may also be disabled to reduce external

power dissipation.

Pins Output Function

IAD15:0 32

I/O

O

IDMA Port Address/Data Bus

Power-Down

The ADSP-21mod970 modem pool has a low power feature

that lets the modem pool enter a very low power dormant state

through software control. Following is a brief list of power-down

features. Refer to the ADSP-2100 Family User’s Manual, Third

Edition, “System Interface” chapter, for detailed information

about the power-down feature.

A0

1

Address Pin for External I/O, Pro-

gram, Data, or Byte Access (Modem

Processor 1 Only)

D23:8

32

I/O

Data I/O Pins for Program, Data

Byte and I/O Spaces

IWR

IRD

IAL

IS

2

6

2

I

IDMA Write Enable

IDMA Read Enable

IDMA Address Latch Pin

IDMA Select

•

Quick recovery from power-down. The modem pool begins

executing instructions in as few as 400 CLKIN cycles.

I

•

Support for an externally generated TTL or CMOS proces-

sor clock. The external clock can continue running during

power-down without affecting the lowest power rating and 400

CLKIN cycle recovery.

I

IACK

O

IDMA Port Acknowledge Config-

urable in Mode D; Open Drain

*In Host Mode, external peripheral addresses can be decoded using the A0,

CMS, PMS, DMS, BMS and IOMS signals of Modem Processor 1.

•

Power-down is initiated by the software power-down force

bit. Interrupt support allows an unlimited number of instruc-

tions to be executed before optionally powering down. The

power-down interrupt also can be used as a nonmaskable,

edge-sensitive interrupt.

Interrupts

The interrupt controller allows each modem processor in the

modem pool to respond individually to eleven possible inter-

rupts and reset with minimum overhead. The ADSP-21mod970

provides four dedicated external interrupt input pins, IRQ2,

IRQL1, IRQL0, and IRQE (shared with the PF7:4 pins) for

each modem processor. The ADSP-21mod970 also supports

internal interrupts from the timer, the byte DMA port, the serial

port, software and the power-down control circuit. The inter-

rupt levels are internally prioritized and individually maskable

(except power-down and reset). The IRQ2, IRQL1, and IRQL0

input pins can be programmed to be either level- or edge-sensitive.

IRQL0 and IRQL1 are level-sensitive and IRQE is edge sensi-

tive. The priorities and vector addresses of all interrupts are

shown in Table I.

•

Context clear/save control allows the modem pool to con-

tinue where it left off or start with a clean context when leav-

ing the power-down state.

The RESET pin also can be used to terminate power-down.

Idle

When the ADSP-21mod970 is in the idle mode, the modem

pool waits indefinitely in a low power state until an interrupt

occurs. When an unmasked interrupt occurs, it is serviced;

execution then continues with the instruction following the

IDLE instruction. In idle mode IDMA, BDMA and autobuffer

cycle steals still occur.

–6–

REV. 0

ADSP-21mod970

the host access server data directly from the ADSP-21mod970’s

internal memory. In this configuration, the Modem Processor 1

should be put into host memory mode where Mode D = 1,

Mode C = 1, Mode B = 0, and Mode A = 1 (see Table II).

Slow Idle

The IDLE instruction is enhanced on the ADSP-21mod970 to

let the modem pool’s internal clock signal be slowed, further

reducing power consumption. The reduced clock frequency, a

programmable fraction of the normal clock rate, is specified by a

selectable divisor given in the IDLE instruction.

CLOCK SIGNALS

The ADSP-21mod970 is clocked by a TTL-compatible clock

signal that runs at half the instruction rate; a 26 MHz input clock

yields a 19 ns processor cycle (which is equivalent to 52 MHz).

Normally, instructions are executed in a single processor cycle.

All device timing is relative to the internal instruction clock

rate, which is indicated by the CLKOUT signal when enabled.

The clock input signal is connected to the processor’s CLKIN

input.

The format of the instruction is

IDLE (n);

where n = 16, 32, 64 or 128. This instruction keeps the modem

pool fully functional, but operating at the slower clock rate.

While it is in this state, the modem pool’s other internal clock

signals, such as SCLK, CLKOUT and timer clock, are reduced

by the same ratio. The default form of the instruction, when no

clock divisor is given, is the standard IDLE instruction.

The CLKIN input cannot be halted, changed during operation,

or operated below the specified frequency during normal opera-

tion. The only exception is while the processor is in the power-

down state. For additional information, refer to Chapter 9,

ADSP-2100 Family User’s Manual, Third Edition, for a detailed

explanation of this power-down feature.

When the IDLE (n) instruction is used, it effectively slows down

the modem pool’s internal clock and thus its response time to

incoming interrupts. The one-cycle response time of the stan-

dard idle state is increased by n, the clock divisor. When an

enabled interrupt is received, the ADSP-21mod970 will remain

in the idle state for up to a maximum of n modem pool cycles

(n = 16, 32, 64 or 128) before resuming normal operation.

A clock output (CLKOUT) signal is generated by the processor

at the processor’s cycle rate.

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the modem pool’s reduced internal clock

rate. Under these conditions, interrupts must not be generated

at a faster rate than can be serviced, due to the additional time

the modem pool takes to come out of the idle state (a maximum

of n cycles).

Reset

The RESET signals initiate a reset of each modem processor in

the ADSP-21mod970. The RESET signals must be asserted

during the power-up sequence to assure proper initialization.

RESET during initial power-up must be held long enough to

let the internal clocks stabilize. If RESETs are activated any

time after power-up, the clocks continue to run and do not

require stabilization time.

SYSTEM CONFIGURATION

The power-up sequence is defined as the total time required for

the oscillator circuits to stabilize after a valid V_DDis applied to

the processors, and for the internal phase-locked loops (PLL)

to lock onto the specific frequency. A minimum of 2000 CLKIN

cycles ensures that the PLLs have locked, but this does not

include the oscillators start-up time. During this power-up

sequence, the RESET signals should be held low. On any sub-

sequent resets, the RESET signals must meet the minimum

Figure 5 shows a typical multichannel modem configuration

with the ADSP-21mod970. A line interface can be used to

connect the multichannel subscriber or client data stream to the

multichannel serial port of the ADSP-21mod970. The ADSP-

21mod970 can support up to 64 channels. The IDMA port of

the ADSP-21mod970 is used to give a host processor full access

to the internal memory of the ADSP-21mod970. This lets the

host dynamically configure the ADSP-21mod970 by loading code

and data into its internal memory. This configuration also lets

pulsewidth specification, t_RSP

.

T1/E1

LINE

INTERFACE

SPORT

ADSP-21mod970

(SLAVE MODE)

ADSP-21mod970

(SLAVE MODE)

ADSP-21mod970

(SLAVE MODE)

ADSP-21mod970

(SLAVE MODE)

ST/CNTL IDMA

STATUS

& CONTROL

HOST CONTROL

HOST ADDRESS

HOST DATA

STATUS

&

CONTROL

PAL

HOST

MICRO

IDMA CONTROL

IDMA ADDRESS

IDMA

PAL

Figure 5. Multichannel Modem Configuration

REV. 0

–7–

ADSP-21mod970

The RESET inputs contain some hysteresis; however, if an RC

circuit is used to generate the RESET signals, the use of external

Schmidt triggers are recommended.

Memory and I/O. Refer to the figures and tables below for PM

and DM memory allocations in the ADSP-21mod970.

The ADSP-21mod970 modem pool operates in one of two

memory modes: Slave Mode or Master Mode. The memory

modes determine the memory access to Modem Processor 1. In

Slave Mode, the memory of Modem Processor 1 is configured

for Host Mode; in Master Mode, the memory of Modem Pro-

cessor 1 is configured for Full-Memory Mode. Memories for

Modem Processors 2–6 are configured only for Host Mode.

The differences between these memory modes are explained in

the following sections. Figure 6 shows Program Memory, while

Figure 7 shows Data Memory. Table II summarizes ADSP-

21mod970 operating modes. Table III explains the mode bits

and memory booting.

The reset for each individual modem processor sets the internal

stack pointers to the empty stack condition, masks all interrupts

and clears the MSTAT register. When a RESET is released, if

there is no pending bus request and the modem processor is

configured for booting, the boot-loading sequence is performed.

The first instruction is fetched from on-chip program memory

location 0x0000 once boot loading completes.

MEMORY ARCHITECTURE

The ADSP-21mod970 provides a variety of memory and pe-

ripheral interface options for Modem Processor 1. The key

functional groups are Program Memory, Data Memory, Byte

MODE B = 0

PROGRAM MEMORY

MODE B = 0

DATA MEMORY

DATA MEMORY ADDRESS

ADDRESS

0x3FFF

ALWAYS

0x3FFF

32 MEMORY

MAPPED

ALWAYS

ACCESSIBLE

AT ADDRESS

0x0000 – 0x1FFF

8K INTERNAL

PMOVLAY = 0, 4, 5

OR

8K EXTERNAL

PMOVLAY = 1, 2

ACCESSIBLE

AT ADDRESS

0x2000 – 0x3FFF

REGISTERS

0x2000–

0x3FFF

0x3FE0

0x3FDF

0x0000–

0x1FFF

0x2000

0x1FFF

ACCESSIBLE WHEN

PMOVLAY = 0

ACCESSIBLE WHEN

DMOVLAY = 0

0x2000–

0x3FFF

0x0000–

0x1FFF

0x0000–

0x1FFF

INTERNAL

8160 WORDS

0x2000–

0x3FFF

8K INTERNAL

ACCESSIBLE WHEN

PMOVLAY = 4

ACCESSIBLE WHEN

DMOVLAY = 4

0x2000

INTERNAL

MEMORY

INTERNAL

MEMORY

0x1FFF

0x2000–

0x3FFF

ACCESSIBLE WHEN

PMOVLAY = 5

8K INTERNAL

0x0000–

0x1FFF

0x0000

ACCESSIBLE WHEN

DMOVLAY = 5

DMOVLAY = 0, 4, 5

OR

8K EXTERNAL

0x2000–

0x3FFF

ACCESSIBLE WHEN

PMOVLAY = 1

0x0000–

0x1FFF

ACCESSIBLE WHEN

DMOVLAY = 1

EXTERNAL

MEMORY

DMOVLAY = 1, 2

EXTERNAL

MEMORY

0x0000

ACCESSIBLE WHEN

PMOVLAY = 2

ACCESSIBLE WHEN

DMOVLAY = 2

PMOVLAY MEMORY

A13*

A12:0*

PMOVLAY MEMORY

A13*

A12:0*

0, 4, 5

1

INTERNAL

NOT APPLICABLE NOT APPLICABLE

0, 4, 5

1

INTERNAL

NOT APPLICABLE NOT APPLICABLE

EXTERNAL

OVERLAY1

0

1

13 LSBs OF ADDRESS BETWEEN

0x2000 AND 0x3FFF

EXTERNAL

OVERLAY1

0

1

13 LSBs OF ADDRESS BETWEEN

0x2000 AND 0x3FFF

2

EXTERNAL

OVERLAY2

13 LSBs OF ADDRESS BETWEEN

0x2000 AND 0x3FFF

2

EXTERNAL

OVERLAY2

13 LSBs OF ADDRESS BETWEEN

0x2000 AND 0x3FFF

*FULL-MEMORY MODE ONLY

Figure 6. Program Memory (Memory Shown in Grey Is

Accessible Only in Full-Memory Mode)

Figure 7. Data Memory

Table II. Processor and Memory Mode

ADSP-21mod970 Modes

Memory Modes

for

Modem Processor 1

Master

Slave

Host

• All Internal Program Memory Available

• All Internal Data Memory Available

• IDMA Port Enabled

• All Internal Program Memory Available

• All Internal Data Memory Available

• IDMA Port Enabled

Full-Memory

• All Internal and External Program Memory Available

• All Internal and External Data Memory Available

• I/O Space Available

Not Applicable

• Byte Memory DMA (BDMA) Enabled

–8–

REV. 0

ADSP-21mod970

Table III. Modes of Operation

MODE A Booting Method

MODE D

MODE C

MODE B

X

0

BDMA feature is used to load the first 32 program memory words from

byte memory space. Program execution is held off until all 32 words are

loaded. Chip is configured in Full-Memory Mode¹

0

1

0

BDMA feature is used to load the first 32 program memory words from

byte memory space. Program execution is held off until all 32 words are

loaded. Chip is configured in Host Mode. IACK requires pull-down.

(REQUIRES ADDITIONAL HARDWARE.)

0

1

0

1

0

IDMA feature is used to load internal memory as desired. Program execu-

tion is held off until internal program memory location 0x0000 is written

to. Chip is configured in Host Mode.¹IACK requires pull-down.

BDMA feature is used to load the first 32 program memory words from

byte memory space. Program execution is held off until all 32 words are

loaded. Chip is configured in Host Mode. IACK requires external pull-

down. (REQUIRES ADDITIONAL HARDWARE.)

1

0

1

IDMA feature is used to load internal memory as desired. Program execu-

tion is held off until internal program memory location 0x0000 is written

to. Chip is configured in Host Mode.¹IACK requires external pull-down.¹

NOTE

¹Considered standard operating settings. These configurations simplify your design and improve memory management.

Slave Mode

5. Host checks IACK line to see if the processor has completed

This section describes the Slave Mode memory configuration of

Modem Processor 1. Modem Processors 2–6 are always config-

ured for Slave Mode.

the previous IDMA operation.

6. Host ends IDMA transfer.

The IDMA port has a 16-bit multiplexed address and data bus

and supports 24-bit program memory. The IDMA port is com-

pletely asynchronous and can be written to while the ADSP-

21mod970 is operating at full speed.

Program Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single external

address line (A0). External program execution is not available in

host mode due to a restricted data bus that is 16-bits wide only.

The processor memory address is latched and then automati-

cally incremented after each IDMA transaction. An external

device can therefore access a block of sequentially addressed

memory by specifying only the starting address of the block.

This increases throughput as the address does not have to be

sent for each memory access.

Data Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single external

address line (A0).

Internal Memory DMA Port (IDMA Port; Host Memory

Mode)

The IDMA Port provides an efficient way for a host system and

the ADSP-21mod970 to communicate. The port is used to

access the on-chip program memory and data memory of each

modem processor with only one processor cycle per word over-

head. The IDMA port cannot be used, however, to write to the

processor’s memory-mapped control registers. A typical IDMA

transfer process is described as follows:

IDMA Port access occurs in two phases. The first is the IDMA

Address Latch cycle. When the acknowledge is asserted, a 14-bit

address and 1-bit destination type can be driven onto the bus by

an external device. The address specifies an on-chip memory

location, the destination type specifies whether it is a DM or

PM access. The falling edge of the address latch signal latches

this value into the IDMAA register.

1. Host starts IDMA transfer.

Once the address is stored, data can then either be read from or

written to, the ADSP-21mod970’s on-chip memory. Asserting

the select line (IS) and the appropriate read or write line (IRD

and IWR respectively) signals the ADSP-21mod970 that a par-

ticular transaction is required. In either case, there is a one-

processor-cycle delay for synchronization. The memory access

consumes one additional processor cycle.

2. Host checks IACK control line to see if the processor is busy.

3. Host uses IS and IAL control lines to latch either the DMA

starting address (IDMAA) or the PM/DM OVLAY selection

into the processor’s IDMA control registers.

If IAD [15] = 1, the value of IAD [7:0] represent the IDMA

overlay: IAD [14:8] must be set to 0.

Once an access has occurred, the latched address is automati-

cally incremented, and another access can occur.

If IAD [15] = 0, the value of IAD [13:0] represent the start-

ing address of internal memory to be accessed and IAD [14]

reflects PM or DM for access.

Through the IDMAA register, the processor can also specify the

starting address and data format for DMA operation. Asserting

the IDMA port select (IS) and address latch enable (IAL)

directs the ADSP-21mod970 to write the address onto the

4. Host uses IS and IRD (or IWR) to read (or write) processor

internal memory (PM or DM).

REV. 0

–9–

ADSP-21mod970

IAD0[14.0] bus into the IDMA Control Register. If IAD[15]

is set to 0, IDMA latches the address. If IAD[15] is set to 1,

IDMA latches OVLAY memory. The IDMAA register is memory

mapped at address DM (0x3FE0). Note that the latched address

(IDMAA) cannot be read back by the host. The IDMA Overlay

Register is memory mapped at address DM (0x3FE7). See Fig-

ure 8 for more information on IDMA memory maps.

I/O Space (Full Memory Mode)

The ADSP-21mod970 supports an additional external memory

space called I/O space. This space is designed to support simple

connections to peripherals (such as data converters and external

registers) or to bus interface ASIC data registers. I/O space

supports 2048 locations of 16-bit wide data. The lower eleven

bits of the external address bus are used; the upper three bits are

undefined. Two instructions were added to the core ADSP-2100

Family instruction set to read from and write to I/O memory

space. The I/O space also has four dedicated three-bit wait state

registers, IOWAIT0-3, which specify up to seven wait states to

be automatically generated for each of four regions. The wait

states act on address ranges as shown in Table IV.

DMA

PROGRAM MEMORY

OVLAY

DMA

DATA MEMORY

OVLAY

ALWAYS

ACCESSIBLE

AT ADDRESS

0x2000 – 0x3FFF

ACCESSIBLE

AT ADDRESS

0x2000 – 0x3FFF

0x2000–

0x3FFF

0x0000–

0x1FFF

ACCESSIBLE WHEN

PMOVLAY = 0

ACCESSIBLE WHEN

DMOVLAY = 0

0x2000–

0x3FFF

0x0000–

0x1FFF

Table IV. Wait States

ACCESSIBLE WHEN

PMOVLAY = 4

ACCESSIBLE WHEN

DMOVLAY = 4

0x2000–

0x3FFF

0x0000–

0x1FFF

Address Range

Wait State Register

ACCESSIBLE WHEN

PMOVLAY = 5

ACCESSIBLE WHEN

DMOVLAY = 5

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

IOWAIT0

IOWAIT1

IOWAIT2

IOWAIT3

NOTE:

IDMA AND BDMA HAVE SEPERATE DMA CONTROL REGISTERS

IDMA OVERLAY

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

3

0

2

0

1

0

DM

(0x3FE7)

0

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. The byte memory space

consists of 256 pages, each of which is 16K × 8.

RESERVED

SET TO 0

ID DMOVLAY

ID PMOVLAY

IDMA CONTROL (U = UNDEFINED AT RESET)

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DM

(0x3FE0)

U

The byte memory space on the ADSP-21mod970 supports read

and write operations as well as four different data formats. The

byte memory uses data bits 15:8 for data. The byte memory uses

Data Bits 23:16 and Address Bits 13:0 to create a 22-bit ad-

dress. This allows up to a 4 meg × 8 (32 megabit) ROM or

RAM to be used without glue logic. All byte memory accesses

are timed by the BMWAIT register.

IDMAA ADDRESS

IDMAD

DESTINATION MEMORY

TYPE:

0 = PM

1 = DM

Figure 8. IDMA Control/OVLAY Registers

IDMA Port Booting

Byte Memory DMA (BDMA, Full Memory Mode)

The ADSP-21mod970 can also boot programs through its Inter-

nal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1,

the ADSP-21mod970 boots from the IDMA port. IDMA fea-

ture can load as much on-chip memory as desired. Program

execution is held off until on-chip program memory location 0 is

written to.

The byte memory DMA controller allows loading and storing of

program instructions and data using the byte memory space.

The BDMA circuit can access the byte memory space while the

processor is operating normally and steals only one processor

cycle per 8-, 16- or 24-bit word transferred.

The BDMA circuit supports four different data formats that are

selected by the BTYPE register field. The appropriate number

of 8-bit accesses are done from the byte memory space to build

the word size selected. Table V shows the data formats sup-

ported by the BDMA circuit.

Master Mode

This section describes the Master Mode memory configuration

of Modem Processor 1. Master Mode is not available for

Modem Processors 2–6.

Program Memory (Full Memory Mode) is a 24-bit-wide

space for storing both instruction op codes and data. The

ADSP-21mod970 has 32K words of Program Memory RAM on

chip, and it can access up to two 8K external memory overlay

spaces using the external data bus.

Table V. Data Formats

Internal

BTYPE

Memory Space

Word Size

Alignment

Data Memory (Full Memory Mode) is a 16-bit-wide space

used for the storage of data variables and for memory-mapped

control registers. The ADSP-21mod970 has 32K words on Data

Memory RAM on chip, consisting of 16,352 user-accessible

locations and 32 memory-mapped registers. The ADSP-21mod970

also supports up to two 8K external memory overlay spaces

through the external data bus. All internal accesses complete

in one cycle. Accesses to external memory are timed using the

wait states specified by the DWAIT register.

00

01

10

11

Program Memory

Data Memory

24

16

8

Full Word

MSBs

8

LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.

The BIAD register field is used to specify the starting address

for the on-chip memory involved with the transfer. The 14-bit

BEAD register specifies the starting address for the external byte

–10–

REV. 0

ADSP-21mod970

memory space. The 8-bit BMPAGE register specifies the start-

ing page for the external byte memory space. The BDIR register

field selects the direction of the transfer. Finally the 14-bit

BWCOUNT register specifies the number of DSP words to

transfer and initiates the BDMA circuit transfers.

The ADSP-2100 Family development software (Revision 5.02

and later) fully supports the BDMA booting feature and can

generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to

hold off execution while booting continues through the BDMA

interface. For BDMA accesses while in Host Mode, the addresses

to boot memory must be constructed externally to the ADSP-

21mod970. The only memory address bit provided by the pro-

cessor is A0.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers specified by the BWCOUNT register.

The BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches

zero, the transfers have finished and a BDMA interrupt is gener-

ated. The BMPAGE and BEAD registers must not be accessed

by the processor during BDMA operations.

Composite Memory Select (CMS)

The ADSP-21mod970 has a programmable memory select

signal that is useful for generating memory select signals for

memories mapped to more than one space. The CMS signal is

generated to have the same timing as each of the individual

memory select signals (PMS, DMS, BMS, IOMS) but can

combine their functionality.

The source or destination of a BDMA transfer will always be

on-chip program or data memory.

When the BWCOUNT register is written with a nonzero value

the BDMA circuit starts executing byte memory accesses with

wait states set by BMWAIT. These accesses continue until the

count reaches zero. When enough accesses have occurred to

create a destination word, it is transferred to or from on-chip

memory. The transfer takes one processor cycle. Processor

accesses to external memory have priority over BDMA byte

memory accesses.

Each bit in the CMSSEL register, when set, causes the CMS

signal to be asserted when the selected memory select is as-

serted. For example, to use a 32K word memory to act as both

program and data memory, set the PMS and DMS bits in the

CMSSEL register and use the CMS pin to drive the chip select

of the memory, and use either DMS or PMS as the additional

address bit.

The CMS pin functions like the other memory select signals

with the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

selected memory select signal. All enable bits default to 1 at

reset, except the BMS bit.

The BDMA Context Reset bit (BCR) controls whether the

processor is held off while the BDMA accesses are occurring.

Setting the BCR bit to 0 allows the processor to continue opera-

tions. Setting the BCR bit to 1 causes the processor to stop

execution while the BDMA accesses are occurring, to clear the

context of the processor, and start execution at Address 0 when

the BDMA accesses have completed. The BDMA overlay bits

specify the OVLAY memory blocks to be accessed for internal

memory.

Boot Memory Select (BMS) Disable

The ADSP-21mod970 also lets you boot the processor from one

external memory space while using a different external memory

space for BDMA transfers during normal operation. You can

use the CMS to select the first external memory space for BDMA

transfers and BMS to select the second external memory space

for booting. The BMS signal can be disabled by setting Bit 3 of

the System Control Register to 1. The System Control Register

is illustrated in Figure 9.

Bootstrap Loading (Booting)

The ADSP-21mod970 has two mechanisms to allow automatic

loading of the internal program memory after reset. The method

for booting is controlled by the Mode A, B and C configuration

bits. When the MODE pins specify BDMA booting, the ADSP-

21mod970 initiates a BDMA boot sequence when reset is released.

Bus Request and Bus Grant

Each modem processor in the ADSP-21mod970 can relinquish

control of the data and address buses to an external device.

When the external device requires access to memory, it asserts

the bus request (BR) signal. If the modem processor is not per-

forming an external memory access, then it responds to the

active BR input in the following processor cycle by:

The BDMA interface is set up during reset to the following

defaults when BDMA booting is specified: the BDIR, BMPAGE,

BIAD and BEAD registers are set to 0, the BTYPE register is

set to 0 to specify program memory 24-bit words, and the

BWCOUNT register is set to 32. This causes 32 words of on-

chip program memory to be loaded from byte memory. These

32 words are used to set up the BDMA to load in the remaining

program code. The BCR bit is also set to 1, which causes pro-

gram execution to be held off until all 32 words are loaded into

on-chip program memory. Execution then begins at Address 0.

•

Three-stating the data and address buses and the PMS,

DMS, BMS, CMS, IOMS, RD, WR output drivers,

Asserting the bus grant (BG) signal, and

Halting program execution.

•

SYSTEM CONTROL REGISTER

15 14 13 12 11 10

9

8

7

6

5

4

3

0

2

1

0

1

0

1

0

DM (0x3FFF)

SPORT0A/SPORT0B ENABLED

1 = ENABLED, 0 = DISABLED

PWAIT

PROGRAM MEMORY

WAIT STATES

SPORT1 ENABLED

1 = ENABLED, 0 = DISABLED

BMS ENABLE

0 = ENABLED, 1 = DISABLED

1 = SERIAL PORT

0 = FI, FO, IRQ0, IRQ1, SCLK

Figure 9. System Control Register

–11–

REV. 0

ADSP-21mod970

If Go Mode is enabled, the modem processor will not halt pro-

gram execution until it encounters an instruction that requires

an external memory access.

of its memory mode. Therefore, it is vital that the mode pins are

set correctly PRIOR to issuing a chip reset command from the

emulator user interface. As the mode pins share functionality

with PF0:3 on the ADSP-21mod970, it may be necessary to

reset the target hardware separately to insure the proper mode

selection state on emulator chip reset. See the ADSP-2100 Fam-

ily EZ-Tools data sheet for complete information on ICE products.

If a modem processor is performing an external memory access

when an external device asserts the BR signal, it will not three-

state the memory interfaces or assert the BG signal until the

processor cycle after the access completes. The instruction does

not need to be completed when the bus is granted. If a single

instruction requires two external memory accesses, the bus will

be granted between the two accesses.

The ICE-Port interface consists of the following ADSP-21mod970

pins:

EBR

EBG

ERESET

EMS

EINT

ECLK

ELIN

ELOUT

EE

When the BR signal is released, the processor releases the BG

signal, reenables the output drivers and continues program

execution from the point where it stopped.

These ADSP-21mod970 pins must be connected only to the

EZ-ICE connector in the target system. These pins have no

function except during emulation, and do not require pull-up or

pull-down resistors. The traces for these signals between the

ADSP-21mod970 and the connector must be kept as short as

possible, no longer that 3 inches.

The bus request feature operates at all times, including when

the processor is booting and when RESET is active.

The BGH pin is asserted when a modem processor is ready to

execute an instruction, but is stopped because the external bus

is already granted to another device. The other device can release

the bus by deasserting bus request. Once the bus is released, the

modem processor deasserts BG and BGH and executes the

external memory access.

ADSP-21

mod970

ELOUT

EBR

EBG

When the ADSP-21mod970 is powered up, all the modem

processors must relinquish bus control, and only one processor

at a time may control the bus.

EINT

ELIN

ECLK

EMS

ICE-PORT

CONNECTOR

ERESET

Flag I/O Pins

Each modem processor has eight general purpose programmable

input/output flag pins. They are controlled by two memory

mapped registers. The PFTYPE register determines the direc-

tion, 1 = output and 0 = input. The PFDATA register is used to

read and write the values on the pins. Data being read from a

pin configured as an input is synchronized to the ADSP-

21mod970’s clock. Bits that are programmed as outputs will

read the value being output. The PF pins default to input dur-

ing reset.

BG

GND

EBG

EBR

BG0

BR0

RESET0

EE0

1

3

2

4

BR

BG1

BR1

RESET1

EE1

EINT

ELIN

ECLK

EMS

ERESET

6

5

KEY

ELOUT

EE

8

7

BG2

BR2

RESET2

EE2

10

12

14

9

In addition to the programmable flags, each modem processor

has three fixed-mode output flags, FL0, FL1, and FL2.

BG3

BR3

RESET3

EE3

11

13

Note: Pins PF0, PF1, PF2 and PF3 are also used for device

configuration during reset.

RESET

BG4

BR4

RESET4

EE4

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-21mod970 has on-chip emulation support and an

ICE-Port, a special set of pins that interface to the EZ-ICE.

These features allow in-circuit emulation without replacing the

target system processor by using only a 14-pin connection from

the target system to the EZ-ICE. Target systems must have a

14-pin connector to accept the EZ-ICE’s in-circuit probe, a

14-pin plug.

BG5

BR5

RESET5

EE5

Figure 10. Selecting a Modem Processor in the

ADSP-21mod970

The EZ-ICE can emulate only one modem processor at a time.

You must include hardware to select which processor in the

ADSP-21mod970 you want to emulate. Figure 10 is a functional

representation of the modem processor selection hardware. You

can use one ICE-Port connector with two ADSP-21mod970

processors without using additional buffers.

The following pins are also used by the EZ-ICE:

BR

BG

RESET

GND

The EZ-ICE uses the EE (emulator enable) signal to take con-

trol of the ADSP-21mod970 in the target system. This causes

the processor to use its ERESET, EBR and EBG pins instead of

the RESET, BR and BG pins. The BG output is three-stated.

These signals do not need to be jumper-isolated in a system.

Issuing the “chip reset” command during emulation causes the

modem processor to perform a full chip reset, including a reset

–12–

REV. 0

ADSP-21mod970

The EZ-ICE connects to target system via a ribbon cable and a

14-pin female plug. The female plug is plugged onto the 14-pin

connector (a pin strip header) on the target board.

this data sheet. The performance of the EZ-ICE may approach

published worst case specification for some memory access

timing requirements and switching characteristics.

Target Board Connector for EZ-ICE Probe

Note: If your target does not meet the worst case chip specifica-

tion for memory access parameters, you may not be able to

emulate your circuitry at the desired CLKIN frequency. De-

pending on the severity of the specification violation, you may

have trouble manufacturing your system as processor compo-

nents statistically vary in switching characteristic and timing

requirements within published limits.

The EZ-ICE connector (a standard pin strip header) is shown in

Figure 11. This connector must be added to the target board

design if the EZ-ICE is to be used. Be sure to allow enough

room in the system to fit the EZ-ICE probe onto the 14-pin

connector.

BG

GND

EBG

EBR

Restriction: All memory strobe signals on the ADSP-21mod970

(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your

target system must have 10 kΩ pull-up resistors connected when

the EZ-ICE is being used. The pull-up resistors are necessary

because there are no internal pull-ups to guarantee their state

during prolonged three-state conditions resulting from typical

EZ-ICE debugging sessions. These resistors may be removed at

your option when the EZ-ICE is not being used.

BR

EINT

ELIN

KEY (NO PIN)

ELOUT

ECLK

EMS

EE

ERESET

RESET

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some

system signals changes. Design your system to be compatible

with the following system interface signal changes introduced by

the EZ-ICE board:

Figure 11. Target Board Connector for EZ-ICE

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-

tion—you must remove Pin 7 from the header. The pins must

be 0.025 inch square and at least 0.20 inch in length. Pin spac-

ing should be 0.1 × 0.1 inches. The pin strip header must have

at least 0.15 inch clearance on all sides to accept the EZ-ICE

probe plug.

•

EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the processor on the

RESET signal.

•

EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the processor on the BR

signal.

Pin strip headers are available from vendors such as 3M,

McKenzie, and Samtec.

Target Memory Interface

•

EZ-ICE emulation ignores RESET and BR when single-

stepping.

For your target system to be compatible with the EZ-ICE emu-

lator, it must comply with the memory interface guidelines listed

below.

EZ-ICE emulation ignores RESET and BR when in Emula-

tor Space (processor halted).

PM, DM, BM, IOM, and CM

EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the

processor’s external memory bus only if bus grant (BG) is

asserted by the EZ-ICE board’s processor.

Design the Program Memory (PM), Data Memory (DM), Byte

Memory (BM), I/O Memory (IOM) and Composite Memory

(CM) external interfaces to comply with worst case device tim-

ing requirements and switching characteristics as specified in

REV. 0

–13–

ADSP-21mod970–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

Parameter

Min

Max

Unit

V_DD

T_AMB

3.15

0

3.45

+70

V

°C

ELECTRICAL CHARACTERISTICS

K/B Grades

Typ

Parameter

Test Conditions

Min

Max

Unit

V_IH

V_IL

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= max

@ V_DD= min

2.0

2.2

V

0.8

V_OH

I

_OH= –0.5 mA

@ V_DD= min

_OH= –100 µA⁶

2.4

V

I

V_DD– 0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

@ V_DD= min

I_OL= 2 mA

@ V_DD= max

0.4

10

V

_IN= V_DDmax

@ V_DD= max

_IN= 0 V

µA

I_IL

Lo-Level Input Current³

Three-State Leakage Current⁷

Supply Current (Idle)⁹

V

I_OZH

I_OZL

I_DD

@ V_DD= max

V_IN= V_DDmax⁸

@ V_DD= max

V

_IN= 0 V⁸

µA

mA

@ V_DD= 3.3

_CK= 19 ns¹⁰

t_CK= 25 ns¹⁰

_CK= 30 ns¹⁰

t

62

53

47

t

I_DD

Supply Current (Dynamic)¹¹

@ V_DD= 3.3

T_AMB= +25°C

t

_CK= 19 ns¹⁰

_CK= 25 ns¹⁰

387

299

253

mA

t_CK= 30 ns¹⁰

C_I

Input Pin Capacitance⁶

@ V_IN= 2.5 V,

f

_IN= 1.0 MHz,

40

pF

C_O

Output Pin Capacitance^{6, 7, 12}

T_AMB= +25°C

@ V_IN= 2.5 V,

f

_IN= 1.0 MHz,

T_AMB= +25°C

pF

NOTES

¹Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

²Input only pins: RESET, BR, DR0, DR1, PWD.

³Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

⁴Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.

⁵Although specified for TTL outputs, all ADSP-21mod970 outputs are CMOS-compatible and will drive to V _DDand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1.

⁸0 V on BR.

⁹Idle refers to ADSP-21mod970 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V_DDor GND.

10

11

V

= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2

IN

I

DD

and type 6, and 20% are idle instructions.

¹²Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

–14–

REV. 0

ADSP-21mod970

ABSOLUTE MAXIMUM RATINGS*

MEMORY TIMING SPECIFICATIONS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Table VI shows common memory device specifications and the

corresponding ADSP-21mod970 timing parameter.

Table VI. Memory Devices and Timing Parameters

ADSP-

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. These are stress ratings only; functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Memory

Device

21mod970

Timing

Parameter

Specification

Parameter Definition

Address Setup to

Write Start

t_ASWA0–A13, xMS Setup

before WR Low

TIMING PARAMETERS

Address Setup to

Write End

t_AW

t_WRA

t_DW

A0–A13, xMS Setup

before WR Deasserted

GENERAL NOTES

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add up parameters to derive longer times.

Address Hold Time

A0–A13, xMS Hold

before WR Low

Data Setup Time

Data Setup before WR

High

Data Hold Time

t_DH

Data Hold after WR High

RD Low to Data Valid

OE to Data Valid

t_RDD

TIMING NOTES

Address Access Time t_AA

A0–A13, xMS to Data

Valid

Switching characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

Note: xMS = PMS, DMS, BMS, CMS, IOMS.

FREQUENCY DEPENDENCY FOR TIMING

SPECIFICATIONS

t_CKis defined as 0.5 t_CKI. The ADSP-21mod970 uses an input

clock with a frequency equal to half the instruction rate: a

26.32 MHz input clock (which is equivalent to 38.0 ns) yields a

19 ns processor cycle (equivalent to 52 MHz). t_CKvalues within

the range of 0.5 t_CKIperiod should be substituted for all relevant

timing parameters to obtain the specification value.

Timing requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input for a

read operation. Timing requirements guarantee that the proces-

sor operates correctly with other devices.

Example: t_CKH= 0.5 t_CK– 7 ns = 0.5 (19 ns) – 7 ns = 2.5 ns

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

T_AMB

T_J

PD

θ_JA

=

T_J– (PD × θ_JA)

Junction Temperature in °C

Power Dissipation in W

Thermal Resistance (Junction-to-Ambient)

Package

␪

JA

PBGA

26.9°C/W

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADSP-21mod970 features proprietary ESD protection circuitry, permanent damage may occur

on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–15–

ADSP-21mod970

POWER DISSIPATION

CAPACITIVE LOADING

To determine total power dissipation in a specific application,

the following equation should be applied for each output:

Figures 13 and 14 show the capacitive loading characteristics of

the ADSP-21mod970.

C × V_DD²× f

20

C = load capacitance, f = output switching frequency.

T = +85؇C

18

V

= +3.0V

DD

16

14

12

10

8

POWER, INTERNAL

1600

1537.2

1400

3.6V

1277.1

1029

1200

1000

800

3.3V

3.0V

1008

6

4

834.9

678

0

50

100

150

200

250

C

– pF

L

600

Figure 13. Typical Output Rise Time vs. Load Capaci-

tance, C_L(at Maximum Ambient Operating Temperature)

52

33.3

FREQUENCY – MHz

POWER, IDLE

250

200

10

8

223.2

V

= 3.6V

DD

V

= 3.3V

204.6

186

DD

6

169.2

155.1

4

2

150

100

V

= 3.0V

DD

141

NOMINAL

33.33

52

FREQUENCY – MHz

–2

–4

POWER, IDLE n MODES

210

190

170

150

130

110

90

0

40

80

120

160

200

204.6

IDLE

C

– pF

L

Figure 14. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maximum Ambient Operating

Temperature)

155.1

86.3709

83.0709

82.4076

79.2

IDLE (16)

IDLE (128)

70

33.33

52

FREQUENCY – MHz

Figure 12. Power vs. Frequency

–16–

REV. 0

ADSP-21mod970

TEST CONDITIONS

Output Disable Time

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured

output high or low voltage to a high impedance state. The out-

put disable time (t_DIS) is the difference between t_MEASUREDand

output has reached a specified high or low trip point, as shown

in Figure 16. If multiple pins (such as the data bus) are enabled,

the measurement value is that of the first pin to start driving.

REFERENCE

SIGNAL

t_MEASURED

t_DIS

t

_DECAY,as shown in Figure 15. The time is the interval from

t_ENA

when a reference signal reaches a high or low voltage level to

when the output voltages have changed by 0.5 V from the mea-

sured output high or low voltage.

V

OH

V

OH

(MEASURED)

V

(MEASURED) –0.5V

(MEASURED) +0.5V

2.0V

1.0V

OH

OUTPUT

The decay time, t_DECAY, is dependent on the capacitive load,

C_L, and the current load, i_L, on the output pin. It can be ap-

proximated by the following equation:

OL

V

OL

t_DECAY

(MEASURED)

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

C_L× 0.5 V

t_DECAY

=

i_L

HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

from which

Figure 16. Output Enable/Disable

t

_DIS= t_MEASURED– t_DECAY

I

is calculated. If multiple pins (such as the data bus) are dis-

abled, the measurement value is that of the last pin to stop

driving.

OL

TO

OUTPUT

INPUT

1.5V

+1.5V

OR

OUTPUT

50pF

Figure 15. Voltage Reference Levels for AC Measure-

ments (Except Output Enable/Disable)

Output Enable Time

I

OH

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start

driving. The output enable time (t_ENA) is the interval from when

a reference signal reaches a high or low voltage level to when the

Figure 17. Equivalent Device Loading for AC Measure-

ments (Including All Fixtures)

REV. 0

–17–

ADSP-21mod970

TIMING PARAMETERS

Parameter

Min

Max

Unit

Clock Signals and Reset

Timing Requirements:

t_CKI

t_CKIL

t_CKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

38

15

100

ns

Switching Characteristics:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

0.5 t_CK– 7

0

ns

20

Control Signals

Timing Requirements:

1

t_RSP

t_MS

t_MH

RESET Width Low

Mode Setup before RESET High

Mode Setup after RESET High

5 t_CK

2

5

ns

NOTE

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

PF(3:0)

*

t_MH

t_MS

RESET

*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 18. Clock Signals

–18–

REV. 0

ADSP-21mod970

Parameter

Min

Max

Unit

Interrupts and Flags

Timing Requirements:

t_IFS

t_IFH

IRQx, FI, or PFx Setup before CLKOUT Low^{1, 2, 3, 4}

IRQx, FI, or PFx Hold after CLKOUT High^{1, 2, 3, 4}

0.25 t_CK+ 15

0.25 t_CK

ns

Switching Characteristics:

t_FOH

Flag Output Hold after CLKOUT Low⁵

t_FOD

Flag Output Delay from CLKOUT Low⁵

0.25 t_CK– 7

ns

0.5 t_CK+ 6

NOTES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the

following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further information

on interrupt servicing.)

²Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

⁴PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

⁵Flag outputs = PFx, FL0, FL1, FL2, Flag_out.

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

PFx

t_IFS

Figure 19. Interrupts and Flags

REV. 0

–19–

ADSP-21mod970

TIMING PARAMETERS

Parameter

Min

Max

Unit

Bus Request–Bus Grant

Timing Requirements:

t_BH

t_BS

BR Hold after CLKOUT High¹

BR Setup before CLKOUT Low¹

0.25 t_CK+ 2

0.25 t_CK+ 17

ns

Switching Characteristics:

t_SD

t_SDB

t_SE

t_SEC

t_SDBH

t_SEH

CLKOUT High to xMS, RD, WR Disable

0.25 t_CK+ 10

ns

xMS, RD, WR Disable to BG Low

BG High to xMS, RD, WR Enable

xMS, RD, WR Enable to CLKOUT High

xMS, RD, WR Disable to BGH Low²

BGH High to xMS, RD, WR Enable²

0

0.25 t_CK– 4

0

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS.

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized

on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.

²BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

t_SD

WR

t_SEC

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 20. Bus Request–Bus Grant

–20–

REV. 0

ADSP-21mod970

Parameter

Min

Max

Unit

Memory Read

Timing Requirements:

t_RDD

t_AA

t_RDH

RD Low to Data Valid

A0–A13, xMS to Data Valid

Data Hold from RD High

0.5 t_CK– 9 + w

0.75 t_CK– 12.5 + w

ns

0

Switching Characteristics:

t_RP

RD Pulsewidth

CLKOUT High to RD Low

A0–A13, xMS Setup before RD Low

A0–A13, xMS Hold after RD Deasserted

RD High to RD or WR Low

0.5 t_CK– 5 + w

0.25 t_CK– 5

0.25 t_CK– 6

0.25 t_CK– 3

0.5 t_CK– 5

ns

t_CRD

t_ASR

t_RDA

t_RWR

0.25 t_CK+ 7

w = wait states × t_CK

.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, IOMS,

CMS

t_RDA

RD

D

t_ASR

t_CRD

t_RP

t_RWR

t_RDD

t_RDH

t_AA

WR

Figure 21. Memory Read

REV. 0

–21–

ADSP-21mod970

TIMING PARAMETERS

Parameter

Min

Max

Unit

Memory Write

Switching Characteristics:

t_DW

t_DH

t_WP

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

t_WRA

t_WWR

Data Setup before WR High

Data Hold after WR High

WR Pulsewidth

WR Low to Data Enabled

A0–A13, xMS Setup before WR Low

Data Disable before WR or RD Low

CLKOUT High to WR Low

A0–A13, xMS, Setup before WR Deasserted

A0–A13, xMS Hold after WR Deasserted

WR High to RD or WR Low

0.5 t_CK– 7 + w

0.25 t_CK– 2

0.5 t_CK– 5 + w

0

0.25 t_CK– 6

0.25 t_CK– 7

0.25 t_CK– 5

0.75 t_CK– 9 + w

0.25 t_CK– 3

0.5 t_CK– 5

ns

0.25 t_CK+ 7

w = wait states × t_CK

.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

IOMS

t_WRA

WR

t_WWR

t_ASW

t_WP

t_AW

t_DH

t_DDR

t_CWR

D

t_DW

t_WDE

RD

Figure 22. Memory Write

–22–

REV. 0

ADSP-21mod970

Parameter

Min

Max

Unit

Serial Ports

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

38

4

7

ns

DR/TFS/RFS Setup before SCLK Low

DR/TFS/RFS Hold after SCLK Low

SCLK_INWidth

15

Switching Characteristics:

t_CC

CLKOUT High to SCLK_OUT

SCLK High to DT Enable

SCLK High to DT Valid

TFS/RFS_OUTHold after SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

0.25 t_CK

0

0.25 t_CK+ 10

ns

t_SCDE

t_SCDV

t_RH

15

0

t_RD

t_SCDH

t_TDE

t_TDV

t_SCDD

t_RDV

0

14

15

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCS

t_SCH

DR

TFS

IN

RFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

OUT

ALTERNATE

FRAME MODE

t_RDV

RFS

OUT

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

t_TDE

t_TDV

TFS

IN

ALTERNATE

FRAME MODE

t_RDV

RFS

IN

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

Figure 23. Serial Ports

REV. 0

–23–

ADSP-21mod970

TIMING PARAMETERS

Parameter

Min

Max

Unit

IDMA Address Latch

Timing Requirements:

t_IALP

t_IASU

t_IAH

t_IKA

t_IALS

t_IALD

Duration of Address Latch^{1, 2}

10

5

2

0

3

ns

IAD15–0 Address Setup before Address Latch End²

IAD15–0 Address Hold after Address Latch End²

IACK Low before Start of Address Latch^{2, 3}

Start of Write or Read after Address Latch End^{1, 2}

Address Latch Start after Address Latch End^{1, 2}

2

NOTES

¹Start of Address Latch = IS Low and IAL High.

²End of Address Latch = IS High or IAL Low.

³Start of Write or Read = IS Low and IWR Low or IRD Low.

IACK

t_IKA

t_IALD

IAL

t_IALP

IS

IAD15–0

t_IASU

t_IAH

t_IALS

RD OR WR

Figure 24. IDMA Address Latch

–24–

REV. 0

ADSP-21mod970

Parameter

Min

Max

Unit

IDMA Write, Short Write Cycle

Timing Requirements:

t_IKW

t_IWP

t_IDSU

t_IDH

IACK Low before Start of Write¹

0

15

5

ns

Duration of Write^{1, 2}

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

2

Switching Characteristic:

t_IKHW

Start of Write to IACK High

4

15

ns

NOTES

¹Start of Write = IS Low and IWR Low.

²End of Write = IS High or IWR High.

³If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

⁴If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

t_IKW

IACK

t_IKHW

IS

t_IWP

IWR

t_IDH

t_IDSU

DATA

IAD15–0

Figure 25. IDMA Write, Short Write Cycle

REV. 0

–25–

ADSP-21mod970

TIMING PARAMETERS

Parameter

Min

Max

Unit

IDMA Write, Long Write Cycle

Timing Requirements:

t_IKW

t_IKSU

t_IKH

IACK Low before Start of Write¹

0

ns

IAD15–0 Data Setup before IACK Low^{2, 3, 4}

IAD15–0 Data Hold after IACK Low^{2, 3, 4}

0.5 t_CK+ 10

2

Switching Characteristics:

t_IKLW

Start of Write to IACK Low⁴

t_IKHWStart of Write to IACK High

1.5 t_CK

4

ns

15

NOTES

¹Start of Write = IS Low and IWR Low.

²If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

³If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

⁴This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition.

t_IKW

IACK

t_IKHW

t_IKLW

IS

IWR

t_IKSU

t_IKH

DATA

IAD15–0

Figure 26. IDMA Write, Long Write Cycle

–26–

REV. 0

ADSP-21mod970

Parameter

Min

Max

Unit

IDMA Read, Long Read Cycle

Timing Requirements:

t_IKR

t_IRK

IACK Low before Start of Read¹

End of Read after IACK Low²

0

2

ns

Switching Characteristics:

t_IKHR

t_IKDS

t_IKDH

t_IKDD

t_IRDE

t_IRDV

t_IRDH1

t_IRDH2

IACK High after Start of Read¹

4

15

ns

IAD15–0 Data Setup before IACK Low

0.5 t_CK– 7

0

IAD15–0 Data Hold after End of Read²

IAD15–0 Data Disabled after End of Read²

10

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

IAD15–0 Previous Data Hold after Start of Read (DM/PM1)³

IAD15–0 Previous Data Hold after Start of Read (PM2)⁴

0

2 t_CK– 5

t_CK– 5

NOTES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

³DM read or first half of PM read.

⁴Second half of PM read.

IACK

IS

t_IKHR

t_IKR

t_IRK

IRD

t_IKDH

t_IKDS

t_IRDE

READ

DATA

IAD15–0

t_IRDV

t_IKDD

t_IRDH

Figure 27. IDMA Read, Long Read Cycle

REV. 0

–27–

ADSP-21mod970

TIMING PARAMETERS

Parameter

Min

Max

Unit

IDMA Read, Short Read Cycle

Timing Requirements:

t_IKR

t_IRP

IACK Low before Start of Read¹

Duration of Read

0

15

ns

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High after Start of Read¹

4

0

15

10

ns

IAD15–0 Data Hold after End of Read²

IAD15–0 Data Disabled after End of Read²

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

0

NOTES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

IACK

IS

t_IKR

t_IKHR

t_IRP

IRD

t_IRDE

t_IKDH

IAD15–0

t_IKDD

t_IRDV

Figure 28. IDMA Read, Short Read Cycle

–28–

REV. 0

ADSP-21mod970

304-Ball PBGA Package Pinout

The ADSP-21mod970 package pinout is shown in the table below.

Ball

Number

Signal

Name

Ball

Number

Signal

Name

Ball

Number

Signal

Name

Ball

Number

Signal

Name

A1

GND

PF0_1

PF2_1

FL1_1

D23_1

D21_1

D13_1

D16_1

GND

PF0_2

PF1_2

FL0_2

FL1_2

V_DD

B23

C1

IAD1

D22

D23

E1

IAD4

K4

CMS_1

PF5_3

EBG

A2

IAD5_1

IAD0_1

GND

IAD3

K20

K21

K22

K23

L1

A3

C2

IAD8_1

IAD7_1

IAD2_1

IAD1_1

CLKIN

GND

A4

C3

E2

EBR

A5

C4

BGH_1

PF3_1

FL2_1

D12_1

D17_1

GND

E3

EINT

D17

A6

C5

E4

A7

C6

E20

E21

E22

E23

F1

L2

D18

A8

C7

L3

PF5_1

PF7_1

V_DD

A9

C8

GND

L4

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

B1

C9

GND

L20

L21

L22

L23

M1

M2

M3

M4

M20

M21

M22

M23

N1

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

D1

IAD13_1

IAD15_1

PF2_2

V_DD

IAD12_1

IAD9_1

IAD10_1

IWR_1

GND

ERESET

ELIN

ELOUT

D15

F2

F3

F4

V_DD

F20

F21

F22

F23

G1

G2

G3

G4

G20

G21

G22

G23

H1

H2

H3

H4

H20

H21

H22

H23

J1

D16

PF0_3

PF1_3

FL0_3

FL1_3

D21

V_DD

GND

PF6_1

BGH_4

V_DD

IS_2

GND

CLKOUT_2

PF4_2

DT1_2

EE_2

GND

CLKIN_1

IAD11_1

D8_1

V_DD

D22

V_DD

D23

GND

IRD_1

IAL

D13

GND

IAD3_1

GND

PF1_1

FL0_1

D22_1

D20_1

D19_1

D15_1

GND

D14_1

BGH_2

PF3_2

FL2_2

V_DD

IAD2

N2

D12

IAD0

IRD

N3

D14

B2

IAD6_1

IAD4_1

A0_1

IWR

N4

PF1_4

V_DD

B3

D2

GND

N20

N21

N22

N23

P1

B4

D3

RD_1

PF6_3

ECLK

EMS

B5

D4

GND

WR_1

B6

D5

D10_1

D11_1

D9_1

IAL_1

IS_1

B7

D6

GND

TFS0_1

DT1_3

PF2_6

RESET_3

EE_3

IAD6

IAD7

IAD5

PF0_4

PF0_6

PF1_6

FL2_6

FL1_6

B8

D7

CLKOUT_3

RFS0A

DR0A

IS_3

P2

B9

D8

D18_1

GND

P3

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

D9

P4

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

IAD14_1

BR_1

P20

P21

P22

P23

R1

DMS_1

BMS_1

PMS_1

CLKOUT_1

SCLK0A

PF4_3

BG_3

BG_1

J2

IACK_1

V_DD

J3

V_DD

J4

BGH_3

PF2_3

PF3_3

FL2_3

D20

V_DD

J20

J21

J22

J23

K1

R2

BG_2

R3

BR_2

R4

PF5_2

RESET_2

GND

BR_3

R20

R21

R22

R23

D19

DT0A

GND

K2

PF4_1

IOMS_1

GND

K3

REV. 0

–29–

ADSP-21mod970

304-Ball PBGA Package Pinout (continued)

Ball

Number

Signal

Name

Ball

Number

Signal

Name

Ball

Number

Signal

Name

Ball

Number

Signal

Name

T1

D10

W23

Y1

GND

V_DD

AA8

PF4_5

GND

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

PF2_5

CLKOUT_6

RFS0B

GND

T2

D9

AA9

T3

D11

Y2

V_DD

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AB1

PF6_5

V_DD

T4

EE_1

Y3

V_DD

T20

T21

T22

T23

U1

BGH_6

TFS0_3

PF3_6

FL0_6

IAD9

Y4

GND

FL0_4

V_DD

DT1_5

BGH_5

PF7_2

PF1_5

FL1_5

TFS1

DR1

SCLK0B

RESET_6

GND

Y5

Y6

Y7

FL2_4

CLKOUT_5

GND

IS_5

BG_6

Y8

GND

U2

IAD11

IAD8

Y9

AC2

BR_4

U3

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AC3

PF7_4

GND

U4

PF2_4

GND

IAD10

IAD12

DT1_1

PF3_4

GND

D8

V_DD

GND

AC4

U20

U21

U22

U23

V1

TFS0_2

PF6_2

PF0_5

FL0_5

FL2_5

RFS1

SCLK1

GND

BR_5

IAD13

IACK

PF4_4

BG_4

GND

FL1_4

V_DD

DT1_6

GND

AC5

TFS0_4

V_DD

AC6

BG_5

IAD14

PF5_4

GND

AC7

V_DD

AC8

GND

AC9

GND

V2

AB2

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

TFS0_5

V_DD

V3

AB3

PF6_4

GND

V4

AB4

EE_5

V20

V21

V22

V23

W1

W2

W3

W4

W20

W21

W22

AB5

DT1_4

V_DD

PF5_6

GND

AB6

AB7

RESET_4

PF5_5

GND

PF6_6

PF7_6

DT0B

TFS0_6

GND

AB8

AB9

CLKOUT_4

RESET_1

IS_4

AB10

AB11

AB12

AB13

AB14

AB15

PF7_5

V_DD

RESET_5

PF4_6

GND

DR0B

EE_6

IS_6

PF7_3

IAD15

BR_6

EE_4

PF3_5

GND

ORDERING GUIDE

Part

Number

Ambient

Temperature Range

Package

Description

Package

Option

Processor Clock

26.0 MHz

ADSP-21mod970-000

0°C to +70°C

304-Ball PBGA

B-304


型号：	ADSP-21MOD970-000
厂家：	ETC
描述：	DSP For MODEM DSP调制解调器\n 调制解调器
文件：	总32页 (文件大小：258K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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