ADSP-BF527BBCZ-5A_技术文档

Blackfin

Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

FEATURES

PERIPHERALS

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

USB 2.0 high speed on-the-go (OTG) with integrated PHY

IEEE 802.3-compliant 10/100 Ethernet MAC

Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Accepts a wide range of supply voltages for internal and I/O

operations. See Specifications on Page 28

Programmable on-chip voltage regulator (ADSP-BF523/

ADSP-BF525/ADSP-BF527 processors only)

Qualified for Automotive Applications. See Automotive

Products on Page 87

Host DMA port (HOSTDP)

2 dual-channel, full-duplex synchronous serial ports

(SPORTs), supporting eight stereo I²S channels

12 peripheral DMAs, 2 mastered by the Ethernet MAC

2 memory-to-memory DMAs with external request lines

Event handler with 54 interrupt inputs

Serial peripheral interface (SPI) compatible port

2 UARTs with IrDA support

289-ball and 208-ball CSP_BGA packages

2-wire interface (TWI) controller

Eight 32-bit timers/counters with PWM support

32-bit up/down counter with rotary support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), with programmable

hysteresis

NAND flash controller (NFC)

Debug/JTAG interface

On-chip PLL capable of frequency multiplication

MEMORY

132K bytes of on-chip memory (See Table 1 on Page 3 for L1

and L3 memory size details)

External memory controller with glueless support for SDRAM

and asynchronous 8-bit and 16-bit memories

Flexible booting options from external flash, SPI, and TWI

memory or from host devices including SPI, TWI, and UART

Code security with Lockbox Secure Technology

one-time-programmable (OTP) memory

Memory management unit providing memory protection

WATCHDOG TIMER

OTP MEMORY

RTC

VOLTAGE REGULATOR*

JTAG TEST AND EMULATION

COUNTER

SPORT0

SPORT1

UART1

UART0

NFC

PERIPHERAL

ACCESS BUS

INTERRUPT

CONTROLLER

GPIO

PORT F

B

L1 INSTRUCTION

MEMORY

L1 DATA

MEMORY

GPIO

PORT G

DMA

CONTROLLER

PPI

DMA

ACCESS

BUS

EAB

16

SPI

DCB

USB

TIMER7-1

GPIO

PORT H

DEB

TIMER0

BOOT

ROM

EXTERNAL PORT

EMAC

HOST DMA

TWI

FLASH, SDRAM CONTROL

PORT J

*REGULATOR ONLY AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS

Figure 1. Processor Block Diagram

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

TABLE OF CONTENTS

Features ................................................................. 1

Memory ................................................................ 1

Peripherals ............................................................. 1

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

Processor Peripherals ............................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 9

Host DMA Port .................................................... 9

Real-Time Clock ................................................... 9

Watchdog Timer ................................................ 10

Timers ............................................................. 10

Up/Down Counter and Thumbwheel Interface .......... 10

Serial Ports ........................................................ 10

Serial Peripheral Interface (SPI) Port ....................... 11

UART Ports ...................................................... 11

TWI Controller Interface ...................................... 12

10/100 Ethernet MAC .......................................... 12

Ports ................................................................ 12

Parallel Peripheral Interface (PPI) ........................... 13

USB On-The-Go Dual-Role Device Controller ........... 14

Code Security with Lockbox Secure Technology ......... 14

Dynamic Power Management ................................ 14

Clock Signals ...................................................... 16

Booting Modes ................................................... 18

Instruction Set Description .................................... 20

Development Tools .............................................. 20

Additional Information ........................................ 21

Related Signal Chains ........................................... 22

Lockbox Secure Technology Disclaimer .................... 22

Signal Descriptions ................................................. 23

Specifications ........................................................ 28

Operating Conditions

for ADSP-BF522/ADSP-BF524/ADSP-BF526

Processors ...................................................... 28

Operating Conditions for ADSP-BF523/ADSP-BF525/

ADSP-BF527 Processors .................................... 30

Electrical Characteristics ....................................... 32

Absolute Maximum Ratings ................................... 37

Package Information ............................................ 38

ESD Sensitivity ................................................... 38

Timing Specifications ........................................... 39

Output Drive Currents ......................................... 73

Test Conditions .................................................. 75

Environmental Conditions .................................... 79

289-Ball CSP_BGA Ball Assignment ........................... 80

208-Ball CSP_BGA Ball Assignment ........................... 83

Outline Dimensions ................................................ 86

Surface-Mount Design .......................................... 87

Automotive Products .............................................. 87

Ordering Guide ..................................................... 88

ADSP-BF523/ADSP-BF525/ADSP-BF527

Voltage Regulation ........................................... 16

ADSP-BF522/ADSP-BF524/ADSP-BF526

Voltage Regulation ........................................... 16

REVISION HISTORY

7/13—Rev. C to Rev. D

Updated Development Tools .................................... 20

Corrected footnote 9 and added footnote 11 in

Operating Conditions for ADSP-BF523/ADSP-BF525/

ADSP-BF527 Processors .......................................... 30

Rev. D

| Page 2 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

GENERAL DESCRIPTION

The ADSP-BF52x processors are members of the Blackfin fam-

ily of products, incorporating the Analog Devices/Intel Micro

Signal Architecture (MSA). Blackfin^®processors combine a

dual-MAC state-of-the-art signal processing engine, the advan-

tages of a clean, orthogonal RISC-like microprocessor

instruction set, and single-instruction, multiple-data (SIMD)

multimedia capabilities into a single instruction-set

architecture.

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like program-

mability, multimedia support, and leading-edge signal

processing in one integrated package.

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. They are produced with a low power and low

voltage design methodology and feature on-chip dynamic

power management, which is the ability to vary both the voltage

and frequency of operation to significantly lower overall power

consumption. This capability can result in a substantial reduc-

tion in power consumption, compared with just varying the

frequency of operation. This allows longer battery life for

portable appliances.

The ADSP-BF52x processors are completely code compatible

with other Blackfin processors. The ADSP-BF523/

ADSP-BF525/ADSP-BF527 processors offer performance up to

600 MHz. The ADSP-BF522/ADSP-BF524/ADSP-BF526 pro-

cessors offer performance up to 400 MHz and reduced static

power consumption. Differences with respect to peripheral

combinations are shown in Table 1.

Table 1. Processor Comparison

SYSTEM INTEGRATION

The ADSP-BF52x processors are highly integrated system-on-a-

chip solutions for the next generation of embedded network

connected applications. By combining industry-standard inter-

faces with a high performance signal processing core, cost-

effective applications can be developed quickly, without the

need for costly external components. The system peripherals

include an IEEE-compliant 802.3 10/100 Ethernet MAC, a USB

2.0 high speed OTG controller, a TWI controller, a NAND flash

controller, two UART ports, an SPI port, two serial ports

(SPORTs), eight general purpose 32-bit timers with PWM capa-

bility, a core timer, a real-time clock, a watchdog timer, a Host

DMA (HOSTDP) interface, and a parallel peripheral interface

(PPI).

Feature

Host DMA

1

–

1

2

1

8

1

–

1

2

1

8

1

–

1

2

1

8

1

–

1

2

1

8

1

–

1

2

1

8

1

2

1

8

1

USB

Ethernet MAC

Internal Voltage Regulator

TWI

SPORTs

UARTs

SPI

PROCESSOR PERIPHERALS

GP Timers

GP Counter

Watchdog Timers

RTC

The ADSP-BF52x processors contain a rich set of peripherals

connected to the core via several high bandwidth buses, provid-

ing flexibility in system configuration as well as excellent overall

system performance (see the block diagram on Page 1).

Parallel Peripheral Interface

GPIOs

These Blackfin processors contain dedicated network commu-

nication modules and high speed serial and parallel ports, an

interrupt controller for flexible management of interrupts from

the on-chip peripherals or external sources, and power manage-

ment control functions to tailor the performance and power

characteristics of the processor and system to many application

scenarios.

48 48 48 48 48 48

48K 48K 48K 48K 48K 48K

L1 Instruction SRAM

L1 Instruction SRAM/Cache 16K 16K 16K 16K 16K 16K

L1 Data SRAM

32K 32K 32K 32K 32K 32K

4K 4K 4K 4K 4K 4K

32K 32K 32K 32K 32K 32K

L1 Data SRAM/Cache

L1 Scratchpad

L3 Boot ROM

All of the peripherals, except for the general-purpose I/O, TWI,

real-time clock, and timers, are supported by a flexible DMA

structure. There are also separate memory DMA channels dedi-

cated to data transfers between the processor's various memory

spaces, including external SDRAM and asynchronous memory.

Multiple on-chip buses running at up to 133 MHz provide

enough bandwidth to keep the processor core running along

with activity on all of the on-chip and external peripherals.

Maximum Instruction Rate¹

Maximum System Clock Speed

Package Options

400 MHz

100 MHz

600 MHz

133 MHz

289-Ball CSP_BGA

208-Ball CSP_BGA

¹Maximum instruction rate is not available with every possible SCLK selection.

The ADSP-BF523/ADSP-BF525/ADSP-BF527 processors

include an on-chip voltage regulator in support of the proces-

sor’s dynamic power management capability. The voltage

Rev. D

| Page 3 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

regulator provides a range of core voltage levels when supplied

from V_DDEXT. The voltage regulator can be bypassed at the user's

discretion.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

BLACKFIN PROCESSOR CORE

As shown in Figure 2, the Blackfin processor core contains two

16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,

four video ALUs, and a 40-bit shifter. The computation units

process 8-, 16-, or 32-bit data from the register file.

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation

are supported.

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

P3

DAG0

P2

P1

P0

DA1

DA0

32

RAB

32

PREG

SD

LD1

LD0

32

ASTAT

32

SEQUENCER

R7.H

R7.L

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

ALIGN

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

A0

A1

CONTROL

UNIT

32

DATAARITHMETIC UNIT

Figure 2. Blackfin Processor Core

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2³²multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations,

16-bit and 8-bit adds with clipping, 8-bit average operations,

and 8-bit subtract/absolute value/accumulate (SAA) operations.

Also provided are the compare/select and vector search

instructions.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If the second ALU is used,

quad 16-bit operations are possible.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

Rev. D

| Page 4 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

0xFFFF FFFF

CORE MMR REGISTERS (2M BYTES)

SYSTEM MMR REGISTERS (2M BYTES)

RESERVED

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 C000

0xFFA0 8000

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

SCRATCHPAD SRAM (4K BYTES)

RESERVED

INSTRUCTION SRAM / CACHE (16K BYTES)

RESERVED

INSTRUCTION BANK B SRAM (16K BYTES)

INSTRUCTION BANK A SRAM (32K BYTES)

RESERVED

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

0xFFA0 0000

0xFF90 8000

DATA BANK B SRAM / CACHE (16K BYTES)

DATA BANK B SRAM (16K BYTES)

RESERVED

0xFF90 4000

0xFF90 0000

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

0xFF80 8000

0xFF80 4000

DATA BANK A SRAM / CACHE (16K BYTES)

DATA BANK A SRAM (16K BYTES)

0xFF80 0000

0xEF00 8000

0xEF00 0000

RESERVED

BOOT ROM (32K BYTES)

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

RESERVED

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x08 00 0000

0x0000 0000

ASYNC MEMORY BANK 3 (1M BYTES)

ASYNC MEMORY BANK 2 (1M BYTES)

ASYNC MEMORY BANK 1 (1M BYTES)

ASYNC MEMORY BANK 0 (1M BYTES)

RESERVED

SDRAM MEMORY (16M BYTES 128M BYTES)

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

Figure 3. Internal/External Memory Map

Internal (On-Chip) Memory

The processor has three blocks of on-chip memory providing

high-bandwidth access to the core.

MEMORY ARCHITECTURE

The Blackfin processor views memory as a single unified

4G byte address space, using 32-bit addresses. All resources,

including internal memory, external memory, and I/O control

registers, occupy separate sections of this common address

space. The memory portions of this address space are arranged

in a hierarchical structure to provide a good cost/performance

balance of some very fast, low-latency on-chip memory as cache

or SRAM, and larger, lower-cost and performance off-chip

memory systems. See Figure 3.

The first block is the L1 instruction memory, consisting of

64K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

The second on-chip memory block is the L1 data memory, con-

sisting of up to two banks of up to 32K bytes each. Each memory

bank is configurable, offering both cache and SRAM functional-

ity. This memory block is accessed at full processor speed.

The on-chip L1 memory system is the highest-performance

memory available to the Blackfin processor. The off-chip

memory system, accessed through the external bus interface

unit (EBIU), provides expansion with SDRAM, flash memory,

and SRAM, optionally accessing up to 132M bytes of

physical memory.

The third memory block is a 4K byte scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM), as well as up to four banks of asynchronous memory

devices including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

The memory DMA controller provides high-bandwidth data-

movement capability. It can perform block transfers of code

or data between the internal memory and the external

memory spaces.

Rev. D

| Page 5 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

The SDRAM controller can be programmed to interface to up

to 128M bytes of SDRAM. A separate row can be open for each

SDRAM internal bank and the SDRAM controller supports up

to 4 internal SDRAM banks, improving overall performance.

ID, MAC address, etc. Hence, generic parts can be shipped,

which are then programmed and protected by the developer

within this non-volatile memory.

I/O Memory Space

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

requirements for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks are only contiguous if each is fully populated

with 1M byte of memory.

The processor does not define a separate I/O space. All

resources are mapped through the flat 32-bit address space.

On-chip I/O devices have their control registers mapped into

memory-mapped registers (MMRs) at addresses near the top of

the 4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The MMRs are accessible only in supervisor mode and appear

as reserved space to on-chip peripherals.

NAND Flash Controller (NFC)

The ADSP-BF52x processors provide a NAND flash controller

(NFC). NAND flash devices provide high-density, low-cost

memory. However, NAND flash devices also have long random

access times, invalid blocks, and lower reliability over device

lifetimes. Because of this, NAND flash is often used for read-

only code storage. In this case, all DSP code can be stored in

NAND flash and then transferred to a faster memory (such as

SDRAM or SRAM) before execution. Another common use of

NAND flash is for storage of multimedia files or other large data

segments. In this case, a software file system may be used to

manage reading and writing of the NAND flash device. The file

system selects memory segments for storage with the goal of

avoiding bad blocks and equally distributing memory accesses

across all address locations. Hardware features of the NFC

include:

Booting

The processor contains a small on-chip boot kernel, which con-

figures the appropriate peripheral for booting. If the processor is

configured to boot from boot ROM memory space, the proces-

sor starts executing from the on-chip boot ROM. For more

information, see Booting Modes on Page 18.

Event Handling

The event controller on the processor handles all asynchronous

and synchronous events to the processor. The processor pro-

vides event handling that supports both nesting and

prioritization. Nesting allows multiple event service routines to

be active simultaneously. Prioritization ensures that servicing of

a higher-priority event takes precedence over servicing of a

lower-priority event. The controller provides support for five

different types of events:

• Support for page program, page read, and block erase of

NAND flash devices, with accesses aligned to page

boundaries.

• Error checking and correction (ECC) hardware that facili-

tates error detection and correction.

• Emulation — An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• A single 8-bit external bus interface for commands,

addresses, and data.

• Support for SLC (single level cell) NAND flash devices

unlimited in size, with page sizes of 256 and 512 bytes.

Larger page sizes can be supported in software.

• RESET — This event resets the processor.

• Nonmaskable Interrupt (NMI) — The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

• Capability of releasing external bus interface pins during

long accesses.

• Support for internal bus requests of 16 bits.

• Exceptions — Events that occur synchronously to program

flow (in other words, the exception is taken before the

instruction is allowed to complete). Conditions such as

data alignment violations and undefined instructions cause

exceptions.

• DMA engine to transfer data between internal memory and

NAND flash device.

One-Time Programmable Memory

The processor has 64K bits of one-time programmable non-

volatile memory that can be programmed by the developer only

one time. It includes the array and logic to support read access

and programming. Additionally, its pages can be write

protected.

• Interrupts — Events that occur asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

OTP enables developers to store both public and private data

on-chip. In addition to storing public and private key data for

applications requiring security, it also allows developers to store

completely user-definable data such as customer ID, product

The processor event controller consists of two stages, the core

event controller (CEC) and the system interrupt controller

(SIC). The core event controller works with the system interrupt

Rev. D

| Page 6 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

controller to prioritize and control all system events. Conceptu-

ally, interrupts from the peripherals enter into the SIC and are

then routed directly into the general-purpose interrupts of the

CEC.

Table 2. Core Event Controller (CEC)

Priority

(0 is Highest) Event Class

EVT Entry

EMU

0

Emulation/Test Control

RESET

Core Event Controller (CEC)

1

RST

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority

interrupts (IVG15–14) are recommended to be reserved for

software interrupt handlers, leaving seven prioritized interrupt

inputs to support the peripherals of the processor. Table 2

describes the inputs to the CEC, identifies their names in the

event vector table (EVT), and lists their priorities.

2

Nonmaskable Interrupt

Exception

NMI

3

EVX

4

Reserved

—

5

Hardware Error

IVHW

IVTMR

IVG7

6

Core Timer

7

General-Purpose Interrupt 7

General-Purpose Interrupt 8

General-Purpose Interrupt 9

General-Purpose Interrupt 10

General-Purpose Interrupt 11

General-Purpose Interrupt 12

General-Purpose Interrupt 13

General-Purpose Interrupt 14

General-Purpose Interrupt 15

8

IVG8

System Interrupt Controller (SIC)

9

IVG9

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Although the processor provides a default mapping, the user

can alter the mappings and priorities of interrupt events by writ-

ing the appropriate values into the interrupt assignment

registers (SIC_IARx). Table 3 describes the inputs into the SIC

and the default mappings into the CEC.

Table 3. System Interrupt Controller (SIC)

General Purpose

Default

Core Interrupt ID

SIC Registers

Peripheral Interrupt Event

PLL Wakeup Interrupt

DMA Error 0 (generic)

DMAR0 Block Interrupt

DMAR1 Block Interrupt

DMAR0 Overflow Error

DMAR1 Overflow Error

PPI Error

Interrupt (at RESET) Peripheral Interrupt ID

IVG7

IVG8

IVG9

IVG10

0

1

2

3

IAR0 IMASK0, ISR0, IWR0

IAR1 IMASK0, ISR0, IWR0

IAR2 IMASK0, ISR0, IWR0

IAR3 IMASK0, ISR0, IWR0

1

2

3

4

5

6

MAC Status

7

SPORT0 Status

8

SPORT1 Status

9

Reserved

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Reserved

UART0 Status

UART1 Status

RTC

DMA Channel 0 (PPI/NFC)

DMA Channel 3 (SPORT0 RX)

DMA Channel 4 (SPORT0 TX)

DMA Channel 5 (SPORT1 RX)

DMA Channel 6 (SPORT1 TX)

TWI

DMA Channel 7 (SPI)

DMA Channel 8 (UART0 RX)

DMA Channel 9 (UART0 TX)

DMA Channel 10 (UART1 RX)

DMA Channel 11 (UART1 TX)

Rev. D

|

Page 7 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 3. System Interrupt Controller (SIC) (Continued)

General Purpose

Default

Core Interrupt ID

Peripheral Interrupt Event

OTP Memory Interrupt

GP Counter

Interrupt (at RESET) Peripheral Interrupt ID

SIC Registers

IVG11

IVG12

IVG13

IVG7

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

4

5

6

0

3

IAR3 IMASK0, ISR0, IWR0

IAR4 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

DMA Channel 1 (MAC RX/HOSTDP)

Port H Interrupt A

DMA Channel 2 (MAC TX/NFC)

Port H Interrupt B

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

Timer 5

Timer 6

Timer 7

Port G Interrupt A

Port G Interrupt B

MDMA Stream 0

MDMA Stream 1

Software Watchdog Timer

Port F Interrupt A

Port F Interrupt B

SPI Status

NFC Status

IVG7

HOSTDP Status

Host Read Done

Reserved

IVG7

IVG10

USB_INT0 Interrupt

USB_INT1 Interrupt

USB_INT2 Interrupt

USB_DMAINT Interrupt

Event Control

The processor provides a very flexible mechanism to control the

processing of events. In the CEC, three registers are used to

coordinate and control events. Each register is 16 bits wide.

written while in supervisor mode. (Note that general-

purpose interrupts can be globally enabled and disabled

with the STI and CLI instructions, respectively.)

• CEC interrupt latch register (ILAT) — Indicates when

events have been latched. The appropriate bit is set when

the processor has latched the event and cleared when the

event has been accepted into the system. This register is

updated automatically by the controller, but it may be writ-

ten only when its corresponding IMASK bit is cleared.

• CEC interrupt pending register (IPEND) — The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing

three pairs of 32-bit interrupt control and status registers. Each

register contains a bit corresponding to each of the peripheral

interrupt events shown in Table 3 on Page 7.

• CEC interrupt mask register (IMASK) — Controls the

masking and unmasking of individual events. When a bit is

set in the IMASK register, that event is unmasked and is

processed by the CEC when asserted. A cleared bit in the

IMASK register masks the event, preventing the processor

from servicing the event even though the event may be

latched in the ILAT register. This register may be read or

• SIC interrupt mask registers (SIC_IMASKx) — Control the

masking and unmasking of each peripheral interrupt event.

When a bit is set in these registers, that peripheral event is

Rev. D

| Page 8 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

unmasked and is processed by the system when asserted. A

cleared bit in the register masks the peripheral event, pre-

venting the processor from servicing the event.

Examples of DMA types supported by the processor DMA con-

troller include:

• A single, linear buffer that stops upon completion.

• SIC interrupt status registers (SIC_ISRx) — As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer.

• 1-D or 2-D DMA using a linked list of descriptors.

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page.

• SIC interrupt wakeup enable registers (SIC_IWRx) — By

enabling the corresponding bit in these registers, a periph-

eral can be configured to wake up the processor, should the

core be idled or in sleep mode when the event is generated.

For more information see Dynamic Power Management on

Page 14.

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels provided for transfers between the

various memories of the processor system. This enables trans-

fers of blocks of data between any of the memories—including

external SDRAM, ROM, SRAM, and flash memory—with mini-

mal processor intervention. Memory DMA transfers can be

controlled by a very flexible descriptor-based methodology or

by a standard register-based autobuffer mechanism.

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND

register contents are monitored by the SIC as the interrupt

acknowledgement.

The processor also has an external DMA controller capability

via dual external DMA request pins when used in conjunction

with the external bus interface unit (EBIU). This functionality

can be used when a high speed interface is required for external

FIFOs and high bandwidth communications peripherals such as

USB 2.0. It allows control of the number of data transfers for

memory DMA. The number of transfers per edge is program-

mable. This feature can be programmed to allow memory

DMA to have an increased priority on the external bus relative

to the core.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC recognizes and queues the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

HOST DMA PORT

The host port interface allows an external host to be a DMA

master to transfer data in and out of the device. The host device

masters the transactions and the Blackfin processor is the

DMA slave.

DMA CONTROLLERS

The processor has multiple, independent DMA channels that

support automated data transfers with minimal overhead for

the processor core. DMA transfers can occur between the

processor's internal memories and any of its DMA-capable

peripherals. Additionally, DMA transfers can be accomplished

between any of the DMA-capable peripherals and external

devices connected to the external memory interfaces, including

the SDRAM controller and the asynchronous memory control-

ler. DMA-capable peripherals include the Ethernet MAC, NFC,

HOSTDP, USB, SPORTs, SPI port, UARTs, and PPI. Each indi-

vidual DMA-capable peripheral has at least one dedicated DMA

channel.

The host port is enabled through the PAB interface. Once

enabled, the DMA is controlled by the external host, which can

then program the DMA to send/receive data to any valid inter-

nal or external memory location.

The host port interface controller has the following features.

• Allows external master to configure DMA read/write data

transfers and read port status.

• Uses asynchronous memory protocol for external interface.

• 8-/16-bit external data interface to host device.

• Half duplex operation.

• Little-/big-endian data transfer.

The processor DMA controller supports both one-dimensional

(1-D) and two-dimensional (2-D) DMA transfers. DMA trans-

fer initialization can be implemented from registers or from sets

of parameters called descriptor blocks.

• Acknowledge mode allows flow control on host

transactions.

• Interrupt mode guarantees a burst of FIFO depth host

transactions.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

REAL-TIME CLOCK

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the Blackfin

processor. Connect RTC pins RTXI and RTXO with external

Rev. D

| Page 9 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

components as shown in Figure 4.

unknown state where software, which would normally reset the

timer, has stopped running due to an external noise condition

or software error.

RTXI

RTXO

If configured to generate a hardware reset, the watchdog timer

resets both the core and the processor peripherals. After a reset,

software can determine if the watchdog was the source of the

hardware reset by interrogating a status bit in the watchdog

timer control register.

R1

X1

C1

C2

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f_SCLK

.

TIMERS

SUGGESTED COMPONENTS:

X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR

There are nine general-purpose programmable timer units in

the processors. Eight timers have an external pin that can be

configured either as a pulse width modulator (PWM) or timer

output, as an input to clock the timer, or as a mechanism for

measuring pulse widths and periods of external events. These

timers can be synchronized to an external clock input to the sev-

eral other associated PF pins, an external clock input to the

PPI_CLK input pin, or to the internal SCLK.

EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)

C1 = 22 pF

C2 = 22 pF

R1 = 10 M:

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

Figure 4. External Components for RTC

The RTC peripheral has dedicated power supply pins so that it

can remain powered up and clocked even when the rest of the

processor is in a low power state. The RTC provides several pro-

grammable interrupt options, including interrupt per second,

minute, hour, or day clock ticks, interrupt on programmable

stopwatch countdown, or interrupt at a programmed alarm

time.

The timer units can be used in conjunction with the two UARTs

to measure the width of the pulses in the data stream to provide

a software auto-baud detect function for the respective serial

channels.

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter.

In addition to the eight general-purpose programmable timers,

a ninth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generation of operating system periodic interrupts.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day. The second alarm is for a day and time of

that day.

UP/DOWN COUNTER AND THUMBWHEEL

INTERFACE

A 32-bit up/down counter is provided that can sense 2-bit

quadrature or binary codes as typically emitted by industrial

drives or manual thumb wheels. The counter can also operate in

general-purpose up/down count modes. Then, count direction

is either controlled by a level-sensitive input pin or by two edge

detectors.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch is

enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the processor

from sleep mode upon generation of any RTC wake-up event.

Additionally, an RTC wakeup event can wake up the processor

from deep sleep mode or cause a transition from the hibernate

state.

A third input can provide flexible zero marker support and can

alternatively be used to input the push-button signal of thumb

wheels. All three pins have a programmable debouncing circuit.

An internal signal forwarded to the timer unit enables one timer

to measure the intervals between count events. Boundary regis-

ters enable auto-zero operation or simple system warning by

interrupts when programmable count values are exceeded.

WATCHDOG TIMER

The processor includes a 32-bit timer that can be used to imple-

ment a software watchdog function. A software watchdog can

improve system availability by forcing the processor to a known

state through generation of a hardware reset, nonmaskable

interrupt (NMI), or general-purpose interrupt, if the timer

expires before being reset by software. The programmer initial-

izes the count value of the timer, enables the appropriate

interrupt, then enables the timer. Thereafter, the software must

reload the counter before it counts to zero from the pro-

grammed value. This protects the system from remaining in an

SERIAL PORTS

The processors incorporate two dual-channel synchronous

serial ports (SPORT0 and SPORT1) for serial and multiproces-

sor communications. The SPORTs support the following

features:

• I²S capable operation.

Rev. D

|

Page 10 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

• Bidirectional operation — Each SPORT has two sets of

independent transmit and receive pins, enabling eight

channels of I²S stereo audio.

The SPI port’s clock rate is calculated as:

f_SCLK

SPI Clock Rate = -----------------------------------

2  SPI_BAUD

• Buffered (8-deep) transmit and receive ports — Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

Where the 16-bit SPI_BAUD register contains a value of 2

to 65,535.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

• Clocking — Each transmit and receive port can either use

an external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-bit

first or least-significant-bit first.

UART PORTS

The processors provide two full-duplex universal asynchronous

receiver/transmitter (UART) ports, which are fully compatible

with PC-standard UARTs. Each UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. A UART port includes support for five to eight data bits,

one or two stop bits, and none, even, or odd parity. Each UART

port supports two modes of operation:

• Framing — Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

• Companding in hardware — Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without

additional latencies.

• PIO (programmed I/O) — The processor sends or receives

data by writing or reading I/O mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) — The DMA controller

transfers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

• DMA operations with single-cycle overhead — Each

SPORT can automatically receive and transmit multiple

buffers of memory data. The processor can link or chain

sequences of DMA transfers between a SPORT and

memory.

• Interrupts — Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer, or buffers,

through DMA.

Each UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_SCLK/1,048,576) to

(f_SCLK/16) bits per second.

• Multichannel capability — Each SPORT supports 128

channels out of a 1024-channel window and is compatible

with the H.100, H.110, MVIP-90, and HMVIP standards.

• Supporting data formats from seven to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The processors have an SPI-compatible port that enables the

processor to communicate with multiple SPI-compatible

devices.

The UART port’s clock rate is calculated as:

f_SCLK

UART Clock Rate = -----------------------------------------------

16  UART_Divisor

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSI, and Master Input-

Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI

chip select input pin (SPISS) lets other SPI devices select the

processor, and seven SPI chip select output pins (SPISEL7–1) let

the processor select other SPI devices. The SPI select pins are

reconfigured general-purpose I/O pins. Using these pins, the

SPI port provides a full-duplex, synchronous serial interface,

which supports both master/slave modes and multimaster

environments.

Where the 16-bit UART_Divisor comes from the UART_DLH

(most significant 8 bits) and UART_DLL (least significant

8 bits) registers.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

The capabilities of the UARTs are further extended with sup-

port for the infrared data association (IrDA®) serial infrared

physical layer link specification (SIR) protocol.

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA channel,

configurable to support transmit or receive data streams. The

SPI’s DMA channel can only service unidirectional accesses at

any given time.

Rev. D

|

Page 11 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

• Convenient frame alignment modes support even 32-bit

alignment of encapsulated Rx or Tx IP packet data in mem-

ory after the 14-byte MAC header.

TWI CONTROLLER INTERFACE

The processors include a 2-wire interface (TWI) module for

providing a simple exchange method of control data between

multiple devices. The TWI is compatible with the widely used

I²C^®bus standard. The TWI module offers the capabilities of

simultaneous master and slave operation and support for both

7-bit addressing and multimedia data arbitration. The TWI

interface utilizes two pins for transferring clock (SCL) and data

(SDA) and supports the protocol at speeds up to 400k bits/sec.

The TWI interface pins are compatible with 5 V logic levels.

• Programmable Ethernet event interrupt supports any com-

bination of:

• Any selected Rx or Tx frame status conditions.

• PHY interrupt condition.

• Wake-up frame detected.

• Any selected MAC management counter(s) at half-

full.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

• DMA descriptor error.

• 47 MAC management statistics counters with selectable

clear-on-read behavior and programmable interrupts on

half maximum value.

10/100 ETHERNET MAC

The ADSP-BF526 and ADSP-BF527 processors offer the capa-

bility to directly connect to a network by way of an embedded

Fast Ethernet Media Access Controller (MAC) that supports

both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec)

operation. The 10/100 Ethernet MAC peripheral on the proces-

sor is fully compliant to the IEEE 802.3-2002 standard and it

provides programmable features designed to minimize supervi-

sion, bus use, or message processing by the rest of the processor

system.

• Programmable Rx address filters, including a 64-bin

address hash table for multicast and/or unicast frames, and

programmable filter modes for broadcast, multicast, uni-

cast, control, and damaged frames.

• Advanced power management supporting unattended

transfer of Rx and Tx frames and status to/from external

memory via DMA during low power sleep mode.

• System wakeup from sleep operating mode upon magic

packet or any of four user-definable wakeup frame filters.

Some standard features are:

• Support of MII and RMII protocols for external PHYs.

• Full duplex and half duplex modes.

• Support for 802.3Q tagged VLAN frames.

• Programmable MDC clock rate and preamble suppression.

• Data framing and encapsulation: generation and detection

of preamble, length padding, and FCS.

• In RMII operation, seven unused pins may be configured

as GPIO pins for other purposes.

• Media access management (in half-duplex operation): col-

lision and contention handling, including control of

retransmission of collision frames and of back-off timing.

PORTS

Because of the rich set of peripherals, the processor groups the

many peripheral signals to four ports—Port F, Port G, Port H,

and Port J. Most of the associated pins are shared by multiple

signals. The ports function as multiplexer controls.

• Flow control (in full-duplex operation): generation and

detection of PAUSE frames.

• Station management: generation of MDC/MDIO frames

for read-write access to PHY registers.

General-Purpose I/O (GPIO)

• Operating range for active and sleep operating modes, see

Table 58 on Page 68 and Table 59 on Page 68.

The processor has 48 bidirectional, general-purpose I/O (GPIO)

pins allocated across three separate GPIO modules—PORTFIO,

PORTGIO, and PORTHIO, associated with Port F, Port G, and

Port H, respectively. Port J does not provide GPIO functional-

ity. Each GPIO-capable pin shares functionality with other

processor peripherals via a multiplexing scheme; however, the

GPIO functionality is the default state of the device upon

power-up. Neither GPIO output nor input drivers are active by

default.

• Internal loopback from Tx to Rx.

Some advanced features are:

• Buffered crystal output to external PHY for support of a

single crystal system.

• Automatic checksum computation of IP header and IP

payload fields of Rx frames.

• Independent 32-bit descriptor-driven Rx and Tx DMA

channels.

• Frame status delivery to memory via DMA, including

frame completion semaphores, for efficient buffer queue

management in software.

• Tx DMA support for separate descriptors for MAC header

and payload to eliminate buffer copy operations.

Rev. D

|

Page 12 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Each general-purpose port pin can be individually controlled by

manipulation of the port control, status, and interrupt registers:

2. Frame capture mode — Frame syncs are outputs from the

PPI, but data are inputs.

• GPIO direction control register — Specifies the direction of

each individual GPIO pin as input or output.

3. Output mode — Frame syncs and data are outputs from

the PPI.

• GPIO control and status registers — The processor

employs a “write one to modify” mechanism that allows

any combination of individual GPIO pins to be modified in

a single instruction, without affecting the level of any other

GPIO pins. Four control registers are provided. One regis-

ter is written in order to set pin values, one register is

written in order to clear pin values, one register is written

in order to toggle pin values, and one register is written in

order to specify a pin value. Reading the GPIO status regis-

ter allows software to interrogate the sense of the pins.

Input Mode

Input mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in PPI_-

CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_COUNT register. The PPI supports 8-bit and 10-bit

through 16-bit data, programmable in the PPI_CONTROL

register.

• GPIO interrupt mask registers — The two GPIO interrupt

mask registers allow each individual GPIO pin to function

as an interrupt to the processor. Similar to the two GPIO

control registers that are used to set and clear individual

pin values, one GPIO interrupt mask register sets bits to

enable interrupt function, and the other GPIO interrupt

mask register clears bits to disable interrupt function.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave

(for frame capture for example). The ADSP-BF52x processors

control when to read from the video source(s). PPI_FS1 is an

HSYNC output, and PPI_FS2 is a VSYNC output.

Output Mode

Output mode is used for transmitting video or other data with

up to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

• GPIO interrupt sensitivity registers — The two GPIO inter-

rupt sensitivity registers specify whether individual pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

PARALLEL PERIPHERAL INTERFACE (PPI)

The processor provides a parallel peripheral interface (PPI) that

can connect directly to parallel analog-to-digital and digital-to-

analog converters, video encoders and decoders, and other gen-

eral-purpose peripherals. The PPI consists of a dedicated input

clock pin, up to three frame synchronization pins, and up to 16

data pins. The input clock supports parallel data rates up to half

the system clock rate, and the synchronization signals can be

configured as either inputs or outputs.

1. Active video only mode

2. Vertical blanking only mode

3. Entire field mode

Active Video Mode

Active video only mode is used when only the active video por-

tion of a field is of interest and not any of the blanking intervals.

The PPI does not read in any data between the end of active

video (EAV) and start of active video (SAV) preamble symbols,

or any data present during the vertical blanking intervals. In this

mode, the control byte sequences are not stored to memory;

they are filtered by the PPI. After synchronizing to the start of

Field 1, the PPI ignores incoming samples until it sees an SAV

code. The user specifies the number of active video lines per

frame (in PPI_COUNT register).

The PPI supports a variety of general-purpose and ITU-R 656

modes of operation. In general-purpose mode, the PPI provides

half-duplex, bidirectional data transfer with up to 16 bits of

data. Up to three frame synchronization signals are also pro-

vided. In ITU-R 656 mode, the PPI provides half-duplex

bidirectional transfer of 8- or 10-bit video data. Additionally,

on-chip decode of embedded start-of-line (SOL) and start-of-

field (SOF) preamble packets is supported.

Vertical Blanking Interval Mode

General-Purpose Mode Descriptions

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

1. Input mode — Frame syncs and data are inputs into the

PPI.

Rev. D

|

Page 13 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Entire Field Mode

DYNAMIC POWER MANAGEMENT

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1. Data is transferred to or from the

synchronous channels through eight DMA engines that work

autonomously from the processor core.

The processor provides five operating modes, each with a differ-

ent performance/power profile. In addition, dynamic power

management provides the control functions to dynamically alter

the processor core supply voltage, further reducing power dissi-

pation. When configured for a 0 V core supply voltage, the

processor enters the hibernate state. Control of clocking to each

of the processor peripherals also reduces power consumption.

See Table 4 for a summary of the power settings for each mode.

USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER

Table 4. Power Settings

The USB OTG dual-role device controller (USBDRC) provides

a low-cost connectivity solution for consumer mobile devices

such as cell phones, digital still cameras, and MP3 players,

allowing these devices to transfer data using a point-to-point

USB connection without the need for a PC host. The USBDRC

module can operate in a traditional USB peripheral-only mode

as well as the host mode presented in the On-the-Go (OTG)

supplement to the USB 2.0 specification. In host mode, the USB

module supports transfers at high speed (480 Mbps), full speed

(12 Mbps), and low speed (1.5 Mbps) rates. Peripheral-only

mode supports the high- and full-speed transfer rates.

Core

Clock

System

Clock

PLL

Core

Mode/State PLL

Bypassed (CCLK) (SCLK) Power

Full-On

Active

Enabled No

Enabled Enabled On

Enabled/ Yes

Enabled Enabled On

Disabled

Enabled

Sleep

—

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

Deep Sleep Disabled —

Hibernate Disabled —

The USB clock (USB_XI) is provided through a dedicated exter-

nal crystal or crystal oscillator. See Universal Serial Bus (USB)

On-The-Go—Receive and Transmit Timing on Page 60 for

related timing requirements. If using a crystal to provide the

USB clock, use a parallel-resonant, fundamental mode, micro-

processor-grade crystal.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

The USB on-the-go dual-role device controller includes a phase

locked loop with programmable multipliers to generate the nec-

essary internal clocking frequency for USB. The multiplier value

should be programmed based on the USB_XI frequency to

achieve the necessary 480 MHz internal clock for USB high

speed operation. For example, for a USB_XI crystal frequency of

24 MHz, the USB_PLLOSC_CTRL register should be pro-

grammed with a multiplier value of 20 to generate a 480 MHz

internal clock.

Active Operating Mode—Moderate Dynamic Power

Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. DMA

access is available to appropriately configured L1 memories.

In the active mode, it is possible to disable the control input to

the PLL by setting the PLL_OFF bit in the PLL control register.

This register can be accessed with a user-callable routine in the

on-chip ROM called bfrom_SysControl(). If disabled, the PLL

control input must be re-enabled before transitioning to the

full-on or sleep modes.

CODE SECURITY WITH LOCKBOX SECURE

TECHNOLOGY

A security system consisting of a blend of hardware and soft-

ware provides customers with a flexible and rich set of code

TM

security features with Lockbox Secure Technology. Key fea-

tures include:

For more information about PLL controls, see the “Dynamic

Power Management” chapter in the ADSP-BF52x Blackfin Pro-

cessor Hardware Reference.

• OTP memory

• Unique chip ID

• Code authentication

• Secure mode of operation

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally, an external event or RTC activity wakes up the processor.

When in the sleep mode, asserting a wakeup enabled in the

SIC_IWRx registers causes the processor to sense the value of

the BYPASS bit in the PLL control register (PLL_CTL). If

BYPASS is disabled, the processor transitions to the full-on

mode. If BYPASS is enabled, the processor transitions to the

active mode.

The security scheme is based upon the concept of authentica-

tion of digital signatures using standards-based algorithms and

provides a secure processing environment in which to execute

code and protect assets. See Lockbox Secure Technology Dis-

claimer on Page 22.

Rev. D

|

Page 14 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

System DMA access to L1 memory is not supported in

sleep mode.

Power Savings

As shown in Table 5, the processor supports six different power

domains, which maximizes flexibility while maintaining com-

pliance with industry standards and conventions. By isolating

the internal logic of the processor into its own power domain,

separate from the RTC and other I/O, the processor can take

advantage of dynamic power management without affecting the

RTC or other I/O devices. There are no sequencing require-

ments for the various power domains, but all domains must be

powered according to the appropriate Specifications table for

processor Operating Conditions; even if the feature/peripheral

is not used.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals,

such as the RTC, may still be running but cannot access internal

resources or external memory. This powered-down mode can

only be exited by assertion of the reset interrupt (RESET) or by

an asynchronous interrupt generated by the RTC. When in deep

sleep mode, an RTC asynchronous interrupt causes the proces-

sor to transition to the Active mode. Assertion of RESET while

in deep sleep mode causes the processor to transition to the full

on mode.

Table 5. Power Domains

Power Domain

V_DDRange

All internal logic, except RTC, Memory, USB, OTP V_DDINT

Hibernate State—Maximum Static Power Savings

RTC internal logic and crystal I/O

Memory logic

V_DDRTC

V_DDMEM

V_DDUSB

V_DDOTP

V_DDEXT

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all of

the synchronous peripherals (SCLK). The internal voltage regu-

lator (ADSP-BF523/ADSP-BF525/ADSP-BF527 only) for the

processor can be shut off by writing b#00 to the FREQ bits of the

VR_CTL register, using the bfrom_SysControl() function. This

setting sets the internal power supply voltage (V_DDINT) to 0 V to

provide the lowest static power dissipation. Any critical infor-

mation stored internally (for example, memory contents,

register contents, and other information) must be written to a

non volatile storage device prior to removing power if the pro-

cessor state is to be preserved. Writing b#00 to the FREQ bits

also causes EXT_WAKE0 and EXT_WAKE1 to transition low,

which can be used to signal an external voltage regulator to

shut down.

USB PHY logic

OTP logic

All other I/O

The dynamic power management feature of the processor

allows both the processor’s input voltage (V_DDINT) and clock fre-

quency (f_CCLK) to be dynamically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation, while reducing the

voltage by 25% reduces dynamic power dissipation by more

than 40%. Further, these power savings are additive, in that if

the clock frequency and supply voltage are both reduced, the

power savings can be dramatic, as shown in the following

equations.

Since V_DDEXTand V_DDMEMcan still be supplied in this mode, all

of the external pins three-state, unless otherwise specified. This

allows other devices that may be connected to the processor to

still have power applied without drawing unwanted current.

Power Savings Factor

The Ethernet or USB modules can wake up the internal supply

regulator (ADSP-BF525 and ADSP-BF527 only) or signal an

external regulator to wake up using EXT_WAKE0 or

2

f_CCLKRED

-------------------------

f_CCLKNOM

V_DDINTRED

-------------------------------

V_DDINTNOM

T_RED

--------------

T_NOM

















=



EXT_WAKE1. If PG15 does not connect as a PHYINT signal to

an external PHY device, PG15 can be pulled low by any other

device to wake the processor up. The processor can also be

woken up by a real-time clock wakeup event or by asserting the

RESET pin. All hibernate wake-up events initiate the hardware

reset sequence. Individual sources are enabled by the VR_CTL

register. The EXT_WAKEx signals are provided to indicate the

occurrence of wake-up events.

% Power Savings = 1 – Power Savings Factor  100%

where the variables in the equations are:

f

_CCLKNOMis the nominal core clock frequency

_CCLKREDis the reduced core clock frequency

As long as V_DDEXTis applied, the VR_CTL register maintains its

state during hibernation. All other internal registers and memo-

ries, however, lose their content in the hibernate state. State

variables may be held in external SRAM or SDRAM. The

SCKELOW bit in the VR_CTL register controls whether or not

SDRAM operates in self-refresh mode, which allows it to retain

its content while the processor is in hibernate and through the

subsequent reset sequence.

V

_DDINTNOMis the nominal internal supply voltage

_DDINTREDis the reduced internal supply voltage

T_NOMis the duration running at f_CCLKNOM

_REDis the duration running at f_CCLKRED

T

Rev. D

|

Page 15 of 88

|

July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

regulator, it is Power Good. The Soft Start feature is recom-

mended to reduce the inrush currents and to reduce V_DDINT

voltage overshoot when coming out of hibernate or changing

voltage levels. The Power Good (PG) input signal allows the

processor to start only after the internal voltage has reached a

chosen level. In this way, the startup time of the external

regulator is detected after hibernation. For a complete

description of Soft Start and Power Good functionality, refer

to the ADSP-BF52x Blackfin Processor Hardware Reference.

ADSP-BF523/ADSP-BF525/ADSP-BF527

VOLTAGE REGULATION

The ADSP-BF523/ADSP-BF525/ADSP-BF527 provides an on-

chip voltage regulator that can generate processor core voltage

levels from an external supply. Figure 5 shows the typical exter-

nal components required to complete the power management

system.

SET OF DECOUPLING

ADSP-BF522/ADSP-BF524/ADSP-BF526

VOLTAGE REGULATION

CAPACITORS

2.25V TO 3.6V

INPUTVOLTAGE

RANGE

V

DDEXT

(LOW-INDUCTANCE)

V

The ADSP-BF522/ADSP-BF524/ADSP-BF526 processor

requires an external voltage regulator to power the V_DDINT

domain. To reduce standby power consumption, the external

voltage regulator can be signaled through EXT_WAKE0 or

EXT_WAKE1 to remove power from the processor core. These

identical signals are high-true for power-up and may be con-

nected directly to the low-true shut down input of many

common regulators. While in the hibernate state, all external

supplies (V_DDEXT, V_DDMEM, V_DDUSB, V_DDOTP) can still be applied,

eliminating the need for external buffers. V_DDRTCmust be

applied at all times for correct hibernate operation. The external

voltage regulator can be activated from this power down state

either through an RTC wakeup, a USB wakeup, an Ethernet

wakeup, or by asserting the RESET pin, each of which then initi-

ates a boot sequence. EXT_WAKE0 or EXT_WAKE1 indicate a

wakeup to the external voltage regulator. The Power Good (PG)

input signal allows the processor to start only after the internal

voltage has reached a chosen level. In this way, the startup time

of the external regulator is detected after hibernation. For a

complete description of the Power Good functionality, refer to

the ADSP-BF52x Blackfin Processor Hardware Reference.

DDEXT

+

100μF

10μH

100μF

+

100nF

DDINT

+

FDS9431A

SS/PG

10μF

LOW ESR

ZHCS1000 100μF

VR

OUT

SHORT AND LOW-

INDUCTANCE WIRE

EXT_WAKE1

SEE H/W REFERENCE,

SYSTEM DESIGN CHAPTER,

TO DETERMINE VALUE

VR

SEL

GND

NOTE: DESIGNER SHOULD MINIMIZE

TRACE LENGTH TO FDS9431A.

Figure 5. ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulator Circuit

The regulator controls the internal logic voltage levels and is

programmable with the voltage regulator control register

(VR_CTL) in increments of 50 mV. This register can be

accessed using the bfrom_SysControl() function in the on-chip

ROM. To reduce standby power consumption, the internal volt-

age regulator can be programmed to remove power to the

processor core while keeping I/O power supplied. While in the

CLOCK SIGNALS

The processor can be clocked by an external crystal, a sine wave

input, or a buffered, shaped clock derived from an external

clock oscillator.

hibernate state, all external supplies (V_DDEXT, V_DDMEM, V_DDUSB

_DDOTP) can still be applied, eliminating the need for external

,

V

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

buffers. V_DDRTCmust be applied at all times for correct hibernate

operation. The voltage regulator can be activated from this

power-down state either through an RTC wakeup, a USB wake-

up, an Ethernet wake-up, or by asserting the RESET pin, each of

which then initiates a boot sequence. The regulator can also be

disabled and bypassed at the user’s discretion.

Alternatively, because the processor includes an on-chip oscilla-

tor circuit, an external crystal may be used. For fundamental

frequency operation, use the circuit shown in Figure 6. A

parallel-resonant, fundamental frequency, microprocessor-

grade crystal is connected across the CLKIN and XTAL pins.

The on-chip resistance between CLKIN and the XTAL pin is in

the 500 kΩ range. Further parallel resistors are typically not rec-

ommended. The two capacitors and the series resistor shown in

Figure 6 fine tune phase and amplitude of the sine frequency.

The voltage regulator has two modes set by the VR_SELpin—the

normal pulse width control of an external FET and the external

supply mode which can signal a power down during hibernate

to an external regulator. Set VR_SELto V_DDEXTto use an external

regulator or set VR_SELto GND to use the internal regulator. In

the external mode VR_OUTbecomes EXT_WAKE1. If the internal

regulator is used, EXT_WAKE0 can control other power

sources in the system during the hibernate state. Both signals

are high-true for power-up and may be connected directly to the

low-true shutdown input of many common regulators. The

mode of the SS/PG (Soft Start/Power Good) signal also changes

according to the state of VR_SEL. When using an internal regula-

tor, the SS/PG pin is Soft Start, and when using an external

The capacitor and resistor values shown in Figure 6 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

Rev. D

|

Page 16 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations on multiple

devices over temperature range.

permitted to run up to the frequency specified by the part’s

maximum instruction rate. The CLKOUT pin reflects the SCLK

frequency to the off-chip world. It is part of the SDRAM inter-

face, but it functions as a reference signal in other timing

specifications as well. While active by default, it can be disabled

using the EBIU_SDGCTL and EBIU_AMGCTL registers.

BLACKFIN

CLKOUT

TO PLL CIRCUITRY

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

EN

CLKBUF

560 ⍀

CCLK

SCLK

÷ 1, 2, 4, 8

÷ 1 to 15

EN

PLL

5u to 64u

CLKIN

VCO

XTAL

CLKIN

18 pF *

330 ⍀*

FOR OVERTONE

OPERATION ONLY:

18 pF *

SCLK d CCLK

Figure 7. Frequency Modification Methods

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED

RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Figure 6. External Crystal Connections

A third-overtone crystal can be used for frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone by adding a tuned inductor circuit as

shown in Figure 6. A design procedure for third-overtone oper-

ation is discussed in detail in application note (EE-168) Using

Third Overtone Crystals with the ADSP-218x DSP on the Analog

Devices website (www.analog.com)—use site search on

“EE-168.”

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f_SCLK. The SSEL value can be

dynamically changed without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV)

using the bfrom_SysControl() function in the on-chip ROM.

Table 6. Example System Clock Ratios

The CLKBUF pin is an output pin, which is a buffered version

of the input clock. This pin is particularly useful in Ethernet

applications to limit the number of required clock sources in the

system. In this type of application, a single 25 MHz or 50 MHz

crystal may be applied directly to the processor. The 25 MHz or

50 MHz output of CLKBUF can then be connected to an exter-

nal Ethernet MII or RMII PHY device. If, instead of a crystal, an

external oscillator is used at CLKIN, CLKBUF will not have the

40/60 duty cycle required by some devices. The CLKBUF output

is active by default and can be disabled for power savings rea-

sons using the VR_CTL register.

Example Frequency Ratios

(MHz)

Signal Name Divider Ratio

SSEL3–0

VCO/SCLK

VCO

100

300

500

SCLK

100

50

0001

1:1

0110

6:1

1010

10:1

50

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 7, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable multiplication factor

(bounded by specified minimum and maximum VCO frequen-

cies). The default multiplier can be modified by a software

instruction sequence. This sequence is managed by the

bfrom_SysControl() function in the on-chip ROM.

Table 7. Core Clock Ratios

Example Frequency Ratios

(MHz)

Signal Name Divider Ratio

CSEL1–0

VCO/CCLK

VCO

300

500

200

CCLK

00

01

10

11

1:1

2:1

4:1

8:1

300

150

125

25

On-the-fly CCLK and SCLK frequency changes can be applied

by using the bfrom_SysControl() function in the on-chip ROM.

The maximum allowed CCLK and SCLK rates depend on the

applied voltages V_DDINT, V_DDEXT, and V_DDMEM; the VCO is always

Rev. D

|

Page 17 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

The maximum CCLK frequency not only depends on the part's

maximum instruction rate (see Page 88). This frequency also

depends on the applied V_DDINTvoltage. See Table 12 and

Table 15 for details. The maximal system clock rate (SCLK)

kernel performs an 8- or 16-bit boot or starts program exe-

cution at the address provided by the header. By default, all

configuration settings are set for the slowest device possible

(3-cycle hold time, 15-cycle R/W access times, 4-cycle

setup).

depends on the chip package and the applied V_DDINT, V_DDEXT

,

and V_DDMEMvoltages (see Table 14 and Table 17).

The ARDY is not enabled by default, but it can be enabled

through OTP programming. Similarly, all interface behav-

ior and timings can be customized through OTP

BOOTING MODES

The processor has several mechanisms (listed in Table 8) for

automatically loading internal and external memory after a

reset. The boot mode is defined by four BMODE input pins

dedicated to this purpose. There are two categories of boot

modes. In master boot modes the processor actively loads data

from parallel or serial memories. In slave boot modes the pro-

cessor receives data from external host devices.

programming. This includes activation of burst-mode or

page-mode operation. In this mode, all asynchronous

interface signals are enabled at the port muxing level.

• Boot from 16-bit asynchronous FIFO (BMODE = 0x2) —

In this mode, the boot kernel starts booting from address

0x2030 0000. Every 16-bit word that the boot kernel has to

read from the FIFO must be requested by placing a low

pulse on the DMAR1 pin.

The boot modes listed in Table 8 provide a number of mecha-

nisms for automatically loading the processor’s internal and

external memories after a reset. By default, all boot modes use

the slowest meaningful configuration settings. Default settings

can be altered via the initialization code feature at boot time or

by proper OTP programming at pre-boot time. The BMODE

pins of the reset configuration register, sampled during power-

on resets and software-initiated resets, implement the modes

shown in Table 8.

• Boot from serial SPI memory, EEPROM or flash

(BMODE = 0x3) — 8-, 16-, 24-, or 32-bit addressable

devices are supported. The processor uses the PG1 GPIO

pin to select a single SPI EEPROM/flash device and sub-

mits a read command and successive address bytes (0x00)

until a valid 8-, 16-, 24-, or 32-bit addressable device is

detected. Pull-up resistors are required on the SPISEL1 and

MISO pins. By default, a value of 0x85 is written to the

SPI_BAUD register.

Table 8. Booting Modes

• Boot from SPI host device (BMODE = 0x4) — The proces-

sor operates in SPI slave mode and is configured to receive

the bytes of the LDR file from an SPI host (master) agent.

The HWAIT signal must be interrogated by the host before

every transmitted byte. A pull-up resistor is required on the

SPISS input. A pull-down on the serial clock (SCK) may

improve signal quality and booting robustness.

BMODE3–0 Description

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

Idle — No boot

Boot from 8- or 16-bit external flash memory

Boot from 16-bit asynchronous FIFO

Boot from serial SPI memory (EEPROM or flash)

Boot from SPI host device

Boot from serial TWI memory (EEPROM/flash)

Boot from TWI host

• Boot from serial TWI memory, EEPROM/flash

(BMODE = 0x5) — The processor operates in master mode

and selects the TWI slave connected to the TWI with the

unique ID 0xA0.

Boot from UART0 Host

Boot from UART1 Host

The processor submits successive read commands to the

memory device starting at internal address 0x0000 and

begins clocking data into the processor. The TWI memory

device should comply with the Philips I²C^®Bus Specifica-

tion version 2.1 and should be able to auto-increment its

internal address counter such that the contents of the

memory device can be read sequentially. By default, a

PRESCALE value of 0xA and a TWI_CLKDIV value of

0x0811 are used. Unless altered by OTP settings, an I²C

memory that takes two address bytes is assumed. The

development tools ensure that data booted to memories

that cannot be accessed by the Blackfin core is written to an

intermediate storage location and then copied to the final

destination via memory DMA.

Reserved

Boot from SDRAM

Boot from OTP memory

Boot from 8-bit NAND flash

via NFC using PORTF data pins

1101

Boot from 8-bit NAND flash

via NFC using PORTH data pins

1110

1111

Boot from 16-Bit Host DMA

Boot from 8-Bit Host DMA

• Idle/no boot mode (BMODE = 0x0) — In this mode, the

processor goes into idle. The idle boot mode helps recover

from illegal operating modes, such as when the OTP mem-

ory has been misconfigured.

• Boot from TWI host (BMODE = 0x6) — The TWI host

selects the slave with the unique ID 0x5F.

The processor replies with an acknowledgement and the

host then downloads the boot stream. The TWI host agent

should comply with the Philips I²C Bus Specification

• Boot from 8-bit or 16-bit external flash memory

(BMODE = 0x1) — In this mode, the boot kernel loads the

first block header from address 0x2000 0000, and (depend-

ing on instructions contained in the header) the boot

Rev. D

|

Page 18 of 88

|

July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

version 2.1. An I²C multiplexer can be used to select one

processor at a time when booting multiple processors from

a single TWI.

—Software-configurable boot mode for booting from

boot streams spanning multiple blocks, including bad

blocks

• Boot from UART0 host on Port G (BMODE = 0x7) —

Using an autobaud handshake sequence, a boot-stream for-

matted program is downloaded by the host. The host

selects a bit rate within the UART clocking capabilities.

—Software-configurable boot mode for booting from

multiple copies of the boot stream, allowing for han-

dling of bad blocks and uncorrectable errors

—Configurable timing via OTP memory

When performing the autobaud, the UART expects a “@”

(0x40) character (eight bits data, one start bit, one stop bit,

no parity bit) on the UART0RX pin to determine the bit

rate. The UART then replies with an acknowledgement

composed of 4 bytes (0xBF, the value of UART0_DLL, the

value of UART0_DLH, then 0x00). The host can then

download the boot stream. To hold off the host the Blackfin

processor signals the host with the boot host wait

(HWAIT) signal. Therefore, the host must monitor

HWAIT before every transmitted byte.

Small page NAND flash devices must have a 512-byte page

size, 32 pages per block, a 16-byte spare area size, and a bus

configuration of 8 bits. By default, all read requests from

the NAND flash are followed by four address cycles. If the

NAND flash device requires only three address cycles, the

device must be capable of ignoring the additional address

cycles.

The small page NAND flash device must comply with the

following command set:

—Reset: 0xFF

• Boot from UART1 host on Port F (BMODE = 0x8). Same

as BMODE = 0x7 except that the UART1 port is used.

—Read lower half of page: 0x00

—Read upper half of page: 0x01

—Read spare area: 0x50

• Boot from SDRAM (BMODE = 0xA) This is a warm boot

scenario, where the boot kernel starts booting from address

0x0000 0010. The SDRAM is expected to contain a valid

boot stream and the SDRAM controller must be configured

by the OTP settings.

For large-page NAND-flash devices, the four-byte elec-

tronic signature is read in order to configure the kernel for

booting, which allows support for multiple large-page

devices. The fourth byte of the electronic signature must

comply with the specification in Table 9 on Page 20.

• Boot from OTP memory (BMODE = 0xB) — This provides

a stand-alone booting method. The boot stream is loaded

from on-chip OTP memory. By default, the boot stream is

expected to start from OTP page 0x40 and can occupy all

public OTP memory up to page 0xDF. This is 2560 bytes.

Since the start page is programmable, the maximum size of

the boot stream can be extended to 3072 bytes.

Any NAND flash array configuration from Table 9, exclud-

ing 16-bit devices, that also complies with the command set

listed below are directly supported by the boot kernel.

There are no restrictions on the page size or block size as

imposed by the small-page boot kernel.

• Boot from 8-bit external NAND flash memory (BMODE =

0xC and BMODE = 0xD) — In this mode, auto detection of

the NAND flash device is performed.

For devices consisting of a five-byte signature, only four are

read. The fourth must comply as outlined above.

Large page devices must support the following command

set:

BMODE = 0xC, the processor configures PORTF GPIO

pins PF7:0 for the NAND data pins and PORTH pins

PH15:10 for the NAND control signals.

—Reset: 0xFF

BMODE = 0xD, the processor configures PORTH GPIO

pins PH7:0 for the NAND data pins and PORTH pins

PH15:10 for the NAND control signals.

—Read Electronic Signature: 0x90

—Read: 0x00, 0x30 (confirm command)

Large-page devices must not support or react to NAND

flash command 0x50. This is a small-page NAND flash

command used for device auto detection.

For correct device operation pull-up resistors are required

on both ND_CE (PH10) and ND_BUSY (PH13) signals. By

default, a value of 0x0033 is written to the NFC_CTL regis-

ter. The booting procedure always starts by booting from

byte 0 of block 0 of the NAND flash device.

By default, the boot kernel will always issue five address

cycles; therefore, if a large page device requires only four

cycles, the device must be capable of ignoring the addi-

tional address cycles.

NAND flash boot supports the following features:

—Device Auto Detection

• Boot from 16-Bit Host DMA (BMODE = 0xE) — In this

mode, the host DMA port is configured in 16-bit Acknowl-

edge mode, with little endian data formatting. Unlike other

modes, the host is responsible for interpreting the boot

stream. It writes data blocks individually into the Host

DMA port. Before configuring the DMA settings for each

block, the host may either poll the ALLOW_CONFIG bit in

HOST_STATUS or wait to be interrupted by the HWAIT

—Error Detection & Correction for maximum reliability

—No boot stream size limitation

—Peripheral DMA providing efficient transfer of all data

(excluding the ECC parity data)

Rev. D

|

Page 19 of 88

|

July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

signal. When using HWAIT, the host must still check

ALLOW_CONFIG at least once before beginning to con-

figure the Host DMA Port. After completing the

configuration, the host is required to poll the READY bit in

HOST_STATUS before beginning to transfer data. When

the host sends an HIRQ control command, the boot kernel

issues a CALL instruction to address 0xFFA0 0000. It is the

host's responsibility to ensure that valid code has been

placed at this address. The routine at 0xFFA0 0000 can be a

simple initialization routine to configure internal

resources, such as the SDRAM controller, which then

returns using an RTS instruction. The routine may also by

the final application, which will never return to the boot

kernel.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and super-

visor (O/S kernel, device drivers, debuggers, ISRs) modes

of operation, allowing multiple levels of access to core

processor resources.

• Boot from 8-Bit Host DMA (BMODE = 0xF) — In this

mode, the Host DMA port is configured in 8-bit interrupt

mode, with little endian data formatting. Unlike other

modes, the host is responsible for interpreting the boot

stream. It writes data blocks individually into the Host

DMA port. Before configuring the DMA settings for each

block, the host may either poll the ALLOW_CONFIG bit in

HOST_STATUS or wait to be interrupted by the HWAIT

signal. When using HWAIT, the host must still check

ALLOW_CONFIG at least once before beginning to con-

figure the Host DMA Port. The host will receive an

interrupt from the HOST_ACK signal every time it is

allowed to send the next FIFO depths worth (sixteen 32-bit

words) of information. When the host sends an HIRQ con-

trol command, the boot kernel issues a CALL instruction to

address 0xFFA0 0000. It is the host's responsibility to

ensure valid code has been placed at this address. The rou-

tine at 0xFFA0 0000 can be a simple initialization routine

to configure internal resources, such as the SDRAM con-

troller, which then returns using an RTS instruction. The

routine may also by the final application, which will never

return to the boot kernel.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded

in 16 bits.

DEVELOPMENT TOOLS

Table 9. Fourth Byte for Large Page Devices

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore^®Embed-

ded Studio and/or VisualDSP++^®), evaluation products,

emulators, and a wide variety of software add-ins.

Bit

D1:D0 Page Size

(excluding spare area)

Parameter

Value

Meaning

00

01

10

11

1K byte

2K byte

4K byte

8K byte

Integrated Development Environments (IDEs)

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

D2

Spare Area Size

00

01

8 byte/512 byte

16 byte/512 byte

The newest IDE, CrossCore Embedded Studio, is based on the

D5:D4 Block Size

(excluding spare area)

00

01

10

11

64K byte

128K byte

256K byte

512K byte

TM

Eclipse framework. Supporting most Analog Devices proces-

sor families, it is the IDE of choice for future processors,

including multicore devices. CrossCore Embedded Studio

seamlessly integrates available software add-ins to support real

time operating systems, file systems, TCP/IP stacks, USB stacks,

algorithmic software modules, and evaluation hardware board

support packages. For more information, visit www.ana-

log.com/cces.

D6

Bus width

00

01

x8

not supported

D3, D7 Not Used for configuration

Rev. D

|

Page 20 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

Middleware Packages

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and TCP/

IP stacks. For more information see the following web pages:

• www.analog.com/ucos3

• www.analog.com/ucfs

• www.analog.com/ucusbd

• www.analog.com/lwip

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite^®evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders^®, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

VisualDSP++. For more information visit www.analog.com and

search on “Blackfin software modules” or “SHARC software

modules”.

EZ-KIT Lite Evaluation Kits

Designing an Emulator-Compatible DSP Board (Target)

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the Engineer-to-Engineer

Note “Analog Devices JTAG Emulation Technical Reference”

(EE-68) on the Analog Devices website (www.analog.com)—use

site search on “EE-68.” This document is updated regularly to

keep pace with improvements to emulator support.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

ADDITIONAL INFORMATION

The following publications that describe the ADSP-BF52x pro-

cessors (and related processors) can be ordered from any

Analog Devices sales office or accessed electronically on

our website:

Board Support Packages for Evaluation Hardware

• Getting Started With Blackfin Processors

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

• ADSP-BF52x Blackfin Processor Hardware Reference (vol-

umes 1 and 2)

• Blackfin Processor Programming Reference

• ADSP-BF522/ADSP-BF524/ADSP-BF526 Blackfin Proces-

sor Anomaly List

• ADSP-BF523/ADSP-BF525/ADSP-BF527 Blackfin Proces-

sor Anomaly List

Rev. D

|

Page 21 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in

Wikipedia or the Glossary of EE Terms on the Analog Devices

website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The Application Signal Chains page in the Circuits from the

Lab^TMsite (http:\\www.analog.com\signalchains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

LOCKBOX SECURE TECHNOLOGY DISCLAIMER

Analog Devices products containing Lockbox Secure Technol-

ogy are warranted by Analog Devices as detailed in the Analog

Devices Standard Terms and Conditions of Sale. To our knowl-

edge, the Lockbox Secure Technology, when used in accordance

with the data sheet and hardware reference manual specifica-

tions, provides a secure method of implementing code and data

safeguards. However, Analog Devices does not guarantee that

this technology provides absolute security.

ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS

ANY AND ALL EXPRESS AND IMPLIED WARRANTIES

THAT THE LOCKBOX SECURE TECHNOLOGY CANNOT

BE BREACHED, COMPROMISED, OR OTHERWISE CIR-

CUMVENTED AND IN NO EVENT SHALL ANALOG

DEVICES BE LIABLE FOR ANY LOSS, DAMAGE,

DESTRUCTION, OR RELEASE OF DATA, INFORMATION,

PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY.

Rev. D

|

Page 22 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

SIGNAL DESCRIPTIONS

Signal definitions for the ADSP-BF52x processors are listed in

Table 10. In order to maintain maximum function and reduce

package size and ball count, some balls have dual, multiplexed

functions. In cases where ball function is reconfigurable, the

default state is shown in plain text, while the alternate function

is shown in italics.

All I/O pins have their input buffers disabled with the exception

of the pins that need pull-ups or pull-downs, as noted in

Table 10.

It is strongly advised to use the available IBIS models to ensure

that a given board design meets overshoot/undershoot and sig-

nal integrity requirements. If no IBIS simulation is performed, it

is strongly recommended to add series resistor terminations for

all Driver Types A, C and D.

All pins are three-stated during and immediately after reset,

with the exception of the external memory interface, asynchro-

nous and synchronous memory control, and the buffered XTAL

output pin (CLKBUF). On the external memory interface, the

control and address lines are driven high, with the exception of

CLKOUT, which toggles at the system clock rate. During hiber-

nate, all outputs are three-stated unless otherwise noted in

Table 10.

The termination resistors should be placed near the processor to

reduce transients and improve signal integrity. The resistance

value, typically 33 ꢀ or 47 ꢀ, should be chosen to match the

average board trace impedance.

Additionally, adding a parallel termination to CLKOUT may

prove useful in further enhancing signal integrity. Be sure to

verify overshoot/undershoot and signal integrity specifications

on actual hardware.

Table 10. Signal Descriptions

Driver

Type¹

Signal Name

EBIU

Type Function

ADDR19–1

DATA15–0

ABE1–0/SDQM1–0

AMS3–0

ARDY

O

I/O

O

I

Address Bus

Data Bus

A

Byte Enables/Data Mask

A

Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used.) A

Hardware Ready Control

AOE

O

Asynchronous Output Enable

Asynchronous Read Enable

Asynchronous Write Enable

SDRAM Row Address Strobe

SDRAM Column Address Strobe

SDRAM Write Enable

A

ARE

AWE

SRAS

SCAS

SWE

SCKE

SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM self-

refresh is used.)

CLKOUT

SA10

O

SDRAM Clock Output

SDRAM A10 Signal

SDRAM Bank Select

B

A

SMS

Rev. D

|

Page 23 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 10. Signal Descriptions (Continued)

Driver

Signal Name

USB 2.0 HS OTG

USB_DP

Type Function

Type¹

I/O

I

Data + (This ball should be pulled low when USB is unused or not present.) F

USB_DM

Data – (This ball should be pulled low when USB is unused or not present.)

F

USB_XI

USB Crystal Input (This ball should be pulled low when USB is unused or not

present.)

USB_XO

USB_ID

O

I

USB Crystal Output (This ball should be left unconnected when USB is unused F

or not present.)

USB OTG mode (This ball should be pulled low when USB is unused or not

present.)

USB_VREF

A

USB voltage reference (Connect to GND through a 0.1 μF capacitor or leave

unconnected when not used.)

USB_RSET

USB_VBUS

A

USB resistance set. (This ball should be left unconnected.)

I/O 5V USB VBUS. USB_VBUS is an output only in peripheral mode during SRP

signaling. Host mode requires that an external voltage source of 5 V at 8 mA

or more (per the OTG specification) be applied to VBUS. The voltage source

needs to be able to charge and discharge VBUS, thus an ON/OFF switch is

required to control the voltage source. A GPIO can be used for this purpose

(This ball should be pulled low when USB is unused or not present.)

F

Port F: GPIO and Multiplexed Peripherals

PF0/PPI D0/DR0PRI /ND_D0A

I/O

GPIO/PPI Data 0/SPORT0 Primary Receive Data

/NAND Alternate Data 0

C

D

C

D

C

PF1/PPI D1/RFS0/ND_D1A

GPIO/PPI Data 1/SPORT0 Receive Frame Sync

/NAND Alternate Data 1

PF2/PPI D2/RSCLK0/ND_D2A

GPIO/PPI Data 2/SPORT0 Receive Serial Clock

/NAND Alternate Data 2/Alternate Capture Input 0

PF3/PPI D3/DT0PRI/ND_D3A

GPIO/PPI Data 3/SPORT0 Transmit Primary Data

/NAND Alternate Data 3

PF4/PPI D4/TFS0/ND_D4A/TACLK0

PF5/PPI D5/TSCLK0/ND_D5A/TACLK1

PF6/PPI D6/DT0SEC/ND_D6A/TACI0

PF7/PPI D7/DR0SEC/ND_D7A/TACI1

GPIO/PPI Data 4/SPORT0 Transmit Frame Sync

/NAND Alternate Data 4/Alternate Timer Clock 0

GPIO/PPI Data 5/SPORT0 Transmit Serial Clock

/NAND Alternate Data 5/Alternate Timer Clock 1

GPIO/PPI Data 6/SPORT0 Transmit Secondary Data

/NAND Alternate Data 6/Alternate Capture Input 0

GPIO/PPI Data 7/SPORT0 Receive Secondary Data

/NAND Alternate Data 7/Alternate Capture Input 1

PF8/PPI D8/DR1PRI

I/O

GPIO/PPI Data 8/SPORT1 Primary Receive Data

C

D

C

PF9/PPI D9/RSCLK1/SPISEL6

PF10/PPI D10/RFS1/SPISEL7

PF11/PPI D11/TFS1/CZM

PF12/PPI D12/DT1PRI/SPISEL2/CDG

GPIO/PPI Data 9/SPORT1 Receive Serial Clock/SPI Slave Select 6

GPIO/PPI Data 10/SPORT1 Receive Frame Sync/SPI Slave Select 7

GPIO/PPI Data 11/SPORT1 Transmit Frame Sync/Counter Zero Marker

GPIO/PPI Data 12/SPORT1 Transmit Primary Data/SPI Slave Select 2/Counter

Down Gate

PF13/PPI D13/TSCLK1/SPISEL3/CUD

I/O

GPIO/PPI Data 13/SPORT1 Transmit Serial Clock/SPI Slave Select 3/Counter Up D

Direction

PF14/PPI D14/DT1SEC/UART1TX

I/O

GPIO/PPI Data 14/SPORT1 Transmit Secondary Data/UART1 Transmit

C

PF15/PPI D15/DR1SEC/UART1RX/TACI3

GPIO/PPI Data 15/SPORT1 Receive Secondary Data

/UART1 Receive /Alternate Capture Input 3

Rev. D

|

Page 24 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 10. Signal Descriptions (Continued)

Driver

Signal Name

Type Function

Type¹

Port G: GPIO and Multiplexed Peripherals

PG0/HWAIT

I/O

GPIO/Boot Host Wait²

C

D

C

PG1/SPISS/SPISEL1

GPIO/SPI Slave Select Input/SPI Slave Select 1

PG2/SCK

GPIO/SPI Clock

PG3/MISO/DR0SECA

PG4/MOSI/DT0SECA

GPIO/SPI Master In Slave Out/Sport 0 Alternate Receive Data Secondary

GPIO/SPI Master Out Slave In/Sport 0 Alternate Transmit Data Secondary

GPIO/Timer1/PPI Frame Sync2

PG5/TMR1/PPI_FS2

PG6/DT0PRIA/TMR2/PPI_FS3

PG7/TMR3/DR0PRIA/UART0TX

PG8/TMR4/RFS0A/UART0RX/TACI4

GPIO/SPORT0 Alternate Primary Transmit Data / Timer2 / PPI Frame Sync3

GPIO/Timer3/Sport 0 Alternate Receive Data Primary/UART0 Transmit

GPIO/Timer 4/Sport 0 Alternate Receive Clock/Frame Sync

/UART0 Receive/Alternate Capture Input 4

PG9/TMR5/RSCLK0A/TACI5

PG10/TMR6/TSCLK0A/TACI6

I/O

GPIO/Timer5/Sport 0 Alternate Receive Clock

/Alternate Capture Input 5

D

GPIO/Timer 6 /Sport 0 Alternate Transmit

/Alternate Capture Input 6

PG11/TMR7/HOST_WR

I/O

GPIO/Timer7/Host DMA Write Enable

C

PG12/DMAR1/UART1TXA/HOST_ACK

GPIO/DMA Request 1/Alternate UART1 Transmit/Host DMA Acknowledge

PG13/DMAR0/UART1RXA/HOST_ADDR/TACI2 I/O

GPIO/DMA Request 0/Alternate UART1 Receive/Host DMA Address/Alternate

Capture Input 2

PG14/TSCLK0A1/MDC/HOST_RD I/O

GPIO/SPORT0 Alternate 1 Transmit/Ethernet Management Channel Clock

/Host DMA Read Enable

D

PG15³/TFS0A/MII PHYINT/RMII MDINT/HOST_CE I/O

Port H: GPIO and Multiplexed Peripherals

GPIO/SPORT0 Alternate Transmit Frame Sync/Ethernet/MII PHY Interrupt/RMII C

Management Channel Data Interrupt/Host DMA Chip Enable

PH0/ND_D0/MIICRS/RMIICRSDV/HOST_D0

PH1/ND_D1/ERxER/HOST_D1

I/O

GPIO/NAND D0/Ethernet MII or RMII Carrier Sense/Host DMA D0

GPIO/NAND D1/Ethernet MII or RMII Receive Error/Host DMA D1

GPIO/NAND D2/Ethernet Management Channel Serial Data/Host DMA D2

GPIO/NAND D3/Ethernet MII Transmit Enable/Host DMA D3

GPIO/NAND D4/Ethernet MII or RMII Reference Clock/Host D4

GPIO/NAND D5/Ethernet MII or RMII Transmit D0/Host DMA D5

GPIO/NAND D6/Ethernet MII or RMII Receive D0/Host DMA D6

GPIO/NAND D7/Ethernet MII or RMII Transmit D1/Host DMA D7

C

PH2/ND_D2/MDIO/HOST_D2

PH3/ND_D3/ETxEN/HOST_D3

PH4/ND_D4/MIITxCLK/RMIIREF_CLK/HOST_D4 I/O

PH5/ND_D5/ETxD0/HOST_D5

PH6/ND_D6/ERxD0/HOST_D6

PH7/ND_D7/ETxD1/HOST_D7

PH8/SPISEL4/ERxD1/HOST_D8/TACLK2

I/O

GPIO/Alternate Timer Clock 2/Ethernet MII or RMII Receive D1/Host DMA D8

/SPI Slave Select 4

PH9/SPISEL5/ETxD2/HOST_D9/TACLK3

I/O

GPIO/SPI Slave Select 5/Ethernet MII Transmit D2/Host DMA D9

/Alternate Timer Clock 3

C

PH10/ND_CE/ERxD2/HOST_D10

PH11/ND_WE/ETxD3/HOST_D11

PH12/ND_RE/ERxD3/HOST_D12

PH13/ND_BUSY/ERxCLK/HOST_D13

PH14/ND_CLE/ERxDV/HOST_D14

I/O

GPIO/NAND Chip Enable/Ethernet MII Receive D2/Host DMA D10

GPIO/NAND Write Enable/Ethernet MII Transmit D3/Host DMA D11

GPIO/NAND Read Enable/Ethernet MII Receive D3/Host DMA D12

GPIO/NAND Busy/Ethernet MII Receive Clock/Host DMA D13

C

GPIO/NAND Command Latch Enable/Ethernet MII or RMII Receive Data Valid/

Host DMA D14

PH15/ND_ALE/COL/HOST_D15

I/O

GPIO/NAND Address Latch Enable/Ethernet MII Collision/Host DMA Data 15

C

Rev. D

|

Page 25 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 10. Signal Descriptions (Continued)

Driver

Signal Name

Type Function

Type¹

Port J: Multiplexed Peripherals

PJ0: PPI_FS1/TMR0

PJ1: PPI_CLK/TMRCLK

PJ2: SCL

I/O

I

PPI Frame Sync1/Timer0

PPI Clock/Timer Clock

C

I/O 5V TWI Serial Clock (This pin is an open-drain output and requires a pull-up

resistor.⁴)

E

PJ3: SDA

I/O 5V TWI Serial Data (This pin is an open-drain output and requires a pull-up

resistor.⁴)

Real Time Clock

RTXI

I

RTC Crystal Input (This ball should be pulled low when not used.)

RTC Crystal Output (Does not three-state during hibernate.)

RTXO

O

JTAG Port

TCK

I

JTAG Clock

TDO

O

I

JTAG Serial Data Out

C

TDI

JTAG Serial Data In

TMS

I

JTAG Mode Select

TRST

I

JTAG Reset (This ball should be pulled low if the JTAG port is not used.)

Emulation Output

EMU

O

Clock

CLKIN

I

Clock/Crystal Input

XTAL

O

Crystal Output (If CLKBUF is enabled, does not three-state during hibernate.)

Buffered XTAL Output (If enabled, does not three-state during hibernate.)

CLKBUF

Mode Controls

RESET

NMI

I

Reset

Nonmaskable Interrupt (This ball should be pulled high when not used.)

Boot Mode Strap 3-0

BMODE3–0

ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage

Regulation I/F

VR_SEL

I

Internal/External Voltage Regulator Select

VR_OUT/EXT_WAKE1

O

External FET Drive/Wake up Indication 1 (Does not three-state during

hibernate.)

G

C

EXT_WAKE0

SS/PG

O

A

Wake up Indication 0 (Does not three-state during hibernate.)

Soft Start/Power Good

ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage

Regulation I/F

EXT_WAKE1

EXT_WAKE0

PG

O

A

Wake up Indication 1 (Does not three-state during hibernate.)

Wake up Indication 0 (Does not three-state during hibernate.)

Power Good (This signal should be pulled low when not used.)

C

Rev. D

|

Page 26 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 10. Signal Descriptions (Continued)

Driver

Signal Name

Type Function

ALL SUPPLIES MUST BE POWERED

Type¹

Power Supplies

See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527

Processors on Page 30, and see Operating Conditions for ADSP-BF522/

ADSP-BF524/ADSP-BF526 Processors on Page 28.

V_DDEXT

V_DDINT

V_DDRTC

V_DDUSB

V_DDMEM

V_DDOTP

V_PPOTP

GND

P

G

I/O Power Supply

Internal Power Supply

Real Time Clock Power Supply

3.3 V USB Phy Power Supply

MEM Power Supply

OTP Power Supply

OTP Programming Voltage

Ground for All Supplies

¹See Output Drive Currents on Page 73 for more information about each driver type.

²HWAIT must be pulled high or low to configure polarity. It is driven as an output and toggle during processor boot. See Booting Modes on Page 18.

³When driven low, this ball can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as MII PHYINT. If the ball is

used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the ball with a resistor.

⁴Consult version 2.1 of the I²C specification for the proper resistor value.

Rev. D

|

Page 27 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

SPECIFICATIONS

Specifications are subject to change without notice.

OPERATING CONDITIONS

FOR ADSP-BF522/ADSP-BF524/ADSP-BF526 PROCESSORS

Parameter

V_DDINT

Conditions

Min

1.235

1.7

Nominal

Max

1.47

1.9

Unit

V

Internal Supply Voltage

External Supply Voltage¹

RTC Power Supply Voltage²

MEM Supply Voltage^{1, 3}

OTP Supply Voltage¹

V_DDEXT

1.8

2.5

3.3

V

V_DDEXT

2.25

3

2.75

3.6

V

V_DDEXT

V

V_DDRTC

2.25

1.7

3.6

V

V_DDMEM

V_DDOTP

V_PPOTP

1.8

2.5

3.3

2.5

1.9

V

2.25

3

2.75

3.6

V

2.25

2.75

V

OTP Programming Voltage¹

For Reads

2.25

6.9

3.0

1.1

1.7

2.0

2.5

7.0

3.3

2.75

7.1

V

°C

For Writes⁴

V_DDUSB

V_IH

USB Supply Voltage⁵

3.6

High Level Input Voltage^{6, 7}

High Level Input Voltage^{6, 8}

High Level Input Voltage

Low Level Input Voltage^{6, 7}

Low Level Input Voltage^{6, 8}

Low Level Input Voltage

Junction Temperature

V_DDEXT/V_DDMEM= 1.90 V

V_DDEXT/V_DDMEM= 2.75 V

V_DDEXT/V_DDMEM= 3.6 V

V_IH

9

V_IHTWI

V_DDEXT= 1.90 V/2.75 V/3.6 V 0.7 × V_BUSTWI

V_DDEXT/V_DDMEM= 1.7 V

V_BUSTWI

0.6

V_IL

V_DDEXT/V_DDMEM= 2.25 V

0.7

V_IL

V_DDEXT/V_DDMEM= 3.0 V

0.8

10

V_ILTWI

T_J

V_DDEXT= Minimum

0.3 × V_BUSTWI

+105

289-Ball CSP_BGA

0

@ T_AMBIENT= 0°C to +70°C

T_J

Junction Temperature

208-Ball CSP_BGA

@ T_AMBIENT= 0°C to +70°C

0

+105

°C

208-Ball CSP_BGA

–40

@ T_AMBIENT= –40°C to +85°C

¹Must remain powered (even if the associated function is not used).

²If not used, power with V_DDEXT

³Balls that use V_DDMEMare DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AOE, AMS3–0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant

.

to voltages higher than V_DDMEM

.

⁴The V_PPOTPvoltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent

on voltage and junction temperature) over the lifetime of the part. Please see Table 30 on Page 38 for details.

⁵When not using the USB peripheral on the ADSP-BF524/ADSP-BF526 or terminating V_DDUSBon the ADSP-BF522, V_DDUSBmust be powered by V_DDEXT

⁶Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL.

.

⁷Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are

2.5 V tolerant (always accept up to 2.7 V maximum V_IH). Voltage compliance (on outputs, V_OH) is limited by the V_DDEXTsupply voltage.

⁸Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are

3.3 V tolerant (always accept up to 3.6 V maximum V_IH). Voltage compliance (on outputs, V_OH) is limited by the V_DDEXTsupply voltage.

⁹The V_IHTWImin and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See V_BUSTWImin and max values in Table 11.

¹⁰SDA and SCL are pulled up to V_BUSTWI. See Table 11.

Rev. D

|

Page 28 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 11 shows settings for TWI_DT in the NONGPIO_DRIVE

register. Set this register prior to using the TWI port.

Table 11. TWI_DT Field Selections and V_DDEXT/V_BUSTWI

TWI_DT

V_DDEXTNominal

V_BUSTWIMin

2.97

1.7

V_BUSTWINominal

V_BUSTWIMax

3.63

1.98

3.63

5.5

Unit

V

000 (default)¹

3.3

1.8

2.5

1.8

3.3

1.8

2.5

–

3.3

1.8

3.3

5

001

V

010

2.97

4.5

V

011

V

100

V

101

2.25

–

2.5

–

2.75

–

V

110

V

111 (reserved)

–

¹Designs must comply with the V_DDEXTand V_BUSTWIvoltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.

Clock Related Operating Conditions

for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

Table 12 describes the core clock timing requirements for the

ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Take care

in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the

maximum core clock and system clock (see Table 14). Table 13

describes phase-locked loop operating conditions.

Table 12. Core Clock (CCLK) Requirements (All Instruction Rates¹) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

Parameter

f_CCLK

Nominal Voltage Setting Max

Unit

MHz

Core Clock Frequency (V_DDINT=1.33 V minimum)

Core Clock Frequency (V_DDINT= 1.235 V minimum)

1.40 V

1.30 V

400²

f_CCLK

300

¹See the Ordering Guide on Page 88.

²Applies to 400 MHz models only. See the Ordering Guide on Page 88.

Table 13. Phase-Locked Loop Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

Parameter

Min

Max

Instruction Rate¹

Unit

f_VCO

Voltage Controlled Oscillator (VCO) Frequency

70

MHz

¹See the Ordering Guide on Page 88.

Table 14. SCLK Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

V_DDEXT/V_DDMEM

2.5 V or 3.3 V Nominal

Max

1.8 V Nominal¹

Parameter

f_SCLK

Max

80

Unit

MHz

CLKOUT/SCLK Frequency (V_DDINT≥ 1.33 V)²

CLKOUT/SCLK Frequency (V_DDINT< 1.33 V)

100

f_SCLK

80

¹If either V_DDEXTor V_DDMEMare operating at 1.8 V nominal, f_SCLKis constrained to 80 MHz.

²f_SCLKmust be less than or equal to f_CCLKand is subject to additional restrictions for SDRAM interface operation. See Table 37 on Page 47.

Rev. D

|

Page 29 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

OPERATING CONDITIONS FOR ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS

Parameter

V_DDINT

Conditions

Nonautomotive models²

Automotive 533 MHz models³1.093

Automotive 400 MHz models³1.045

Min

Nominal

Max

1.26

1.20

1.9

Unit

Internal Supply Voltage¹

External Supply Voltage^{4, 5}

0.95

V

V_DDINT

1.15

1.10

1.8

V_DDINT

V_DDEXT

Nonautomotive models,

Internal Voltage Regulator

Disabled

1.7

V_DDEXT

V_DDRTC

V_DDMEM

V_DDOTP

V_PPOTP

V_DDUSB

V_IH

External Supply Voltage^{4, 5}

RTC Power Supply Voltage⁶Nonautomotive models

RTC Power Supply Voltage⁶Automotive models

MEM Supply Voltage^{4, 7}

OTP Supply Voltage⁴

OTP Programming Voltage⁴

USB Supply Voltage⁸

High Level Input Voltage^{9, 10}V_DDEXT/V_DDMEM= 1.90 V

High Level Input Voltage^{10, 11}V_DDEXT/V_DDMEM= 2.75 V

High Level Input Voltage^{10, 11}V_DDEXT/V_DDMEM= 3.6 V

High Level Input Voltage¹²V_DDEXT= 1.90 V/2.75 V/3.6 V 0.7 × V_BUSTWI

Low Level Input Voltage^{9, 10}V_DDEXT/V_DDMEM= 1.7 V

Low Level Input Voltage^{10, 11}V_DDEXT/V_DDMEM= 2.25 V

Low Level Input Voltage^{10, 11}V_DDEXT/V_DDMEM= 3.0 V

Nonautomotive models

Automotive models

2.25

3

2.5

3.3

2.75

3.6

V

°C

2.7

2.25

2.7

1.7

2.25

3

3.6

3.3

1.8

2.5

3.3

2.5

3.3

3.6

Nonautomotive models

Automotive models

1.9

2.75

3.6

2.7

2.25

3.0

1.1

1.7

2.0

3.6

2.75

3.6

V_IH

V_IHTWI

V_IL

V_BUSTWI

0.6

V_IL

0.7

V_IL

0.8

13

V_ILTWI

T_J

Low Level Input Voltage

Junction Temperature

V_DDEXT= Minimum

0.3 × V_BUSTWI

+105

289-Ball CSP_BGA

0

@ T_AMBIENT= 0°C to +70°C

T_J

Junction Temperature

289-Ball CSP_BGA

@ T_AMBIENT= –40°C to +70°C

–40

0

+105

°C

208-Ball CSP_BGA

@ T_AMBIENT= 0°C to +70°C

208-Ball CSP_BGA

–40

@ T_AMBIENT= –40°C to +85°C

¹The voltage regulator can generate V_DDINTat levels of 1.00 V to 1.20 V with –5% to +5% tolerance when VRCTL is programmed with the bfrom_SysControl() API. This

specification is only guaranteed when the API is used.

²See Ordering Guide on Page 88.

³See Automotive Products on Page 87.

⁴Must remain powered (even if the associated function is not used).

⁵V_DDEXTis the supply to the voltage regulator and GPIO.

⁶If not used, power with V_DDEXT

.

⁷Balls that use V_DDMEMare DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AOE, AMS3–0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant

to voltages higher than V_DDMEM

.

⁸When not using the USB peripheral on the ADSP-BF525/ADSP-BF527 or terminating V_DDUSBon the ADSP-BF523, V_DDUSBmust be powered by V_DDEXT

.

⁹Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are

2.5 V tolerant (always accept up to 2.7 V maximum V_IH). Voltage compliance (on outputs, V_OH) is limited by the V_DDEXTsupply voltage.

¹⁰Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL.

¹¹Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are

3.3 V tolerant (always accept up to 3.6 V maximum V_IH). Voltage compliance (on outputs, V_OH) is limited by the V_DDEXTsupply voltage.

¹²The V_IHTWImin and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See V_BUSTWImin and max values in Table 11 on Page 29.

¹³SDA and SCL are pulled up to V_BUSTWI. See Table 11 on Page 29.

Rev. D

|

Page 30 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Clock Related Operating Conditions

for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

Table 15 describes the core clock timing requirements for the

ADSP-BF523/ADSP-BF525/ADSP-BF527 processors. Take care

in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the

maximum core clock and system clock (see Table 17). Table 16

describes phase-locked loop operating conditions.

Use the nominal voltage setting (Table 15) for internal and

external regulators.

Table 15. Core Clock (CCLK) Requirements (All Instruction Rates¹) for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

Parameter

f_CCLK

Nominal Voltage Setting Max

Unit

MHz

Core Clock Frequency (V_DDINT=1.14 V minimum)

Core Clock Frequency (V_DDINT=1.093 V minimum)

Core Clock Frequency (V_DDINT= 1.045 V minimum)⁴

Core Clock Frequency (V_DDINT= 0.95 V minimum)

1.20 V

1.15 V

1.10 V

1.0 V

600²

533³

400

f_CCLK

400

¹See the Ordering Guide on Page 88.

²Applies to 600 MHz models only. See the Ordering Guide on Page 88.

³Applies to 533 MHz and 600 MHz models only. See the Ordering Guide on Page 88.

⁴Applies only to automotive products. See Automotive Products on Page 87.

Table 16. Phase-Locked Loop Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

Parameter

Min

Max

Instruction Rate¹

Unit

f_VCO

Voltage Controlled Oscillator (VCO) Frequency

(Commercial/Industrial Models)

60

MHz

f_VCO

Voltage Controlled Oscillator (VCO) Frequency

(Automotive Models)

70

Instruction Rate¹

MHz

¹See the Ordering Guide on Page 88.

Table 17. SCLK Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

V_DDEXT/V_DDMEM

2.5 V or 3.3 V Nominal

Max

1.8 V Nominal¹

Parameter

f_SCLK

Max

100

Unit

MHz

CLKOUT/SCLK Frequency (V_DDINT≥ 1.14 V)²

CLKOUT/SCLK Frequency (V_DDINT< 1.14 V)²

133³

f_SCLK

100

¹If either V_DDEXTor V_DDMEMare operating at 1.8 V nominal, f_SCLKis constrained to 100 MHz.

²f_SCLKmust be less than or equal to f_CCLKand is subject to additional restrictions for SDRAM interface operation. See Table 38 on Page 47.

³Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 38 on Page 47.

Rev. D

|

Page 31 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

ELECTRICAL CHARACTERISTICS

Table 18. Common Electrical Characteristics for All ADSP-BF52x Processors

Parameter

Test Conditions

Min

Typical

Max

Unit

V_OH

High Level Output Voltage

Low Level Output Voltage

V_DDEXT/V_DDMEM= 1.7 V,

I_OH= –0.5 mA

1.35

V

V_OH

V_OL

V_DDEXT/V_DDMEM= 2.25 V,

I_OH= –0.5 mA

2.0

2.4

V

V_DDEXT/V_DDMEM= 3.0 V,

I_OH= –0.5 mA

V_DDEXT/V_DDMEM= 1.7 V/2.25 V/

3.0 V,

0.4

I_OL= 2.0 mA

I_IH

High Level Input Current¹

Low Level Input Current¹

High Level Input Current JTAG²V_DDEXT= 3.6 V, V_IN= 3.6 V

Three-State Leakage Current³V_DDEXT/V_DDMEM= 3.6 V,

V_IN= 3.6 V

V_DDEXT/V_DDMEM=3.6 V,

V_IN= 3.6 V

10.0

μA

I_IL

V_DDEXT/V_DDMEM=3.6 V, V_IN= 0 V

10.0

75.0

10.0

μA

I_IHP

I_OZH

I_OZHTWI

I_OZL

Three-State Leakage Current⁴V_DDEXT=3.0 V, V_IN= 5.5 V

Three-State Leakage Current³V_DDEXT/V_DDMEM= 3.6 V, V_IN= 0 V

10.0

8

μA

pF

C_IN

Input Capacitance^5,6

f_IN= 1 MHz, T_AMBIENT= 25°C,

V_IN= 2.5 V

5

C_INTWI

Input Capacitance^4,6

f_IN= 1 MHz, T_AMBIENT= 25°C,

V_IN= 2.5 V

15

pF

¹Applies to input balls.

²Applies to JTAG input balls (TCK, TDI, TMS, TRST).

³Applies to three-statable balls.

⁴Applies to bidirectional balls SCL and SDA.

⁵Applies to all signal balls, except SCL and SDA.

⁶Guaranteed, but not tested.

Rev. D

|

Page 32 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 19. Electrical Characteristics for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

Parameter

Test Conditions

Min

Typical

Max

Unit

1

I_DDDEEPSLEEP

V_DDINTCurrent in V_DDINT= 1.3 V, f_CCLK= 0 MHz, f_SCLK= 0 MHz,

Deep Sleep Mode T_J= 25°C, ASF = 0.00

2

mA

I_DDSLEEP

I_DD-IDLE

I_DD-TYP

V_DDINTCurrent in V_DDINT= 1.3 V, f_SCLK= 25 MHz, T_J= 25°C

Sleep Mode

13

mA

μA

V_DDINTCurrent in V_DDINT= 1.3 V, f_CCLK= 300 MHz, f_SCLK= 25 MHz,

44

Idle

T_J= 25°C, ASF = 0.4

V_DDINTCurrent

V_DDINT= 1.3 V, f_CCLK= 300 MHz, f_SCLK= 25 MHz,

T_J= 25°C, ASF = 1.00

83

V_DDINTCurrent

V_DDINT= 1.4 V, f_CCLK= 400 MHz, f_SCLK= 25 MHz,

T_J= 25°C, ASF = 1.00

114

40

1, 2

I_DDHIBERNATE

Hibernate State V_DDEXT=V_DDMEM=V_DDRTC=V_DDUSB= 3.30 V,

Current

V_DDOTP=V_PPOTP=2.5 V, T_J= 25°C, CLKIN = 0 MHz

with voltage regulator off (V_DDINT= 0 V)

I_DDRTC

V_DDRTCCurrent

V_DDRTC= 3.3 V, T_J= 25°C

20

9

μA

I_DDUSB-FS

V_DDUSBCurrent in V_DDUSB= 3.3 V, T_J= 25°C, Full Speed USB Transmit

mA

Full/Low Speed

Mode

I_DDUSB-HS

V_DDUSBCurrent in V_DDUSB= 3.3 V, T_J= 25°C, High Speed USB Transmit

High Speed Mode

25

mA

mA⁴

mA

1, 3

I_DDSLEEP

V_DDINITCurrent in f_CCLK= 0 MHz, f_SCLK> 0 MHz

Sleep Mode

Table 22 +

(0.52 × V_DDINT× f_SCLK

4

)

1, 3

I_DDDEEPSLEEP

V_DDINTCurrent in f_CCLK= 0 MHz, f_SCLK= 0 MHz

Deep Sleep Mode

Table 22

3, 5

I_DDINT

V_DDINTCurrent

f_CCLK> 0 MHz, f_SCLK≥ 0 MHz

Table 22 +

(Table 23 × ASF) +

(0.52 × V_DDINT× f_SCLK

I_DDOTP

I_PPOTP

V_DDOTPCurrent

V_PPOTPCurrent

V_DDOTP= 2.5 V, T_J= 25°C, OTP Memory Read

V_DDOTP= 2.5 V, T_J= 25°C, OTP Memory Write

V_PPOTP= 2.5 V, T_J= 25°C, OTP Memory Read

2

mA

μA

2

100

3

V_PPOTP= see Table 30, T_J= 25°C, OTP Memory

Write

mA

¹See the ADSP-BF52x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.

²Includes current on V_DDEXT, V_DDUSB, V_DDMEM, V_DDOTP, and V_PPOTPsupplies. Clock inputs are tied high or low.

³Guaranteed maximum specifications.

⁴Unit for V_DDINTis V (Volts). Unit for f_SCLKis MHz. Example: 1.4 V, 75 MHz would be 0.52 × 1.4 × 75 = 54.6 mA adder.

⁵See Table 21 for the list of I_DDINTpower vectors covered.

Rev. D

|

Page 33 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 20. Electrical Characteristics for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

Parameter

Test Conditions

Min

Typical

Max

Unit

1

I_DDDEEPSLEEP

V_DDINTCurrent in V_DDINT= 1.0 V, f_CCLK= 0 MHz, f_SCLK= 0 MHz,

Deep Sleep Mode T_J= 25°C, ASF = 0.00

10

mA

I_DDSLEEP

I_DD-IDLE

I_DD-TYP

V_DDINTCurrent in V_DDINT= 1.0 V, f_SCLK= 25 MHz, T_J= 25°C

Sleep Mode

20

mA

μA

V_DDINTCurrent in V_DDINT= 1.0 V, f_CCLK= 400 MHz, f_SCLK= 25 MHz,

53

Idle

T_J= 25°C, ASF = 0.44

V_DDINTCurrent

V_DDINT= 1.0 V, f_CCLK= 400 MHz, f_SCLK= 25 MHz,

T_J= 25°C, ASF = 1.00

94

V_DDINTCurrent

V_DDINT= 1.15 V, f_CCLK= 533 MHz, f_SCLK= 25 MHz,

T_J= 25°C, ASF = 1.00

144

170

40

V_DDINT= 1.2 V, f_CCLK= 600 MHz, f_SCLK= 25 MHz,

T_J= 25°C, ASF = 1.00

1, 2

I_DDHIBERNATE

Hibernate State V_DDEXT=V_DDMEM=V_DDRTC= V_DDUSB= 3.30 V,

Current

V_DDOTP=V_PPOTP=2.5 V, T_J= 25°C, CLKIN = 0 MHz

with voltage regulator off (V_DDINT= 0 V)

I_DDRTC

V_DDRTCCurrent

V_DDRTC= 3.3 V, T_J= 25°C

20

9

μA

I_DDUSB-FS

V_DDUSBCurrent in V_DDUSB= 3.3 V, T_J= 25°C, Full Speed USB Transmit

mA

Full/Low Speed

Mode

I_DDUSB-HS

V_DDUSBCurrent in V_DDUSB= 3.3 V, T_J= 25°C, High Speed USB

High Speed Mode Transmit

25

mA

mA⁴

mA

1, 3

I_DDSLEEP

V_DDINTCurrent in f_CCLK= 0 MHz, f_SCLK> 0 MHz

Sleep Mode

Table 24 + (0.61 ×

4

V_DDINT× f_SCLK

)

1, 3

I_DDDEEPSLEEP

V_DDINTCurrent in f_CCLK= 0 MHz, f_SCLK= 0 MHz

Deep Sleep Mode

Table 24

3, 5

I_DDINT

V_DDINTCurrent

f_CCLK> 0 MHz, f_SCLK≥ 0 MHz

Table 24 + (Table 25 mA

× ASF) + (0.61 × V_DDINT

× f_SCLK

)

I_DDOTP

I_PPOTP

V_DDOTPCurrent

V_PPOTPCurrent

V_DDOTP= 2.5 V, T_J= 25°C, OTP Memory Read

V_DDOTP= 2.5 V, T_J= 25°C, OTP Memory Write

V_PPOTP= 2.5 V, T_J= 25°C, OTP Memory Read

V_PPOTP= 2.5 V, T_J= 25°C, OTP Memory Write

1

mA

25

0

¹See the ADSP-BF52x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.

²Includes current on V_DDEXT, V_DDUSB, V_DDMEM, V_DDOTP, and V_PPOTPsupplies. Clock inputs are tied high or low.

³Guaranteed maximum specifications.

⁴Unit for V_DDINTis V (Volts). Unit for f_SCLKis MHz. Example: 1.2 V, 75 MHz would be 0.61 × 1.2 × 75 = 54.9 mA adder.

⁵See Table 21 for the list of I_DDINTpower vectors covered.

Rev. D

|

Page 34 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Total Power Dissipation

Total power dissipation has two components:

1. Static, including leakage current

The ASF is combined with the CCLK Frequency and V_DDINT

dependent data in Table 23 or Table 25 to calculate this part.

The second part is due to transistor switching in the system

clock (SCLK) domain, which is included in the I_DDINTspecifica-

tion equation.

2. Dynamic, due to transistor switching characteristics

Many operating conditions can also affect power dissipation,

including temperature, voltage, operating frequency, and pro-

cessor activity. Electrical Characteristics on Page 32 shows the

current dissipation for internal circuitry (V_DDINT). I_DDDEEPSLEEP

specifies static power dissipation as a function of voltage

(V_DDINT) and temperature (see Table 22 or Table 24), and I_DDINT

specifies the total power specification for the listed test condi-

tions, including the dynamic component as a function of voltage

(V_DDINT) and frequency (Table 23 or Table 25).

Table 21. Activity Scaling Factors (ASF)¹

I_DDINTPower Vector

I_DD-PEAK

Activity Scaling Factor (ASF)

1.29

1.26

1.00

0.88

0.72

0.44

I_DD-HIGH

I_DD-TYP

I_DD-APP

There are two parts to the dynamic component. The first part is

due to transistor switching in the core clock (CCLK) domain.

This part is subject to an Activity Scaling Factor (ASF) which

represents application code running on the processor core and

L1 memories (Table 21).

I_DD-NOP

I_DD-IDLE

¹See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors

(EE-297). The power vector information also applies to the ADSP-BF52x

processors.

Table 22. Static Current — I_DD-DEEPSLEEP(mA) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

1

Voltage (V_DDINT

1.35 V

1.64

)

T_J(°C)¹

–40

–20

0

1.2 V

1.47

1.67

1.97

2.49

3.12

4.07

5.77

8.32

12.11

13.78

1.25 V

1.42

1.3 V

1.50

1.89

2.15

2.79

3.57

4.82

6.71

9.56

13.94

15.74

1.4 V

1.85

1.45 V

2.12

1.5 V

2.09

1.81

1.95

2.01

2.07

2.12

2.07

2.22

2.30

2.39

2.47

25

2.66

2.92

3.07

3.20

3.36

40

3.37

3.75

3.96

4.18

4.40

55

4.47

5.11

5.41

5.73

6.06

70

6.28

7.17

7.61

8.09

8.60

85

8.88

10.25

14.76

16.81

10.94

15.76

17.91

11.63

16.77

19.06

12.36

17.83

20.27

100

12.93

105

14.72

¹Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page 28.

Table 23. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)¹for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

2

f_CCLK

Voltage (V_DDINT

1.35 V

95.7

)

(MHz)²

1.2 V

N/A

1.25 V

N/A

1.3 V

91.41

80.56

69.78

58.88

48.08

26.29

1.4 V

100.11

88.26

76.51

64.64

52.86

29.12

1.45 V

104.51

92.17

79.93

67.56

55.28

30.56

1.5 V

109.01

96.17

83.42

70.55

57.77

32.04

400

350

300

250

200

100

N/A

84.37

63.31

53.36

43.49

23.6

66.51

56.10

45.76

24.93

73.09

61.72

50.44

27.68

¹The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 32.

²Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page 28.

Rev. D

|

Page 35 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 24. Static Current — I_DD-DEEPSLEEP(mA) for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

1

Voltage (V_DDINT

)

T_J(°C)¹

–40

–20

0

0.95 V

6.5

1.00 V

7.8

1.05 V

9.3

1.10 V

11.1

1.15 V

13.1

1.20 V

15.4

1.25 V

18.0

1.30 V

21.0

9.0

10.6

12.4

14.6

17.0

19.8

22.9

26.4

13.2

22.3

30.8

42.9

59.1

80.4

109.3

120.8

144.4

173.9

15.2

17.7

20.4

23.5

27.0

30.9

35.3

25

25.4

28.9

32.8

37.2

42.1

47.6

53.7

40

34.8

39.2

44.1

49.6

55.7

62.5

70.0

55

47.9

53.6

59.9

66.9

74.6

83.2

92.6

70

65.6

72.9

80.8

89.7

99.4

110.2

145.1

189.7

209.3

246.4

292.2

122.0

159.8

208.1

229.2

269.2

318.7

85

88.6

97.9

107.8

143.2

158.8

188.4

224.9

119.2

157.4

174.2

206.0

245.4

131.5

172.8

190.9

225.3

267.8

100

105

115

125

118.7

132.1

157.5

189.1

130.5

144.7

172.3

206.4

¹Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page 30.

Table 25. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)¹for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

2

f_CCLK

Voltage (V_DDINT)

(MHz)²

0.95 V

N/A

1.00 V

N/A

1.05 V

N/A

1.10 V

N/A

1.15 V

130.4

116.7

109.1

88.5

1.20 V

137.6

123.3

115.0

93.5

1.25 V

145.1

129.8

121.3

98.6

1.30 V

152.5

136.4

127.7

103.9

80.0

600

533

500

400

300

200

100

N/A

110.3

103.1

83.6

N/A

97.3

78.9

60.4

41.9

23.6

69.8

53.4

36.9

20.5

74.3

56.9

39.4

22.0

64.1

68.0

71.8

75.8

44.6

47.4

50.1

53.0

56.0

25.3

27.0

28.8

30.6

32.5

¹The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 32.

²Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page 30.

Rev. D

|

Page 36 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 26 may cause perma-

nent damage to the device. These are stress ratings only.

Functional operation of the device at these or any other condi-

Table 26. Absolute Maximum Ratings

Parameter

Rating

Internal Supply Voltage (V_DDINT) for ADSP-BF523/ADSP-BF525/ADSP-BF527 processors

Internal Supply Voltage (V_DDINT) for ADSP-BF522/ADSP-BF524/ADSP-BF526 processors

–0.3 V to +1.26 V

–0.3 V to +1.47 V

–0.3 V to +3.8 V

–0.5 V to +3.8 V

–0.5 V to +3.0 V

–0.5 V to +7.1 V

–0.5 V to +3.8 V

–0.5 V to +5.5 V

–0.5 V to +5.25 V

–0.5 V to V_DDEXT/V_DDMEM+ 0.5 V

82 mA (max)

External (I/O) Supply Voltage (V_DDEXT/V_DDMEM

Real-Time Clock Supply Voltage (V_DDRTC

OTP Supply Voltage (V_DDOTP

)

1

OTP Programming Voltage (V_PPOTP

)

2

USB PHY Supply Voltage (V_DDUSB

Input Voltage^{3, 4, 5}

)

Input Voltage^{3, 4, 6}

Input Voltage^{3, 4, 7}

Output Voltage Swing

I_OH/I_OLCurrent per Pin Group^{3, 8}

Storage Temperature Range

–65°C to +150°C

+110°C

Junction Temperature While Biased

¹Applies to OTP memory reads and writes for ADSP-BF523/ADSP-BF525/ADSP-BF527 processors and to OTP memory reads for ADSP-BF522/ADSP-BF524/ADSP-BF526

processors.

²Applies only to OTP memory writes for ADSP-BF522/ADSP-BF524/ADSP-BF526 processors.

³Applies to 100% transient duty cycle.

⁴Applies only when V_DDEXTis within specifications. When V_DDEXTis outside specifications, the range is V_DDEXT0.2 V.

⁵For other duty cycles see Table 27.

⁶Applies to balls SCL and SDA.

⁷Applies to balls USB_DP, USB_DM, and USB_VBUS.

⁸For pin group information, see Table 28. For other duty cycles see Table 29.

Table 27. Maximum Duty Cycle for Input Transient Volt-

age^{1, 2}

Table 26 specifies the maximum total source/sink (I_OH/I_OL) cur-

rent for a group of pins. Permanent damage can occur if this

value is exceeded. To understand this specification, if pins PH4,

PH3, PH2, PH1, and PH0 from group 1 in Table 28 were sourc-

ing or sinking 2 mA each, the total current for those pins would

be 10 mA. This would allow up to 72 mA total that could be

sourced or sunk by the remaining pins in the group without

damaging the device. For a list of all groups and their pins, see

the Table 28 table. For duty cycles that are less than 100%, see

Table 29. Note that the V_OHand V_OLspecifications have separate

per-pin maximum current requirements (see Table 19 on

Page 33 and Table 20 on Page 34).

Maximum Duty Cycle³V_INMin (V)⁴

V_INMax (V)⁶

+3.80

100%

40%

25%

15%

10%

–0.50

–0.70

–0.80

–0.90

–1.00

+4.00

+4.10

+4.20

+4.30

¹Applies to all signal balls with the exception of CLKIN, XTAL, VR_OUT

/

EXT_WAKE1, SCL, SDA, USB_DP, USB_DM, and USB_VBUS.

²Applies only when V_DDEXTis within specifications. When V_DDEXTis outside specifi-

cations, the range is V_DDEXT0.2 V.

Table 28. Total Current Pin Groups

³Duty cycle refers to the percentage of time the signal exceeds the value for the 100%

case. The is equivalent to the measured duration of a single instance of overshoot

or undershoot as a percentage of the period of occurrence.

Group Pins in Group

1

2

3

4

5

PH4, PH3, PH2, PH1, PH0, PF15, PF14, PF13

PF12, SDA, SCL, PF11, PF10, PF9, PF8, PF7

⁴The individual values cannot be combined for analysis of a single instance of

overshoot or undershoot. The worst case observed value must fall within one of the

voltagesspecified, andthetotaldurationoftheovershootorundershoot(exceeding

the 100% case) must be less than or equal to the corresponding duty cycle.

PF6, PF5, PF4, PF3, PF2, PF1, PF0, PPI_FS1

PPI_CLK, PG15, PG14, PG13, PG12, PG11, PG10, PG9

PG8, PG7, PG6, PG5, PG4, BMODE3, BMODE2, BMODE1

Rev. D

|

Page 37 of 88

|

July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 28. Total Current Pin Groups (Continued)

PACKAGE INFORMATION

The information presented in Figure 8 and Table 31 provides

details about the package branding for the ADSP-BF52x proces-

sors. For a complete listing of product availability, see Ordering

Guide on Page 88.

Group Pins in Group

6

BMODE0, PG3, PG2, PG1, PG0, TDI, TDO, EMU

TCK, TRST, TMS

7

8

PH12, PH11, PH10, PH9, PH8, PH7, PH6, PH5

PH15, PH14, PH13, CLKBUF, NMI, RESET

DATA15, DATA14, DATA13, DATA12, DATA11, DATA10

DATA9, DATA8, DATA7, DATA6, DATA5, DATA4

DATA3, DATA2, DATA1, DATA0, ADDR19, ADDR18

ADDR17, ADDR16, ADDR15, ADDR14, ADDR13

ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7

ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1

ABE1, ABE0, SA10, SWE, SCAS, SRAS

9

10

11

12

13

14

15

16

17

18

a

ADSP-BF52x

tppZccc

vvvvvv.x n.n

#yyww country_of_origin

B

Figure 8. Product Information on Package

Table 31. Package Brand Information¹

SMS, SCKE, ARDY, AWE, ARE, AOE

AMS3, AMS2, AMS1, AMS0, CLKOUT

Table 29. Maximum Duty Cycle for I_OH/I_OLCurrent Per Pin

Group

Brand Key

Field Description

Product Name²

ADSP-BF52x

t

Temperature Range

Package Type

Maximum Duty Cycle

RMS Current (mA)

pp

100%

80%

60%

40%

25%

10%

82

Z

Lead Free Option

See Ordering Guide

Assembly Lot Code

Silicon Revision

92

ccc

106

130

165

261

vvvvvv.x

n.n

#

RoHS Compliance Designator

Date Code

yyww

When programming OTP memory on the ADSP-BF522/

ADSP-BF524/ADSP-BF526 processors, the VPPOTP ball must

be set to the write value specified in the Operating Conditions

for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on

Page 28. There is a finite amount of cumulative time that the

write voltage may be applied (dependent on voltage and junc-

tion temperature) to VPPOTP over the lifetime of the part.

Therefore, maximum OTP memory programming time for the

ADSP-BF522/ADSP-BF524/ADSP-BF526 processors is shown

in Table 30. The ADSP-BF523/ADSP-BF525/ADSP-BF527 pro-

cessors do not have a similar restriction.

¹Non Automotive only. For branding information specific to Automotive

products, contact Analog Devices Inc.

²See product names in the Ordering Guide on Page 88.

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

Table 30. Maximum OTP Memory Programming Time for

ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

Temperature (T_J)

V_PPOTPVoltage (V)

25°C

85°C

105°C

25 sec

12 sec

4.5 sec

6.9

7.0

7.1

6000 sec

2400 sec

1000 sec

100 sec

44 sec

18 sec

Rev. D

|

Page 38 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

TIMING SPECIFICATIONS

Specifications are subject to change without notice.

Clock and Reset Timing

Table 32 and Figure 9 describe clock and reset operations. Per

the CCLK and SCLK timing specifications in Table 12 to

Table 17, combinations of CLKIN and clock multipliers must

not select core/peripheral clocks in excess of the processor's

maximum instruction rate.

Table 32. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

f_CKIN

CLKIN Frequency (Commercial/ Industrial Models) ^{1, 2, 3, 4}12

50

MHz

ns

CLKIN Frequency (Automotive Models) ^{1, 2, 3, 4}

CLKIN Low Pulse¹

14

t_CKINL

t_CKINH

t_WRST

10

CLKIN High Pulse¹

10

ns

RESET Asserted Pulse Width Low⁵

11 × t_CKIN

ns

Switching Characteristic

t_BUFDLAY

CLKIN to CLKBUF Delay

10

ns

¹Applies to PLL bypass mode and PLL nonbypass mode.

²Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f_VCO, f_CCLK, and f_SCLKsettings discussed in Table 12 on Page 29 through

Table 14 on Page 29 and Table 15 on Page 31 through Table 17 on Page 31.

³The t_CKINperiod (see Figure 9) equals 1/f_CKIN

.

⁴If the DF bit in the PLL_CTL register is set, the minimum f_CKINspecification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.

⁵Applies after power-up sequence is complete. See Table 33 and Figure 10 for power-up reset timing.

t_CKIN

CLKIN

t_BUFDLAY

t_CKINL

t_CKINH

t_BUFDLAY

CLKBUF

t_WRST

RESET

Figure 9. Clock and Reset Timing

Rev. D

|

Page 39 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 33. Power-Up Reset Timing

Parameter

Min

Max

Unit

Timing Requirement

t_{RST_IN_PWR}RESET Deasserted after the V_DDINT, V_DDEXT, V_DDRTC, V_DDUSB, V_DDMEM, V_DDOTP, and CLKIN 3500 × t_CKIN

Pins are Stable and Within Specification

ns

t_{RST_IN_PWR}

RESET

CLKIN

V

DD_SUPPLIES

In Figure 10, V_{DD_SUPPLIES}is V_DDINT, V_DDEXT, V_DDRTC, V_DDUSB, V_DDMEM, and V_DDOTP

.

Figure 10. Power-Up Reset Timing

Rev. D

|

Page 40 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Asynchronous Memory Read Cycle Timing

Table 34. Asynchronous Memory Read Cycle Timing

ADSP-BF522/ADSP-BF524/

ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDMEM

1.8 V Nominal

V_DDMEM

2.5 V or 3.3 V

Nominal

V_DDMEM

1.8 V Nominal

V_DDMEM

2.5 V or 3.3 V

Nominal

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

t_SDAT

DATA15–0 Setup Before CLKOUT

2.1

1.2

4.0

0.2

2.1

0.8

4.0

0.2

2.1

0.9

4.0

0.2

2.1

0.8

4.0

0.2

ns

t_HDAT

t_SARDY

t_HARDY

DATA15–0 Hold After CLKOUT

ARDY Setup Before CLKOUT

ARDY Hold After CLKOUT

Switching Characteristics

t_DO

t_HO

Output Delay After CLKOUT¹

Output Hold After CLKOUT¹

6.0

ns

0.8

¹Output balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

SETUP

PROGRAMMED READ

ACCESS 4 CYCLES

ACCESS EXTENDED

3 CYCLES

HOLD

2 CYCLES

1 CYCLE

CLKOUT

t_DO

t_HO

AMSx

ABE1–0

ADDR19–1

AOE

ARE

t_DO

t_HO

t_SARDY

t_HARDY

ARDY

t_SARDY

t_HARDY

t_SDAT

t_HDAT

DATA 15–0

Figure 11. Asynchronous Memory Read Cycle Timing

Rev. D

|

Page 41 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Asynchronous Memory Write Cycle Timing

Table 35. Asynchronous Memory Write Cycle Timing

ADSP-BF522/ADSP-BF524/

ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDMEM

1.8 V Nominal

V_DDMEM

2.5 V or 3.3 V

Nominal

V_DDMEM

1.8 V Nominal

V_DDMEM

2.5 V or 3.3 V

Nominal

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

t_SARDY

t_HARDY

Switching Characteristics

ARDY Setup Before CLKOUT

4.0

0.2

4.0

0.2

4.0

0.2

4.0

0.2

ns

ARDY Hold After CLKOUT

t_DDAT

t_ENDAT

t_DO

DATA15–0 Disable After CLKOUT

6.0

ns

DATA15–0 Enable After CLKOUT

Output Delay After CLKOUT¹

Output Hold After CLKOUT¹

0.0

0.8

0.0

0.8

0.0

0.8

0.0

0.8

t_HO

¹Output balls include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AWE.

PROGRAMMED

WRITE

ACCESS

EXTEND HOLD

1 CYCLE 1 CYCLE

SETUP

2 CYCLES

ACCESS

2 CYCLES

CLKOUT

AMSx

t_DO

t_HO

ABE1–0

ADDR19–1

t_DO

t_HO

AWE

ARDY

t_SARDY

t_HARDY

t_ENDAT

t_HARDY

t_DDAT

t_SARDY

DATA 15–0

Figure 12. Asynchronous Memory Write Cycle Timing

Rev. D

|

Page 42 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

NAND Flash Controller Interface Timing

Table 36 and Figure 13 on Page 44 through Figure 17 on

Page 46 describe NAND Flash Controller Interface operations.

Table 36. NAND Flash Controller Interface Timing

V_DDEXT

1.8 V Nominal

2.5 V or 3.3 V Nominal

Parameter

Min

Unit

Write Cycle

Switching Characteristics

t_CWL

t_CH

t_CLEWL

t_CLH

t_ALEWL

t_ALH

ND_CE Setup Time to AWE Low

1.0 × t_SCLK– 4

ns

ND_CE Hold Time From AWE High

ND_CLE Setup Time to AWE Low

ND_CLE Hold Time From AWE high

ND_ALE Setup Time to AWE Low

ND_ALE Hold Time From AWE High

AWE Low to AWE high

3.0 × t_SCLK– 4

0.0

2.5 × t_SCLK– 4

0.0

2.5 × t_SCLK– 4

1

t_WP

(WR_DLY +1.0) × t_SCLK– 4

4.0 × t_SCLK– 4

(WR_DLY +1.0) × t_SCLK– 4

4.0 × t_SCLK– 4

t_WHWL

AWE High to AWE Low

1

t_WC

AWE Low to AWE Low

(WR_DLY +5.0) × t_SCLK– 4

(WR_DLY +1.5) × t_SCLK– 4

2.5 × t_SCLK– 4

(WR_DLY +5.0) × t_SCLK– 4

(WR_DLY +1.5) × t_SCLK– 4

2.5 × t_SCLK– 4

1

t_DWS

Data Setup Time for a Write Access

Data Hold Time for a Write Access

t_DWH

Read Cycle

Switching Characteristics

t_CRLND_CE Setup Time to ARE Low

t_CRH

1.0 × t_SCLK– 4

ns

ND_CE Hold Time From ARE High

ARE Low to ARE High

3.0 × t_SCLK– 4

1

t_RP

(RD_DLY +1.0) × t_SCLK– 4

4.0 × t_SCLK– 4

(RD_DLY +1.0) × t_SCLK– 4

4.0 × t_SCLK– 4

t_RHRL

ARE High to ARE Low

1

t_RC

ARE Low to ARE Low

(RD_DLY +5.0) × t_SCLK– 4

Timing Requirements (ADSP-BF522/ADSP-BF524/ADSP-BF526)

t_DRS

t_DRH

Data Setup Time for a Read Transaction

Data Hold Time for a Read Transaction

14.0

0.0

10.0

0.0

ns

Timing Requirements (ADSP-BF523/ADSP-BF525/ADSP-BF527)

t_DRS

t_DRH

Data Setup Time for a Read Transaction

Data Hold Time for a Read Transaction

11.0

0.0

8.0

0.0

ns

Write Followed by Read

Switching Characteristic

t_WHRL

AWE High to ARE Low

5.0 × t_SCLK– 4

ns

¹WR_DLY and RD_DLY are defined in the NFC_CTL register.

Rev. D

|

Page 43 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

t_CWL

t_CH

ND_CE

ND_CLE

t_CLEWL

t_ALEWL

t_CLH

t_ALH

ND_ALE

AWE

t_WP

t_DWH

t_DWS

ND_DATA

In Figure 13, ND_DATA is ND_D0–D7.

Figure 13. NAND Flash Controller Interface Timing — Command Write Cycle

t_CWL

ND_CE

ND_CLE

ND_ALE

t_CLEWL

t_ALH

t_ALEWL

t_WP

t_WHWL

AWE

t_WC

t_DWS

t_DWH

t_DWS

t_DWH

ND_DATA

In Figure 14, ND_DATA is ND_D0–D7.

Figure 14. NAND Flash Controller Interface Timing — Address Write Cycle

Rev. D

|

Page 44 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

t_CWL

ND_CE

t_CLEWL

ND_CLE

t_ALEWL

ND_ALE

t_WP

t_WC

AWE

t_WP

t_WHWL

t_DWS

t_DWH

t_DWS

t_DWH

ND_DATA

In Figure 15, ND_DATA is ND_D0–D7.

Figure 15. NAND Flash Controller Interface Timing — Data Write Operation

t_CRL

t_CRH

ND_CE

ND_CLE

ND_ALE

t_RP

t_RC

ARE

t_RP

t_RHRL

t_DRS

t_DRH

t_DRS

t_DRH

ND_DATA

In Figure 16, ND_DATA is ND_D0–D7.

Figure 16. NAND Flash Controller Interface Timing — Data Read Operation

Rev. D

|

Page 45 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

t_CLWL

ND_CE

ND_CLE

t_CLEWL

t_CLH

t_WP

AWE

ARE

t_WHRL

t_RP

t_DWS

t_DWH

t_DRS

t_DRH

ND_DATA

In Figure 17, ND_DATA is ND_D0–D7.

Figure 17. NAND Flash Controller Interface Timing — Write Followed by Read Operation

Rev. D

|

Page 46 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

SDRAM Interface Timing

Table 37. SDRAM Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

V_DDMEM

1.8V Nominal

2.5 V or 3.3V Nominal

Parameter

Timing Requirements

t_SSDAT

Min

Max

Min

Max

Unit

Data Setup Before CLKOUT

Data Hold After CLKOUT

1.5

1.3

1.5

0.8

ns

t_HSDAT

Switching Characteristics

t_SCLK

CLKOUT Period¹

12.5

5.0

10

ns

t_SCLKH

t_SCLKL

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

CLKOUT Width High

4.0

CLKOUT Width Low

5.0

Command, Address, Data Delay After CLKOUT²

Command, Address, Data Hold After CLKOUT²

Data Disable After CLKOUT

5.0

5.5

4.0

5.0

1.0

Data Enable After CLKOUT

0.0

¹The t_SCLKvalue is the inverse of the f_SCLKspecification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here.

²Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Table 38. SDRAM Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

V_DDMEM

1.8V Nominal

2.5 V or 3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SSDAT

t_HSDAT

Switching Characteristics

Data Setup Before CLKOUT

1.5

1.0

1.5

0.8

ns

Data Hold After CLKOUT

t_SCLK

CLKOUT Period¹

10

7.5

2.5

ns

t_SCLKH

t_SCLKL

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

CLKOUT Width High

2.5

CLKOUT Width Low

Command, Address, Data Delay After CLKOUT²

Command, Address, Data Hold After CLKOUT²

Data Disable After CLKOUT

4.0

5.0

4.0

1.0

Data Enable After CLKOUT

0.0

¹The t_SCLKvalue is the inverse of the f_SCLKspecification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here.

²Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Rev. D

|

Page 47 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

t_SCLK

CLKOUT

t_SSDAT

t_HSDAT

t_SCLKL

t_SCLKH

DATA (IN)

t_DCAD

t_DSDAT

t_ENSDAT

t_HCAD

DATA (OUT)

t_DCAD

t_HCAD

COMMAND,

ADDRESS

(OUT)

NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Figure 18. SDRAM Interface Timing

Rev. D

|

Page 48 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

External DMA Request Timing

Table 39, Table 40, and Figure 19 describe the External DMA

Request operations.

Table 39. External DMA Request Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors¹

V

_DDEXT/V_DDMEM

V_DDEXT/V_DDMEM

1.8 V Nominal

2.5 V or 3.3 V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_DS

DMARx Asserted to CLKOUT High Setup

9.0

0.0

6.0

ns

t_DH

CLKOUT High to DMARx Deasserted Hold Time

DMARx Active Pulse Width

0.0

t_DMARACT

t_DMARINACT

1.0 × t_SCLK

1.75 × t_SCLK

DMARx Inactive Pulse Width

1.75 × t_SCLK

¹Because the external DMA control pins are part of the V_DDEXTpower domain and the CLKOUT signal is part of the V_DDMEMpower domain, systems in which V_DDEXTand

_DDMEMare NOT equal may require level shifting logic for correct operation.

V

Table 40. External DMA Request Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors¹

V_DDEXT/V_DDMEM

1.8 V Nominal

V_DDEXT/V_DDMEM

2.5 V or 3.3 V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_DS

DMARx Asserted to CLKOUT High Setup

8.0

6.0

ns

t_DH

CLKOUT High to DMARx Deasserted Hold Time

DMARx Active Pulse Width

0.0

t_DMARACT

t_DMARINACT

1.0 × t_SCLK

1.75 × t_SCLK

1.0 × t_SCLK

1.75 × t_SCLK

DMARx Inactive Pulse Width

¹Because the external DMA control pins are part of the V_DDEXTpower domain and the CLKOUT signal is part of the V_DDMEMpower domain, systems in which V_DDEXTand

V_DDMEMare NOT equal may require level shifting logic for correct operation.

CLKOUT

t_DS

t_DH

DMAR0/1

(ACTIVE LOW)

t_DMARACT

t_DMARINACT

DMAR0/1

(ACTIVE HIGH)

Figure 19. External DMA Request Timing

Rev. D

|

Page 49 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Parallel Peripheral Interface Timing

Table 41 and Figure 20 on Page 51, Figure 24 on Page 55, and

Figure 27 on Page 57 describe parallel peripheral interface

operations.

Table 41. Parallel Peripheral Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

V_DDEXT

2.5 V or 3.3 V Nominal

1.8V Nominal

Parameter

Timing Requirements

t_PCLKW

Min

Max

Min

Max

Unit

PPI_CLK Width¹

PPI_CLK Period¹

6.4

ns

t_PCLK

25.0

20.0

Timing Requirements - GP Input and Frame Capture Modes

t_SFSPE

External Frame Sync Setup Before PPI_CLK

6.7

ns

(Nonsampling Edge for Rx, Sampling Edge for Tx)

t_HFSPE

t_SDRPE

t_HDRPE

External Frame Sync Hold After PPI_CLK

Receive Data Setup Before PPI_CLK

Receive Data Hold After PPI_CLK

1.2

4.1

2.0

1.2

3.5

1.6

ns

Switching Characteristics - GP Output and Frame Capture Modes

t_DFSPE

t_HOFSPE

t_DDTPE

t_HDTPE

Internal Frame Sync Delay After PPI_CLK

Internal Frame Sync Hold After PPI_CLK

Transmit Data Delay After PPI_CLK

Transmit Data Hold After PPI_CLK

8.0

8.2

8.0

ns

1.7

2.3

1.7

1.9

¹PPI_CLK frequency cannot exceed f_SCLK/2.

Table 42. Parallel Peripheral Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

V_DDEXT

1.8V Nominal

V_DDEXT

2.5 V or 3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_PCLKW

t_PCLK

Timing Requirements - GP Input and Frame Capture Modes

PPI_CLK Width¹

PPI_CLK Period¹

6.0

ns

20.0

15.0

t_SFSPE

External Frame Sync Setup Before PPI_CLK

6.7

ns

(Nonsampling Edge for Rx, Sampling Edge for Tx)

t_HFSPE

t_SDRPE

t_HDRPE

External Frame Sync Hold After PPI_CLK

Receive Data Setup Before PPI_CLK

Receive Data Hold After PPI_CLK

1.0

3.5

2.0

1.0

3.5

1.6

ns

Switching Characteristics - GP Output and Frame Capture Modes

t_DFSPE

t_HOFSPE

t_DDTPE

t_HDTPE

Internal Frame Sync Delay After PPI_CLK

Internal Frame Sync Hold After PPI_CLK

Transmit Data Delay After PPI_CLK

Transmit Data Hold After PPI_CLK

8.0

ns

1.7

2.3

1.7

1.9

¹PPI_CLK frequency cannot exceed f_SCLK/2.

Rev. D

|

Page 50 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

DATA SAMPLED /

FRAME SYNC SAMPLED

PPI_CLK

t_PCLKW

t_SFSPE

t_HFSPE

t_PCLK

PPI_FS1/2

PPI_DATA

t_SDRPE

t_HDRPE

Figure 20. PPI GP Rx Mode with External Frame Sync Timing

DATA DRIVEN /

FRAME SYNC SAMPLED

PPI_CLK

PPI_FS1/2

PPI_DATA

t_SFSPE

t_HFSPE

t_PCLKW

t_PCLK

t_DDTPE

t_HDTPE

Figure 21. PPI GP Tx Mode with External Frame Sync Timing

FRAME SYNC

DRIVEN

DATA

SAMPLED

PPI_CLK

PPI_FS1/2

PPI_DATA

t_DFSPE

t_PCLKW

t_HOFSPE

t_PCLK

t_SDRPE

t_HDRPE

Figure 22. PPI GP Rx Mode with Internal Frame Sync Timing

Rev. D

|

Page 51 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

FRAME SYNC

DRIVEN

DATA

DRIVEN

t_PCLK

DATA

DRIVEN

PPI_CLK

PPI_FS1/2

PPI_DATA

t_DFSPE

t_PCLKW

t_HOFSPE

t_DDTPE

t_HDTPE

Figure 23. PPI GP Tx Mode with Internal Frame Sync Timing

Rev. D

|

Page 52 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Serial Ports

Table 43 through Table 47 on Page 57 and Figure 24 on Page 55

through Figure 27 on Page 57 describe serial port operations.

Table 43. Serial Ports—External Clock

ADSP-BF522/ADSP-BF524/

ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDEXT

2.5 V or 3.3V

Nominal

V_DDEXT

2.5 V or 3.3V

Nominal

V_DDEXT

1.8V Nominal

V_DDEXT

1.8V Nominal

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

t_SFSETFSx/RFSx SetupBefore TSCLKxRSCLKx¹3.0

t_HFSETFSx/RFSx Hold After TSCLKx/RSCLKx¹3.0

3.0

ns

3.0

t_SDREReceive Data Setup Before RSCLKx¹

t_HDREReceive Data Hold After RSCLKx¹

t_SCLKEWTSCLKx/RSCLKx Width

3.0

3.5

3.0

3.5

3.0

7.0

4.5

7.0

4.5

t_SCLKETSCLKx/RSCLKx Period

2.0 × t_SCLK

4.0 × t_SCLKE

2.0 × t_SCLK

4.0 × t_SCLKE

2.0 × t_SCLK

4.0 × t_SCLKE

t_SUDTEStart-Up Delay From SPORT Enable To 4.0 × t_SCLKE

First External TFSx²

t_SUDREStart-Up Delay From SPORT Enable To 4.0 × t_SCLKE

First External RFSx²

4.0 × t_SCLKE

ns

Switching Characteristics

t_DFSETFSx/RFSx Delay After TSCLKx/RSCLKx

(Internally Generated TFSx/RFSx)³

10.0

ns

t_HOFSETFSx/RFSx Hold After TSCLKx/RSCLKx 0.0

(Internally Generated TFSx/RFSx)³

t_DDTETransmit Data Delay After TSCLKx³

0.0

ns

t_HDTETransmit Data Hold After TSCLKx³

0.0

¹Referenced to sample edge.

²Verified in design but untested.

³Referenced to drive edge.

Rev. D

|

Page 53 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 44. Serial Ports—Internal Clock for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

V_DDEXT

2.5 V or 3.3V Nominal

1.8V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SFSI

t_HFSI

t_SDRI

t_HDRI

TFSx/RFSx Setup Before TSCLKx/RSCLKx¹

11.0

–1.5

11.0

–1.5

9.6

ns

TFSx/RFSx Hold After TSCLKx/RSCLKx¹

Receive Data Setup Before RSCLKx¹

Receive Data Hold After RSCLKx¹

–1.5

9.6

–1.5

Switching Characteristics

t_SCLKIWTSCLKx/RSCLKx Width

10.0

8.0

ns

t_DFSI

t_HOFSI

t_DDTI

t_HDTI

TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)²

TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)²–2.0

Transmit Data Delay After TSCLKx²

3.0

–1.0

–1.5

Transmit Data Hold After TSCLKx²

–1.8

¹Referenced to sample edge.

²Referenced to drive edge.

Table 45. Serial Ports—Internal Clock for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

V_DDEXT

1.8V Nominal

V_DDEXT

2.5 V or 3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SFSI

t_HFSI

t_SDRI

t_HDRI

TFSx/RFSx Setup Before TSCLKx/RSCLKx¹

11.0

–1.5

11.0

–1.5

9.6

ns

TFSx/RFSx Hold After TSCLKx/RSCLKx¹

Receive Data Setup Before RSCLKx¹

Receive Data Hold After RSCLKx¹

–1.5

9.6

–1.5

Switching Characteristics

t_SCLKIWTSCLKx/RSCLKx Width

t_DFSI

4.5

ns

TFSx/RFSx Delay After TSCLKx/RSCLKx

(Internally Generated TFSx/RFSx)²

3.0

t_HOFSI

TFSx/RFSx Hold After TSCLKx/RSCLKx

(Internally Generated TFSx/RFSx)²

–1.0

–1.8

–1.0

–1.5

ns

t_DDTI

t_HDTI

Transmit Data Delay After TSCLKx²

Transmit Data Hold After TSCLKx²

ns

¹Referenced to sample edge.

²Referenced to drive edge.

Rev. D

|

Page 54 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

DATA RECEIVE—INTERNAL CLOCK

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DRIVE EDGE

SAMPLE EDGE

t_SCLKE

t_SCLKIW

t_SCLKEW

RSCLKx

t_DFSI

t_DFSE

t_HOFSI

t_HOFSE

RFSx

(OUTPUT)

t_SFSI

t_HFSI

t_SFSE

t_HFSE

RFSx

(INPUT)

t_HDRE

t_SDRI

t_HDRI

t_SDRE

DRx

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

SAMPLE EDGE

t_SCLKE

t_SCLKIW

t_SCLKEW

TSCLKx

t_DFSI

t_DFSE

t_HOFSI

t_HOFSE

TFSx

(OUTPUT)

t_SFSI

t_HFSI

t_SFSE

t_HFSE

TFSx

(INPUT)

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DTx

Figure 24. Serial Ports

TSCLKx

(INPUT)

t_SUDTE

TFSx

(INPUT)

RSCLKx

(INPUT)

t_SUDRE

RFSx

(INPUT)

FIRST

TSCLKx/RSCLKx

EDGE AFTER

SPORT ENABLED

Figure 25. Serial Port Start Up with External Clock and Frame Sync

Rev. D

|

Page 55 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 46. Serial Ports—Enable and Three-State

ADSP-BF522/ADSP-BF524/ADSP-BF526

ADSP-BF523/ADSP-BF525/ADSP-BF527

V_DDEXT

2.5 V or 3.3V Nominal

1.8V Nominal

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Switching Characteristics

t_DTENE

t_DDTTE

t_DTENI

t_DDTTI

Data Enable Delay from 0.0

0.0

ns

External TSCLKx¹

Data Disable Delay from

External TSCLKx¹

t_SCLK+1

Data Enable Delay from –2.0

Internal TSCLKx¹

–2.0

Data Disable Delay from

Internal TSCLKx¹

t_SCLK+1

¹Referenced to drive edge.

DRIVE EDGE

TSCLKx

DTx

t_DTENE/I

t_DDTTE/I

Figure 26. Serial Ports — Enable and Three-State

Rev. D

|

Page 56 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 47. Serial Ports — External Late Frame Sync

ADSP-BF522/ADSP-BF524/

ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Switching Characteristics

t_DDTLFSE

Data Delay from Late External TFSx

12.0

10.0

12.0

10.0

ns

or External RFSx in multi-channel mode

with MFD = 0^{1, 2}

t_DTENLFSE

Data Enable from External RFSx in multi- 0.0

channel mode with MFD = 0^{1, 2}

0.0

ns

¹When in multi-channel mode, TFSx enable and TFSx valid follow t_DTENLFSEand t_DDTLFSE

.

²If external RFSx/TFSx setup to RSCLKx/TSCLKx > t_SCLKE/2 then t_DDTTE/Iand t_DTENE/Iapply, otherwise t_DDTLFSEand t_DTENLFSEapply.

EXTERNAL RFSx IN MULTI-CHANNEL MODE

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

RSCLKx

RFSx

t_DDTLFSE

t_DTENLFSE

DTx

1ST BIT

LATE EXTERNAL TFSx

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

TSCLKx

TFSx

t_DDTLFSE

DTx

1ST BIT

Figure 27. Serial Ports — External Late Frame Sync

Rev. D

|

Page 57 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Serial Peripheral Interface (SPI) Port—Master Timing

Table 48 and Figure 28 describe SPI port master operations.

Table 48. Serial Peripheral Interface (SPI) Port—Master Timing

ADSP-BF522/ADSP-BF524/

ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

Parameter

Min

Max Min

Max Unit

Timing Requirements

t_SSPIDM

Data Input Valid to SCK Edge (Data 11.6

Input Setup)

9.6

11.6

–1.5

9.6

ns

t_HSPIDMSCK Sampling Edge to Data Input –1.5

Invalid

–1.5

Switching Characteristics

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

t_HDSM

SPISELx low to First SCK Edge

Serial Clock High Period

Serial Clock Low Period

Serial Clock Period

2 × t_SCLK–1.5

4 × t_SCLK–1.5

2 × t_SCLK–1.5

4 × t_SCLK–1.5

2 × t_SCLK–1.5

4 × t_SCLK–1.5

2 × t_SCLK–1.5

4 × t_SCLK–1.5

2 × t_SCLK–1.5

ns

Last SCK Edge to SPISELx High

Sequential Transfer Delay

t_SPITDM

t_DDSPIDMSCK Edge to Data Out Valid (Data

Out Delay)

6

ns

t_HDSPIDMSCK Edge to Data Out Invalid (Data –1.0

Out Hold)

–1.0

ns

SPIxSELy

(OUTPUT)

t_SDSCIM

t_SPICLM

t_SPICHM

t_SPICLK

t_HDSM

t_SPITDM

SPIxSCK

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

SPIxMOSI

(OUTPUT)

t_SSPIDM

CPHA = 1

t_HSPIDM

SPIxMISO

(INPUT)

t_HDSPIDM

t_DDSPIDM

SPIxMOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

CPHA = 0

SPIxMISO

(INPUT)

Figure 28. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. D

|

Page 58 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 49 and Figure 29 describe SPI port slave operations.

Table 49. Serial Peripheral Interface (SPI) Port—Slave Timing

ADSP-BF522/ADSP-BF524/

ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

Parameter

Min

Max Min

Max Unit

Timing Requirements

t_SPICHS

t_SPICLS

t_SPICLK

Serial Clock High Period

2×t_SCLK–1.5

2 × t_SCLK–1.5

4 × t_SCLK–1.5

ns

Serial Clock Low Period

Serial Clock Period

2 × t_SCLK–1.5

4 × t_SCLK–1.5

4 ×

t_SCLK–1.5

t_HDS

Last SCK Edge to SPISS Not Asserted

Sequential Transfer Delay

2×t_SCLK–1.5

2 ×t_SCLK–1.5

2×t_SCLK–1.5

1.6

2 × t_SCLK–1.5

1.6

2 × t_SCLK–1.5

1.6

2 × t_SCLK–1.5

1.6

ns

t_SPITDS

t_SDSCI

t_SSPID

SPISS Assertion to First SCK Edge

Data Input Valid to SCK Edge (Data Input

Setup)

t_HSPID

SCK Sampling Edge to Data Input Invalid

2.0

0

1.6

ns

Switching Characteristics

t_DSOE

SPISS Assertion to Data Out Active

12.0 0

10.3

8.5

10

0

12.0 0

10.3 ns

t_DSDHI

t_DDSPID

t_HDSPID

SPISS Deassertion to Data High Impedance 0

11.0 0

8.5

10

0

8

ns

SCK Edge to Data Out Valid (Data Out Delay)

SCK Edge to Data Out Invalid (Data Out Hold) 0

10

0

10

0

SPIxSS

(INPUT)

t_SDSCI

t_SPICLS

t_SPICHS

t_SPICLK

t_HDS

t_SPITDS

SPIxSCK

(INPUT)

t_DSOE

t_DDSPID

t_HDSPID

t_DDSPID

t_DSDHI

SPIxMISO

(OUTPUT)

CPHA = 1

t_SSPID

t_HSPID

SPIxMOSI

(INPUT)

t_DSOE

t_HDSPID

t_DDSPID

t_DSDHI

SPIxMISO

(OUTPUT)

t_HSPID

CPHA = 0

t_SSPID

SPIxMOSI

(INPUT)

Figure 29. Serial Peripheral Interface (SPI) Port—Slave Timing

Rev. D

|

Page 59 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing

Table 50 describes the USB On-The-Go receive and transmit

operations.

Table 50. USB On-The-Go—Receive and Transmit Timing

ADSP-BF522/ADSP-BF524/ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDEXT

2.5 V or 3.3V Nominal

1.8V Nominal

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

f_USBS

USB_XI Frequency

12

33.3

+50

12

33.3

+50

9

33.3

+50

9

33.3

+50

MHz

ppm

FS_USB

USB_XI Clock Frequency

Stability

–50

Rev. D

|

Page 60 of 88

|

July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

For information on the UART port receive and transmit opera-

tions, see the ADSP-BF52x Hardware Reference Manual.

General-Purpose Port Timing

Table 51 and Figure 30 describe general-purpose

port operations.

Table 51. General-Purpose Port Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors

V_DDEXT

2.5 V or 3.3V Nominal

1.8V Nominal

Parameter

Min

Max

Min

Max

Unit

ns

Timing Requirement

t_WFI

General-Purpose Port Ball Input Pulse Width

t_SCLK+ 1

Switching Characteristic

t_GPOD

General-Purpose Port Ball Output Delay from CLKOUT 0

Low

11.0

0

8.2

ns

Table 52. General-Purpose Port Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors

V_DDEXT

1.8V Nominal

V_DDEXT

2.5 V or 3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

ns

Timing Requirement

t_WFI

General-Purpose Port Ball Input Pulse Width

t_SCLK+ 1

Switching Characteristic

t_GPOD

General-Purpose Port Ball Output Delay from CLKOUT Low 0

8.2

0

6.5

ns

CLKOUT

GPIO OUTPUT

GPIO INPUT

t_GPOD

t_WFI

Figure 30. General-Purpose Port Timing

Rev. D

|

Page 61 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Timer Cycle Timing

Table 53 and Figure 31 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of (f_SCLK/2) MHz.

Table 53. Timer Cycle Timing

ADSP-BF522/ADSP-BF524/ADSP-BF526

ADSP-BF523/ADSP-BF525/ADSP-BF527

V_DDEXT

2.5 V or 3.3V Nominal

1.8V Nominal

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

t_WL

Timer Pulse Width Input t_SCLK

Low (Measured In SCLK

Cycles)¹

t_SCLK

ns

t_WH

Timer Pulse Width Input t_SCLK

High (Measured In SCLK

Cycles)¹

t_SCLK

ns

t_TIS

t_TIH

Timer Input Setup Time 10

Before CLKOUT Low²

7

8.1

–2

6.2

–2

ns

Timer Input Hold Time

After CLKOUT Low²

–2

Switching Characteristics

t_HTO

TimerPulseWidth Output t_SCLK–1.5 (2³²– 1)t_SCLKt_SCLK– 1

(Measured In SCLK Cycles)

(2³²– 1)t_SCLKt_SCLK– 1

6

(2³²– 1)t_SCLKt_SCLK– 1

6

(2³²– 1)t_SCLKns

ns

t_TOD

Timer Output Update

6

Delay After CLKOUT High

¹The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.

²Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

CLKOUT

t_TOD

TMRx OUTPUT

t_TIS

t_TIH

t_HTO

TMRx INPUT

t_WH,t_WL

Figure 31. Timer Cycle Timing

Rev. D

|

Page 62 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Timer Clock Timing

Table 54 and Figure 32 describe timer clock timing.

Table 54. Timer Clock Timing

V_DDEXT

2.5 V or 3.3V Nominal

1.8V Nominal

Parameter

Min

Max

Min

Max

Unit

Switching Characteristic

t_TODP

Timer Output Update Delay After PPI_CLK High

12.0

ns

PPI_CLK

t_TODP

TMRx OUTPUT

Figure 32. Timer Clock Timing

Up/Down Counter/Rotary Encoder Timing

Table 55. Up/Down Counter/Rotary Encoder Timing

V_DDEXT

1.8V Nominal

V_DDEXT

2.5 V or 3.3V Nominal

Parameter

Min

Max

Min Max

Unit

Timing Requirements

t_WCOUNT

t_CIS

Up/Down Counter/Rotary Encoder Input Pulse Width t_SCLK+ 1

t_SCLK+ 1

ns

Counter Input Setup Time Before CLKOUT High¹

Counter Input Hold Time After CLKOUT High¹

9.0

0

7.0

0

t_CIH

¹Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.

CLKOUT

t_CIS

t_CIH

CUD/CDG/CZM

t_WCOUNT

Figure 33. Up/Down Counter/Rotary Encoder Timing

Rev. D

|

Page 63 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

HOSTDP A/C Timing- Host Read Cycle

Table 56 describes the HOSTDP A/C Host Read Cycle timing

requirements.

Table 56. Host Read Cycle Timing Requirements

ADSP-BF522/ADSP-BF524/

ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

Parameter

Timing Requirements

Min

Max

Min

Max

Min

Max

Min

Max

Unit

ns

t_SADRDL

HOST_ADDR and HOST_CE Setup

before HOST_RD falling edge

4

t_HADRDHHOST_ADDR and HOST_CE Hold

after HOST_RD rising edge

2.5

ns

t_RDWL

HOST_RD pulse width low

(ACK mode)

t_DRDYRDL

+

t_DRDYRDL

+

t_DRDYRDL

+

t_DRDYRDL

t_RDYPRD+

+

ns

t_RDYPRD

+

t_RDYPRD

+

t_RDYPRD

+

t_DRDHRDY

t_RDWL

t_RDWH

HOST_RD pulse width low

(INT mode)

HOST_RD pulse width high or time 2 × t_SCLK

between HOST_RD rising edge and

HOST_WR falling edge

1.5 × t_SCLK

+ 8.7

1.5 × t_SCLK

+ 8.7

2 × t_SCLK

1.5 × t_SCLK

+ 8.7

2 × t_SCLK

1.5 × t_SCLK

+ 8.7

2 × t_SCLK

ns

t_DRDHRDYHOST_RD rising edge delay after 2.0

HOST_ACK rising edge (ACK mode)

Switching Characteristics

t_SDATRDYData valid prior HOST_ACK rising 4.5

edge (ACK mode)

2.0

3.5

0

ns

4.5

3.5

ns

t_DRDYRDLHost_ACK falling edge after

HOST_CE (ACK mode)

12.5

NM¹

11.25

NM¹

11.25

NM¹

11.25

NM¹

9.0

t_RDYPRD

HOST_ACK low pulse-width for

Read access (ACK mode)

t_DDARWHData disable after HOST_RD

11.0

9.0

t_ACC

Data valid after HOST_RD falling

edge (INT mode)

1.5 × t_SCLK

1.5 × t_SCLKns

t_HDARWHData hold after HOST_RD rising

edge

1.0

ns

¹NM (Not Measured) — This parameter is based on t_SCLK. It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO

status and is system design dependent.

Rev. D

|

Page 64 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

HOST_ADDR

HOST_CE

t_SADRDL

t_HADRDH

t_RDWL

t_RDWH

HOST_RD

t_SDATRDY

t_ACC

t_DDARWH

t_HDARWH

HOST_DATA

t_DRDHRDY

t_DRDYRDL

t_RDYPRD

HOST_ACK

In Figure 34, HOST_DATA is HOST_D0–D15.

Figure 34. HOSTDP A/C- Host Read Cycle

Rev. D

|

Page 65 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

HOSTDP A/C Timing- Host Write Cycle

Table 57 describes the HOSTDP A/C Host Write Cycle timing

requirements.

Table 57. Host Write Cycle Timing Requirements

ADSP-BF522/ADSP-BF524/

ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

t_SADWRLHOST_ADDR/HOST_CE Setup

before HOST_WR falling edge

4

ns

t_HADWRHHOST_ADDR/HOST_CE Hold

after HOST_WR rising edge

2.5

t_WRWL

HOST_WR pulse width low

(ACK mode)

t_DRDYWRL

t_RDYPRD

+

t_DRDYWRL

t_RDYPRD

+

t_DRDYWRL

t_RDYPRD

+

t_DRDYWRL+

t_RDYPRD+

t_DWRHRDY

HOST_WR pulse width low

(INT mode)

1.5 × t_SCLK

+ 8.7

1.5 × t_SCLK

+ 8.7

1.5 × t_SCLK

+ 8.7

1.5 × t_SCLK

+ 8.7

ns

t_WRWH

HOST_WR pulse width high

or time between HOST_WR

rising edge and HOST_RD

falling edge

2 × t_SCLK

t_DWRHRDYHOST_WR rising edge delay

after HOST_ACK rising edge

(ACK mode)

2.0

0

ns

t_HDATWHData Hold after HOST_WR rising edge 2.5

2.5

ns

t_SDATWHData Setup before HOST_WR

rising edge

3.5

Switching Characteristics

t_DRDYWRLHOST_ACK falling edge after HOST_CE

asserted (ACK mode)

12.5

NM¹

11.5

NM¹

11.5

NM¹

11.5

NM¹

ns

t_RDYPWRHOST_ACK low pulse-width for Write

access (ACK mode)

¹NM (Not Measured) — This parameter is based on t_SCLK. It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO

status and is system design dependent.

Rev. D

|

Page 66 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

HOST_ADDR

HOST_CE

t_SADWRL

t_HADWRH

t_WRWH

t_WRWL

HOST_WR

HOST_DATA

HOST_ACK

t_SDATWH

t_HDATWH

t_RDYPWR

t_DRDYWRL

t_DWRHRDY

In Figure 35, HOST_DATA is HOST_D0–D15.

Figure 35. HOSTDP A/C- Host Write Cycle

Rev. D

|

Page 67 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

10/100 Ethernet MAC Controller Timing

Table 58 through Table 63 and Figure 36 through Figure 41

describe the 10/100 Ethernet MAC Controller operations.

Table 58. 10/100 Ethernet MAC Controller Timing: MII Receive Signal

V_DDEXT

2.5 V or 3.3V Nominal

1.8V Nominal

Parameter¹

Min

Max

Min

Max

Unit

Timing Requirements

t_ERXCLKF

t_ERXCLKW

t_ERXCLKIS

t_ERXCLKIH

ERxCLK Frequency (f_SCLK= SCLK Frequency)

ERxCLK Width (t_ERxCLK= ERxCLK Period)

None

25 + 1%

None

25 + 1%

MHz

t_ERxCLK× 40% t_ERxCLK× 60% t_ERxCLK× 35% t_ERxCLK× 65% ns

Rx Input Valid to ERxCLK Rising Edge (Data In Setup) 7.5

ERxCLK Rising Edge to Rx Input Invalid (Data In Hold) 7.5

7.5

ns

¹MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.

t_ERXCLK

t_ERXCLKW

ERx_CLK

ERxD3–0

ERxDV

ERxER

t_ERXCLKISt_ERXCLKIH

Figure 36. 10/100 Ethernet MAC Controller Timing: MII Receive Signal

Table 59. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

V_DDEXT

1.8V Nominal

V_DDEXT

2.5 V or 3.3V Nominal

Parameter¹

Min

Max

Min

Max

Unit

Switching Characteristics

t_ETXCLKF

ETxCLK Frequency (f_SCLK= SCLK Frequency)

None

25 + 1%

None

25 + 1%

MHz

t_ETXCLKW

t_ETXCLKOV

t_ETXCLKOH

ETxCLK Width (t_ETxCLK= ETxCLK Period)

t_ETxCLK× 40% t_ETxCLK× 60% t_ETxCLK× 35% t_ETxCLK× 65% ns

ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)

20

ns

ETxCLK Rising Edge to Tx Output Invalid (Data Out

Hold)

0

¹MII outputs synchronous to ETxCLK are ETxD3–0.

t_ETXCLK

MIITxCLK

t_ETXCLKW

t_ETXCLKOH

ETxD3–0

ETxEN

t_ETXCLKOV

Figure 37. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

Rev. D

|

Page 68 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 60. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

V_DDEXT

2.5 V or 3.3V Nominal

1.8V Nominal

Parameter¹

Min

Max

Min

Max

Unit

Timing Requirements

t_EREFCLKF

t_EREFCLKW

t_EREFCLKIS

REF_CLK Frequency (f_SCLK= SCLK Frequency)

None

50 + 1%

None

50 + 1%

MHz

EREF_CLK Width (t_EREFCLK= EREFCLK Period)

t_EREFCLK× 40% t_EREFCLK× 60% t_EREFCLK× 35% t_EREFCLK× 65% ns

Rx Input Valid to RMII REF_CLK Rising Edge (Data In

Setup)

4

ns

t_EREFCLKIH

RMII REF_CLK Rising Edge to Rx Input Invalid (Data In

Hold)

2

ns

¹RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.

t_REFCLK

t_REFCLKW

RMII_REF_CLK

ERxD1–0

ERxDV

ERxER

t_REFCLKISt_REFCLKIH

Figure 38. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

Table 61. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

ADSP-BF522/ADSP-BF524/

ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

Parameter¹

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Switching Characteristics

t_EREFCLKOV

RMII REF_CLK Rising Edge

to Tx Output Valid (Data Out Valid)

8.1

7.5

ns

t_EREFCLKOH

RMII REF_CLK Rising Edge

2

to Tx Output Invalid (Data Out Hold)

¹RMII outputs synchronous to RMII REF_CLK are ETxD1–0.

t_REFCLK

RMII_REF_CLK

t_REFCLKOH

ETxD1–0

ETxEN

t_REFCLKOV

Figure 39. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

Rev. D

|

Page 69 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 62. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal

V_DDEXT

2.5 V or 3.3V Nominal

1.8V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_ECOLH

COL Pulse Width High¹

t_ETxCLK× 1.5

t_ERxCLK× 1.5

t_ETxCLK× 1.5

t_ERxCLK× 1.5

ns

t_ECOLL

COL Pulse Width Low¹

t_ETxCLK× 1.5

t_ERxCLK× 1.5

t_ETxCLK× 1.5

t_ERxCLK× 1.5

t_ETxCLK× 1.5

t_ECRSH

t_ECRSL

CRS Pulse Width High²

CRS Pulse Width Low²

t_ETxCLK× 1.5

ns

¹MII/RMII asynchronous signals are COL and CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to

both the ETxCLK and the ERxCLK, and the COL input must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.

²The asynchronous CRS input is synchronized to the ETxCLK, and the CRS input must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.

MIICRS, COL

t_ECRSH

t_ECOLH

t_ECRSL

t_ECOLL

Figure 40. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal

Table 63. 10/100 Ethernet MAC Controller Timing: MII Station Management

ADSP-BF522/ADSP-BF524/

ADSP-BF526

ADSP-BF523/ADSP-BF525/

ADSP-BF527

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

V_DDEXT

1.8V Nominal

2.5 V or 3.3V

Nominal

Parameter¹

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

t_MDIOS

MDIO Input Valid to MDC Rising Edge 11.5

(Setup)

11.5

10

ns

t_MDCIH

MDC Rising Edge to MDIO Input Invalid 11.5

(Hold)

Switching Characteristics

t_MDCOVMDC Falling Edge to MDIO Output Valid

t_MDCOH

25

ns

MDC Falling Edge to MDIO Output

Invalid (Hold)

–1

¹MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple

of the system clock SCLK. MDIO is a bidirectional data line.

Rev. D

|

Page 70 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

MDC (OUTPUT)

t_MDCOH

MDIO (OUTPUT)

t_MDCOV

MDIO (INPUT)

t_MDIOS

t_MDCIH

Figure 41. 10/100 Ethernet MAC Controller Timing: MII Station Management

Rev. D

|

Page 71 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

JTAG Test And Emulation Port Timing

Table 64 and Figure 42 describe JTAG port operations.

Table 64. JTAG Port Timing

V_DDEXT

2.5 V or 3.3V Nominal

1.8V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

20

4

20

4

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

ns

TDI, TMS Hold After TCK High

4

ns

System Inputs Setup Before TCK High¹

System Inputs Hold After TCK High¹

TRST Pulse Width²(measured in TCK cycles)

12

5

12

5

ns

4

TCK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low³

10

12

10

12

ns

¹System Inputs = DATA15–0, ARDY, SCL, SDA, PF15–0, PG15–0, PH15–0, RESET, NMI, BMODE3–0.

²50 MHz Maximum.

³System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, PF15–0, PG15–0, PH15–0.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 42. JTAG Port Timing

Rev. D

|

Page 72 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

OUTPUT DRIVE CURRENTS

Figure 43 through Figure 57 show typical current-voltage char-

acteristics for the output drivers of the ADSP-BF52x processors.

The curves represent the current drive capability of the output

drivers. See Table 10 on Page 23 for information about which

driver type corresponds to a particular ball.

200

V_DDEXT= 3.6V @ – 40

°C

240

160

120

80

V_DDEXT= 3.6V @ – 40

°C

V_DDEXT= 3.3V @ 25

°

C

200

160

120

80

V_DDEXT= 3.3V @ 25

°C

V_DDEXT= 3.0V @ 105°C

V

OH

40

V

OH

40

0

–40

–80

–120

–160

V

OL

–120

V

OL

–160

–200

–240

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 43. Driver Type A Current (3.3V V_DDEXT/V_DDMEM

)

Figure 46. Driver Type B Current (3.3V V_DDEXT/V_DDMEM

)

160

120

V_DDEXT= 2.75V @ – 40

V_DDEXT= 2.5V @ 25

°C

160

°

C

V_DDEXT= 2.75V @ – 40

V_DDEXT= 2.5V @ 25

°C

120

80

V

_DDEXT= 2.25V @ 105°C

°

C

80

40

V

_DDEXT= 2.25V @ 105°C

40

V

OH

V

OH

0

–40

–80

0

–40

–80

V

OL

–120

–160

–200

–120

–160

0.5

1.0

1.5

2.0

2.5

0

0.5

1.0

1.5

2.0

2.5

SOURCE VOLTAGE (V)

Figure 44. Driver Type A Current (2.5V V_DDEXT/V_DDMEM

)

Figure 47. Driver Type B Current (2.5V V_DDEXT/V_DDMEM

)

80

60

V_DDEXT= 1.9V @ – 40

V_DDEXT= 1.8V @ 25

°C

80

60

°

C

V_DDEXT= 1.9V @ – 40

V_DDEXT= 1.8V @ 25

°C

V_DDEXT= 1.7V @ 105°C

°

C

40

20

V_DDEXT= 1.7V @ 105°C

40

20

V

OH

V

OH

0

–20

V

OL

–40

–60

–40

–60

V

OL

–80

0.5

1.0

1.5

–100

0

0.5

1.0

1.5

SOURCE VOLTAGE (V)

Figure 45. Driver Type A Current (1.8V V_DDEXT/V_DDMEM

)

Figure 48. Driver Type B Current (1.8V V_DDEXT/V_DDMEM

)

Rev. D

|

Page 73 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

100

80

160

120

V_DDEXT= 3.6V @ – 40

°

C

V_DDEXT= 3.6V @ – 40

°C

V_DDEXT= 3.3V @ 25

°C

V_DDEXT= 3.3V @ 25°C

60

40

V_DDEXT= 3.0V @ 105

°C

V_DDEXT= 3.0V @ 105°C

80

40

0

V

OH

20

0

–20

–40

–80

V

OL

–60

–80

V

OL

–120

–160

–100

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 49. Driver Type C Current (3.3V V_DDEXT/V_DDMEM

)

Figure 52. Driver Type D Current (3.3V V_DDEXT/V_DDMEM

)

80

120

100

V_DDEXT= 2.75V @ – 40

V_DDEXT= 2.5V @ 25

°C

V_DDEXT= 2.75V @ – 40

V_DDEXT= 2.5V @ 25

°C

60

40

20

°C

80

60

V

_DDEXT= 2.25V @ 105°C

V_DDEXT= 2.25V @ 105°C

40

V

OH

V

20

OH

0

–20

–40

–60

–80

–100

–120

–20

–40

–60

V

OL

–80

0.5

1.0

1.5

2.0

2.5

0.5

1.0

1.5

2.0

2.5

SOURCE VOLTAGE (V)

Figure 50. Drive Type C Current (2.5V V_DDEXT/V_DDMEM

)

Figure 53. Driver Type D Current (2.5V V_DDEXT/V_DDMEM

)

40

30

60

V_DDEXT= 1.9V @ – 40

V_DDEXT= 1.8V @ 25

°C

V_DDEXT= 1.9V @ – 40

V_DDEXT= 1.8V @ 25

°C

°

C

°

C

40

20

V_DDEXT= 1.7V @ 105°C

20

10

V

OH

V

OH

0

–20

–40

–60

–10

V

OL

–20

–30

V

OL

–40

0.5

1.0

1.5

0.5

1.0

1.5

SOURCE VOLTAGE (V)

Figure 51. Driver Type C Current (1.8V V_DDEXT/V_DDMEM

)

Figure 54. Driver Type D Current (1.8V V_DDEXT/V_DDMEM

)

Rev. D

|

Page 74 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

TEST CONDITIONS

60

V_DDEXT= 3.6V @ – 40

°C

50

40

All Timing Requirements appearing in this data sheet were

measured under the conditions described in this section.

Figure 58 shows the measurement point for AC measurements

(except output enable/disable). The measurement point V_MEASis

V_DDEXT/2 or V_DDMEM/2 for V_DDEXT/V_DDMEM(nominal) = 1.8 V/

2.5 V/3.3 V.

V_DDEXT= 3.3V @ 25

°C

V_DDEXT= 3.0V @ 105°C

30

20

10

0

–10

–20

–30

–40

–50

–60

INPUT

OR

OUTPUT

V

MEAS

V

MEAS

OL

Figure 58. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable)

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 55. Driver Type E Current (3.3V V_DDEXT/V_DDMEM

)

Output Enable Time Measurement

Output balls are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving.

40

30

V_DDEXT= 2.75V @ – 40

V_DDEXT= 2.5V @ 25

_DDEXT= 2.25V @ 105°C

°C

V

The output enable time t_ENAis the interval from the point when

a reference signal reaches a high or low voltage level to the point

when the output starts driving as shown on the right side of

Figure 59.

20

10

0

–10

–20

–30

–40

REFERENCE

SIGNAL

V

OL

t_{DIS_MEASURED}

t_{ENA_MEASURED}

t_DIS

t_ENA

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

OH

V

(MEASURED)

OH

(MEASURED)

V

(MEASURED) ؊ ⌬V

(MEASURED) + ⌬V

OH

SOURCE VOLTAGE (V)

V

(HIGH)

TRIP

V

(LOW)

OL

V

TRIP

OL

V

Figure 56. Driver Type E Current (2.5V V_DDEXT/V_DDMEM

)

OL

V

(MEASURED)

t_DECAY

t_TRIP

20

15

V_DDEXT= 1.9V @ – 40

V_DDEXT= 1.8V @ 25

°C

°

C

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

V_DDEXT= 1.7V @ 105°C

10

5

Figure 59. Output Enable/Disable

0

The time t_{ENA_MEASURED}is the interval from when the reference

signal switches to when the output voltage reaches V_TRIP(high)

or V_TRIP(low). For V_DDEXT/V_DDMEM(nominal) = 1.8 V, V_TRIP

(high) is 1.05 V, and V_TRIP(low) is 0.75 V. For V_DDEXT/V_DDMEM

(nominal) = 2.5 V, V_TRIP(high) is 1.5 V and V_TRIP(low) is 1.0 V.

For V_DDEXT/V_DDMEM(nominal) = 3.3 V, V_TRIP(high) is 1.9 V, and

V_TRIP(low) is 1.4 V. Time t_TRIPis the interval from when the out-

put starts driving to when the output reaches the V_TRIP(high) or

–5

V

OL

–10

–15

–20

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

V_TRIP(low) trip voltage.

Time t_ENAis calculated as shown in the equation:

Figure 57. Driver Type E Current (1.8V V_DDEXT/V_DDMEM

)

t_ENA= t_{ENA_MEASURED}– t_TRIP

If multiple balls (such as the data bus) are enabled, the measure-

ment value is that of the first ball to start driving.

Rev. D

|

Page 75 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Output Disable Time Measurement

TESTER PIN ELECTRONICS

50Ω

Output balls are considered to be disabled when they stop driv-

V

LOAD

T1

ing, go into a high impedance state, and start to decay from their

DUT

OUTPUT

output high or low voltage. The output disable time t_DISis the

45Ω

70Ω

difference between t_{DIS_MEASURED}and t_DECAYas shown on the left

side of Figure 59.

ZO = 50Ω (impedance)

TD = 4.04 1.18 ns

t_DIS= t_{DIS_MEASURED}– t_DECAY

50Ω

0.5pF

4pF

2pF

The time for the voltage on the bus to decay by ΔV is dependent

on the capacitive load C_Land the load current I_L. This decay

time can be approximated by the equation:

400Ω

t_DECAY= C_LV  I_L

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

The time t_DECAYis calculated with test loads C_Land I_L, and with

V equal to 0.25 V for V_DDEXT/V_DDMEM(nominal) = 2.5 V/3.3 V

and 0.15 V for V_DDEXT/V_DDMEM(nominal) = 1.8V.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

The time t_{DIS_MEASURED}is the interval from when the reference

signal switches, to when the output voltage decays ΔV from the

measured output high or output low voltage.

Figure 60. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose ΔV

to be the difference between the processor’s output voltage and

the input threshold for the device requiring the hold time. C_Lis

the total bus capacitance (per data line), and I_Lis the total leak-

age or three-state current (per data line). The hold time will be

t_DECAYplus the various output disable times as specified in the

Timing Specifications on Page 39 (for example t_DSDATfor an

SDRAM write cycle as shown in SDRAM Interface Timing on

Page 47).

12

10

t_RISE

8

t_FALL

6

4

2

Capacitive Loading

t_RISE= 1.8V @ 25°C

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all balls (see Figure 60). V_LOADis equal

to (V_DDEXT/V_DDMEM) /2. The graphs of Figure 61 through

Figure 72 show how output rise time varies with capacitance.

The delay and hold specifications given should be derated by a

factor derived from these figures. The graphs in these figures

may not be linear outside the ranges shown.

t_FALL= 1.8V @ 25

°C

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 61. Driver Type A Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (1.8V V_DDEXT/V_DDMEM

)

Rev. D

|

Page 76 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

8

7

6

5

6

t_RISE

5

t_FALL

4

t_FALL

4

3

2

1

3

2

1

t_RISE= 2.5V @ 25°C

t_FALL= 2.5V @ 25

°C

t_FALL= 2.5V @ 25

°C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 62. Driver Type A Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (2.5V V_DDEXT/V_DDMEM

Figure 65. Driver Type B Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (2.5V V_DDEXT/V_DDMEM

)

6

5

4

5

4

t_RISE

t_FALL

3

2

1

3

2

1

t_RISE= 3.3V @ 25

°C

t_RISE= 3.3V @ 25

°C

t_FALL= 3.3V @ 25

°

C

t_FALL= 3.3V @ 25

°

C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 63. Driver Type A Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (3.3V V_DDEXT/V_DDMEM

Figure 66. Driver Type B Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (3.3V V_DDEXT/V_DDMEM

)

9

8

25

t_RISE

20

15

10

5

7

6

5

t_RISE

t_FALL

4

3

2

1

t_RISE= 1.8V @ 25°C

t_FALL= 1.8V @ 25

°C

t_FALL= 1.8V @ 25

°C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 64. Driver Type B Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (1.8V V_DDEXT/V_DDMEM

Figure 67. Driver Type C Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (1.8V V_DDEXT/V_DDMEM

)

Rev. D

|

Page 77 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

10

16

9

14

8

12

10

7

t_RISE

6

5

t_FALL

8

6

4

2

4

3

2

1

t_RISE= 2.5V @ 25°C

t_FALL= 2.5V @ 25

°C

t_FALL= 2.5V @ 25

°C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 71. Driver Type D Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (2.5V V_DDEXT/V_DDMEM

Figure 68. Driver Type C Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (2.5V V_DDEXT/V_DDMEM

)

14

8

7

6

5

4

12

10

8

t_RISE

t_FALL

6

3

4

2

1

t_RISE= 3.3V @ 25

°C

t_RISE= 3.3V @ 25

°C

t_FALL= 3.3V @ 25

°C

t_FALL= 3.3V @ 25

°

C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 69. Driver Type C Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (3.3V V_DDEXT/V_DDMEM

Figure 72. Driver Type D Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (3.3V V_DDEXT/V_DDMEM

)

9

8

14

12

10

8

t_RISE

7

6

5

t_FALL

4

6

3

2

4

2

t_RISE= 1.8V @ 25°C

1

0

t_FALL= 1.8V @ 25

°C

t_FALL= 1.8V @ 25

°C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 73. Driver Type G Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (1.8V V_DDEXT/V_DDMEM

Figure 70. Driver Type D Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (1.8V V_DDEXT/V_DDMEM

)

Rev. D

|

Page 78 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Values of _JAare provided for package comparison and printed

9

circuit board design considerations. _JAcan be used for a first

8

order approximation of T_Jby the equation:

7

T_J= T_A+ _JA P_D

6

t_RISE

5

t_FALL

where:

4

T_A= Ambient temperature (°C)

3

Values of _JCare provided for package comparison and printed

2

circuit board design considerations when an external heat sink

t_RISE= 2.5V @ 25°C

1

0

is required.

t_FALL= 2.5V @ 25

°C

Values of _JBare provided for package comparison and printed

circuit board design considerations.

0

50

100

150

200

LOAD CAPACITANCE (pF)

In Table 66, airflow measurements comply with JEDEC stan-

dards JESD51-2 and JESD51-6, and the junction-to-board

measurement complies with JESD51-8. The junction-to-case

measurement complies with MIL-STD-883 (Method 1012.1).

All measurements use a 2S2P JEDEC test board.

Figure 74. Driver Type G Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (2.5V V_DDEXT/V_DDMEM

)

9

8

7

Table 65. Thermal Characteristics for BC-208-1 Package

t_RISE

Parameter Condition

Typical Unit

6

5

4

_JA

0 linear m/s air flow

23.20

20.20

19.20

13.05

6.92

°C/W

t_FALL

_JMA

_JB

1 linear m/s air flow

2 linear m/s air flow

3

2

1

_JC

t_RISE= 3.3V @ 25°C

_JT

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

0.18

t_FALL= 3.3V @ 25

°C

0

0.27

0

50

100

150

200

LOAD CAPACITANCE (pF)

0.32

Figure 75. Driver Type G Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (3.3V V_DDEXT/V_DDMEM

Table 66. Thermal Characteristics for BC-289-2 Package

Parameter Condition Typical Unit

)

ENVIRONMENTAL CONDITIONS

_JA

0 linear m/s air flow

34.5

31.1

29.8

20.3

8.8

°C/W

To determine the junction temperature on the application

printed circuit board use:

_JMA

_JB

1 linear m/s air flow

2 linear m/s air flow

T_J= T_CASE+ _JT P_D

_JC

_JT

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

0.24

0.44

0.53

where:

T_J= Junction temperature (°C)

T

_CASE= Case temperature (°C) measured by customer at top

center of package.

_JT= From Table 66

P_D= Power dissipation — For a description, see Total Power

Dissipation on Page 35.

Rev. D

|

Page 79 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

289-BALL CSP_BGA BALL ASSIGNMENT

Table 67 lists the CSP_BGA balls by signal mnemonic.

Table 68 on Page 81 lists the CSP_BGA by ball number.

Table 67. 289-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)

Ball

No. Signal

Ball

No. Signal

Ball

No. Signal

Ball

No.

Signal

No. Signal No. Signal No. Signal

ABE0/SDQM0 AB9 DATA6

ABE1/SDQM1 AC9 DATA7

T2

T1

GND M10 NC

GND M11 NC

D23 PH0

E22 PH1

E23 PH2

F22 PH3

F23 PH4

G22 PH5

H23 PH6

J23 PH7

U22 PH8

A11 USB_XO AA23 V_DDINT

R8

A12 V_DDEXT

A13 V_DDEXT

B14 V_DDEXT

A14 V_DDEXT

K23 V_DDEXT

K22 V_DDEXT

L23 V_DDEXT

L22 V_DDEXT

T23 V_DDEXT

M22 V_DDEXT

R22 V_DDEXT

M23 V_DDEXT

N22 V_DDEXT

N23 V_DDEXT

P22 V_DDEXT

G7 V_DDINT

G8 V_DDINT

G9 V_DDINT

G10 V_DDINT

G11 V_DDINT

G12 V_DDINT

G13 V_DDINT

G14 V_DDINT

G15 V_DDINT

H7 V_DDINT

J17 V_DDMEM

K17 V_DDMEM

L17 V_DDMEM

M17 V_DDMEM

N17 V_DDMEM

P17 V_DDMEM

R17 V_DDMEM

T17 V_DDMEM

U17 V_DDMEM

B5 V_DDMEM

H8 V_DDMEM

H9 V_DDMEM

H10 V_DDMEM

H11 V_DDMEM

H12 V_DDMEM

H13 V_DDMEM

H14 V_DDMEM

H15 V_DDMEM

H16 V_DDOTP

R16

T8

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

ADDR17

ADDR18

ADDR19

AMS0

AB8 DATA8

AC8 DATA9

AB7 DATA10

AC7 DATA11

AC6 DATA12

AB6 DATA13

AB4 DATA14

AB5 DATA15

AC5 EMU

R1 GND M12 NC

P1

P2

GND M13 NC

GND M14 NC

T9

T10

T11

T12

T13

T14

T15

T16

J7

R2 GND M15 NC

N1 GND N9 NC

N2 GND N10 NC

M2 GND N11 NMI

M1 GND N12 VPPOTP AB11 PH9

J2

GND N13 PF0

A7 PH10

B8 PH11

A8 PH12

B9 PH13

B11 PH14

B10 PH15

AC4 EXT_WAKE0 AC19 GND N14 PF1

AB3 GND

AC3 GND

AB2 GND

AC2 GND¹

AA2 GND

W2 GND¹

Y2 GND

AA1 GND¹

AB1 GND

AC17 GND

AB16 GND

AC16 GND

AB15 GND

AC15 GND

AC14 GND

AB17 GND

AB14 GND

G2 GND

A1 GND N15 PF2

A23 GND P9 PF3

B6 GND P10 PF4

G16 GND P11 PF5

G17 GND P12 PF6

H17 GND P13 PF7

H22 GND P14 PF8

J22 GND P15 PF9

K7

L7

M7

N7

B12 PPI_CLK/TMRCLK A6 V_DDEXT

P7

B13 PPI_FS1/TMR0

B16 RESET

A20 RTXI

B7 V_DDEXT

V22 V_DDEXT

U23 V_DDEXT

V23 V_DDINT

AC10 V_DDINT

AC11 V_DDINT

AB13 V_DDINT

B22 V_DDINT

C22 V_DDINT

AC13 V_DDINT

AB12 V_DDINT

AC20 V_DDINT

AB10 V_DDINT

R7

T7

U7

J9

GND R9 PF10

B15 RTXO

B17 SA10

B18 SCAS

B19 SCKE

A9 SCL

U8

J10 GND R10 PF11

J11 GND R11 PF12

J12 GND R12 PF13

J13 GND R13 PF14

J14 GND R14 PF15

J15 GND R15 PG0

K9 GND T22 PG1

K10 GND AC1 PG2

K11 GND AC23 PG3

U9

AMS1

U10

U11

U12

U13

U14

U15

U16

AC12

W23

W22

Y23

G23

AMS2

AMS3

AOE

A10 SDA

ARDY

H2 SMS

ARE

G1 SRAS

H1 SS/PG

AWE

BMODE0

BMODE1

BMODE2

BMODE3

CLKBUF

CLKIN

F1

SWE

F2

E1

E2

GND

K12 NC

K13 NC

K14 NC

K15 NC

A15 PG4

A16 PG5

A17 PG6

A18 PG7

A19 PG8

A21 PG9

D1 TCK

L1

J1

V_DDINT

J8

V_DDRTC

D2 TDI

J16 V_DDUSB

K8 V_DDUSB

K16 NC

C2 TDO

B1 TMS

C1 TRST

B2 USB_DM

K1 V_DDINT

L2 V_DDINT

AB19 GND

R23 GND

AB18 GND

Y1 GND

V2 GND

W1 GND

U2 GND

V1 GND

U1 GND

L9

NC

K2 V_DDINT

AB21 V_DDINT

AA22 V_DDINT

Y22 V_DDINT

AC21 V_DDINT

AB20 V_DDINT

AC22 V_DDINT

AB23 V_DDINT

L8

VR_OUT/EXT_WAKE1 AC18

CLKOUT

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

L10 NC

L11 NC

L12 NC

L13 NC

L14 NC

L15 NC

M9 NC

L16 VR_SEL/V_DDEXT

AB22

P23

A22 PG10 B4 USB_DP

B20 PG11 B3 USB_ID

B21 PG12 A2 USB_RSET

B23 PG13 A3 USB_VBUS

C23 PG14 A4 USB_VREF

D22 PG15 A5 USB_XI

M8 XTAL

M16

N8

N16

P8

P16

NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors.

¹For ADSP-BF52xC compatibility, connect this ball to V_DDEXT

.

Rev. D

|

Page 80 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 68. 289-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)

Ball

No. Signal

No. Signal No. Signal

No. Signal

A1 GND

A2 PG12

A3 PG13

A4 PG14

A5 PG15

B20 NC

B21 NC

B22 SCL

B23 NC

C1 PG8

H12 V_DDINT

H13 V_DDINT

H14 V_DDINT

H15 V_DDINT

H16 V_DDINT

H17 GND¹

H22 GND

H23 NC

L9

GND

P2 DATA10 T22 GND

AB10 SWE

L10 GND

L11 GND

L12 GND

L13 GND

L14 GND

L15 GND

L16 V_DDINT

L17 V_DDEXT

L22 PH8

L23 PH7

P7 V_DDMEM

P8 V_DDINT

P9 GND

P10 GND

P11 GND

P12 GND

P13 GND

P14 GND

P15 GND

P16 V_DDINT

T23 PH9

AB11 VPPOTP

AB12 SRAS

U1 DATA5

U2 DATA3

U7 V_DDMEM

U8 V_DDMEM

U9 V_DDMEM

U10 V_DDMEM

U11 V_DDMEM

U12 V_DDMEM

U13 V_DDMEM

U14 V_DDMEM

U15 V_DDMEM

U16 V_DDMEM

U17 V_DDEXT

AB13 SCKE

AB14 AWE

A6 PPI_CLK/TMRCLK C2 PG6

AB15 AMS3

A7 PF0

A8 PF2

A9 PF14

A10 PF15

A11 PH0

A12 PH1

A13 PH2

A14 PH4

A15 NC

C22 SDA

C23 NC

D1 PG4

D2 PG5

D22 NC

D23 NC

AB16 AMS1

AB17 ARE

J1

J2

J7

J8

TDI

AB18 CLKOUT

AB19 CLKBUF

AB20 USB_VBUS

AB21 USB_DM

AB22 VR_SEL/V_DDEXT

AB23 USB_XI

AC1 GND

EMU

V_DDMEM

V_DDINT

GND

M1 DATA15 P17 V_DDEXT

M2 DATA14 P22 PH15

E1

E2

BMODE2 J9

BMODE3 J10 GND

M7 V_DDMEM

M8 V_DDINT

M9 GND

M10 GND

M11 GND

M12 GND

M13 GND

M14 GND

M15 GND

M16 V_DDINT

M17 V_DDEXT

M22 PH10

M23 PH12

P23 XTAL

E22 NC

E23 NC

J11 GND

J12 GND

R1 DATA8

A16 NC

R2 DATA11 U22 NMI

AC2 ADDR14

AC3 ADDR12

AC4 ADDR10

AC5 ADDR9

AC6 ADDR5

AC7 ADDR4

AC8 ADDR2

AC9 ABE1/SDQM1

AC10 SA10

A17 NC

F1

F2

PG3

J13 GND

R7 V_DDMEM

R8 V_DDINT

R9 GND

R10 GND

R11 GND

R12 GND

R13 GND

R14 GND

R15 GND

R16 V_DDINT

U23 RTXI

A18 NC

BMODE1 J14 GND

V1 DATA4

V2 DATA1

V22 RESET

A19 NC

F22 NC

F23 NC

G1 PG1

J15 GND

J16 V_DDINT

J17 V_DDEXT

A20 PF9

A21 NC

V23 RTXO

A22 NC

G2 BMODE0 J22 GND¹

W1 DATA2

W2 ADDR16

W22 V_DDUSB

A23 GND

B1 PG7

B2 PG9

B3 PG11

B4 PG10

B5 V_DDINT

B6 GND

B7 PPI_FS1/TMR0

B8 PF1

B9 PF3

B10 PF5

B11 PF4

B12 PF6

B13 PF7

B14 PH3

B15 PF10

B16 PF8

B17 PF11

B18 PF12

B19 PF13

G7 V_DDEXT

G8 V_DDEXT

G9 V_DDEXT

G10 V_DDEXT

G11 V_DDEXT

G12 V_DDEXT

G13 V_DDEXT

G14 V_DDEXT

G15 V_DDEXT

G16 GND¹

G17 GND

G22 NC

J23 NC

K1 TDO

K2 TRST

K7 V_DDMEM

K8 V_DDINT

K9 GND

K10 GND

K11 GND

K12 GND

K13 GND

K14 GND

K15 GND

K16 V_DDINT

K17 V_DDEXT

K22 PH6

K23 PH5

W23 V_DDRTC

AC11 SCAS

Y1 DATA0

Y2 ADDR17

Y22 USB_ID

Y23 V_DDUSB

AC12 V_DDOTP

N1 DATA12 R17 V_DDEXT

N2 DATA13 R22 PH11

AC13 SMS

AC14 ARDY

N7 V_DDMEM

N8 V_DDINT

N9 GND

N10 GND

N11 GND

N12 GND

N13 GND

N14 GND

N15 GND

N16 V_DDINT

N17 V_DDEXT

N22 PH13

N23 PH14

P1 DATA9

R23 CLKIN

AC15 AOE

T1

T2

T7

T8

T9

DATA7

DATA6

V_DDMEM

V_DDINT

AA1 ADDR18

AA2 ADDR15

AA22 USB_DP

AA23 USB_XO

AB1 ADDR19

AB2 ADDR13

AB3 ADDR11

AB4 ADDR7

AB5 ADDR8

AB6 ADDR6

AB7 ADDR3

AB8 ADDR1

AB9 ABE0/SDQM0

AC16 AMS2

AC17 AMS0

AC18 VR_OUT/EXT_WAKE1

AC19 EXT_WAKE0

AC20 SS/PG

AC21 USB_RSET

AC22 USB_VREF

AC23 GND

V_DDINT

G23 NC

T10 V_DDINT

T11 V_DDINT

T12 V_DDINT

T13 V_DDINT

T14 V_DDINT

T15 V_DDINT

T16 V_DDINT

T17 V_DDEXT

H1 PG2

H2 PG0

H7 V_DDEXT

H8 V_DDINT

H9 V_DDINT

H10 V_DDINT

H11 V_DDINT

L1

L2

L7

L8

TCK

TMS

V_DDMEM

V_DDINT

NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors.

¹For ADSP-BF52xC compatibility, connect this ball to V_DDEXT

.

Rev. D

|

Page 81 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Figure 76 shows the top view of the BC-289-2 CSP_BGA ball

configuration. Figure 77 shows the bottom view of the

BC-289-2 CSP_BGA ball configuration.

A1 BALL

PAD CORNER

A

B

C

D

E

F

G

H

J

K

L

M

N

TOP VIEW

P

KEY:

R

T

V

GND

I/O

NC

V

DDINT

U

V

W

Y

DDEXT

DDMEM

AA

AB

AC

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Figure 76. 289-Ball CSP_BGA Ball Configuration (Top View)

A1 BALL

PAD CORNER

A

B

C

D

E

BOTTOM VIEW

F

G

H

KEY:

J

K

V

GND

I/O

NC

V

L

DDINT

M

N

DDEXT

DDMEM

P

R

T

U

V

W

Y

AA

AB

AC

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Figure 77. 289-Ball CSP_BGA Ball Configuration (Bottom View)

Rev. D

|

Page 82 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

208-BALL CSP_BGA BALL ASSIGNMENT

Table 69 lists the CSP_BGA balls by signal mnemonic.

Table 70 on Page 84 lists the CSP_BGA by ball number.

Table 69. 208-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)

Ball

No. Signal

Ball

No. Signal

Ball

No. Signal

Ball

No. Signal

Ball

No. Signal

Ball

No.

Signal

ABE0/SDQM0 V19 CLKOUT

ABE1/SDQM1 V20 DATA0

K20 GND

K11 PF13

K12 PF14

K13 PF15

A5

B6

A6

R2

P1

P2

N1

N2

PPI_CLK/TMRCLK

G2

F2

V_DDEXT

J8

Y8

W8 GND

Y7 GND

W7 GND

Y6 GND

W6 GND

Y5 GND

W5 GND

Y4 GND

W4 GND

Y3 GND

W3 GND

Y2 GND

GND

PPI_FS1/TMR0

RESET

RTXI

K7

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

ADDR17

ADDR18

ADDR19

AMS0

W20 DATA1

W19 DATA2

Y19 DATA3

W18 DATA4

Y18 DATA5

W17 DATA6

Y17 DATA7

W16 DATA8

Y16 DATA9

W15 DATA10

Y15 DATA11

W14 DATA12

Y14 DATA13

W13 DATA14

Y13 DATA15

W12 EMU

B18 V_DDEXT

A14 V_DDEXT

A15 V_DDINT

U19 V_DDINT

U20 V_DDINT

P20 V_DDINT

K8

L9

PG0

L7

L10 PG1

L11 PG2

L12 PG3

L13 PG4

M9 PG5

M10 PG6

M11 PG7

M12 PG8

M13 PG9

RTXO

G12

G13

G14

H14

J14

K14

L14

M14

N14

P12

P13

P14

L8

SA10

SCAS

SCKE

M1 SCL

M2 SDA

A4

B4

V_DDINT

L1

L2

K1

K2

J1

SMS

R19 V_DDINT

T19 V_DDINT

G19 V_DDINT

T20 V_DDINT

SRAS

SS/PG

SWE

N9

PG10

W2 GND

W1 GND

N10 PG11

N11 PG12

N12 PG13

N13 PG14

TCK

V2

R1

T1

U2

U1

V_DDINT

J2

TDI

V_DDINT

V1

T2

GND

H1

H2

G1

A7

B7

A8

B8

A9

B9

TDO

V_DDMEM

TMS

M7

M8

N7

Y12 EXT_WAKE0

W11 GND

J20 GND

A1 GND

A17 NMI

Y1

PG15

TRST

Y20 PH0

B19 PH1

USB_DM

USB_DP

USB_ID

USB_RSET

USB_VBUS

USB_VREF

F20 V_DDMEM

E20 V_DDMEM

C20 V_DDMEM

D20 V_DDMEM

E19 V_DDMEM

H19 V_DDMEM

A19 V_DDMEM

A18 V_DDOTP

Y11 GND

N8

J19 GND

A20 VPPOTP L19 PH2

P7

AMS1

K19 GND

B20 PF0

H9 PF1

F1

E1

E2

D1

D2

C1

C2

B1

B2

A2

B3

A3

B5

PH3

P8

AMS2

M19 GND

PH4

P9

AMS3

L20 GND

H10 PF2

H11 PF3

H12 PF4

H13 PF5

PH5

P10

P11

R20

A16

D19

G20

AOE

N20 GND

PH6

B10 USB_XI

B11 USB_XO

A12 V_DDEXT

B12 V_DDEXT

A13 V_DDEXT

B13 V_DDEXT

B14 V_DDEXT

B15 V_DDEXT

B16 V_DDEXT

B17 V_DDEXT

ARDY

P19 GND

PH7

ARE

M20 GND

PH8

G7

G8

G9

V_DDRTC

V_DDUSB

AWE

N19 GND

J9

PF6

PH9

BMODE0

BMODE1

BMODE2

BMODE3

CLKBUF

CLKIN

Y10 GND

J10 PF7

J11 PF8

J12 PF9

J13 PF10

PH10

PH11

PH12

PH13

PH14

PH15

W10 GND

G10 VR_OUT/EXT_WAKE1 H20

Y9

GND

G11 VR_SEL/V_DDEXT

F19

A10

W9 GND

C19 GND

A11 GND

H7

H8

J7

XTAL

K9

PF11

K10 PF12

NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors.

Rev. D

|

Page 83 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 70. 208-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)

Ball

No. Signal

A1

A2

A3

A4

A5

A6

A7

A8

A9

GND

PF9

B16 PH14

B17 PH15

B18 RESET

B19 NMI

B20 GND

H7

H8

H9

V_DDEXT

GND

L2

L7

L8

L9

PG8

P1

P2

P7

P8

P9

PG1

W8 DATA1

W9 BMODE3

W10 BMODE1

W11 ADDR18

W12 ADDR16

W13 ADDR14

W14 ADDR12

W15 ADDR10

W16 ADDR8

W17 ADDR6

W18 ADDR4

W19 ADDR2

W20 ADDR1

V_DDEXT

V_DDMEM

GND

PG2

PF11

SCL

V_DDMEM

H10 GND

PF13

PF15

PH0

PH2

PH4

H11 GND

L10 GND

L11 GND

L12 GND

L13 GND

L14 V_DDINT

C1

C2

PF5

PF6

H12 GND

P10 V_DDMEM

P11 V_DDMEM

P12 V_DDINT

P13 V_DDINT

H13 GND

C19 CLKBUF

C20 USB_ID

H14 V_DDINT

H19 USB_VREF

H20 VR_OUT/EXT_WAKE1

A10 XTAL

A11 CLKIN

A12 PH8

A13 PH10

A14 RTXI

A15 RTXO

A16 V_DDRTC

A17 GND

D1

D2

PF3

PF4

L19 VPPOTP P14 V_DDINT

J1

J2

J7

J8

J9

PG11

PG12

V_DDEXT

GND

L20 AMS3

M1 PG5

M2 PG6

M7 V_DDMEM

M8 V_DDMEM

M9 GND

M10 GND

M11 GND

M12 GND

M13 GND

M14 V_DDINT

M19 AMS2

M20 ARE

P19 ARDY

P20 SCKE

D19 V_DDUSB

D20 USB_RSET

R1

R2

TDI

E1

E2

PF1

PF2

PG0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

GND

R19 SMS

DATA12

DATA10

DATA8

DATA6

DATA4

DATA2

DATA0

BMODE2

E19 USB_VBUS

E20 USB_DP

J10 GND

R20 V_DDOTP

J11 GND

T1

T2

TDO

EMU

A18 USB_XO F1

PF0

J12 GND

A19 USB_XI

A20 GND

F2

PPI_FS1/TMR0

J13 GND

T19 SRAS

T20 SWE

F19 VR_SEL/V_DDEXT

J14 V_DDINT

J19 AMS0

J20 EXT_WAKE0

B1

B2

B3

B4

B5

B6

B7

B8

B9

PF7

F20 USB_DM

U1

U2

TRST

TMS

PF8

G1

G2

G7

G8

G9

PG15

PF10

SDA

PF12

PF14

PH1

PH3

PH5

PPI_CLK/TMRCLK

V_DDEXT

K1

K2

K7

K8

K9

PG9

U19 SA10

U20 SCAS

Y10 BMODE0

Y11 ADDR19

Y12 ADDR17

Y13 ADDR15

Y14 ADDR13

Y15 ADDR11

Y16 ADDR9

Y17 ADDR7

Y18 ADDR5

Y19 ADDR3

Y20 GND

PG10

V_DDEXT

GND

N1

N2

N7

N8

N9

PG3

V_DDEXT

PG4

V1

V2

DATA15

TCK

V_DDEXT

V_DDMEM

GND

G10 V_DDEXT

G11 V_DDEXT

G12 V_DDINT

G13 V_DDINT

G14 V_DDINT

G19 SS/PG

G20 V_DDUSB

V19 ABE0/SDQM0

V20 ABE1/SDQM1

W1 DATA14

W2 DATA13

W3 DATA11

W4 DATA9

K10 GND

K11 GND

K12 GND

K13 GND

K14 V_DDINT

K19 AMS1

K20 CLKOUT

N10 GND

N11 GND

N12 GND

N13 GND

N14 V_DDINT

N19 AWE

N20 AOE

B10 PH6

B11 PH7

B12 PH9

B13 PH11

B14 PH12

B15 PH13

W5 DATA7

H1

H2

PG13

PG14

W6 DATA5

L1

PG7

W7 DATA3

NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors.

Rev. D

|

Page 84 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Figure 78 shows the top view of the CSP_BGA ball configura-

tion. Figure 79 shows the bottom view of the CSP_BGA

ball configuration.

A1 BALL

PAD CORNER

A

B

C

D

E

F

G

H

J

K

L

TOP VIEW

M

N

P

R

T

KEY:

VDDINT

VDDEXT

GND

I/O

U

V

W

Y

VDDMEM

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

Figure 78. 208-Ball CSP_BGA Ball Configuration (Top View)

A1 BALL

PAD CORNER

A

B

C

D

E

F

G

H

J

BOTTOM VIEW

K

L

M

N

P

R

T

KEY:

VDDINT

GND

U

V

W

Y

VDDEXT

VDDMEM

I/O

20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Figure 79. 208-Ball CSP_BGA Ball Configuration (Bottom View)

Rev. D

|

Page 85 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

OUTLINE DIMENSIONS

Dimensions in the outline dimension figures (Figure 80 and

Figure 81) are shown in millimeters.

12.00 BSC SQ

A1 BALL

CORNER

22 20 18 16 14 12 10

23 21 19 17 15 13 11

8

6

4

2

9

7

5

3

1

A

C

E

G

J

B

D

F

H

K

M

P

T

V

Y

AB

11.00

BSC SQ

L

N

R

U

W

0.50

BSC

AA

AC

TOP VIEW

DETAIL A

BOTTOM VIEW

1.40

1.26

1.11

DETAIL A

0.20 MIN

0.35

0.30

SEATING

PLANE

COPLANARITY

0.08

0.25

BALL DIAMETER

*

COMPLIANT WITH JEDEC STANDARD MO-275-GGCE-1

Figure 80. 289-Ball CSP_BGA (BC-289-2)

17.10

17.00 SQ

16.90

A1 BALL

CORNER

A1 BALL

CORNER

20 18 16 14 12 10

8

6

4

2

19 17 15 13 11

9

7

5

3

1

A

B

C

E

D

F

15.20

G

BSC SQ

H

J

L

K

0.80

BSC

M

P

T

N

R

U

V

W

Y

TOP VIEW

DETAIL A

BOTTOM VIEW

DETAIL A

*

1.36

1.26

1.16

*

1.75

1.61

1.46

0.35 NOM

0.30 MIN

0.50

0.45

0.40

COPLANARITY

0.12

SEATING

PLANE

BALL DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-275-MMAB-1 WITH

EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.

Figure 81. 208-Ball CSP_BGA (BC-208-2)

Rev. D

|

Page 86 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

SURFACE-MOUNT DESIGN

Table 71 is provided as an aid to PCB design. For industry-stan-

dard design recommendations, refer to IPC-7351, Generic

Requirements for Surface Mount Design and Land Pattern

Standard.

Table 71. Surface-Mount Design Supplement

Package Solder Mask

Package

Package Ball Attach Type

Solder Mask Defined

Opening

Package Ball Pad Size

0.35 mm diameter

0.50 mm diameter

289-Ball CSP_BGA

208-Ball CSP_BGA

0.26 mm diameter

0.40 mm diameter

AUTOMOTIVE PRODUCTS

The ADBF525W model is available with controlled manufactur-

ing to support the quality and reliability requirements of

automotive applications. Note that these automotive models

may have specifications that differ from the commercial models

and designers should review the product Specifications section

of this data sheet carefully. Only the automotive grade products

shown in Table 72 are available for use in automotive applica-

tions. Contact your local ADI account representative for specific

product ordering information and to obtain the specific auto-

motive Reliability reports for these models.

Table 72. Automotive Products

Temperature

Package Instruction

Automotive Models^{1, 2}

ADBF525WBBCZ4xx

ADBF525WBBCZ5xx

ADBF525WYBCZxxx

Range³

Package Description

208-Ball CSP_BGA

Option

Rate (Max)

–40°C to +85°C

BC-208-2 400 MHz

BC-208-2 533 MHz

–40°C to +105°C 208-Ball CSP_BGA

BC-208-2 For product details, please contact your

ADI account representative.

¹Z = RoHS Compliant Part.

²The information indicated by x in the model number will be provided by your ADI account representative.

³Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions for ADSP-BF523/ADSP-BF525/

ADSP-BF527 Processors on Page 30 for junction temperature (T_J) specification which is the only temperature specification.

Rev. D

|

Page 87 of 88 | July 2013

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

ORDERING GUIDE

Temperature

Range²

Instruction

Rate (Max) Package Description

Package

Option

Model¹

ADSP-BF522BBCZ-3A

ADSP-BF522BBCZ-4A

ADSP-BF522KBCZ-3

ADSP-BF522KBCZ-4

ADSP-BF523BBCZ-5A

ADSP-BF523KBCZ-5

ADSP-BF523KBCZ-6

ADSP-BF523KBCZ-6A

ADSP-BF524BBCZ-3A

ADSP-BF524BBCZ-4A

ADSP-BF524KBCZ-3

ADSP-BF524KBCZ-4

ADSP-BF525ABCZ-5

ADSP-BF525ABCZ-6

ADSP-BF525BBCZ-5A

ADSP-BF525KBCZ-5

ADSP-BF525KBCZ-6

ADSP-BF525KBCZ-6A

ADSP-BF526BBCZ-3A

ADSP-BF526BBCZ-4A

ADSP-BF526KBCZ-3

ADSP-BF526KBCZ-4

ADSP-BF527BBCZ-5A

ADSP-BF527KBCZ-5

ADSP-BF527KBCZ-6

ADSP-BF527KBCZ-6A

¹Z = RoHS Compliant Part.

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

0°C to +70°C

300 MHz

400 MHz

300 MHz

400 MHz

533 MHz

600 MHz

300 MHz

400 MHz

300 MHz

400 MHz

500 MHz

600 MHz

533 MHz

600 MHz

300 MHz

400 MHz

300 MHz

400 MHz

533 MHz

600 MHz

208-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

BC-208-2

BC-289-2

BC-208-2

BC-289-2

BC-208-2

BC-289-2

BC-208-2

BC-289-2

BC-208-2

BC-289-2

BC-208-2

BC-289-2

BC-208-2

208-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

208-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

208-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

208-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

208-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

208-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

208-Ball Chip Scale Package Ball Grid Array (CSP_BGA)

²Referencedtemperatureisambienttemperature. Theambienttemperatureisnotaspecification.PleaseseeOperatingConditionsforADSP-BF522/ADSP-BF524/ADSP-BF526

Processors on Page 28 and Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page 30 for junction temperature (T_J) specification which is

the only temperature specification.

registered trademarks are the property of their respective owners.

D06675-0-7/13(D)

Rev. D

|

Page 88 of 88 | July 2013


型号：	ADSP-BF527BBCZ-5A
厂家：	ADI
描述：	Blackfin Embedded Processor Blackfin嵌入式处理器微控制器和处理器外围集成电路数字信号处理器 PC 时钟
文件：	总88页 (文件大小：2932K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF527BBCZ-5A [ADI]

相关型号：

ADSP-BF527BBCZ-5AX

ADSP-BF527C

ADSP-BF527C_15

ADSP-BF527KBCZ-5

ADSP-BF527KBCZ-5C2

ADSP-BF527KBCZ-6

ADSP-BF527KBCZ-6A

ADSP-BF527KBCZ-6AX

ADSP-BF527KBCZ-6C2

ADSP-BF527KBCZ-6X

ADSP-BF527_15

ADSP-BF531