ADSP-BF539_08_技术文档

Blackfin

Embedded Processor

ADSP-BF539/ADSP-BF539F

External memory controller with glueless support

for SDRAM, SRAM, flash, and ROM

Flexible memory booting options from SPI and external

memory

FEATURES

1.0 V to 1.25 V core V_DDwith on-chip voltage regulation

3.0 V to 3.3 V I/O V_DD

Up to 3.3 V tolerant I/O with specific 5 V tolerant pins

316-ball Pb-free CSP_BGA package

PERIPHERALS

Up to 533 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler friendly support

Advanced debug, trace, and performance monitoring

Parallel peripheral interface (PPI),

supporting ITU-R 656 video data formats

4 dual-channel, full-duplex synchronous serial ports, sup-

porting 16 stereo I²S channels

2 DMA controllers supporting 26 peripheral DMAs

4 memory-to-memory DMAs

Controller area network (CAN) 2.0B controller

Media transceiver (MXVR) for connection

to a MOST network

3 SPI-compatible ports

Three 32-bit timer/counters with PWM support

3 UARTs with support for IrDA

2 TWI controllers compatible with I²C industry standard

Up to 38 general-purpose I/O pins (GPIO)

Up to 16 general-purpose flag pins (GPF)

Real-time clock, watchdog timer, and 32-bit core timer

On-chip PLL capable of 0.5ꢀ to 64ꢀ frequency multiplication

Debug/JTAG interface

MEMORY

148K bytes of on-chip memory:

16K bytes of instruction SRAM/cache

64K bytes of instruction SRAM

32K bytes of data SRAM

32K bytes of data SRAM/cache

4K bytes of scratchpad SRAM

512K ꢀ 16-bit or 256K ꢀ 16-bit flash memory

(ADSP-BF539F only)

Memory management unit providing memory protection

JTAG TEST AND EMULATION

VOLTAGE REGULATOR

PERIPHERAL ACCESS BUS

TWI0-1

INTERRUPT

WATCHDOG

CONTROLLER

TIMER

B

CAN 2.0B

MXVR

GPIO

PORT

C

DMA CORE

BUS 2

RTC

PPI

DMA

CONTROLLER1

L1 INSTRUCTION

MEMORY

L1 DATA

MEMORY

DMA

SPI1-2

CONTROLLER 0

GPIO

PORT

D

GPIO

PORT

F

TIMER0-2

SPI0

DMA

EXTERNAL

BUS 0

UART1-2

SPORT2-3

DMA CORE

BUS 1

DMA

EXTERNAL

BUS 1

DMA CORE BUS 0

GPIO

PORT

E

UART0

EXTERNAL PORT

FLASH, SDRAM CONTROL

SPORT0-1

16

512kB OR 1MB

BOOT ROM

FLASH MEMORY

(ADSP-BF539F ONLY)

Figure 1. Functional Block Diagram

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADSP-BF539/ADSP-BF539F

TABLE OF CONTENTS

General Description ................................................. 3

Low Power Architecture ......................................... 3

Automotive Products ............................................. 3

System Integration ................................................ 3

ADSP-BF539/ADSP-BF539F Processor Peripherals ....... 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 4

DMA Controllers .................................................. 9

Real-Time Clock ................................................... 9

Watchdog Timer .................................................. 9

Timers ............................................................. 10

Serial Ports (SPORTs) .......................................... 10

Serial Peripheral Interface (SPI) Ports ...................... 10

2-Wire Interface ................................................. 11

UART Ports ...................................................... 11

Programmable I/O Pins ........................................ 11

Parallel Peripheral Interface ................................... 12

Controller Area Network (CAN) Interface ................ 13

Media Transceiver MAC layer (MXVR) ................... 13

Dynamic Power Management ................................ 13

Voltage Regulation .............................................. 15

Clock Signals ..................................................... 15

Booting Modes ................................................... 16

Instruction Set Description ................................... 17

Development Tools ............................................. 17

Designing an Emulator Compatible Processor Board ... 18

Example Connections and Layout Considerations ...... 18

Voltage Regulator Layout Guidelines ....................... 20

MXVR Board Layout Guidelines ............................ 19

Pin Descriptions .................................................... 21

Specifications ........................................................ 26

Operating Conditions ........................................... 26

Electrical Characteristics ....................................... 27

Absolute Maximum Ratings ................................... 28

Package Information ............................................ 28

ESD Sensitivity ................................................... 28

Timing Specifications ........................................... 29

Clock and Reset Timing ..................................... 30

Asynchronous Memory Read Cycle Timing ............ 31

Asynchronous Memory Write Cycle Timing ........... 33

SDRAM Interface Timing .................................. 35

External Port Bus Request and Grant Cycle Timing .. 36

Parallel Peripheral Interface Timing ...................... 38

Serial Ports Timing ........................................... 41

Serial Peripheral Interface Ports—Master Timing ..... 44

Serial Peripheral Interface Ports—Slave Timing ....... 45

General-Purpose Port Timing ............................. 46

Timer Cycle Timing .......................................... 47

JTAG Test And Emulation Port Timing ................. 48

MXVR Timing ................................................ 49

Output Drive Currents ......................................... 50

Power Dissipation ............................................... 52

Test Conditions .................................................. 52

Thermal Characteristics ........................................ 55

316-Ball CSP_BGA Ball Assignment ........................... 56

Outline Dimensions ................................................ 59

Surface-Mount Design .......................................... 60

Ordering Guide ..................................................... 60

REVISION HISTORY

2/08—Rev. 0 to Rev. A

Identifying pins CANRX and PC4 as 5 V-tolerant when config-

ured as an input and an open-drain when configured as an

output.

Rev. A

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ADSP-BF539/ADSP-BF539F

GENERAL DESCRIPTION

The ADSP-BF539/ADSP-BF539F processors are members of

the Blackfin^®family of products, incorporating the Analog

Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin

processors combine a dual-MAC, state-of-the-art signal pro-

cessing engine, the advantages of a clean, orthogonal RISC-like

microprocessor instruction set, and single-instruction, multi-

ple-data (SIMD) multimedia capabilities into a single

instruction set architecture.

substantial reduction in power consumption, compared with

simply varying the frequency of operation. This translates into

longer battery life and lower heat dissipation.

AUTOMOTIVE PRODUCTS

Some ADSP-BF539/ADSP-BF539F models are available for

automotive applications with controlled manufacturing. Note

that these special models may have specifications that differ

from the general release models. For information on which

models are available for automotive applications, see “Ordering

Guide” on page 60.

The ADSP-BF539/ADSP-BF539F processors are completely

code compatible with other Blackfin processors, differing only

with respect to performance, peripherals, and on-chip memory.

Specific performance, peripherals, and memory configurations

are shown in Table 1 on Page 3.

SYSTEM INTEGRATION

The ADSP-BF539/ADSP-BF539F processors are highly inte-

grated system-on-a-chip solutions for the next generation of

industrial and automotive applications including audio and

video signal processing. By combining advanced memory con-

figurations, such as on-chip flash memory, with industry-

standard interfaces with a high performance signal processing

core, users can develop cost-effective solutions quickly without

the need for costly external components. The system peripherals

include a MOST Network Media Transceiver (MXVR), three

UART ports, three SPI ports, four serial ports (SPORT), one

CAN interface, two 2-wire interfaces (TWI), four general-pur-

pose timers (three with PWM capability), a real-time clock, a

watchdog timer, a parallel peripheral interface, general-purpose

I/O, and general-purpose flag pins.

Table 1. Processor Features

Feature

SPORTs

UARTs

SPI

ADSP-BF539 ADSP-BF539F4 ADSP-BF539F8

4

3

TWI

2

CAN

1

MXVR

PPI

1

Instruction

16K bytes

SRAM/Cache

ADSP-BF539/ADSP-BF539F PROCESSOR

PERIPHERALS

Instruction

SRAM

64K bytes

32K bytes

64K bytes

32K bytes

64K bytes

32K bytes

The ADSP-BF539/ADSP-BF539F processors contain a rich set

of peripherals connected to the core via several high bandwidth

buses, providing flexibility in system configuration as well as

excellent overall system performance (see Figure 1 on Page 1).

The general-purpose peripherals include functions such as

UART, timers with PWM (pulse-width modulation) and pulse

measurement capability, general-purpose flag I/O pins, a real-

time clock, and a watchdog timer. This set of functions satisfies

a wide variety of typical system support needs and is augmented

by the system expansion capabilities of the device. In addition to

these general-purpose peripherals, the ADSP-BF539/ADSP-

BF539F processors contain high speed serial and parallel ports

for interfacing to a variety of audio, video, and modem codec

functions. An MXVR transceiver transmits and receives audio

and video data and control information on a MOST automotive

multimedia network. A CAN 2.0B controller is provided for

automotive control networks. An interrupt controller manages

interrupts from the on-chip peripherals or external sources.

And power management control functions tailor the perfor-

mance and power characteristics of the processor and system to

many application scenarios.

Data

SRAM/Cache

Data SRAM

Scratchpad

Flash

32K bytes

4K bytes

32K bytes

4K bytes

32K bytes

4K bytes

Not

applicable

256K ꢀ 16-bit 512K ꢀ 16-bit

Maximum

533 MHz

1066 MMACS

Speed Grade 1066 MMACS 1066 MMACS

Package

Option

BC-316

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next generation applications that require RISC-like program-

mability, multimedia support, and leading edge signal

processing in one integrated package.

LOW POWER ARCHITECTURE

Blackfin processors provide world class power management and

performance. Blackfin processors are designed in a low power

and low voltage design methodology and feature dynamic

power management, the ability to vary both the voltage and fre-

quency of operation to significantly lower overall power

consumption. Varying the voltage and frequency can result in a

All of the peripherals, except for general-purpose I/O, CAN,

TWI, real-time clock, and timers, are supported by a flexible

DMA structure. There are also four separate memory DMA

channels dedicated to data transfers between the processor’s

Rev. A

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February 2008

ADSP-BF539/ADSP-BF539F

various memory spaces, including external SDRAM and asyn-

chronous memory. Multiple on-chip buses running at up to

133 MHz provide enough bandwidth to keep the processor core

running along with activity on all of the on-chip and external

peripherals.

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

The ADSP-BF539/ADSP-BF539F processors include an on-chip

voltage regulator in support of the ADSP-BF539/ADSP-BF539F

processor dynamic power management capability. The voltage

regulator provides a range of core voltage levels from a single

2.7 V to 3.6 V input. The voltage regulator can be bypassed at

the user's discretion.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The Memory Manage-

ment Unit (MMU) provides memory protection for individual

tasks that can be operating on the core and can protect system

registers from unintended access.

BLACKFIN PROCESSOR CORE

As shown in Figure 2, the Blackfin processor core contains two

16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,

four video ALUs, and a 40-bit shifter. The computation units

process 8-bit, 16-bit, or 32-bit data from the register file.

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation are

supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2³²multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations, 16-

bit and 8-bit adds with clipping, 8-bit average operations, and 8-

bit subtract/absolute value/accumulate (SAA) operations. Also

provided are the compare/select and vector search instructions.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF539/ADSP-BF539F processors view memory as a

single unified 4G byte address space, using 32-bit addresses. All

resources, including internal memory, external memory, and

I/O control registers, occupy separate sections of this common

address space. The memory portions of this address space are

arranged in a hierarchical structure to provide a good cost/per-

formance balance of some very fast, low latency on-chip

memory as cache or SRAM, and larger, lower cost and perfor-

mance off-chip memory systems. See Figure 3.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). By also using the second

ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

The L1 memory system is the primary highest performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the external bus interface unit

(EBIU), provides expansion with SDRAM, flash memory, and

SRAM, optionally accessing up to 516M bytes of physical

memory.

The memory DMA controller provides high bandwidth data

movement capability. It performs block transfers of code or data

between the internal memory and the external memory spaces.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

Rev. A

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February 2008

ADSP-BF539/ADSP-BF539F

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

P3

P2

P1

P0

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

DAG0

DA1

DA0

32

PREG

32

RAB

SD

LD1

LD0

32

ASTAT

32

SEQUENCER

R7.H

R7.L

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

ALIGN

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

The PC133-compliant SDRAM controller can be programmed

to interface to up to 512M bytes of SDRAM. The SDRAM con-

troller allows one row to be open for each internal SDRAM

bank, for up to four internal SDRAM banks, improving overall

system performance.

Internal (On-Chip) Memory

The ADSP-BF539/ADSP-BF539F processor has three blocks of

on-chip memory providing high bandwidth access to the core.

The first is the L1 instruction memory, consisting of 80K bytes

SRAM, of which 16K bytes can be configured as a four-way set-

associative cache. This memory is accessed at full

processor speed.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks will only be contiguous if each is fully popu-

lated with 1M byte of memory.

The second on-chip memory block is the L1 data memory, con-

sisting of two banks of up to 32K bytes each. Each memory bank

is configurable, offering both cache and SRAM functionality.

This memory block is accessed at full processor speed.

Flash Memory (ADSP-BF539F Only)

The third memory block is a 4K byte scratch pad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

The ADSP-BF539F4 and ADSP-BF539F8 processors contain a

separate flash die, connected to the EBIU bus, within the pack-

age of the ADSP-BF539F processors. Figure 4 shows how the

flash memory die and Blackfin processor die are connected.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory

devices including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

Rev. A

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February 2008

ADSP-BF539/ADSP-BF539F

The ADSP-BF539F4 contains a 4M bit (256K ꢀ 16-bit) bottom

boot sector Spansion S29AL004D known good die flash mem-

ory^†. The ADSP-BF539F8 contains an 8M bit (512K ꢀ 16-bit)

bottom boot sector Spansion S29AL008D known good die flash

memory. Features include the following:

0xFFFF FFFF

CORE MMR REGISTERS (2M BYTE)

0xFFE0 0000

SYSTEM MMR REGISTERS (2M BYTE)

0xFFC0 0000

RESERVED

0xFFB0 1000

SCRATCHPAD SRAM (4K BYTE)

0xFFB0 0000

• Access times as fast as 70 ns (EBIU registers be set

appropriately)

RESERVED

0xFFA1 4000

INSTRUCTION SRAM / CACHE (16K BYTE)

0xFFA1 0000

INSTRUCTION SRAM (64K BYTE)

0xFFA0 0000

• Sector protection

• One million write cycles per sector

• 20 year data retention

RESERVED

0xFF90 8000

DATA BANK B SRAM / CACHE (16K BYTE)

0xFF90 4000

The Blackfin processor connects to the flash memory die with

address, data, chip enable, write enable, and output enable con-

trols as if it were an external memory device.

DATA BANK B SRAM (16K BYTE)

0xFF90 0000

RESERVED

0xFF80 8000

DATA BANK A SRAM / CACHE (16K BYTE)

0xFF80 4000

The flash chip enable pin FCE must be connected to AMS0 or

AMS3–1 through a printed circuit board trace. When connected

to AMS0, the Blackfin processor can boot from the flash die.

When connected to AMS3–1, the flash memory will appear as

nonvolatile memory in the processor memory map, shown in

Figure 3 on Page 6.

DATA BANK A SRAM (16K BYTE)

0xFF80 0000

RESERVED

0xEF00 0000

RESERVED

0x2040 0000

ASYNC MEMORY BANK 3 (1M BYTE) OR

ON-CHIP FLASH (ADSP-BF539F ONLY)

0x2030 0000

ASYNC MEMORY BANK 2 (1M BYTE) OR

ON-CHIP FLASH (ADSP-BF539F ONLY)

Flash Memory Programming

0x2020 0000

ASYNC MEMORY BANK 1 (1M BYTE) OR

ON-CHIP FLASH (ADSP-BF539F ONLY)

The ADSP-BF539F4 and ADSP-BF539F8 flash memory can be

programmed before or after mounting on the printed

circuit board.

0x2010 0000

ASYNC MEMORY BANK 0 (1M BYTE) OR

ON-CHIP FLASH (ADSP-BF539F ONLY)

0x2000 0000

RESERVED

0x0800 0000

SDRAM MEMORY (16M BYTE TO 512M BYTE)

0x0000 0000

To program the flash prior to mounting on the printed circuit

board, use a hardware programming tool that can provide the

data, address, and control stimuli to the flash die through the

external pins on the package. During this programming, V_DDEXT

and GND must be provided to the package and the Blackfin

must be held in reset with bus request (BR) asserted and a

CLKIN provided.

Figure 3. ADSP-BF539/ADSP-BF539F Internal/External Memory Map

The VisualDSP++^‡tools can be used to program the flash mem-

ory after the device is mounted on a printed circuit board.

ADDR19-1

A18-0

OE

WE

RY/BY

DQ15-0

VSS

Flash Memory Sector Protection

ARE

AWE

ARDY

To use the sector protection feature, a high voltage (+12 V nom-

inal) must be applied to the flash FRESET pin. Refer to the flash

data sheet for details.

DATA15-0

GND

DDEXT

V

VCC

BYTE

CE

RESET

I/O Memory Space

AMS3-0

RESET

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory mapped registers (MMRs) at addresses near the top of the

4G byte address space. These are separated into two smaller

blocks, one of which contains the control MMRs for all core

functions, and the other of which contains the registers needed

for setup and control of the on-chip peripherals outside of the

core. The MMRs are accessible only in supervisor mode and

appear as reserved space to on-chip peripherals.

ADSP-BF539F

PACKAGE

Figure 4. Internal Connection of Flash Memory (ADSP-BF539Fx)

^†Refer to the Spansion website for the appropriate data sheets.

^‡VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. A

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ADSP-BF539/ADSP-BF539F

Table 2. Core Event Controller (CEC)

Booting

The ADSP-BF539/ADSP-BF539F processor contains a small

boot kernel, which configures the appropriate peripheral for

booting. If the ADSP-BF539/ADSP-BF539F processor is config-

ured to boot from boot ROM memory space, the processor

starts executing from the on-chip boot ROM. For more infor-

mation, see Booting Modes on Page 16.

Priority

(0 is Highest)

Event Class

EVT Entry

EMU

0

Emulation/Test Control

Reset

1

RST

2

Nonmaskable Interrupt

Exception

NMI

3

EVX

Event Handling

4

Reserved

—

The event controller on the ADSP-BF539/ADSP-BF539F pro-

cessor handles all asynchronous and synchronous events to the

processor. The ADSP-BF539/ADSP-BF539F processor provides

event handling that supports both nesting and prioritization.

Nesting allows multiple event service routines to be active

simultaneously. Prioritization ensures that servicing of a higher

priority event takes precedence over servicing of a lower priority

event. The controller provides support for five different types of

events:

5

Hardware Error

IVHW

IVTMR

IVG7

6

Core Timer

7

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

8

IVG8

9

IVG9

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

• Nonmaskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

System Interrupt Controllers (SIC)

The system interrupt controllers (SIC0, SIC1) provide the map-

ping and routing of events from the many peripheral interrupt

sources to the prioritized general-purpose interrupt inputs of

the CEC. Although the ADSP-BF539/ADSP-BF539F processors

provide a default mapping, the user can alter the mappings and

priorities of interrupt events by writing the appropriate values

into the interrupt assignment registers (SIC_IARx). Table 3

describes the inputs into the SICs and the default mappings into

the CEC.

• Exceptions – Events that occur synchronously to program

flow (i.e., the exception will be taken before the instruction

is allowed to complete). Conditions such as data alignment

violations and undefined instructions cause exceptions.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

Table 3. System and Core Event Mapping

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

Core

Event Name

Event Source

PLL Wake-up Interrupt

DMA Controller 0 Error

DMA Controller 1 Error

PPI Error Interrupt

IVG7

The ADSP-BF539/ADSP-BF539F processor’s event controller

consists of two stages, the core event controller (CEC) and the

system interrupt controllers (SIC). The core event controller

works with the system interrupt controllers to prioritize and

control all system events. Conceptually, interrupts from the

peripherals enter into one of the SIC, and are then routed

directly into the general-purpose interrupts of the CEC.

IVG7

SPORT0 Error Interrupt

SPORT1 Error Interrupt

SPORT2 Error Interrupt

SPORT3 Error Interrupt

MXVR Synchronous Data Interrupt

SPI0 Error Interrupt

IVG7

Core Event Controller (CEC)

IVG7

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the ADSP-BF539/ADSP-BF539F pro-

cessors. Table 2 describes the inputs to the CEC, identifies their

names in the event vector table (EVT), and lists their priorities.

IVG7

SPI1 Error Interrupt

IVG7

SPI2 Error Interrupt

IVG7

UART0 Error Interrupt

UART1 Error Interrupt

IVG7

Rev. A

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February 2008

ADSP-BF539/ADSP-BF539F

Table 3. System and Core Event Mapping (Continued)

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

it can also be written to clear (cancel) latched events. This

register may be read while in supervisor mode and may

only be written while in supervisor mode when the corre-

sponding IMASK bit is cleared.

Core

Event Source

Event Name

UART2 Error Interrupt

IVG7

CAN Error Interrupt

IVG7

• CEC Interrupt Mask Register (IMASK) – The IMASK reg-

ister controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and will be processed by the CEC when asserted.

A cleared bit in the IMASK register masks the event,

preventing the processor from servicing the event even

though the event can be latched in the ILAT register. This

register can be read or written while in supervisor mode.

(Note that general-purpose interrupts can be globally

enabled and disabled with the STI and CLI instructions,

respectively.)

Real-Time Clock Interrupt

DMA0 Interrupt (PPI)

IVG8

DMA1 Interrupt (SPORT0 Rx)

DMA2 Interrupt (SPORT0 Tx)

DMA3 Interrupt (SPORT1 Rx)

DMA4 Interrupt (SPORT1 Tx)

DMA8 Interrupt (SPORT2 Rx)

DMA9 Interrupt (SPORT2 Tx)

DMA10 Interrupt (SPORT3 Rx)

DMA11 Interrupt (SPORT3 Tx)

DMA5 Interrupt (SPI0)

IVG9

• CEC Interrupt Pending Register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates whether the event is currently

active or nested at some level. This register is updated auto-

matically by the controller but can be read while in

supervisor mode.

IVG9

IVG10

IVG11

IVG12

IVG13

DMA14 Interrupt (SPI1)

DMA15 Interrupt (SPI2)

DMA6 Interrupt (UART0 Rx)

DMA7 Interrupt (UART0 Tx)

DMA16 Interrupt (UART1 Rx)

DMA17 Interrupt (UART1 Tx)

DMA18 Interrupt (UART2 Rx)

DMA19 Interrupt (UART2 Tx)

Timer0, Timer1, Timer2 Interrupts

TWI0 Interrupt

Each SIC allows further control of event processing by provid-

ing three 32-bit interrupt control and status registers. Each

register contains a bit corresponding to each of the peripheral

interrupt events shown in Table 3 on Page 7.

• SIC Interrupt Mask Registers (SIC_IMASKx)– These regis-

ters control the masking and unmasking of each peripheral

interrupt event. When a bit is set in these registers, that

peripheral event is unmasked and will be processed by the

system when asserted. A cleared bit in these registers masks

the peripheral event, preventing the processor from servic-

ing the event.

TWI1 Interrupt

CAN Receive Interrupt

• SIC Interrupt Status Registers (SIC_ISRx) – As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

source triggered the interrupt. A set bit indicates that the

peripheral is asserting the interrupt, and a cleared bit indi-

cates that the peripheral is not asserting the event.

CAN Transmit Interrupt

MXVR Status Interrupt

MXVR Control Message Interrupt

MXVR Asynchronous Packet Interrupt

Programmable Flags Interrupts

MDMA0 Stream 0 Interrupt

MDMA0 Stream 1 Interrupt

MDMA1 Stream 0 Interrupt

MDMA1 Stream 1 Interrupt

Software Watchdog Timer

• SIC Interrupt Wake-up Enable Registers (SIC_IWRx) – By

enabling the corresponding bit in these registers, a periph-

eral can be configured to wake up the processor, should the

core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 13.)

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

Event Control

The ADSP-BF539/ADSP-BF539F processors provide the user

with a very flexible mechanism to control the processing of

events. In the CEC, three registers are used to coordinate and

control events. Each register is 16 bits wide:

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC will recognize and queue the

• CEC Interrupt Latch Register (ILAT) – The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and is

Rev. A

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February 2008

ADSP-BF539/ADSP-BF539F

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

32.768 kHz crystal external to the ADSP-BF539/ADSP-BF539F

processors. The RTC peripheral has dedicated power supply

pins so that it can remain powered up and clocked even when

the rest of the processor is in a low power state. The RTC pro-

vides several programmable interrupt options, including

interrupt per second, minute, hour, or day clock ticks, interrupt

on programmable stopwatch countdown, or interrupt at a pro-

grammed alarm time.

DMA CONTROLLERS

The ADSP-BF539/ADSP-BF539F processor has multiple, inde-

pendent DMA controllers that support automated data transfers

with minimal overhead for the processor core. DMA transfers

can occur between the ADSP-BF539/ADSP-BF539F processor

internal memories and any of its DMA capable peripherals.

Additionally, DMA transfers can be accomplished between any

of the DMA-capable peripherals and external devices connected

to the external memory interfaces, including the SDRAM con-

troller and the asynchronous memory controller. DMA capable

peripherals include the SPORTs, SPI ports, UARTs, and PPI.

Each individual DMA capable peripheral has at least one dedi-

cated DMA channel. In addition, the MXVR peripheral has its

own dedicated DMA controller, which supports its own unique

set of operating modes.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: the first alarm is

for a time of day. The second alarm is for a day and time of

that day.

The stopwatch function counts down from a programmed

value, with one second resolution. When the stopwatch is

enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the ADSP-

BF539/ADSP-BF539F processor from sleep mode upon genera-

tion of any RTC wake-up event. Additionally, an RTC wake-up

event can wake up the ADSP-BF539/ADSP-BF539F processor

from deep sleep mode, and wake up the on-chip internal voltage

regulator from a powered down state.

The ADSP-BF539/ADSP-BF539F processor DMA controllers

support both 1-dimensional (1-D) and 2-dimensional (2-D)

DMA transfers. DMA transfer initialization can be imple-

mented from registers or from sets of parameters called

descriptor blocks.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements and arbitrary row and

column step sizes up to 32K elements. Furthermore, the col-

umn step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be

deinterleaved on the fly.

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 5.

RTXI

RTXO

R1

X1

Examples of DMA types supported by the ADSP-BF539/ADSP-

BF539F processors DMA controller include:

• A single, linear buffer that stops upon completion

C1

C2

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

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C1 = 22pF

C2 = 22pF

R1 = 10MΩ

In addition to the dedicated peripheral DMA channels, there are

four memory DMA channels provided for transfers between the

various memories of the ADSP-BF539/ADSP-BF539F processor

system. This enables transfers of blocks of data between any of

the memories—including external SDRAM, ROM, SRAM, and

flash memory—with minimal processor intervention. Memory

DMA transfers can be controlled by a very flexible descriptor-

based methodology or by a standard register-based autobuffer

mechanism.

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3pF.

Figure 5. External Components for RTC

WATCHDOG TIMER

The ADSP-BF539/ADSP-BF539F processors include a 32-bit

timer that can be used to implement a software watchdog func-

tion. A software watchdog can improve system availability by

forcing the processor to a known state through generation of a

hardware reset, nonmaskable interrupt (NMI), or general-pur-

pose interrupt, if the timer expires before being reset by

software. The programmer initializes the count value of the

REAL-TIME CLOCK

The ADSP-BF539/ADSP-BF539F processor real-time clock

(RTC) provides a robust set of digital watch features, including

current time, stopwatch, and alarm. The RTC is clocked by a

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ADSP-BF539/ADSP-BF539F

timer, enables the appropriate interrupt, and then enables the

timer. Thereafter, the software must reload the counter before it

counts to zero from the programmed value. This protects the

system from remaining in an unknown state where software,

which would normally reset the timer, has stopped running due

to an external noise condition or software error.

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

• Companding in hardware – Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without additional

latencies.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the ADSP-BF539/ADSP-BF539F pro-

cessor peripherals. After a reset, software can determine if the

watchdog was the source of the hardware reset by interrogating

a status bit in the watchdog timer control register.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f_SCLK

.

TIMERS

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

There are four general-purpose programmable timer units in

the ADSP-BF539/ADSP-BF539F processors. Three timers have

an external pin that can be configured either as a pulse-width

modulator (PWM) or timer output, as an input to clock the

timer, or as a mechanism for measuring pulse widths and peri-

ods of external events. These timers can be synchronized to an

external clock input to the PF1 pin (TACLK), an external clock

input to the PPI_CLK pin (TMRCLK), or to the internal SCLK.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The timer units can be used in conjunction with UART0 to

measure the width of the pulses in the data stream to provide an

auto-baud detect function for a serial channel.

The ADSP-BF539/ADSP-BF539F processors incorporate three

SPI-compatible ports that enable the processor to communicate

with multiple SPI compatible devices.

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

The SPI interface uses three pins for transferring data: two data

pins (master output-slave input, MOSIx, and master input-slave

output, MISOx) and a clock pin (serial clock, SCKx). An SPI

chip select input pin (SPIxSS) lets other SPI devices select the

processor. For SPI0, seven SPI chip select output pins

(SPI0SEL7–1) let the processor select other SPI devices. SPI1

and SPI2 each have a single SPI chip select output pin

(SPI1SEL1 and SPI2SEL1) for SPI point-to-point communica-

tion. Each of the SPI select pins is a reconfigured GPIO pin.

Using these pins, the SPI ports provide a full-duplex, synchro-

nous serial interface, which supports both master/slave modes

and multimaster environments.

In addition to the three general-purpose programmable timers,

a fourth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTs)

The ADSP-BF539/ADSP-BF539F processors incorporate four

dual-channel synchronous serial ports for serial and multipro-

cessor communications. The SPORTs support the following

features:

The SPI ports’ baud rate and clock phase/polarities are pro-

grammable, and they each have an integrated DMA controller,

configurable to support transmit or receive data streams. Each

SPI DMA controller can only service unidirectional accesses at

any given time.

• I²S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling 16 channels of

I²S stereo audio.

The SPI port clock rate is calculated as:

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

f_SCLK

2 × SPIx_BAUD

--------------------------------------

SPI Clock Rate =

where the 16-bit SPIx_BAUD register contains a value of 2 to

65,535.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

• Word length – Each SPORT supports serial data words

from 3 bits to 32 bits in length, transferred most significant

bit first or least significant bit first.

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ADSP-BF539/ADSP-BF539F

2-WIRE INTERFACE

PROGRAMMABLE I/O PINS

The ADSP-BF539/ADSP-BF539F processors incorporate two

2-wire interface (TWI) modules that are compatible with the

Philips Inter-IC bus standard. The TWI modules offer the capa-

bilities of simultaneous master and slave operation, support for

7-bit addressing, and multimedia data arbitration. The TWI also

includes master clock synchronization and support for clock

low extension.

The ADSP-BF539/ADSP-BF539F processor has numerous

peripherals that may not all be required for every application.

Many of the pins thus have a secondary function, as program-

mable I/O pins. There are two types of programmable I/O pins

on the ADSP-BF539/ADSP-BF539F processor, with slightly dif-

ferent functionality: programmable flags and general-purpose

I/O.

The TWI interface uses two pins for transferring clock (SCLx)

and data (SDAx) and supports the protocol at speeds up to

400 kbps.

Programmable Flags (PFx)

The ADSP-BF539/ADSP-BF539F processors have 16 bidirec-

tional, general-purpose programmable flag (PF15–0) pins. Each

programmable flag can be individually controlled by manipula-

tion of the flag control, status, and interrupt registers:

The TWI interface pins are compatible with 5 V logic levels.

UART PORTS

• Flag direction control register – Specifies the direction of

each individual PFx pin as input or output.

The ADSP-BF539/ADSP-BF539F processor incorporates three

full-duplex universal asynchronous receiver/transmitter

(UART) ports, which are fully compatible with PC standard

UARTs. The UART ports provide a simplified UART interface

to other peripherals or hosts, supporting full-duplex, DMA sup-

ported, asynchronous transfers of serial data. The UART ports

include support for 5 data bits to 8 data bits, 1-stop bit or 2-stop

bits, and none, even, or odd parity. The UART ports support

two modes of operation:

• Flag control and status registers – The

ADSP-BF539/ADSP-BF539F processors employ a “write

one to modify” mechanism that allows any combination of

individual flags to be modified in a single instruction, with-

out affecting the level of any other flags. Four control

registers are provided. One register is written in order to set

flag values, one register is written in order to clear flag val-

ues, one register is written in order to toggle flag values,

and one register is written in order to specify a flag value.

Reading the flag status register allows software to interro-

gate the sense of the flags.

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O mapped UART registers.

The data is double buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. Each UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

• Flag interrupt mask registers – The two flag interrupt mask

registers allow each individual PFx pin to function as an

interrupt to the processor. Similar to the two flag control

registers that are used to set and clear individual flag values,

one flag interrupt mask register sets bits to enable interrupt

function, and the other flag interrupt mask register clears

bits to disable interrupt function. PFx pins defined as

inputs can be configured to generate hardware interrupts,

while output PFx pins can be triggered by software

interrupts.

Each UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_SCLK/1,048,576) to

(f_SCLK/16) bits per second.

• Flag interrupt sensitivity registers – The two flag interrupt

sensitivity registers specify whether individual PFx pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

• Supporting data formats from 7 bits to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

Each UART port’s clock rate is calculated as:

f_SCLK

-----------------------------------------------

UART Clock Rate =

16 × UART_Divisor

General-Purpose I/O

where the 16-bit UART_Divisor comes from the UARTx_DLH

register (most significant 8 bits) and UARTx_DLL register (least

significant 8 bits).

The ADSP-BF539/ADSP-BF539F processors have 38 general-

purpose I/O pins that are multiplexed with other peripherals.

They are arranged into ports C, D, E, and F as shown in Table 4

on Page 12. The GPIO differ from the programmable flags in

that the GPIO pins cannot generate interrupts to the processor.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported on UART0.

The capabilities of the UARTs are further extended with sup-

port for the Infrared Data Association (IrDA^®) Serial Infrared

Physical Layer Link Specification (SIR) protocol.

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ADSP-BF539/ADSP-BF539F

Table 4. Programmable Flag / GPIO Ports

data. Up to 3 frame synchronization signals are also provided.

In ITU-R 656 mode, the PPI provides half-duplex, bidirectional

transfer of 8- or 10-bit video data. Additionally, on-chip decode

of embedded start-of-line (SOL) and start-of-field (SOF) pre-

amble packets are supported.

Alternate Programmable

Flag / GPIO Port Function

Peripheral

PPI

PF15–3

SPORT2

SPORT3

SPI0

PE7–0

General-Purpose Mode Descriptions

PE15–8

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

PF7–0

SPI1

PD4–0

• Input Mode – Frame syncs and data are inputs into the PPI.

SPI2

PD9–5

UART1

UART2

CAN

PD11–10

PD13–12

PC1–0

• Frame Capture Mode – Frame syncs are outputs from the

PPI, but data are inputs.

• Output Mode – Frame syncs and data are outputs from

the PPI.

MXVR

PC9–4

Input Mode

The general-purpose I/O pins can be individually controlled by

manipulation of the control and status registers. These pins will

not cause interrupts to be generated to the processor but can be

polled to determine their status.

This mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_COUNT register. The PPI supports 8-bit, and 10-bit

through 16-bit data and are programmable in the

• GPIO direction control register – Specifies the direction of

each individual GPIOx pin as input or output.

• GPIO control and status registers – The

ADSP-BF539/ADSP-BF539F processors employ a “write

one to modify” mechanism that allows any combination of

individual GPIO to be modified in a single instruction,

without affecting the level of any other GPIO. Four control

registers and a data register are provided for each GPIO

port. One register is written in order to set GPIO values,

one register is written in order to clear GPIO values, one

register is written in order to toggle GPIO values, and one

register is written in order to specify a GPIO input or out-

put. Reading the GPIO data allows software to determine

the state of the input GPIO pins. PC1 and PC4 are open-

drain when configured as GPIO outputs.

PPI_CONTROL register.

Frame Capture Mode

This mode allows the video source(s) to act as a slave (e.g., for

frame capture). The ADSP-BF539/ADSP-BF539F processors

control when to read from the video source(s). PPI_FS1 is an

HSYNC output, and PPI_FS2 is a VSYNC output.

Output Mode

This mode is used for transmitting video or other data with up

to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

Note that the GP pin is used to specify the status of the GPIO

pins PC9–PC4 at power up. If GP is tied high, then pins

PC9–PC4 are configured as GPIO after reset. The pins cannot

be reconfigured through software, and special care must be

taken with the MLF pin. If the GP pin is tied low, then the pins

are configured as MXVR pins after reset but can be reconfig-

ured as GPIO pins through software.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

PARALLEL PERIPHERAL INTERFACE

• Active Video Only Mode

• Vertical Blanking Only Mode

• Entire Field Mode

The ADSP-BF539/ADSP-BF539F processors provide a parallel

peripheral interface (PPI) that can connect directly to parallel

A/D and D/A converters, video encoders and decoders, and

other general-purpose peripherals. The PPI consists of a dedi-

cated input clock pin, up to 3 frame synchronization pins, and

up to 16 data pins. The input clock supports parallel data rates

up to f_SCLK/2 MHz, and the synchronization signals can be con-

figured as either inputs or outputs.

Active Video Only Mode

This mode is used when only the active video portion of a field

is of interest and not any of the blanking intervals. The PPI will

not read in any data between the end of active video (EAV) and

start of active video (SAV) preamble symbols, or any data

present during the vertical blanking intervals. In this mode, the

control byte sequences are not stored to memory; they are

The PPI supports a variety of general-purpose and ITU-R 656

modes of operation. In general-purpose mode, the PPI provides

half-duplex, bidirectional data transfer with up to 16 bits of

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February 2008

ADSP-BF539/ADSP-BF539F

filtered by the PPI. After synchronizing to the start of Field 1,

the PPI will ignore incoming samples until it sees an SAV code.

The user specifies the number of active video lines per frame (in

PPI_COUNT register).

MEDIA TRANSCEIVER MAC LAYER (MXVR)

The ADSP-BF539/ADSP-BF539F processors provide a media

transceiver (MXVR) MAC layer, allowing the processor to be

connected directly to a MOST network through just an FOT or

electrical PHY.

Vertical Blanking Interval Mode

The MXVR is fully compatible with the industry standard

standalone MOST controller devices, supporting 22.579 Mbps

or 24.576 Mbps data transfer. It offers faster lock times, greater

jitter immunity, a sophisticated DMA scheme for data transfers,

and the high speed internal interface to the core and L1 memory

allows the full bandwidth of the network to be utilized. The

MXVR can operate as either the network master or as a

network slave.

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that can be embedded in horizontal and verti-

cal blanking intervals. Data transfer starts immediately after

synchronization to Field 1.

Synchronous data is transferred to or from the synchronous

data channels through eight programmable DMA engines. The

synchronous data DMA engines can operate in various modes,

including modes that trigger DMA operation when data pat-

terns are detected in the receive data stream. Furthermore, two

DMA engines support asynchronous traffic and a further sup-

port control message traffic.

CONTROLLER AREA NETWORK (CAN) INTERFACE

The ADSP-BF539/ADSP-BF539F processors provide a CAN

controller that is a communication controller implementing the

controller area network (CAN) V2.0B protocol. This protocol is

an asynchronous communications protocol used in both indus-

trial and automotive control systems. CAN is well suited for

control applications due to its ability to communicate reliably

over a network since the protocol incorporates CRC checking,

message error tracking, and fault node confinement.

Interrupts are generated when a user-defined amount of syn-

chronous data has been sent or received by the processor or

when asynchronous packets or control messages have been sent

or received.

The CAN controller is based on a 32-entry mailbox RAM and

supports both the standard and extended identifier (ID) mes-

sage formats specified in the CAN protocol specification,

Revision 2.0, Part B.

The MXVR peripheral can wake up the ADSP-BF539/ADSP-

BF539F processors from sleep mode when a wake-up preamble

is received over the network or based on any other MXVR inter-

rupt event. Additionally, detection of network activity by the

MXVR can be used to wake up the ADSP-BF539/ADSP-BF539F

processors from sleep mode and wake up the on-chip internal

voltage regulator from the powered-down hibernate state. These

features allow the ADSP-BF539/ADSP-BF539F to operate in a

low-power state when there is no network activity or when data

is not currently being received or transmitted by the MXVR.

Each mailbox consists of eight 16-bit data words. The data is

divided into fields, which includes a message identifier, a time

stamp, a byte count, up to 8 bytes of data, and several control

bits. Each node monitors the messages being passed on the net-

work. If the identifier in the transmitted message matches an

identifier in one of its mailboxes, then the module knows that

the message was meant for it, passes the data into its appropriate

mailbox, and signals the processor of message arrival with an

interrupt.

The MXVR clock is provided through a dedicated external crys-

tal or crystal oscillator. For 44.1 kHz frame syncs, use a

45.1584 MHz crystal or oscillator; for 48 kHz frame syncs, use a

49.152 MHz crystal or oscillator. If using a crystal to provide the

MXVR clock, use a parallel-resonant, fundamental mode,

microprocessor-grade crystal.

The CAN controller can wake up the ADSP-BF539/ADSP-

BF539F processors from sleep mode upon generation of a wake-

up event, such that the processor can be maintained in a low

power mode during idle conditions. Additionally, a CAN wake-

up event can wake up the on-chip internal voltage regulator

from the hibernate state.

DYNAMIC POWER MANAGEMENT

The ADSP-BF539/ADSP-BF539F processors provide four oper-

ating modes, each with a different performance/power profile.

In addition, dynamic power management provides the control

functions to dynamically alter the processor core supply voltage,

further reducing power dissipation. Control of clocking to each

of the ADSP-BF539/ADSP-BF539F processor peripherals also

reduces power consumption. See Table 5 for a summary of the

power settings for each mode.

The electrical characteristics of each network connection are

very stringent; therefore, the CAN interface is typically divided

into two parts: a controller and a transceiver. This allows a sin-

gle controller to support different drivers and CAN networks.

The ADSP-BF539/ADSP-BF539F CAN module represents the

controller part of the interface. This module’s network I/O is a

single transmit output and a single receive input, which connect

to a line transceiver.

The CAN clock is derived from the processor system clock

(SCLK) through a programmable divider and therefore does not

require an additional crystal.

Rev. A

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February 2008

ADSP-BF539/ADSP-BF539F

interrupt causes the processor to transition to the active mode.

Assertion of RESET while in deep sleep mode causes the proces-

sor to transition to the full-on mode.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all

the synchronous peripherals (SCLK). The internal voltage regu-

lator for the processor can be shut off by writing b#00 to the

FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V_DDINT) to 0 V to provide the lowest static power

dissipation. Any critical information stored internally (memory

contents, register contents, etc.) must be written to a nonvolatile

storage device prior to removing power if the processor state is

to be preserved. Since V_DDEXTis still supplied in this mode, all of

the external pins three-state, unless otherwise specified. This

allows other devices that can be connected to the processor to

have power still applied without drawing unwanted current.

The internal supply regulator can be woken up either by a real-

time clock wake-up, by CAN bus traffic, by asserting the RESET

pin, or by MOST bus traffic causing the MRXON pin to assert.

If either CAN or MXVR is not used, a general-purpose wake-up

is possible.

Active Operating Mode—Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. In this

mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the full-on mode is

entered. DMA access is available to appropriately configured L1

memories.

In the active mode, it is possible to disable the PLL through the

PLL Control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the full-on or sleep modes.

Table 5. Power Settings

Power Savings

As shown in Table 6, the ADSP-BF539/ADSP-BF539F proces-

sors support five different power domains. The use of multiple

power domains maximizes flexibility, while maintaining com-

pliance with industry standards and conventions:

Full-On

Active

Sleep

Enabled

No

Enabled Enabled On

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

Enabled/ disabled Yes

Enabled

Deep Sleep Disabled

Hibernate Disabled

• The 3.3 V V_DDRTCpower domain supplies the RTC I/O and

logic so that the RTC can remain functional when the rest

of the chip is powered off.

Sleep Operating Mode—High Dynamic Power Savings

• The 3.3 V MXEVDD power domain supplies the MXVR

crystal and is separate to provide noise isolation.

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally an external event or RTC activity will wake up the

processor. When in the sleep mode, assertion of wake-up will

cause the processor to sense the value of the BYPASS bit in the

PLL Control register (PLL_CTL). If Bypass is disabled, the pro-

cessor will transition to the full-on mode. If Bypass is enabled,

the processor will transition to the active mode. When in the

sleep mode, system DMA access to L1 memory is not supported.

• The 1.25 V MPIVDD power domain supplies the MXVR

PLL and is separate to provide noise isolation.

• The 1.25 V V_DDINTpower domain supplies all internal logic

except for the RTC logic and the MXVR PLL.

• The 3.3 V V_DDEXTpower domain supplies all I/O except for

the RTC and MXVR crystals.

There are no sequencing requirements for the various power

domains.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

Table 6. Power Domains

Power Domain

VDD Range

V_DDRTC

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals

such as the RTC may still be running but will not be able to

access internal resources or external memory. This powered-

down mode can only be exited by assertion of the reset interrupt

(RESET) or by an asynchronous interrupt generated by the

RTC. When in deep sleep mode, an RTC asynchronous

RTC Crystal I/O and Logic

MXVR Crystal I/O

MXEVDD

MPIVDD

MXVR PLL Analog and Logic

All Internal Logic Except RTC and MXVR PLL V_DDINT

All I/O Except RTC and MXVR Crystals

V_DDEXT

Rev. A

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February 2008

ADSP-BF539/ADSP-BF539F

The V_DDRTCshould either be connected to an isolated supply

such as a battery (if the RTC is to operate while the rest of the

chip is powered down) or should be connected to the V_DDEXT

plane on the board. The V_DDRTCshould remain powered when

the processor is in hibernate state and should also remain pow-

ered even if the RTC functionality is not being used in an

application. The MXEVDD should be connected to the V_DDEXT

plane on the board at a single location with local bypass capaci-

tors. The MXEVDD should remain powered when the

processor is in hibernate state and should also remain powered

even when the MXVR functionality is not being used in an

application. The MPIVDD should be connected to the V_DDINT

plane on the board at a single location through a ferrite bead

with local bypass capacitors.

logic voltage levels and is programmable with the voltage regu-

lator control register (VR_CTL) in increments of 50 mV. To

reduce standby power consumption, the internal voltage regula-

tor can be programmed to remove power to the processor core

while I/O power (V_DDRTC, MXEVDD, V_DDEXT) is still supplied.

While in the hibernate state, I/O power is still being applied,

eliminating the need for external buffers. The voltage regulator

can be activated from this power-down state through an RTC

wake-up, a CAN wake-up, an MXVR wake-up, a general-pur-

pose wake-up, or by asserting RESET, all of which will then

initiate a boot sequence. The regulator can also be disabled and

bypassed at the user’s discretion.

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

results in a 25% reduction in dynamic power dissipation, while

reducing the voltage by 25% reduces dynamic power dissipation

by more than 40%. Further, these power savings are additive in

that, if the clock frequency and supply voltage are both reduced,

the power savings can be dramatic.

SET OF DECOUPLING

CAPACITORS

2.25V TO 3.6V

INPUT VOLTAGE

RANGE

V

DDEXT

(LOW-INDUCTANCE)

V

DDEXT

DDINT

+

100µF

10µH

100nF

+

100µF

The dynamic power management feature of the

ADSP-BF539/ADSP-BF539F processors allow both the proces-

sor input voltage (V_DDINT) and clock frequency (f_CCLK) to be

dynamically controlled.

FDS9431A

100µF

10µF

LOW ESR

ZHCS1000

VR

OUT

The savings in power dissipation can be modeled using the

power savings factor and % power savings calculations.

SHORT AND LOW-

INDUCTANCE WIRE

The power savings factor is calculated as

NOTE: DESIGNER SHOULD MINIMIZE

TRACE LENGTH TO FDS9431A.

GND

Power Savings Factor

2

f_CCLKRED

---------------------

f_CCLKNOM

V_DDINTRED

--------------------------

V_DDINTNOM

T_RED

------------

T_NOM

⎛

⎝

⎞

⎠

⎛

⎝

⎞

⎠

=

×

Figure 6. Voltage Regulator Circuit

where

CLOCK SIGNALS

f

_CCLKNOMis the nominal core clock frequency.

_CCLKREDis the reduced core clock frequency.

The ADSP-BF539/ADSP-BF539F processors can be clocked by

an external crystal, a sine wave input, or a buffered, shaped

clock derived from an external clock oscillator.

V

_DDINTNOMis the nominal internal supply voltage.

_DDINTREDis the reduced internal supply voltage.

If an external clock is used, it should be a TTL-compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

T_NOMis the duration running at f_CCLKNOM

T_REDis the duration running at f_CCLKRED

The Power Savings Factor is calculated as

.

Alternatively, because the ADSP-BF539/ADSP-BF539F proces-

sors include an on-chip oscillator circuit, an external crystal can

be used. For fundamental frequency operation, use the circuit

shown in Figure 7 on Page 16. A parallel-resonant, fundamental

frequency, microprocessor-grade crystal is connected across the

CLKIN and XTAL pins. The on-chip resistance between CLKIN

and the XTAL pin is in the 500 kΩ range. Further parallel resis-

tors are typically not recommended. The two capacitors and the

series resistor, shown in Figure 7 on Page 16, fine tune the phase

and amplitude of the sine frequency. The capacitor and resistor

values, shown in Figure 7 on Page 16, are typical values only.

The capacitor values are dependent upon the crystal manufac-

turer’s load capacitance recommendations and the physical PCB

% Power Savings = (1 – Power Savings Factor) × 100%

VOLTAGE REGULATION

The Blackfin processor provides an on-chip voltage regulator

that can generate processor core voltage levels 1.0 V

(–5%/+10%) to 1.20 V (–5%/+10%) and 1.25 V (–4%/+10%)

from an external 2.7 V to 3.6 V supply. For operation below

2.7 V, an external voltage regulator must be used. Figure 6

shows the typical external components required to complete the

power management system.^†The regulator controls the internal

^†See Switching Regulator Design Considerations for ADSP-BF533 Blackfin

Processors (EE-228).

Rev. A

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Page 15 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

layout. The resistor value depends on the drive level specified by

the crystal manufacturer. System designs should verify the cus-

tomized values based on careful investigation on multiple

devices over the allowed temperature range.

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 7 illustrates typical system clock ratios.

Table 7. Example System Clock Ratios

A third-overtone crystal can be used at frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 7.

Signal Name Divider Ratio Example Frequency Ratios (MHz)

SSEL3–0

VCO/SCLK

VCO

100

300

500

SCLK

100

50

0001

0110

1010

1:1

6:1

10:1

50

Blackfin

CLKOUT

The maximum frequency of the system clock is f_SCLK. Note that

the divisor ratio must be chosen to limit the system clock fre-

quency to its maximum of f_SCLK. The SSEL value can be changed

dynamically without any PLL lock latencies by writing the

appropriate values to the PLL divisor register (PLL_DIV).

TO PLL CIRCUITRY

EN

Note that when the SSEL value is changed, it will affect all the

peripherals that derive their clock signals from the SCLK signal.

CLKIN

XTAL

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 8. This programmable core clock capability is useful for

fast core frequency modifications.

FOR OVERTONE

OPERATION ONLY

18pF*

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED

DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE

ANALYZE CAREFULLY.

Table 8. Core Clock Ratios

Signal Name Divider Ratio Example Frequency Ratios

Figure 7. External Crystal Connections

CSEL1–0

VCO/CCLK

VCO

300

500

200

CCLK

300

150

125

25

As shown in Figure 8, the core clock (CCLK) and system

peripheral clock (SCLK) are derived from the input clock

(CLKIN) signal. An on-chip PLL is capable of multiplying the

CLKIN signal by a user programmable 0.5× to 64× multiplica-

tion factor (bounded by specified minimum and maximum

VCO frequencies). The default multiplier is 10×, but it can be

modified by a software instruction sequence. On-the-fly fre-

quency changes can be effected by simply writing to the

PLL_DIV register.

00

01

10

11

1:1

2:1

4:1

8:1

BOOTING MODES

The ADSP-BF539/ADSP-BF539F processors have three mecha-

nisms (listed in Table 9) for automatically loading internal L1

instruction memory after a reset. A fourth mode is provided to

execute from external memory, bypassing the boot sequence.

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

Table 9. Booting Modes

÷ 1, 2, 4, 8

CCLK

SCLK

BMODE1–0 Description

PLL

0.5× TO 64×

CLKIN

00

Execute from 16-bit external memory

(bypass boot ROM)

VCO

÷ 1:15

01

Boot from 8-bit or 16-bit flash or boot from on-chip

flash (ADSP-BF539F only)

SCLK ≤ CCLK

10

11

Boot from SPI serial master connected to SPI0

SCLK ≤ 133MHz

Boot from SPI serial slave EEPROM /flash

(8-,16-, or 24-bit address range, or Atmel

AT45DB041, AT45DB081, or AT45DB161serial flash)

connected to SPI0

Figure 8. Frequency Modification Methods

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

Rev. A

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February 2008

ADSP-BF539/ADSP-BF539F

The BMODE pins of the reset configuration register, sampled

during power-on resets and software initiated resets, implement

the following modes:

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

• Execute from 16-bit external memory – Execution starts

from address 0x2000 0000 with 16-bit packing. The boot

ROM is bypassed in this mode. All configuration settings

are set for the slowest device possible (3-cycle hold time;

15-cycle R/W access times; 4-cycle setup).

• Boot from 8-bit or 16-bit external flash memory – The 8-bit

flash boot routine located in boot ROM memory space is

set up using asynchronous memory bank 0. For

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

ADSP-BF539F processors, if FCE is connected to AMS0,

then the on-chip flash is booted. All configuration settings

are set for the slowest device possible (3-cycle hold time;

15-cycle R/W access times; 4-cycle setup).

• Seamlessly integrated DSP/CPU features are optimized for

both 8-bit and 16-bit operations.

• A multi-issue load/store modified Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU plus

two load/store plus two pointer updates per cycle.

• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit

addressable, or Atmel AT45DB041, AT45DB081, or

AT45DB161) connected to SPI0 – The SPI0 port uses the

PF2 output pin to select a single SPI EEPROM/flash device,

submits a read command and successive address bytes

(0x00) until a valid 8-, 16-, or 24-bit, or Atmel addressable

device is detected, and begins clocking data into the begin-

ning of the L1 instruction memory.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data types; and separate user and

supervisor stack pointers.

• Boot from SPI host device connected to SPI0 – The Black-

fin processor operates in SPI slave mode and is configured

to receive the bytes of the .LDR file from an SPI host (mas-

ter) agent. To hold off the host device from transmitting

while the boot ROM is busy, the Blackfin processor asserts

a GPIO pin, called host wait (HWAIT), to signal the host

device not to send any more bytes until the flag is deas-

serted. The flag is chosen by the user and this information

is transferred to the Blackfin processor via bits 10:5 of the

FLAG header in the .LDR image.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded in

16 bits.

DEVELOPMENT TOOLS

The ADSP-BF539/ADSP-BF539F processors are supported by a

complete set of CROSSCORE^†software and hardware develop-

ment tools, including Analog Devices emulators and

VisualDSP++ development environment. The same emulator

hardware that supports other Blackfin processors also fully

emulates the ADSP-BF539/ADSP-BF539F processor.

For each of the boot modes, a 10-byte header is first read from

an external memory device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks can be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the start of L1 instruction SRAM.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to processor assembly. The processor

has architectural features that improve the efficiency of com-

piled C/C++ code.

In addition, Bit 4 of the reset configuration register can be set by

application code to bypass the normal boot sequence during a

software reset. For this case, the processor jumps directly to the

beginning of L1 instruction memory.

To augment the boot modes, a secondary software loader is pro-

vided that adds additional booting mechanisms. This secondary

loader provides the ability to boot from 16-bit flash memory,

fast flash, variable baud rate, and other sources. In all boot

modes except bypass, program execution starts from on-chip L1

memory address 0xFFA0 0000.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

^†CROSSCORE is a registered trademark of Analog Devices, Inc.

Rev. A

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Page 17 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the processor or external memory with the

drag of the mouse and examine run-time stack and heap usage.

The Expert Linker is fully compatible with existing Linker Defi-

nition File (LDF), allowing the developer to move between the

graphical and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG Test

Access Port of the ADSP-BF539/ADSP-BF539F processors to

monitor and control the target board processor during emula-

tion. The emulator provides full-speed emulation, allowing

inspection and modification of memory, registers, and proces-

sor stacks. Nonintrusive in-circuit emulation is assured by the

use of the processor’s JTAG interface—the emulator does not

affect target system loading or timing.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information).

• Insert breakpoints.

• Set conditional breakpoints on registers, memory,

and stacks.

In addition to the software and hardware development tools

available from Analog Devices third parties provide a wide

range of tools supporting the Blackfin processor family. Hard-

ware tools include Blackfin processor PC plug-in cards. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

• Trace instruction execution.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

DESIGNING AN EMULATOR COMPATIBLE

PROCESSOR BOARD

• Create custom debugger windows.

The VisualDSP++ IDDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all of the Blackfin develop-

ment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

The Analog Devices family of emulators are tools that every sys-

tem developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG processor. The emulator

uses the TAP to access the internal features of the processor,

allowing the developer to load code, set breakpoints, observe

variables, observe memory, and examine registers. The proces-

sor must be halted to send data and commands, but once an

operation has been completed by the emulator, the processor

system is set running at full speed with no impact on

system timing.

• Control how the development tools process inputs and

generate outputs.

• Maintain a one-to-one correspondence with the tool’s

command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see Analog Devices JTAG Emulation Technical Reference

(EE-68) on the Analog Devices web site (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

EXAMPLE CONNECTIONS AND LAYOUT

CONSIDERATIONS

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

Figure 9 shows an example circuit connection of the ADSP-

BF539/ADSP-BF539F to a MOST network. This diagram is

intended as an example, and exact connections and recom-

mended circuit values should be obtained from Analog Devices.

Rev. A

|

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February 2008

ADSP-BF539/ADSP-BF539F

5V

5

V

MOST FOT

VDDINT (1.25V)

FB

Rx_Vdd

ADSP-BF539F

Tx_Vdd

MTXON

POWER GATING CIRCUIT

MPIVDD

MOST

276

NETWORK

TX_Data

RX_Data

Status

MTX

0.1MF

MF

0.01

MRX

MXEGND

MRXON

49.152MHz OSCILLATOR

CLKO

MXI

MXO

MLF

RFS0

MFS

33

6

AUDIO DAC

L/RCLK

MCLK

336

MMCLK

MBCLK

R1

220 6

AUDIO

C2

CHANNELS

BCLK

MF

0.01

TSCLK0

RSCLK0

C1

0.1

MF

MXEGND

DT0PRI

SDATA

Figure 9. Example Connections of ADSP-BF539/ADSP-BF539F to MOST Network

MXI/MXO with external crystal

MXVR BOARD LAYOUT GUIDELINES

MLF pin

• The crystal must be a 49.152 MHz or 45.1584 MHz funda-

mental mode crystal.

• Capacitors:

• The crystal and load capacitors should be placed physically

close to the MXI and MXO pins on the board.

C1: 0.1 μF (PPS type, 2% tolerance recommended)

C2: 0.01 μF (PPS type, 2% tolerance recommended)

• Resistor:

• The load capacitors should be grounded to MXEGND.

• The crystal and load capacitors should be wired up using

wide traces.

R1: 220 Ω (1% tolerance)

• The RC network connected to the MLF pin should be

located physically close to the MLF pin on the board.

• Board trace capacitance on each lead should not be more

than 3 pF.

• The RC network should be wired up and connected to the

MLF pin using wide traces.

• Trace capacitance plus load capacitance should equal the

load capacitance specification for the crystal.

• The capacitors in the RC network should be grounded to

MXEGND.

• Avoid routing other switching signals near the crystal and

components to avoid crosstalk. When not possible, shield

traces and components with ground.

•

The RC network should be shielded using MXEGND

traces.

MXEGND–MXVR crystal oscillator and MXVR PLL ground

• Should be routed with wide traces or as ground plane.

• Avoid routing other switching signals near the RC network

to avoid crosstalk.

• Should be tied together to other board grounds at only one

point on the board.

MXI driven with external clock oscillator IC (recommended)

• MXI should be driven with the clock output of a

49.152 MHz or 45.1584 MHz clock oscillator IC.

• Avoid routing other switching signals near to MXEGND to

avoid crosstalk.

• MXO should be left unconnected.

MXEVDD–MXVR crystal oscillator 3.3 V power

• Avoid routing other switching signals near the oscillator

and clock output trace to avoid crosstalk. When not possi-

ble, shield traces with ground.

• Should be routed with wide traces or as power plane.

• Locally bypass MXEVDD with 0.1 μF and 0.01 μF decou-

pling capacitors to MXEGND.

• Avoid routing other switching signals near to MXEVDD to

avoid crosstalk.

Rev. A

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ADSP-BF539/ADSP-BF539F

MPIVDD–MXVR PLL 1.25 V power

• Should be routed with wide traces or as power plane.

• A ferrite bead should be placed between the 1.25 V V_DDINT

power plane and the MPIVDD pin for noise isolation.

• Locally bypass MPIVDD with 0.1 μF and 0.01 μF decou-

pling capacitors to MXEGND.

• Avoid routing other switching signals near to MPIVDD to

avoid crosstalk.

Fiber optic transceiver (FOT) connections

• The traces between the ADSP-BF539/ADSP-BF539F pro-

cessor and the FOT should be kept as short as possible.

• The receive data trace connecting the FOT receive data

output pin to the ADSP-BF539/ADSP-BF539F MRX input

pin should not have a series termination resistor. The edge

rate of the FOT receive data signal driven by the FOT is

typically very slow, and further degradation of the edge rate

is not desirable.

• The transmit data trace connecting the

ADSP-BF539/ADSP-BF539F MTX output pin to the FOT

Transmit Data input pin should have a 27 Ω series termi-

nation resistor placed close to the ADSP-BF539/ADSP-

BF539F MTX pin.

• The receive data trace and the transmit data trace between

the ADSP-BF539/ADSP-BF539F processor and the FOT

should not be routed close to each other in parallel over

long distances to avoid crosstalk.

VOLTAGE REGULATOR LAYOUT GUIDELINES

Regulator external component placement, board routing, and

bypass capacitors all have a significant effect on noise injected

into the other analog circuits on-chip. The VROUT1-0 traces

and voltage regulator external components should be consid-

ered as noise sources when doing board layout and should not

be routed or placed near sensitive circuits or components on the

board. All internal and I/O power supplies should be well

bypassed with bypass capacitors placed as close to the ADSP-

BF539/ADSP-BF539F as possible.

For further details on the on-chip voltage regulator and related

board design guidelines, see the Switching Regulator Design

Considerations for ADSP-BF533 Blackfin Processors (EE-228)

applications note on the Analog Devices website

(www.analog.com)—use site search on “EE-228”.

Rev. A

|

Page 20 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

PIN DESCRIPTIONS

ADSP-BF539/ADSP-BF539F processor pin definitions are listed

in Table 10.

exception of the pins that need pull-ups or pull-downs, as noted

in the table.

All pins are three-stated during and immediately after reset,

except the memory interface, asynchronous memory control,

and synchronous memory control pins, which are driven high.

If BR is active, then the memory pins are also three-stated. All

unused I/O pins have their input buffers disabled with the

In order to maintain maximum functionality and reduce pack-

age size and pin count, some pins have dual, multiplexed

functionality. In cases where pin functionality is reconfigurable,

the default state is shown in plain text, while alternate function-

ality is shown in italics.

Table 10. Pin Descriptions

Driver

Type¹

Pin Name

Type Description

Memory Interface

ADDR19–1

O

Address Bus for Async/Sync Access

Data Bus for Async/Sync Access

A

DATA15–0

I/O

O

I

ABE1–0/SDQM1–0

Byte Enables/Data Masks for Async/Sync Access

Bus Request. (This pin should be pulled high when not used.)

Bus Grant

BR

BG

O

A

BGH

Bus Grant Hang

Asynchronous Memory Control

AMS3–0

ARDY

O

I

Bank Select

A

Hardware Ready Control (This pin should always be pulled low when not used.)

AOE

O

Output Enable

Read Enable

Write Enable

A

ARE

AWE

Flash Control

FCE

I

Flash Enable (This pin should be left unconnected or pulled low for the

ADSP-BF539.)

FRESET

Flash Reset (This pin should be left unconnected or pulled low for the

ADSP-BF539.)

Synchronous Memory Control

SRAS

SCAS

O

Row Address Strobe

Column Address Strobe

Write Enable

A

B

SWE

SCKE

Clock Enable

CLKOUT

SA10

Clock Output

A10 Pin

A

SMS

Bank Select

Timers

TMR0

I/O

Timer 0

C

TMR1/PPI_FS1

TMR2/PPI_FS2

Timer 1/PPI Frame Sync1

Timer 2/PPI Frame Sync2

Rev. A

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Page 21 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

Table 10. Pin Descriptions (Continued)

Driver

Type¹

Pin Name

Type Description

Parallel Peripheral Interface Port/GPIO

PF0/SPI0SS

I/O

I

Programmable Flag 0/SPI0 Slave Select Input

Programmable Flag 1/SPI0 Slave Select Enable 1/Timer Alternate Clock

Programmable Flag 2/SPI0 Slave Select Enable 2

Programmable Flag 3/SPI0 Slave Select Enable 3/PPI Frame Sync 3

Programmable Flag 4/SPI0 Slave Select Enable 4/PPI 15

Programmable Flag 5/SPI0 Slave Select Enable 5/PPI 14

Programmable Flag 6/SPI0 Slave Select Enable 6/PPI 13

Programmable Flag 7/SPI0 Slave Select Enable 7/PPI 12

Programmable Flag 8/PPI 11

C

PF1/SPI0SEL1/TACLK

PF2/SPI0SEL2

PF3/SPI0SEL3/PPI_FS3

PF4/SPI0SEL4/PPI15

PF5/SPI0SEL5/PPI14

PF6/SPI0SEL6/PPI13

PF7/SPI0SEL7/PPI12

PF8/PPI11

PF9/PPI10

Programmable Flag 9/PPI 10

PF10/PPI9

Programmable Flag 10/PPI 9

PF11/PPI8

Programmable Flag 11/PPI 8

PF12/PPI7

Programmable Flag 12/PPI 7

PF13/PPI6

Programmable Flag 13/PPI 6

PF14/PPI5

Programmable Flag 14/PPI 5

PF15/PPI4

Programmable Flag 15/PPI 4

PPI3–0

PPI_CLK/TMRCLK

Controller Area Network

CANTX/PC0

PPI Clock/External Timer Reference

I/O 5 V CAN Transmit/GPIO

C

CANRX/PC1

I/OD CAN Receive/GPIO

C²

5 V

Media Transceiver (MXVR)/

General-Purpose I/O

MTX/PC5

I/O

MXVR Transmit Data/GPIO

MXVR Transmit FOT On/GPIO

C

MTXON/PC9

MRX/PC4

C

C²

I /OD MXVR Receive Data/GPIO (This pin should be pulled low when not used.)

5 V

MRXON

MXI

I 5 V MXVR FOT Receive On (This pin should be pulled high when not used.)

C

I

MXVR Crystal Input (This pin should be pulled low when not used.)

MXO

O

MXVR Crystal Output (This pin should be left unconnected when not used.)

MLF

A I/O MXVR Loop Filter (This pin should be pulled low when not used.)

MMCLK/PC6

MBCLK/PC7

MFS/PC8

GP

I/O

I

MXVR Master Clock/GPIO

C

MXVR Bit Clock/GPIO

MXVR Frame Sync/GPIO

GPIO PC4–9 Enable (This pin should be pulled low when MXVR is used.)

Rev. A

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Page 22 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

Table 10. Pin Descriptions (Continued)

Driver

Type¹

Pin Name

Type Description

These pins are open-drain and require a pull-up resistor. See version 2.1 of

the I²C specification for proper resistor values.

I/O 5 V TWI0 Serial Data

2-Wire Interface Ports

SDA0

SCL0

E

I/O 5 V TWI0 Serial Clock

I/O 5 V TWI1 Serial Data

I/O 5 V TWI1 Serial Clock

SDA1

SCL1

Serial Port0

RSCLK0

RFS0

I/O

I

SPORT0 Receive Serial Clock

D

C

SPORT0 Receive Frame Sync

SPORT0 Receive Data Primary

SPORT0 Receive Data Secondary

SPORT0 Transmit Serial Clock

SPORT0 Transmit Frame Sync

SPORT0 Transmit Data Primary

SPORT0 Transmit Data Secondary

DR0PRI

DR0SEC

TSCLK0

I

I/O

O

D

C

TFS0

DT0PRI

DT0SEC

Serial Port1

RSCLK1

RFS1

O

I/O

I

SPORT1 Receive Serial Clock

SPORT1 Receive Frame Sync

SPORT1 Receive Data Primary

SPORT1 Receive Data Secondary

SPORT1 Transmit Serial Clock

SPORT1 Transmit Frame Sync

SPORT1 Transmit Data Primary

SPORT1 Transmit Data Secondary

D

C

DR1PRI

DR1SEC

TSCLK1

I

I/O

O

D

C

TFS1

DT1PRI

DT1SEC

Serial Port2

RSCLK2/PE0

RFS2/PE1

DR2PRI/PE2

DR2SEC/PE3

TSCLK2/PE4

TFS2/PE5

DT2PRI /PE6

DT2SEC/PE7

O

I/O

SPORT2 Receive Serial Clock/GPIO

SPORT2 Receive Frame Sync/GPIO

SPORT2 Receive Data Primary/GPIO

SPORT2 Receive Data Secondary/GPIO

SPORT2 Transmit Serial Clock/GPIO

SPORT2 Transmit Frame Sync/GPIO

SPORT2 Transmit Data Primary/GPIO

SPORT2 Transmit Data Secondary/GPIO

D

C

D

C

Rev. A

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Page 23 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

Table 10. Pin Descriptions (Continued)

Driver

Type¹

Pin Name

Serial Port3

RSCLK3/PE8

RFS3/PE9

Type Description

I/O

SPORT3 Receive Serial Clock/GPIO

SPORT3 Receive Frame Sync/GPIO

SPORT3 Receive Data Primary/GPIO

SPORT3 Receive Data Secondary/GPIO

SPORT3 Transmit Serial Clock/GPIO

SPORT3 Transmit Frame Sync/GPIO

SPORT3 Transmit Data Primary/GPIO

SPORT3 Transmit Data Secondary/GPIO

D

C

D

C

DR3PRI/PE10

DR3SEC/PE11

TSCLK3/PE12

TFS3/PE13

DT3PRI /PE14

DT3SEC/PE15

SPI0 Port

MOSI0

I/O

SPI0 Master Out Slave In

C

MISO0

SPI0 Master In Slave Out (This pin should always be pulled high through a 4.7 kΩ C

resistor if booting via the SPI port.)

SCK0

I/O

SPI0 Clock

D

SPI1 Port

MOSI1/PD0

MISO1/PD1

SCK1/PD2

SPI1SS/PD3

SPI1SEL1/PD4

SPI2 Port

I/O

SPI1 Master Out Slave In/GPIO

SPI1 Master In Slave Out/GPIO

SPI1 Clock/GPIO

C

D

SPI1 Slave Select Input/GPIO

SPI1 Slave Select Enable/GPIO

MOSI2 /PD5

MISO2/PD6

SCK2/PD7

SPI2SS/PD8

SPI2SEL1/PD9

UART0 Port

RX0

I/O

SPI2 Master Out Slave In/GPIO

SPI2 Master In Slave Out/GPIO

SPI2 Clock/GPIO

C

D

SPI2 Slave Select Input/GPIO

SPI2 Slave Select Enable/GPIO

I

UART Receive

UART Transmit

TX0

O

C

UART1 Port

RX1/PD10

TX1/PD11

UART2 Port

RX2 /PD12

TX2/PD13

Real-Time Clock

RTXI

I/O

UART1 Receive/GPIO

UART1 Transmit/GPIO

D

I/O

UART2 Receive/GPIO

UART2 Transmit/GPIO

D

I

RTC Crystal Input (This pin should be pulled low when not used.)

RTC Crystal Output

RTXO

O

Rev. A

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Page 24 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

Table 10. Pin Descriptions (Continued)

Driver

Type¹

Pin Name

JTAG Port

TCK

Type Description

I

JTAG Clock

TDO

O

I

JTAG Serial Data Out

JTAG Serial Data In

JTAG Mode Select

C

TDI

TMS

I

TRST

I

JTAG Reset (This pin should be pulled low if the JTAG port will not be used.)

Emulation Output

EMU

O

C

Clock

CLKIN

I

Clock/Crystal Input

Crystal Output

XTAL

O

Mode Controls

RESET

I

Reset

NMI

Nonmaskable Interrupt (This pin should be pulled high when not used.)

Boot Mode Strap

BMODE1–0

Voltage Regulator

VROUT0

VROUT1

Supplies

VDDEXT

VDDINT

VDDRTC

MPIVDD

MXEVDD

MXEGND

GND

O

External FET Drive 0 (This pin should be left unconnected when not used.)

External FET Drive 1 (This pin should be left unconnected when not used.)

P

G

I/O Power Supply

Internal Power Supply

Real-Time Clock Power Supply

MXVR Internal Power Supply

MXVR External Power Supply

MXVR Ground

Ground

¹Refer to Figure 30 on Page 50 to Figure 39 on Page 51.

²This pin is 5V-tolerant when configured as an input and an open-drain when configured as an output; therefore, only the VOL curves in Figure 34 on Page 50 and

Figure 35 on Page 50 and the Fall Time curves in Figure 47 on Page 53 and Figure 48 on Page 54 apply when configured as an output.

Rev. A

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Page 25 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

SPECIFICATIONS

Component specifications are subject to change

without notice.

OPERATING CONDITIONS

Parameter

Conditions

Min

0.95

2.7

Nom

1.25

3.3

Max

1.37

3.6

Unit

V_DDINTInternal Supply Voltage^{1, 2}

V_DDEXTExternal Supply Voltage³

V

V_DDRTCReal-Time Clock Power Supply

Voltage

2.7

3.3

3.6

V_IH

High Level Input Voltage⁴

High Level Input Voltage⁵

@ V_DDEXT= Maximum

@ V_DDEXT= Minimum

2.0

3.6

V

V_IH5V

2.0

5.5

V

V_IHCLKINHigh Level Input Voltage⁶

2.2

3.6

V

V_IL

Low Level Input Voltage^{4, 7}

Low Level Input Voltage⁵

Junction Temperature

–0.3

+0.6

+0.8

+105

V

V_IL5V

T_J

V

316-Ball Chip Scale Ball Grid Array (CSP_BGA) 533 MHz –40

@ T_AMBIENT= –40°C to +85°C

°C

¹Parameter value applies also to MPIVDD.

²The regulator can generate V_DDINTat levels of 1.0 V to 1.2 V with –5% to +10% tolerance and 1.25 V with -4% to +10% tolerance.

³Parameter value applies also to MXEVDD.

⁴The 3.3 V tolerant pins are capable of accepting up to 3.6 V maximum V_IHThe following bidirectional pins are 3.3 V tolerant: DATA15–0, SCK2–0, MISO2–0, MOSI2–0,

PF15–0, PPI3–0, MTXON, MMCLK, MBCLK, MFS, MTX, SPI1SS, SPI1SEL1, SPI2SS, SPI2SEL1, RX2–1, TX2–1, DT2PRI, DT2SEC, TSCLK3–0, DR2PRI, DR2SEC, DT3PRI,

DT3SEC, RSCLK3–0, TFS3–0, RFS3–0, DR3PRI, DR3SEC, and TMR2–0. The following input-only pins are 3.3 V tolerant: RESET, RX0, TCK, TDI, TMS, TRST, ARDY,

BMODE1–0, BR, DR0PRI, DR0SEC, DR1PRI, DR1SEC, NMI, PPI_CLK, RTXI, and GP.

⁵The 5 V tolerant pins are capable of accepting up to 5.5 V maximum V_IH. The following bidirectional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1, and CANTX. The

following input-only pins are 5 V tolerant: CANRX, MRX, MRXON.

⁶Parameter value applies to the CLKIN and MXI input pins.

⁷Parameter value applies to all input and bidirectional pins.

Rev. A

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Page 26 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

ELECTRICAL CHARACTERISTICS

Parameter¹

Test Conditions

Min

Typ

Max

Unit

V

V_OH

High Level Output Voltage²

Low Level Output Voltage²

High Level Input Current³

High Level Input Current JTAG⁴

Low Level Input Current³

Three-State Leakage Current⁵

Input Capacitance^{6, 7}

@ V_DDEXT= +3.0 V, I_OH= –0.5 mA

@ V_DDEXT= 3.0 V, I_OL= 2.0 mA

2.4

V_OL

0.4

V

I_IH

@ V_DDEXT= Maximum, V_IN= V_DDMaximum

@ V_DDEXT= Maximum, V_IN= 0 V

10.0

50.0

10.0

8

μA

pF

μA

I_IHP

I_IL

I_OZH

@ V_DDEXT= Maximum, V_IN= V_DDMaximum

@ V_DDEXT= Maximum, V_IN= 0 V

I_OZL

C_IN

f_CCLK= 1 MHz, T_AMBIENT= 25°C, V_IN= 2.5 V

4

I_DDIHIBERNATE

V_DDINTCurrent in Hibernate State

V_DDEXT= 3.65 V with Voltage Regulator Off

(V_DDINT= 0 V)

50

8

I_DDDEEPSLEEP

I_DDSLEEP

V_DDINTCurrent in Deep Sleep Mode V_DDINT= 0.95 V, T_JUNCTION= 25°C

28

32

mA

μA

V_DDINTCurrent in Sleep Mode

V_DDINT= 0.95 V, T_JUNCTION= 25°C @ f_SCLK= 50 MHz

8, 9

I_{DD_TYP}

V_DDINTCurrent Dissipation (Typical) V_DDINT= 0.95 V, f_CCLK= 50 MHz, T_JUNCTION= 25°C

V_DDINTCurrent Dissipation (Typical) V_DDINT= 1.2 V, f_CCLK= 533 MHz, T_JUNCTION= 25°C

47

8, 9

I_{DD_TYP}

227

20

I_DDRTC

V_DDRTCCurrent

V_DDRTC= 3.3 V, T_JUNCTION= 25°C

¹Specifications subject to change without notice.

²Applies to output and bidirectional pins.

³Applies to input pins except JTAG inputs.

⁴Applies to JTAG input pins (TCK, TDI, TMS, TRST).

⁵Applies to three-statable pins.

⁶Applies to all signal pins.

⁷Guaranteed, but not tested.

⁸See Power Dissipation on Page 52.

⁹Processor executing 75% dual MAC, 25% ADD with moderate data bus activity.

Rev. A

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Page 27 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in the table may cause perma-

nent damage to the device. These are stress ratings only.

Functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

PACKAGE INFORMATION

The information presented in Figure 10 and Table 12 provides

information about how to read the package brand and relate it

to specific product features. For a complete listing of product

offerings, see the Ordering Guide on Page 60.

Parameter

Rating

a

ADSP-BF539

1

Internal (Core) Supply Voltage (V_DDINT

)

2

–0.3 V to +1.4 V

–0.3 V to +3.8 V

–0.5 V to +3.6 V

–0.5 V to +5.5 V

–0.5 V to V_DDEXT+ 0.5 V

200 pF

tppZccc

vvvvvv.x n.n

External (I/O) Supply Voltage (V_DDEXT

Input Voltage^{3, 4}

Input Voltage^{4, 5}

)

yyww country_of_origin

B

Output Voltage Swing

Load Capacitance⁶

Figure 10. Product Information on Package

Junction Temperature Under Bias

Storage Temperature Range

¹Parameter value applies also to MPIVDD.

+125°C

Table 12. Package Brand Information

–65°C to +150°C

Brand Key

Field Description

Automotive Grade (Optional)

Temperature Range

Package Type

²Parameter value applies also to MXEVDD and VDDRTC.

³Applies to 100% transient duty cycle. For other duty cycles, see Table 11.

⁴Applies only when V_DDEXTis within specifications. When V_DDEXTis outside speci-

fications, the range is V_DDEXTꢁ 0.2 V.

W

t

⁵Applies to pins designated as 5 V tolerant only.

pp

⁶For proper SDRAM controller operation, the maximum load capacitance is 50 pF

forADDR19–1,DATA15–0, ABE1–0/SDQM1–0, CLKOUT, SCKE, SA10, SRAS,

SCAS, SWE, and SMS.

Z

RoHS Compliant Part

See Ordering Guide

Assembly Lot Code

Silicon Revision

ccc

Table 11. Maximum Duty Cycle for Input Transient Voltage¹

vvvvvv.x

n.n

V_INMin (V)

–0.50

V_INMax (V)²

+3.80

Maximum Duty Cycle

yyww

Date Code

100%

40%

25%

15%

10%

–0.70

+4.00

–0.80

+4.10

–0.90

+4.20

–1.00

+4.30

¹Applies to all signal pins with the exception of CLKIN, MXI, MXO, MLF,

VROUT1–0, XTAL, RTXI, and RTXO

²Only one of the listed options can apply to a particular design.

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary circuitry, damage may occur

on devices subjected to high energy ESD. Therefore,

proper ESD precautions should be take to avoid

performance degradation or loss of functionality.

Rev. A

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Page 28 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

TIMING SPECIFICATIONS

Table 13 describes the timing requirements for the

oscillator (VCO) operating frequencies, as described in Abso-

lute Maximum Ratings on Page 28. Table 14 describes phase-

locked loop operating conditions. Table 15 lists system clock

requirements.

ADSP-BF539/ADSP-BF539F processor clocks. Take care in

selecting MSEL, SSEL, and CSEL ratios so as not to exceed the

maximum core clock, system clock, and voltage-controlled

Table 13. Core Clock (CCLK) Requirements

Internal Regulator

Setting

1.25 V

1.20 V

1.10 V

1.00 V

Parameter Description

Max

533

500

444

400

Unit

MHz

f_CCLK

CLK Frequency (V_DDINT= 1.2 V Minimum)

CLK Frequency (V_DDINT= 1.14 V Minimum)

CLK Frequency (V_DDINT= 1.045 V Minimum)

CLK Frequency (V_DDINT= 0.95 V Minimum)

Table 14. Phase-Locked Loop Operating Conditions

Parameter Description

Min

Max

Unit

f_VCO

Voltage Controlled Oscillator (VCO) Frequency

50

Max f_CCLK

MHz

Table 15. System Clock (SCLK) Requirements

Parameter¹Description

Max

133²

100

Unit

MHz

f_SCLK

CLKOUT/SCLK Frequency (V_DDINT≥ 1.14 V)

CLKOUT/SCLK Frequency (V_DDINT< 1.14 V)

f_SCLK

¹t_SCLK(= 1/f_SCLK) must be greater than or equal to t_CCLK

²Guaranteed to t_SCLK= 7.5 ns. See Table 21 on Page 35.

Rev. A

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Page 29 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

Clock and Reset Timing

Table 16 and Figure 11 describe clock and reset operations. Per

Absolute Maximum Ratings on Page 28, combinations of

CLKIN and clock multipliers must not select core/peripheral

clocks that exceed maximum operating conditions.

Table 16. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

t_CKIN

CLKIN Period^{1, 2, 3}

20.0

8.0

100.0

ns

t_CKINL

t_CKINH

t_WRST

CLKIN Low Pulse

CLKIN High Pulse

RESET Asserted Pulse Width Low⁴

8.0

11 t_CKIN

¹Applies to PLL bypass mode and PLL non-bypass mode.

²If the DF bit in the PLL_CTL register is set, then the maximum t_CKINperiod is 50 ns.

³CLKIN frequency must not change on the fly.

⁴Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,

assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).

t_CKIN

CLKIN

t_CKINL

t_CKINH

t_WRST

RESET

Figure 11. Clock and Reset Timing

Rev. A

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Page 30 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

Asynchronous Memory Read Cycle Timing

Table 17 and Table 18 on Page 32 and Figure 12 and Figure 13

on Page 32 describe asynchronous memory read cycle opera-

tions for synchronous and for asynchronous ARDY.

Table 17. Asynchronous Memory Read Cycle Timing with Synchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_SDAT

t_HDAT

t_SARDY

t_HARDY

t_DO

DATA15–0 Setup Before CLKOUT

DATA15–0 Hold After CLKOUT

2.1

0.8

4.0

0.0

ns

ARDY Setup Before the Falling Edge of CLKOUT

ARDY Hold After the Falling Edge of CLKOUT

Output Delay After CLKOUT¹

6.0

t_HO

Output Hold After CLKOUT¹

0.8

¹Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

HOLD

1 CYCLE

SETUP

2 CYCLES

PROGRAMMED READ ACCESS

4 CYCLES

ACCESS EXTENDED

3 CYCLES

CLKOUT

t_DO

t_HO

AMSx

ABE1–0

BE, ADDRESS

ADDR19–1

AOE

t_DO

t_HO

ARE

t_HARDY

t_SARDY

t_HARDY

ARDY

t_SARDY

t_SDAT

t_HDAT

DATA15–0

READ

Figure 12. Asynchronous Memory Read Cycle Timing with Synchronous ARDY

Rev. A

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Page 31 of 60

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February 2008

ADSP-BF539/ADSP-BF539F

Table 18. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_SDAT

t_HDAT

t_DANR

t_HAA

t_DO

DATA15–0 Setup Before CLKOUT

DATA15–0 Hold After CLKOUT

ARDY Negated Delay from AMSx Asserted¹

ARDY Asserted Hold After ARE Negated

Output Delay After CLKOUT²

2.1

0.8

ns

(S+RA–2) ꢀ t_SCLK

0.0

0.8

6.0

t_HO

Output Hold After CLKOUT²

¹S = number of programmed setup cycles, RA = number of programmed read access cycles.

²Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

HOLD

1 CYCLE

SETUP

2 CYCLES

PROGRAMMED READ ACCESS

4 CYCLES

ACCESS EXTENDED

CLKOUT

t_DO

t_HO

AMSx

ABE1–0

BE, ADDRESS

ADDR19–1

AOE

t_DO

t_HO

ARE

t_HAA

t_DANR

ARDY

t_SDAT

t_HDAT

DATA15–0

READ

Figure 13. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY

Rev. A

|

Page 32 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Asynchronous Memory Write Cycle Timing

Table 19 and Table 20 on Page 34 and Figure 14 and Figure 15

on Page 34 describe asynchronous memory write cycle opera-

tions for synchronous and for asynchronous ARDY.

Table 19. Asynchronous Memory Write Cycle Timing with Synchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_SARDY

t_HARDY

ARDY Setup Before the Falling Edge of CLKOUT

ARDY Hold After the Falling Edge of CLKOUT

4.0

0.0

ns

Switching Characteristics

t_DDAT

t_ENDAT

t_DO

DATA15–0 Disable After CLKOUT

6.0

ns

DATA15–0 Enable After CLKOUT

Output Delay After CLKOUT¹

Output Hold After CLKOUT¹

1.0

0.8

t_HO

¹Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.

ACCESS

EXTENDED

1 CYCLE

SETUP

2 CYCLES

HOLD

1 CYCLE

PROGRAMMED WRITE

ACCESS 2 CYCLES

CLKOUT

AMSx

t_DO

t_HO

ABE1–0

BE, ADDRESS

ADDR19–1

t_DO

t_HO

AWE

t_SARDY

ARDY

t_SARDY

t_HARDY

t_DDAT

t_ENDAT

DATA15–0

WRITE DATA

Figure 14. Asynchronous Memory Write Cycle Timing with Synchronous ARDY

Rev. A

|

Page 33 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Table 20. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_DANR

t_HAA

Switching Characteristics

ARDY Negated Delay from AMSx Asserted¹

ARDY Asserted Hold After ARE Negated

(S+WA–2) ꢀ t_SCLKns

0.0

ns

t_DDAT

t_ENDAT

t_DO

DATA15–0 Disable After CLKOUT

6.0

ns

DATA15–0 Enable After CLKOUT

Output Delay After CLKOUT²

Output Hold After CLKOUT²

1.0

0.8

t_HO

¹S = Number of programmed setup cycles, WA = Number of programmed write access cycles.

²Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.

ACCESS

EXTENDED

SETUP

2 CYCLES

HOLD

1 CYCLE

PROGRAMMED WRITE

ACCESS 2 CYCLES

CLKOUT

AMSx

t_DO

t_HO

ABE1–0

BE, ADDRESS

ADDR19–1

t_DO

t_HO

AWE

t_DANW

t_HAA

ARDY

t_ENDAT

DATA15–0

WRITE DATA

Figure 15. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY

Rev. A

|

Page 34 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

SDRAM Interface Timing

Table 21. SDRAM Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSDAT

t_HSDAT

DATA Setup Before CLKOUT

DATA Hold After CLKOUT

2.1

0.8

ns

Switching Characteristics

t_SCLK

CLKOUT Period¹

7.5

2.5

ns

t_SCLKH

t_SCLKL

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

CLKOUT Width High

CLKOUT Width Low

Command, ADDR, Data Delay After CLKOUT²

Command, ADDR, Data Hold After CLKOUT²

Data Disable After CLKOUT

Data Enable After CLKOUT

6.0

0.8

1.0

¹SDRAM timing for T_JUNCTION= 125°C is limited to 100 MHz.

²Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

t_SCLK

t_SCLKH

CLKOUT

t_SSDAT

t_SCLKL

t_HSDAT

DATA (IN)

t_DCAD

t_DSDAT

t_ENSDAT

t_HCAD

DATA(OUT)

t_DCAD

CMND ADDR

(OUT)

t_HCAD

NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Figure 16. SDRAM Interface Timing

Rev. A

|

Page 35 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

External Port Bus Request and Grant Cycle Timing

Table 22 and Table 23 on Page 37 and Figure 17 and Figure 18

on Page 37 describe external port bus request and grant cycle

operations for synchronous and for asynchronous BR.

Table 22. External Port Bus Request and Grant Cycle Timing with Synchronous BR

Parameter

Min

Max

Unit

Timing Requirements

t_BS

t_BH

BR Setup to Falling Edge of CLKOUT

4.0

0.0

ns

Falling Edge of CLKOUT to BR Deasserted Hold Time

Switching Characteristics

t_SD

CLKOUT Low to AMSx, Address, and ARE/AWE Disable

4.5

3.6

ns

t_SE

CLKOUT Low to AMSx, Address, and ARE/AWE Enable

CLKOUT High to BG High Setup

t_DBG

t_EBG

t_DBH

t_EBH

CLKOUT High to BG Deasserted Hold Time

CLKOUT High to BGH High Setup

CLKOUT High to BGH Deasserted Hold Time

CLKOUT

t_BH

t_BS

BR

t_SD

t_SE

AMSx

t_SD

t_SE

ADDR19-1

ABE1-0

t_SD

t_SE

AWE

ARE

t_DBG

t_EBG

BG

t_DBH

t_EBH

BGH

Figure 17. External Port Bus Request and Grant Cycle Timing with Synchronous BR

Rev. A

|

Page 36 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Table 23. External Port Bus Request and Grant Cycle Timing with Asynchronous BR

Parameter

Min

Max

Unit

Timing Requirement

t_WBR

BR Pulse Width

2 ꢀ t_SCLK

ns

Switching Characteristics

t_SD

CLKOUT Low to AMSx, Address, and ARE/AWE Disable

4.5

3.6

ns

t_SE

CLKOUT Low to AMSx, Address, and ARE/AWE Enable

CLKOUT High to BG High Setup

t_DBG

t_EBG

t_DBH

t_EBH

CLKOUT High to BG Deasserted Hold Time

CLKOUT High to BGH High Setup

CLKOUT High to BGH Deasserted Hold Time

CLKOUT

t_WBR

BR

t_SD

t_SE

AMSx

t_SD

t_SE

ADDR19-1

ABE1-0

t_SD

t_SE

AWE

ARE

t_DBG

t_EBG

BG

t_DBH

t_EBH

BGH

Figure 18. External Port Bus Request and Grant Cycle Timing with Asynchronous BR

Rev. A

|

Page 37 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Parallel Peripheral Interface Timing

Table 24 and Figure 19, Figure 20, Figure 21, and Figure 22

describe Parallel Peripheral Interface operations.

Table 24. Parallel Peripheral Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

t_PCLKW

t_PCLK

PPI_CLK Width

PPI_CLK Period¹

6.0

15.0

5.0

1.0

2.0

4.0

ns

t_SFSPE

t_HFSPE

t_SDRPE

t_HDRPE

External Frame Sync Setup Before PPI_CLK

External Frame Sync Hold After PPI_CLK

Receive Data Setup Before PPI_CLK

Receive Data Hold After PPI_CLK

Switching Characteristics—GP Output and Frame Capture Modes

t_DFSPE

t_HOFSPE

t_DDTPE

t_HDTPE

Internal Frame Sync Delay After PPI_CLK

Internal Frame Sync Hold After PPI_CLK

Transmit Data Delay After PPI_CLK

Transmit Data Hold After PPI_CLK

10.0

ns

0.0

¹PPI_CLK frequency cannot exceed f_SCLK/2

FRAME

SYNC IS

DRIVEN

OUT

DATA0

IS

SAMPLED

POLC = 0

PPI_CLK

POLC = 1

t

DFSPE

t

HOFSPE

POLS = 1

PPI_FS1

POLS = 0

POLS = 1

PPI_FS2

POLS = 0

t

SDRPE

HDRPE

PPI_DATA

Figure 19. PPI GP Rx Mode with Internal Frame Sync Timing

Rev. A

|

Page 38 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

FRAME

SYNC IS

SAMPLED

FOR

DATA0 IS

DATA1 IS

SAMPLED

DATA0

SAMPLED

PPI_CLK

POLC = 0

PPI_CLK

POLC = 1

t

HFSPE

t

SFSPE

POLS = 1

POLS = 0

PPI_FS1

POLS = 1

POLS = 0

PPI_FS2

t

SDRPE

HDRPE

PPI_DATA

Figure 20. PPI GP Rx Mode with External Frame Sync Timing

FRAME

SYNC IS

SAMPLED

DATA0 IS

DRIVEN

OUT

PPI_CLK

POLC = 0

PPI_CLK

POLC = 1

t

HFSPE

t

SFSPE

POLS = 1

POLS = 0

PPI_FS1

POLS = 1

POLS = 0

PPI_FS2

t

HDTPE

PPI_DATA

DATA0

t

DDTPE

Figure 21. PPI GP Tx Mode with External Frame Sync Timing

Rev. A

|

Page 39 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

FRAME

SYNC IS

DRIVEN

OUT

DATA0 IS

DRIVEN

OUT

PPI_CLK

POLC = 0

PPI_CLK

POLC = 1

t

DFSPE

t

HOFSPE

POLS = 1

PPI_FS1

POLS = 0

POLS = 1

PPI_FS2

POLS = 0

t

DDTPE

t

HDTPE

PPI_DATA

DATA0

Figure 22. PPI GP Tx Mode with Internal Frame Sync Timing

Rev. A

|

Page 40 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Serial Ports Timing

Table 25 through Table 28 on Page 42 and Figure 23 on Page 42

through Figure 24 on Page 43 describe Serial Port operations.

Table 25. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSE

TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)¹

3.0

4.5

15.0

ns

t_HFSE

TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)¹

Receive Data Setup Before RSCLKx¹

Receive Data Hold After RSCLKx¹

t_SDRE

t_HDRE

t_SCLKEW

t_SCLKE

TSCLKx/RSCLKx Width

TSCLKx/RSCLKx Period

Switching Characteristics

t_DFSE

t_HOFSE

t_DDTE

t_HDTE

TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)²

TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)²

Transmit Data Delay After TSCLKx²

10.0

ns

0.0

Transmit Data Hold After TSCLKx²

¹Referenced to sample edge.

²Referenced to drive edge.

Table 26. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSI

TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)¹

8.0

ns

t_HFSI

TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)¹

Receive Data Setup Before RSCLKx¹

Receive Data Hold After RSCLKx¹

–1.5

8.0

t_SDRI

t_HDRI

t_SCLKEW

t_SCLKE

–1.5

4.5

TSCLKx/RSCLKx Width

TSCLKx/RSCLKx Period

15.0

Switching Characteristics

t_DFSI

TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)²

TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)²

Transmit Data Delay After TSCLKx²

3.0

ns

t_HOFSI

t_DDTI

–1.0

t_HDTI

Transmit Data Hold After TSCLKx²

–2.0

4.5

t_SCLKIW

TSCLKx/RSCLKx Width

¹Referenced to sample edge.

²Referenced to drive edge.

Table 27. Serial Ports—Enable and Three-State

Parameter

Min

0

Max

Unit

Switching Characteristics

t_DTENE

t_DDTTE

t_DTENI

t_DDTTI

Data Enable Delay from External TSCLKx¹

Data Disable Delay from External TSCLKx¹

Data Enable Delay from Internal TSCLKx¹

Data Disable Delay from Internal TSCLKx¹

ns

10.0

3.0

–2.0

¹Referenced to drive edge.

Rev. A

|

Page 41 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Table 28. External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

t_DDTLFSE

t_DTENLFS

Data Delay from Late External TFSx or External RFSx with MCE = 1, MFD = 0^{1, 2}

Data Enable from Late FS or MCE = 1, MFD = 0^{1, 2}

10.0

ns

0

¹MCE = 1, TFSx enable and TFSx valid follow t_DTENLFSand t_DDTLFSE

²If external RFSx/TFSx setup to RSCLKx/TSCLKx > t_SCLKE/2, then t_DDTTE/Iand t_DTENE/Iapply; otherwise t_DDTLFSEand t_DTENLFSapply.

.

DATA RECEIVE—INTERNAL CLOCK

DATA RECEIVE—EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKEW

RSCLKx

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

RFSx

DRx

RFSx

DRx

t_SDRI

t_HDRI

t_SDRE

t_HDRE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKEW

TSCLKx

TFSx

TSCLKx

TFSx

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DTx

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.

Figure 23. Serial Ports

Rev. A

|

Page 42 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

EXTERNAL RFSx WITH MCE = 1, MFD = 0

DRIVE SAMPLE

DRIVE

RSCLKx

t_SFSE/I

t_HOFSE/I

RFSx

t_DDTTE/I

t_DTENE/I

t_DTENLFS

1ST BIT

2ND BIT

DTx

t_DDTLFSE

LATE EXTERNAL TFSx

DRIVE

SAMPLE

DRIVE

TSCLKx

TFSx

t_HOFSE/I

t_SFSE/I

t_DDTTE/I

t_DTENE/I

t_DTENLFS

DTx

1ST BIT

2ND BIT

t_DDTLFSE

Figure 24. External Late Frame Sync

Rev. A

|

Page 43 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Serial Peripheral Interface Ports—Master Timing

Table 29 and Figure 25 describe SPI ports master operations.

Table 29. Serial Peripheral Interface (SPI) Ports—Master Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

Data Input Valid to SCKx Edge (Data Input Setup)

7.5

ns

SCKx Sampling Edge to Data Input Invalid

–1.5

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

SPIxSELy Low to First SCKx edge

2t_SCLK–1.5

4t_SCLK–1.5

2t_SCLK–1.5

0

ns

Serial Clock High Period

Serial Clock Low Period

Serial Clock Period

t_HDSM

Last SCKx Edge to SPIxSELy High

Sequential Transfer Delay

t_SPITDM

t_DDSPIDM

t_HDSPIDM

SCKx Edge to Data Out Valid (Data Out Delay)

SCKx Edge to Data Out Invalid (Data Out Hold)

6

–1.0

+4.0

SPIxSELy

(OUTPUT)

t_SPICLK

t_HDSM

t_SPITDM

t_SDSCIM

t_SPICHM

t_SPICLM

SCKx

(CPOL = 0)

(OUTPUT)

t_SPICLM

t_SPICHM

SCKx

(CPOL = 1)

(OUTPUT)

t_DDSPIDM

t_HDSPIDM

MOSIx

(OUTPUT)

MSB

LSB

CPHA=1

t_SSPIDM

t_HSPIDM

t_SSPIDM

t_HSPIDM

MISOx

(INPUT)

MSB VALID

LSB VALID

t_DDSPIDM

t_HDSPIDM

MOSIx

(OUTPUT)

MSB

LSB

CPHA=0

t_SSPIDM

t_HSPIDM

MISOx

(INPUT)

MSB VALID

LSB VALID

Figure 25. Serial Peripheral Interface (SPI) Ports—Master Timing

Rev. A

|

Page 44 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Serial Peripheral Interface Ports—Slave Timing

Table 30 and Figure 26 describe SPI ports slave operations.

Table 30. Serial Peripheral Interface (SPI) Ports—Slave Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

Serial Clock High Period

2t_SCLK–1.5

4t_SCLK–1.5

2t_SCLK–1.5

1.6

ns

Serial Clock Low Period

Serial Clock Period

Last SCKx Edge to SPIxSS Not Asserted

Sequential Transfer Delay

t_SPITDS

t_SDSCI

t_SSPID

t_HSPID

SPIxSS Assertion to First SCKx Edge

Data Input Valid to SCKx Edge (Data Input Setup)

SCKx Sampling Edge to Data Input Invalid

1.6

Switching Characteristics

t_DSOE

SPIxSS Assertion to Data Out Active

0

8

ns

t_DSDHI

t_DDSPID

t_HDSPID

SPIxSS Deassertion to Data High impedance

SCKx Edge to Data Out Valid (Data Out Delay)

SCKx Edge to Data Out Invalid (Data Out Hold)

8

10

SPIxSS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

t_SPITDS

SCKx

(CPOL = 0)

(INPUT)

t_SDSCI

t_SPICLS

t_SPICHS

SCKx

(CPOL = 1)

(INPUT)

t_DSOE

t_DDSPID

t_HDSPID

MSB

t_DDSPID

t_DSDHI

LSB

MISOx

(OUTPUT)

t_HSPID

t_SSPID

CPHA=1

t_SSPID

t_HSPID

MOSIx

(INPUT)

MSB VALID

LSB VALID

t_DSOE

t_DDSPID

t_DSDHI

MISOx

(OUTPUT)

MSB

LSB

t_HSPID

CPHA=0

t_SSPID

MOSIx

(INPUT)

MSB VALID

LSB VALID

Figure 26. Serial Peripheral Interface (SPI) Ports—Slave Timing

Rev. A

|

Page 45 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

General-Purpose Port Timing

Table 31 and Figure 27 describe general-purpose operations.

Table 31. General-Purpose Port Timing

Parameter

Min

Max

Unit

ns

Timing Requirement

t_WFI

Switching Characteristic

t_GPODGP Port Pin Output Delay from CLKOUT Low

GP Port Pin Input Pulse Width

t_SCLK+ 1

6

ns

CLKOUT

t_GPOD

GPP OUTPUT

t_GPOD

GPP O/D OUTPUT

GPP INPUT

t_WFI

Figure 27. General-Purpose Port Cycle Timing

Rev. A

|

Page 46 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Timer Cycle Timing

Table 32 and Figure 28 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of f_SCLK/2 MHz.

Table 32. Timer Cycle Timing

Parameter

Min

Max

Unit

Timing Characteristics

t_WL

t_WH

Timer Pulse Width Input Low¹(Measured in SCLK Cycles)

Timer Pulse Width Input High¹(Measured in SCLK Cycles)

1

SCLK

Switching Characteristic

t_HTOTimer Pulse width Output (measured in SCLK Cycles)

1

(2³²– 1)

SCLK

¹The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.

CLKOUT

t_HTO

TMRx

(PWM OUTPUT MODE)

TMRx

t_WL

t_WH

(WIDTH CAPTURE AND

EXTERNAL CLOCK MODES)

Figure 28. Timer PWM_OUT Cycle Timing

Rev. A

|

Page 47 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

JTAG Test And Emulation Port Timing

Table 33 and Figure 29 describe JTAG port operations.

Table 33. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

20

4

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High¹

System Inputs Hold After TCK High¹

TRST Pulse Width²(Measured in TCK Cycles)

ns

4

ns

4

ns

5

ns

4

TCK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low³

10

12

ns

0

¹System Inputs=ARDY, BMODE1–0, BR, DATA15–0, NMI, PF15–0, PPI_CLK, PPI3-0, SCL1-0, SDA1-0, MTXON, MRXON, MMCLK, MBCLK, MFS, MTX, MRX, SPI1SS,

SPI1SEL1, SCK2-0, MISO2-0, MOSI2-0, SPI2SS, SPI2SEL1, RX2-0, TX2-1, DR0PRI, DR0SEC, DR1PRI, DR1SEC, DT2PRI, DT2SEC, DR2PRI, DR2SEC, TSCLK3-0,

RSCLK3-0, TFS3-0, RFS3-0, DT3PRI, DT3SEC, DR3PRI, DR3SEC, CANTX, CANRX, RESET, and TMR2–0.

²50 MHz maximum

³System Outputs = AMS, AOE, ARE, AWE, ABE, BG, DATA15–0, PF15–0, PPI3–0, MTXON, MMCLK, MBCLK, MFS, MTX, SPI1SS, SPI1SEL1, SCK2-0,

MISO2-0, MOSI2-0, SPI2SS, SPI2SEL1, RX2-1, TX2-0, DT2PRI, DT2SEC, DR2PRI, DR2SEC, DT3PRI, DT3SEC, DR3PRI, DR3SEC, TSCLK3-0, TFS3-0, RSCLK3-0,

RFS3-0, CLKOUT, CANTX, SA10, SCAS, SCKE, SMS, SRAS, SWE, and TMR2–0.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 29. JTAG Port Timing

Rev. A

|

Page 48 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

MXVR Timing

Table 34 and Table 35 describe the MXVR timing requirements.

Table 34. MXVR Timing—MXI Center Frequency Requirements

Parameter

fs = 38 kHz

fs = 44.1 kHz fs = 48 kHz

Unit

f_MXI

MXI Center Frequency

38.912

45.1584

49.152

MHz

Table 35. MXVR Timing— MXI Clock Requirements

Parameter

Min

Max

Unit

Timing Requirements

FS_MXI

FT_MXI

DC_MXI

MXI Clock Frequency Stability

MXI Frequency Tolerance Over Temperature

MXI Clock Duty Cycle

–50

–300

40

+50

+300

60

ppm

%

Rev. A

|

Page 49 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

OUTPUT DRIVE CURRENTS

200

150

V_DDEXT= 3.0V

The following figures show typical current-voltage characteris-

tics for the output drivers of the ADSP-BF539/ADSP-BF539F

processor. The curves represent the current drive capability of

the output drivers as a function of output voltage.

V_DDEXT= 3.3V

V_DDEXT= 3.6V

100

50

0

V_{O H}

120

100

-50

80

V_DDEXT= 2.75V

-100

-150

-200

60

V_OL

V_OH

40

20

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE (V)

-

20

40

Figure 33. Drive Current B (High V_DDEXT

)

-

V_OL

-60

80

-80

-100

60

3.0

0

0.5

1.0

1.5

2.0

2.5

V_{DDE XT}=2.75V

SOURCE VOLTAGE (V)

40

20

0

V_OH

Figure 30. Drive Current A (Low V_DDEXT

)

150

100

50

V_{DDE XT}= 3.0V

V_{DDE XT}= 3.3V

-

20

V_{DDEX T}= 3.6V

V_OL

-

40

60

V_{O H}

-

0

0.5

1.0

1.5

2.0

2.5

3.0

SOURCE VOLTAGE (V)

-50

Figure 34. Drive Current C (Low V_DDEXT

)

V_OL

-

100

80

V_DDEXT= 3.0V

-150

V_DDEXT= 3.3V

V_{DDE XT}=3.6V

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

60

SOURCE VOLTAGE (V)

40

Figure 31. Drive Current A (High V_DDEXT

)

V_OH

20

0

150

100

50

-20

-40

-60

-80

V_{DDEX T}= 2.75V

V_{O L}

V_OH

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE (V)

-50

Figure 35. Drive Current C (High V_DDEXT

)

V_OL

-100

-150

0

0.5

1.0

1.5

2.0

2.5

3.0

SOURCE VOLTAGE (V)

Figure 32. Drive Current B (Low V_DDEXT

)

Rev. A

|

Page 50 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

100

80

0

V_{DDEX T}= 3.0 V

V_{DDEX T}= 3.3 V

V_{DDEX T}= 3.6 V

-

10

V_DDEXT= 2.75V

60

-

20

30

40

V_OH

20

0

V_OL

-50

-60

-70

-80

-20

-40

-60

-80

V_OL

4.0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0

0.5

1.0

1.5

2.0

2.5

3.0

SOURCE VOLTAGE (V)

Figure 39. Drive Current E (High V_DDEXT

)

Figure 36. Drive Current D (Low V_DDEXT

)

150

100

V_DDEXT= 3.0V

_DDEXT= 3.3V

_DDEXT= 3.6V

V

50

0

V_OH

-50

V_OL

-

100

150

-

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE (V)

Figure 37. Drive Current D (High V_DDEXT

)

0

-10

-20

-30

-40

-50

-60

V_{DDE XT}= 2.75V

V_OL

0

0.5

1.0

1.5

2.0

2.5

3.0

SOURCE VOLTAGE (V)

Figure 38. Drive Current E (Low V_DDEXT

)

Rev. A

|

Page 51 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

POWER DISSIPATION

t_DECAY= (C_LΔV) ⁄ I_L

Many operating conditions can affect power dissipation. System

designers should refer to Estimating Power for ADSP-

BF538/ADSP-BF539 Blackfin Processors (EE-298) on the Analog

Devices, Inc. website (www.analog.com)—use site search on

“EE-298.” This document provides detailed information for

optimizing your design for lowest power.

The time t_DECAYis calculated with test loads C_Land I_L, and with

ΔV equal to 0.5 V for V_DDEXT(nominal) = 3.3 V.

The time t_{DIS+_MEASURED}is the interval from when the reference

signal switches, to when the output voltage decays ΔV from the

measured output high or output low voltage.

See the ADSP-BF539/BF539F Blackfin Processor Hardware Ref-

erence Manual for definitions of the various operating modes

and for instructions on how to minimize system power.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose ΔV

to be the difference between the ADSP-BF539/ADSP-BF539F

processor output voltage and the input threshold for the device

requiring the hold time. C_Lis the total bus capacitance (per data

line), and I_Lis the total leakage or three-state current (per data

line). The hold time will be t_DECAYplus the various output dis-

able times as specified in the Timing Specifications on Page 29

(for example t_DSDATfor an SDRAM write cycle as shown in

Table 21 on Page 35).

TEST CONDITIONS

All timing parameters appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 40

shows the measurement point for ac measurements (except out-

put enable/disable). The measurement point V_MEASis 1.5 V for

V_DDEXT(nominal) = 3.3 V.

INPUT

OR

OUTPUT

V

MEAS

REFERENCE

SIGNAL

Figure 40. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

t

ENA_MEASURED

DIS_MEASURED

t

ENA

DIS

Output Enable Time Measurement

V

OH

(MEASURED)

V

(MEASURED)

OH

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving.

V

(MEASURED) 2 DV

(MEASURED) + DV

OH

V

(HIGH)

TRIP

V

(LOW)

V

TRIP

OL

V

OL

(MEASURED)

OL

t

TRIP

DECAY

The output enable time t_ENAis the interval from the point when

a reference signal reaches a high or low voltage level to the point

when the output starts driving as shown on the right side of Fig-

ure 41, “Output Enable/Disable,” on Page 52.

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

The time t_{ENA_MEASURED}is the interval, from when the reference

signal switches, to when the output voltage reaches V_TRIP(high)

or V_TRIP(low). V_TRIP(high) is 2.0 V and V_TRIP(low) is 1.0 V for

Figure 41. Output Enable/Disable

V

_DDEXT(nominal) = 3.3 V. Time t_TRIPis the interval from when

50⍀

TO

OUTPUT

the output starts driving to when the output reaches the

V_TRIP(high) or V_TRIP(low) trip voltage.

V

LOAD

30pF

Time t_ENAis calculated as shown in the equation:

t_ENA= t_{ENA_MEASURED}– t_TRIP

If multiple pins (such as the data bus) are enabled, the measure-

ment value is that of the first pin to start driving.

Figure 42. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Output Disable Time Measurement

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The output disable time t_DISis the

difference between t_{DIS_MEASURED}and t_DECAYas shown on the left

side of Figure 41.

t_DIS= t_{DIS_MEASURED}– t_DECAY

The time for the voltage on the bus to decay by ΔV is dependent

on the capacitive load C_Land the load current I_L. This decay

time can be approximated by the equation:

Rev. A

|

Page 52 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Capacitive Loading

12

10

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 42). V_LOADis 1.5 V for V_DDEXT

(nominal) = 3.3 V. Figure 43 on Page 53 through Figure 52 on

Page 54 show how output rise and fall times vary with capaci-

tance. The delay and hold specifications given should be de-

rated by a factor derived from these figures. The graphs in these

figures may not be linear outside the ranges shown.

RISE TIME

8

6

4

2

0

FALL TIME

14

12

RISE TIME

10

8

0

50

100

150

200

250

FALL TIME

LOAD CAPACITANCE (pF)

Figure 45. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver B at V_DDEXT= 2.7 V (MIN)

6

4

10

2

0

9

8

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

RISE TIME

7

Figure 43. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver A at V_DDEXT= 2.7 V (MIN)

6

FALL TIME

5

4

3

2

1

0

12

10

RISE TIME

8

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

FALL TIME

6

Figure 46. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver B at V_DDEXT= 3.65 V (MAX)

4

2

0

30

25

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

RISE TIME

20

Figure 44. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver A at V_DDEXT= 3.65 V (MAX)

15

FALL TIME

10

5

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 47. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver C at V_DDEXT= 2.7 V (MIN)

Rev. A

|

Page 53 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

20

132

18

16

RISE TIME

128

14

12

124

120

116

FALL TIME

10

8

FALL TIME

6

4

2

112

108

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 48. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver C at V_DDEXT= 3.65 V (MAX)

Figure 51. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver E

at V_DDEXT= 2.7 V (MIN)

18

16

124

120

14

RISE TIME

12

10

FALL TIME

116

8

6

4

2

0

FALL TIME

112

108

104

100

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 49. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver D at V_DDEXT= 2.7 V (MIN)

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 52. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver E

at V_DDEXT= 3.65 V (MAX)

14

12

RISE TIME

10

8

FALL TIME

6

4

2

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 50. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver D at V_DDEXT= 3.65 V (MAX)

Rev. A

|

Page 54 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

THERMAL CHARACTERISTICS

To determine the junction temperature on the application

printed circuit board use

T_J= T_CASE+ (Ψ_JT× P_D)

where

T_J= Junction temperature (؇C)

T

_CASE= Case temperature (؇C) measured by customer at top

center of package.

Ψ_JT= From Table 36 or Table 37

P_D= Power dissipation (see Power Dissipation on Page 52 for

the method to calculate P_D)

Values of θ_JAare provided for package comparison and printed

circuit board design considerations. θ_JAcan be used for a first

order approximation of T_Jby the equation:

T_J= T_A+ (θ_JA× P_D)

where:

T_A= Ambient temperature (؇C)

Values of θ_JCare provided for package comparison and printed

circuit board design considerations when an external heatsink is

required.

Values of θ_JBare provided for package comparison and printed

circuit board design considerations.

In Table 36 and Table 37, airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6, and the junction-to-

board measurement complies with JESD51-8. The junction-to-

case measurement complies with MIL-STD-883 (Method

1012.1). All measurements use a 2S2P JEDEC test board.

Table 36. Thermal Characteristics BC-316 Without Flash

Parameter

θ_JA

Condition

Typical

21.6

Unit

؇C/W

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

θ_JMA

θ_JC

18.8

18.1

5.36

0.13

Ψ_JT

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

Ψ_JT

0.25

Ψ_JT

0.25

Table 37. Thermal Characteristics BC-316 With Flash

Parameter

θ_JA

Condition

Typical

20.9

Unit

؇C/W

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

θ_JMA

θ_JC

18.1

17.4

5.01

0.12

Ψ_JT

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

Ψ_JT

0.24

Ψ_JT

0.24

Rev. A

|

Page 55 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

316-BALL CSP_BGA BALL ASSIGNMENT

Figure 53 lists the top view of the CSP_BGA ball assignment.

Figure 54 lists the bottom view of the CSP_BGA ball

assignment.

Table 38 on Page 57 lists the CSP_BGA ball assignment by ball

number. Table 39 on Page 58 lists the CSP_BGA ball assign-

ment by signal.

A1 BALL

A

B

C

D

E

F

G

H

J

A

B

C

D

E

F

G

H

J

K

L

K

L

M

N

P

R

T

U

V

W

Y

M

N

P

R

T

U

V

W

Y

1

2

3

4

5

6

7

8 9 10 11 12 13 14 15 16 17 18 19 20

GND

I/O

VDDRTC

VROUTx

NC

VDDINT

VDDEXT

20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

GND

VDDRTC

VDDINT

NC

Note: H18 andY14 are NC for ADSP-BF539

and I/O (FCE and FRESET) for ADSP-BF539F

I/O

VROUTx

VDDEXT

Note: H18 andY14 are NC for ADSP-BF539

and I/O (FCE and FRESET) for ADSP-BF539F

Figure 53. 316-Ball CSP_BGA Ball Assignment (Top View)

Figure 54. 316-Ball CSP_BGA Ball Assignment (Bottom View)

Rev. A

|

Page 56 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Table 38. 316-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)

Ball No. Signal

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

Ball No. Signal

A1

GND

PF10

PF11

C7

C8

C9

SPI2SEL1 F8

SPI2SS F9

MOSI2 F10

MISO2 F11

GND

J12

J13

J14

J18

J19

J20

K1

GND

AMS0

AMS2

SA10

RFS1

TMR2

GP

M19

M20

N1

ABE0

ABE1

TFS0

T3

T7

T8

GND

W1

TCK

A2

VDDEXT W2

VDDEXT W3

VDDEXT W4

VDDEXT W5

VDDEXT W6

VDDINT W7

VDDINT W8

VDDINT W9

GND

A3

DATA15

DATA13

DATA11

DATA9

DATA7

DATA5

DATA3

DATA1

RSCLK2

DR2PRI

DT2PRI

RX2

A4

PPI_CLK C10

N2

DR0PRI T9

A5

PPI0

PPI2

PF15

PF13

C11

C12

C13

C14

SCK2

F12

N3

GND

T10

A6

MPIVDD F13

SPI1SEL1 F14

MISO1 F18

SPI1SS F19

MOSI1 F20

N7

VDDEXT T11

A7

N8

GND

T12

T13

T14

T18

T19

T20

A8

DT3PRI K2

N9

A9

VDDRTC C15

MRX

MFS

SCK0

K3

K7

K8

N10

N11

N12

N13

N14

N18

N19

N20

P1

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

RTXO

RTXI

GND

CLKIN

XTAL

MLF

C16

C17

C18

C19

C20

D1

GND

AMS3

AMS1

AOE

RFS3

W10

SCK1

GND

G1

G2

ADDR7 W11

ADDR8 W12

MOSI0 K9

DT0SEC K10

MMCLK G3

VDDINT U1

DT3SEC U2

ADDR1 U3

ADDR2 U7

TSCLK0 U8

TRST

TMS

GND

W13

W14

W15

SCKE

PF4

G7

G8

G9

GND

BR

K11

K12

K13

K14

K18

K19

K20

L1

TX2

MXO

MXI

D2

PF5

VDDEXT W16

VDDEXT W17

VDDEXT W18

VDDEXT W19

VDDEXT W20

VDDINT Y1

VDDINT Y2

VDDINT Y3

RSCLK3 Y4

ADDR9 Y5

ADDR10 Y6

ADDR18

ADDR15

ADDR13

GND

D3

DT1SEC G10

MRXON D7

VROUT1 D8

GND

G11

G12

G13

G14

G18

G19

G20

H1

P2

RFS0

GND

U9

P3

U10

GND

PF8

D9

P7

VDDEXT U11

ADDR14

GND

D10

D11

D12

D13

D14

D18

D19

D20

E1

RSCLK1 P8

GND

U12

U13

U14

U18

U19

U20

B2

GND

PF9

L2

TMR1

GND

P9

TDO

B3

CLKOUT L3

SRAS L7

P10

P11

P12

P13

P14

P18

P19

P20

R1

DATA14

DATA12

DATA10

DATA8

DATA6

DATA4

DATA2

DATA0

RFS2

B4

PF3

B5

PPI1

DT1PRI L8

TSCLK1 L9

DR1SEC L10

B6

PPI3

H2

B7

PF14

PF12

SCL0

SDA0

CANRX

CANTX

NMI

MBCLK H3

VDDINT V1

DR3SEC V2

ADDR3 V3

ADDR4 V4

TDI

Y7

Y8

Y9

B8

SMS

PF1

H7

GND

FCE

L11

L12

L13

L14

L18

L19

L20

M1

M2

M3

M7

M8

GND

B9

H8

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

C1

E2

PF2

H9

BMODE1 Y10

BMODE0 Y11

E3

GND

MTX

ARDY

PF0

H10

H11

H12

H13

H14

H18

H19

H20

J1

TX0

RSCLK0 V6

GND V7

VDDEXT V8

V5

E7

TSCLK3 R2

GND

Y12

TSCLK2

TFS2

E8

ARE

R3

R7

VDDEXT Y13

VDDEXT Y14

VDDEXT Y15

VDDEXT Y16

VDDEXT Y17

VDDINT Y18

DR2SEC Y19

RESET

E9

AWE

FRESET

SCL1

MXEVDD E10

MXEGND E11

MTXON E12

DT0PRI R8

GND

V9

TMR0

GND

R9

V10

V11

V12

V13

V14

SDA1

SCAS

SWE

TFS1

R10

ADDR19

ADDR17

ADDR16

GND

E13

E14

VDDEXT R11

GND

R12

R13

R14

R18

R19

R20

VROUT0 E18

J2

DR1PRI M9

DR0SEC M10

BG

Y20

PF6

E19

E20

F1

J3

VDDINT V15

DR3PRI V16

ADDR5 V17

ADDR6 V18

BGH

C2

PF7

J7

GND

M11

M12

M13

M14

M18

DT2SEC

GND

C3

GND

RX1

TX1

J8

C4

F2

MISO0 J9

GND

C5

F3

GND

J10

J11

VDDINT T1

RX0

V19

V20

ADDR11

ADDR12

C6

F7

TFS3

T2

EMU

Rev. A

|

Page 57 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

Table 39. 316-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)

Signal

ABE0

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

Ball No. Signal Ball No. Signal Ball No.

M19

M20

N19

N20

P19

P20

R19

R20

T19

T20

U19

U20

V19

V20

W18

W20

W17

Y19

Y18

W16

Y17

J18

DATA8 Y6

DATA9 W6

DATA10 Y5

DATA11 W5

DATA12 Y4

DATA13 W4

DATA14 Y3

DATA15 W3

DR0PRI N2

DR0SEC J3

DR1PRI J2

DR1SEC H3

DR2PRI W12

DR2SEC V13

DR3PRI R18

DR3SEC P18

DT0PRI M1

DT0SEC G3

DT1PRI H1

DT1SEC D3

DT2PRI W13

DT2SEC V16

DT3PRI F18

DT3SEC N18

GND E7

GND E8

GND K11

GND K12

GND

GP

V17

V18

W2

W19

Y1

PPI2

A6

TSCLK1 H2

TSCLK2 Y12

TSCLK3 L18

ABE1

PPI3

B6

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

ADDR17

ADDR18

ADDR19

AMS0

GND

GND F8

GND F9

E9

GND

GND L13

GND L14

K13

RESET

RFS0

RFS1

RFS2

RFS3

B14

P2

TX0

TX1

TX2

R1

K1

C6

GND F10

GND F11

GND M3

GND M8

Y20

K3

Y11

T18

W15

VDDEXT T8

VDDEXT T9

VDDEXT T10

VDDEXT T11

VDDEXT U7

VDDEXT U8

VDDEXT U9

VDDEXT U10

VDDEXT U11

VDDEXT V7

VDDEXT M7

VDDEXT N7

VDDEXT P7

VDDEXT R7

VDDEXT T7

VDDEXT V8

VDDEXT V9

VDDEXT V10

VDDEXT V11

VDDINT M14

VDDINT N14

VDDINT P14

VDDINT R14

VDDINT T12

VDDINT T13

VDDINT T14

VDDINT U12

VDDINT U13

VDDINT U14

VDDINT V12

VDDRTC A9

VROUT0 B20

VROUT1 A19

GND

F12

F13

F14

G7

GND

M9

MBCLK

MFS

D19

F20

F2

RSCLK0 R2

RSCLK1 L1

RSCLK2 W11

RSCLK3 U18

M10

M11

M12

MISO0

MISO1

MISO2

MLF

C14

C10

A15

GND G8

GND M13

RTXI

RTXO

RX0

A11

A10

T1

GND

G9

GND

N3

K14

L3

E10

E11

E12

E13

E14

MMCLK C19

MOSI0

MOSI1

MOSI2

G2

RX1

C5

L7

C16

C9

RX2

W14

J20

H19

G1

L8

SA10

SCAS

SCK0

SCK1

SCK2

SCKE

SCL0

SCL1

SDA0

SDA1

SMS

L9

MPIVDD C12

MRXON A18

GND E18

GND L10

GND

F3

GND

L11

L12

N8

MRX

MTX

F19

E19

C17

C11

C20

B9

F7

G10

MTXON B17

MXEGND B16

MXEVDD B15

AMS1

K19

J19

GND G11

GND G12

GND N9

AMS2

GND N10

Y15

B10

Y16

D20

AMS3

K18

K20

E20

L19

L20

V14

V15

V5

EMU

FCE

T2

GND

G13

G14

H7

GND

N11

N12

N13

P3

MXI

MXO

NMI

PF0

A17

A16

B13

F1

AOE

H18

ARDY

FRESET Y14

ARE

GND

A1

H8

SPI1SEL1 C13

SPI1SS C15

SPI2SEL1 C7

SPI2SS C8

AWE

A12

A20

B2

GND H9

GND P8

PF1

E1

BG

GND

H10

GND

P9

PF2

E2

BGH

H11

H12

H13

H14

J7

P10

P11

P12

P13

R3

PF3

B4

BMODE0

BMODE1

BR

B18

B19

C3

PF4

D1

D2

C1

C2

B1

SRAS

SWE

TCK

G20

H20

W1

V1

V4

PF5

G18

B11

B12

A13

G19

Y10

W10

Y9

PF6

CANRX

CANTX

CLKIN

C4

PF7

TDI

C18

D7

GND J8

GND R8

PF8

TDO

TFS0

TFS1

TFS2

TFS3

TMR0

TMR1

TMR2

TMS

Y2

GND

J9

GND

R9

PF9

B3

N1

J1

CLKOUT

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

D8

J10

J11

R10

R11

PF10

PF11

PF12

PF13

PF14

PF15

A2

A3

B8

D9

Y13

M18

M2

L2

D10

D11

D12

D13

D14

D18

E3

GND J12

GND J13

GND J14

GND R12

GND R13

GND T3

XTAL

A14

A8

B7

W9

Y8

GND

K7

GND

U3

V2

V3

V6

A7

K2

W8

K8

PPI_CLK A4

U2

Y7

K9

PPI0

PPI1

A5

B5

TRST

U1

W7

K10

TSCLK0 P1

Rev. A

|

Page 58 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

OUTLINE DIMENSIONS

Dimensions in the outline dimensions figures are shown in

millimeters.

15.20 BSC SQ

17.00 BSC SQ

A1 BALL

0.80 BSC BALL PITCH

A1 BALL INDICATOR

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

20 19 18 17 16 1514 13 12 11 10

9 8 7 6 5 4 3 2 1

BOTTOM VIEW

TOP VIEW

0.30 MIN

0.12 MAX

COPLANARITY

1.70

MAX

SIDE VIEW

0.50

0.45

0.40

SEATING PLANE

BALL DIAMETER

DETAIL A

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM,

WITH THE EXCEPTION OF BALL DIAMETER.

3. CENTER DIMENSIONS ARE NOMINAL.

Figure 55. 316-Ball Chip Scale Package Ball Grid Array [CSP_BGA](BC-316)

Rev. A

|

Page 59 of 60

|

February 2008

ADSP-BF539/ADSP-BF539F

SURFACE-MOUNT DESIGN

Table 40 is provided as an aid to PCB design. For industry-

standard design recommendations, refer to IPC-7351,

Generic Requirements for Surface Mount Design and Land Pattern Standard.

Table 40. BGA Data for Use with Surface-Mount Design

Package

Ball Attach Type

Solder Mask Opening

Ball Pad Size

316-Ball Chip Scale Package Ball Grid Array [CSP_BGA](BC-316) Solder Mask Defined

0.40 mm diameter

0.50 mm diameter

ORDERING GUIDE

Temperature

Range²

Package Instruction Operating Voltage

Option Rate (Max) (Nominal)

Model¹

Package Description

ADSP-BF539BBCZ-5A³

–40ꢂC to +85ꢂC

316-Ball Chip Scale Package

Ball Grid Array [CSP_BGA]

BC-316

533 MHz

1.25 V internal/ 3.3 V I/O

ADSP-BF539BBCZ-5F4³

ADSP-BF539BBCZ-5F8³

316-Ball Chip Scale Package

Ball Grid Array [CSP_BGA]

316-Ball Chip Scale Package

Ball Grid Array [CSP_BGA]

¹A similar part is available for use in specific automotive applications. Contact your local ADI sales office for the ADBF539W Automotive Data Sheet which highlights any

specification changes and ordering information.

²Referenced temperature is ambient temperature.

³Z = RoHS compliant part.

registered trademarks are the property of their respective owners.

D06699-0-2/08(A)

Rev. A

|

Page 60 of 60

|

February 2008


型号：	ADSP-BF539_08
厂家：	ADI
描述：	Blackfin Embedded Processor Blackfin嵌入式处理器
文件：	总60页 (文件大小：2361K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF539_08 [ADI]

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