ADSP-BF592KCPZ-X_技术文档

Blackfin

Embedded Processor

Preliminary Technical Data

ADSP-BF592

FEATURES

PERIPHERALS

Up to 400 MHz high-performance Blackfin processor

2 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Accepts a wide range of supply voltages for internal and I/O

operations. See Operating Conditions on Page 18

Off-chip voltage regulator interface

4 32-bit timers/counters, three with PWM support

2 dual-channel, full-duplex synchronous serial ports (SPORT),

supporting eight stereo I²S channels

2 Serial Peripheral Interface (SPI) compatible ports

1 UART with IrDA support

Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats

Two-wire interface (TWI) controller

9 peripheral DMAs

64-lead (9 mm × 9 mm) LFCSP package

2 memory-to-memory DMA channels

Event handler with 28 interrupt inputs

32 general-purpose I/Os (GPIOs), with programmable

hysteresis

Debug/JTAG interface

On-chip PLL capable of frequency multiplication

MEMORY

68K bytes of core-accessible memory:

(See Table 1 on Page 3 for L1 and L3 memory size details)

64K byte L1 instruction ROM

Flexible booting options from internal L1 ROM and SPI mem-

ory or from host devices including SPI, PPI, and UART

Memory management unit providing memory protection

WATCHDOG TIMER

SPORT1

PORT F

VOLTAGE REGULATOR INTERFACE

JTAG TEST AND EMULATION

PERIPHERAL

PPI

TIMER2–0

UART

SPI0

ACCESS BUS

GPIO

INTERRUPT

CONTROLLER

B

L1 INSTRUCTION

SRAM

SPORT0

SPI1

L1 INSTRUCTION

ROM

L1 DATA

SRAM

PORT G

DMA

CONTROLLER

DMA

ACCESS

BUS

DCB

TWI

DEB

BOOT

ROM

Figure 1. Processor Block Diagram

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

Preliminary Technical Data

ADSP-BF592

TABLE OF CONTENTS

Features ................................................................. 1

Memory ................................................................ 1

Peripherals ............................................................. 1

Revision History ...................................................... 2

General Description ................................................. 3

Portable Low-Power Architecture ............................. 3

System Integration ................................................ 3

Processor Peripherals ............................................. 3

Blackfin Processor Core .......................................... 3

Memory Architecture ............................................ 5

DMA Controllers .................................................. 8

Watchdog Timer .................................................. 8

Timers ............................................................... 8

Serial Ports .......................................................... 8

Serial Peripheral Interface (SPI) Ports ........................ 9

UART Port .......................................................... 9

Parallel Peripheral Interface (PPI) ............................. 9

TWI Controller Interface ...................................... 10

Ports ................................................................ 10

Dynamic Power Management ................................ 10

Voltage Regulation .............................................. 12

Clock Signals ..................................................... 12

Booting Modes ................................................... 13

Instruction Set Description .................................... 14

Development Tools .............................................. 14

Designing an Emulator-Compatible

Processor Board (Target) ................................... 14

Related Documents .............................................. 15

Related Signal Chains ........................................... 15

Signal Descriptions ................................................. 16

Specifications ........................................................ 18

Operating Conditions ........................................... 18

Electrical Characteristics ....................................... 20

Absolute Maximum Ratings ................................... 22

ESD Sensitivity ................................................... 22

Package Information ............................................ 22

Timing Specifications ........................................... 23

Output Drive Currents ......................................... 37

Test Conditions .................................................. 38

Environmental Conditions .................................... 40

64-Lead LFCSP Pin assignment ................................. 42

Outline Dimensions ................................................ 44

Surface Mount Design .......................................... 44

Planned Models ..................................................... 44

Ordering Guide ..................................................... 45

REVISION HISTORY

08/10—Rev. PrB to Rev. PrC:

Numerous small corrections and additions to document.

Updated Processor Features ....................................... 3

Revised Core Clock (CCLK) Requirements .................. 19

Revised Electrical Characteristics ............................... 20

Revised Absolute Maximum Ratings ........................... 22

Added 2.5 V/3.3 V specifications for most interfaces in Timing

Specifications ........................................................ 23

Updated Output Drive Currents ................................ 37

Updated Capacitive Loading ..................................... 39

Added Planned Models ........................................... 44

Rev. PrC

|

Page 2 of 46

|

August 2010

Preliminary Technical Data

GENERAL DESCRIPTION

ADSP-BF592

The ADSP-BF592 processor is a member of the Blackfin^®family

of products, incorporating the Analog Devices/Intel Micro

Signal Architecture (MSA). Blackfin processors combine a dual-

MAC state-of-the-art signal processing engine, the advantages

of a clean, orthogonal RISC-like microprocessor instruction set,

and single-instruction, multiple-data (SIMD) multimedia capa-

bilities into a single instruction-set architecture.

SYSTEM INTEGRATION

The ADSP-BF592 processor is a highly integrated system-on-a-

chip solution for the next generation of digital communication

and consumer multimedia applications. By combining indus-

try-standard interfaces with a high-performance signal

processing core, cost-effective applications can be developed

quickly, without the need for costly external components. The

system peripherals include a watchdog timer; three 32-bit tim-

ers/counters with PWM support; two dual-channel, full-duplex

synchronous serial ports (SPORTs); two serial peripheral inter-

face (SPI) compatible ports; one UART^®with IrDA support; a

parallel peripheral interface (PPI); and a two-wire interface

(TWI) controller.

The ADSP-BF592 processor is completely code compatible with

other Blackfin processors. ADSP-BF592 processors offer perfor-

mance up to 400 MHz and reduced static power consumption.

The processor features are shown in Table 1.

Table 1. Processor Features

Feature

Timer/Counters with PWM

SPORTs

ADSP-BF592

PROCESSOR PERIPHERALS

3

The ADSP-BF592 processor contains a rich set of peripherals

connected to the core via several high-bandwidth buses, provid-

ing flexibility in system configuration as well as excellent overall

system performance (see Figure 1). The processor also contain

dedicated communication modules and high-speed serial and

parallel ports, an interrupt controller for flexible management

of interrupts from the on-chip peripherals or external sources,

and power management control functions to tailor the perfor-

mance and power characteristics of the processor and system to

many application scenarios.

The SPORTs, SPIs, UART, and PPI peripherals are supported

by a flexible DMA structure. There are also separate memory

DMA channels dedicated to data transfers between the proces-

sor’s various memory spaces, including boot ROM. Multiple

on-chip buses running at up to 100 MHz provide enough band-

width to keep the processor core running along with activity on

all of the on-chip and external peripherals.

2

SPIs

2

UART

1

Parallel Peripheral Interface

TWI

1

32

GPIOs

L1 Instruction SRAM

L1 Instruction ROM

L1 Data SRAM

32K

64K

32K

L1 Scratchpad SRAM

4K

L3 Boot ROM

4K

Maximum Instruction Rate¹

Maximum System Clock Speed

Package Options

400 MHz

100 MHz

64-Lead LFCSP

¹Maximum instruction rate is not available with every possible SCLK selection.

The ADSP-BF592 processor includes an interface to an off-chip

voltage regulator in support of the processor’s dynamic power

management capability.

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like program-

mability, multimedia support, and leading-edge signal

processing in one integrated package.

BLACKFIN PROCESSOR CORE

As shown in Figure 2, the Blackfin processor core contains two

16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,

four video ALUs, and a 40-bit shifter. The computation units

process 8-, 16-, or 32-bit data from the register file.

PORTABLE LOW-POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. They are produced with a low-power and

low-voltage design methodology and feature on-chip dynamic

power management, which provides the ability to vary both the

voltage and frequency of operation to significantly lower overall

power consumption. This capability can result in a substantial

reduction in power consumption, compared with just varying

the frequency of operation. This allows longer battery life for

portable appliances.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation

are supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and

Rev. PrC

|

Page 3 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

ADDRESS ARITHMETIC UNIT

SP

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

FP

P5

P4

P3

P2

P1

P0

M1

M0

DAG1

DAG0

DA1

DA0

32

PREG

32

RAB

SD

LD1

LD0

32

ASTAT

32

SEQUENCER

ALIGN

R7.H

R7.L

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

population count, modulo 2³²multiply, divide primitives, satu-

ration and rounding, and sign/exponent detection. The set of

video instructions include byte alignment and packing opera-

tions, 16-bit and 8-bit adds with clipping, 8-bit average

operations, and 8-bit subtract/absolute value/accumulate (SAA)

operations. Also provided are the compare/select and vector

search instructions.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If the second ALU is used,

quad 16-bit operations are possible.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. Data memory holds data, and

a dedicated scratchpad data memory stores stack and local vari-

able information.

Multiple L1 memory blocks are provided. The memory man-

agement unit (MMU) provides memory protection for

individual tasks that may be operating on the core and can pro-

tect system registers from unintended access.

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

Rev. PrC

|

Page 4 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

The second core-accessible memory block is the L1 data mem-

ory, consisting of 32K bytes. This memory block is accessed at

full processor speed.

The third memory block is a 4K byte L1 scratchpad SRAM

which runs at the same speed as the other L1 memories.

L1 Utility ROM

The L1 instruction ROM contains utility ROM code. This

includes the TMK (VDK core), C run-time libraries, and DSP

libraries. See the VisualDSP++ documentation for more

information.

Custom ROM (Optional)

The on chip L1 Instruction ROM on the ADSP-BF592 may be

customized to contain user code with the following features:

• 64K bytes of L1 Instruction ROM available for custom code

• Ability to restrict access to all or specific segments of the on

chip ROM

MEMORY ARCHITECTURE

The Blackfin processor views memory as a single unified

4G byte address space, using 32-bit addresses. All resources,

including internal memory and I/O control registers, occupy

separate sections of this common address space. See Figure 3.

Customers wishing to customize the on chip ROM for their own

application needs should contact ADI sales for more informa-

tion on terms and conditions and details on the technical

implementation.

The core-accessible L1 memory system is high-performance

internal memory that operates at the core clock frequency. The

external bus interface unit (EBIU) provides access to the boot

ROM.

The memory DMA controller provides high-bandwidth data-

movement capability. It can perform block transfers of code or

data between the L1 Instruction SRAM and L1 Data SRAM

memory spaces.

I/O Memory Space

The processor does not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory-mapped registers (MMRs) at addresses near the top of the

4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The MMRs are accessible only in supervisor mode and appear

as reserved space to on-chip peripherals.

0xFFFF FFFF

CORE MEMORY MAPPED REGISTERS (2M BYTES)

0xFFE0 0000

SYSTEM MEMORY MAPPED REGISTERS (2M BYTES)

0xFFC0 0000

RESERVED

0xFFB0 1000

L1 SCRATCHPAD RAM (4K BYTES)

0xFFB0 0000

RESERVED

0xFFA2 0000

Booting

L1 INSTRUCTION ROM (64K BYTES)

0xFFA1 0000

RESERVED

The processor contains a small on-chip boot kernel, which con-

figures the appropriate peripheral for booting. If the processor is

configured to boot from boot ROM memory space, the proces-

sor starts executing from the on-chip boot ROM. For more

information, see Booting Modes on Page 13.

0xFFA0 8000

L1 INSTRUCTION BANK B SRAM (16K BYTES)

0xFFA0 4000

L1 INSTRUCTION BANK A SRAM (16K BYTES)

0xFFA0 0000

RESERVED

0xFF80 8000

DATA SRAM (32K BYTES)

0xFF80 0000

Event Handling

RESERVED

0xEF00 1000

The event controller on the processor handles all asynchronous

and synchronous events to the processor. The processor pro-

vides event handling that supports both nesting and

prioritization. Nesting allows multiple event service routines to

be active simultaneously. Prioritization ensures that servicing of

a higher-priority event takes precedence over servicing of a

lower-priority event. The controller provides support for five

different types of events:

BOOT ROM (4K BYTES)

0xEF00 0000

RESERVED

0x0000 0000

Figure 3. Internal/External Memory Map

Internal (Core-Accessible) Memory

The processor has three blocks of core-accessible memory, pro-

viding high-bandwidth access to the core.

The first block is the L1 instruction memory, consisting of

32K bytes SRAM. This memory is accessed at full processor

speed.

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• RESET – This event resets the processor.

Rev. PrC

|

Page 5 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

• Nonmaskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

Table 2. Core Event Controller (CEC)

Priority

(0 is Highest) Event Class

EVT Entry

EMU

0

Emulation/Test Control

1

RESET

RST

• Exceptions – Events that occur synchronously to program

flow (in other words, the exception is taken before the

instruction is allowed to complete). Conditions such as

data alignment violations and undefined instructions cause

exceptions.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

The processor event controller consists of two stages: the core

event controller (CEC) and the system interrupt controller

(SIC). The core event controller works with the system interrupt

controller to prioritize and control all system events. Conceptu-

ally, interrupts from the peripherals enter into the SIC and are

then routed directly into the general-purpose interrupts of the

CEC.

2

Nonmaskable Interrupt

Exception

NMI

3

EVX

4

Reserved

—

5

Hardware Error

IVHW

IVTMR

IVG7

6

Core Timer

7

General-Purpose Interrupt 7

General-Purpose Interrupt 8

General-Purpose Interrupt 9

General-Purpose Interrupt 10

General-Purpose Interrupt 11

General-Purpose Interrupt 12

General-Purpose Interrupt 13

General-Purpose Interrupt 14

General-Purpose Interrupt 15

8

IVG8

9

IVG9

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

event has been accepted into the system. This register is

updated automatically by the controller, but it may be writ-

ten only when its corresponding IMASK bit is cleared.

Core Event Controller (CEC)

• CEC interrupt mask register (IMASK) – Controls the

masking and unmasking of individual events. When a bit is

set in the IMASK register, that event is unmasked and is

processed by the CEC when asserted. A cleared bit in the

IMASK register masks the event, preventing the processor

from servicing the event even though the event may be

latched in the ILAT register. This register may be read or

written while in supervisor mode. (Note that general-pur-

pose interrupts can be globally enabled and disabled with

the STI and CLI instructions, respectively.)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority

interrupts (IVG15–14) are recommended to be reserved for

software interrupt handlers, leaving seven prioritized interrupt

inputs to support the peripherals of the processor. Table 2

describes the inputs to the CEC, identifies their names in the

event vector table (EVT), and lists their priorities.

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Although the processor provides a default mapping, the user

can alter the mappings and priorities of interrupt events by writ-

ing the appropriate values into the interrupt assignment

registers (SIC_IARx). Table 3 describes the inputs into the SIC

and the default mappings into the CEC.

• CEC interrupt pending register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing

three pairs of 32-bit interrupt control and status registers. Each

register contains a bit, corresponding to each of the peripheral

interrupt events shown in Table 3.

Event Control

• SIC interrupt mask registers (SIC_IMASK) – Control the

masking and unmasking of each peripheral interrupt event.

When a bit is set in these registers, that peripheral event is

unmasked and is processed by the system when asserted. A

cleared bit in the register masks the peripheral event, pre-

venting the processor from servicing the event.

• SIC interrupt status registers (SIC_ISR) – As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

The processor provides a very flexible mechanism to control the

processing of events. In the CEC, three registers are used to

coordinate and control events. Each register is 16 bits wide.

• CEC interrupt latch register (ILAT) – Indicates when

events have been latched. The appropriate bit is set when

the processor has latched the event and is cleared when the

Rev. PrC

|

Page 6 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

source triggered the interrupt. A set bit indicates that the

peripheral is asserting the interrupt, and a cleared bit indi-

cates that the peripheral is not asserting the event.

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

• SIC interrupt wakeup enable registers (SIC_IWR) – By

enabling the corresponding bit in these registers, a periph-

eral can be configured to wake up the processor, should the

core be idled or in sleep mode when the event is generated.

For more information, see Dynamic Power Management

on Page 10.

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC recognizes and queues the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

Table 3. System Interrupt Controller (SIC)

General Purpose

Interrupt (at Reset)

Peripheral

Interrupt ID

Default Core

Interrupt ID

SIC Interrupt

Assignment

Peripheral Interrupt Source

PLL Wakeup Interrupt

DMA Error (generic)

PPI0 Status

IVG7

0

1

2

3

4

5

–

6

IAR0

IAR1

IAR2

IAR3

IVG7

1

IVG7

2

SPORT0 Status

IVG7

3

SPORT1 Status

IVG7

4

SPI0 Status

IVG7

5

SPI1 Status

IVG7

6

UART0 Status

IVG7

7

DMA Channel 0 (PPI0)

DMA Channel 1 (SPORT0 RX)

DMA Channel 2 (SPORT0 TX)

DMA Channel 3 (SPORT1 RX)

DMA Channel 4 (SPORT1 TX)

DMA Channel 5 (SPI0 RX/TX)

DMA Channel 6 (SPI1 RX/TX)

DMA Channel 7 (UART0 RX)

DMA Channel 8 (UART0 TX)

Port F Interrupt A

IVG8

8

IVG9

9

IVG9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

IVG9

IVG10

IVG11

IVG12

–

Port F Interrupt B

Timer 0

Timer 1

Timer 2

Port G Interrupt A

Port G Interrupt B

TWI

Reserved

–

Reserved

–

Reserved

–

DMA Channels 12 and 13 (Memory DMA Stream 0)

DMA Channels 14 and 15 (Memory DMA Stream 1)

Software Watchdog Timer

IVG13

Rev. PrC

|

Page 7 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

The timer is clocked by the system clock (SCLK), at a maximum

DMA CONTROLLERS

frequency of f_SCLK

.

The processor has multiple, independent DMA channels that

support automated data transfers with minimal overhead for

the processor core. DMA transfers can occur between the pro-

cessor’s internal memories and any of its DMA-capable

peripherals. DMA-capable peripherals include the SPORTs, SPI

ports, UART, and PPI. Each individual DMA-capable periph-

eral has at least one dedicated DMA channel.

The processor DMA controller supports both one-dimensional

(1-D) and two-dimensional (2-D) DMA transfers. DMA trans-

fer initialization can be implemented from registers or from sets

of parameters called descriptor blocks.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

TIMERS

There are four general-purpose programmable timer units in

the processors. Three timers have an external pin that can be

configured either as a pulse width modulator (PWM) or timer

output, as an input to clock the timer, or as a mechanism for

measuring pulse widths and periods of external events. These

timers can be synchronized: to an external clock input to the

several other associated PF pins, to an external clock input to

the PPI_CLK input pin, or to the internal SCLK.

The timer units can be used in conjunction with the UART to

measure the width of the pulses in the data stream to provide a

software auto-baud detect function for the respective serial

channels.

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

In addition to the three general-purpose programmable timers,

a fourth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generation of operating system periodic interrupts.

Examples of DMA types supported by the processor DMA con-

troller include:

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

SERIAL PORTS

The processors incorporate two dual-channel synchronous

serial ports (SPORT0 and SPORT1) for serial and multiproces-

sor communications. The SPORTs support the following

features:

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels, which are provided for transfers

between the various memories of the processor system with

minimal processor intervention. Memory DMA transfers can be

controlled by a very flexible descriptor-based methodology or

by a standard register-based autobuffer mechanism.

• I²S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I²S stereo audio.

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-bit

first or least-significant-bit first.

WATCHDOG TIMER

The processor includes a 32-bit timer that can be used to imple-

ment a software watchdog function. A software watchdog can

improve system availability by forcing the processor to a known

state through generation of a hardware reset, nonmaskable

interrupt (NMI), or general-purpose interrupt, if the timer

expires before being reset by software. The programmer initial-

izes the count value of the timer, enables the appropriate

interrupt, then enables the timer. Thereafter, the software must

reload the counter before it counts to zero from the pro-

grammed value. This protects the system from remaining in an

unknown state where software, which would normally reset the

timer, has stopped running due to an external noise condition

or software error.

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the processor peripherals. After a reset,

software can determine whether the watchdog was the source of

the hardware reset by interrogating a status bit in the watchdog

timer control register.

• Companding in hardware – Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without

additional latencies.

Rev. PrC

|

Page 8 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer, or buffers,

through DMA.

The PPI supports a variety of general-purpose and ITU-R 656

modes of operation. In general-purpose mode, the PPI provides

half-duplex, bidirectional data transfer with up to 16 bits of

data. Up to three frame synchronization signals are also pro-

vided. In ITU-R 656 mode, the PPI provides half-duplex

bidirectional transfer of 8- or 10-bit video data. Additionally,

on-chip decode of embedded start-of-line (SOL) and start-of-

field (SOF) preamble packets is supported.

General-Purpose Mode Descriptions

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

• Input mode – Frame syncs and data are inputs into the PPI.

• Frame capture mode – Frame syncs are outputs from the

PPI, but data are inputs.

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The processors have two SPI-compatible ports that enable the

processor to communicate with multiple SPI-compatible

devices.

• Output mode – Frame syncs and data are outputs from the

PPI.

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSI, and Master Input-

Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI

chip select input pin (SPIx_SS) lets other SPI devices select the

processor, and many SPI chip select output pins (SPIx_SEL7–1)

let the processor select other SPI devices. The SPI select pins are

reconfigured general-purpose I/O pins. Using these pins, the

SPI port provides a full-duplex, synchronous serial interface,

which supports both master/slave modes and multimaster

environments.

Input Mode

Input mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_COUNT register. The PPI supports 8-bit and 10-bit

through 16-bit data, programmable in the PPI_CONTROL

register.

UART PORT

The ADSP-BF592 processor provides a full-duplex universal

asynchronous receiver/transmitter (UART) port, which is fully

compatible with PC-standard UARTs. The UART port provides

a simplified UART interface to other peripherals or hosts, sup-

porting full-duplex, DMA-supported, asynchronous transfers of

serial data. The UART port includes support for five to

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave

(for frame capture for example). The ADSP-BF592 processor

controls when to read from the video source(s). PPI_FS1 is an

HSYNC output and PPI_FS2 is a VSYNC output.

eight data bits, one or two stop bits, and none, even, or odd par-

ity. The UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

Output Mode

Output mode is used for transmitting video or other data with

up to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

• Active video only mode

• Vertical blanking only mode

• Entire field mode

PARALLEL PERIPHERAL INTERFACE (PPI)

The processor provides a parallel peripheral interface (PPI) that

can connect directly to parallel A/D and D/A converters, video

encoders and decoders, and other general-purpose peripherals.

The PPI consists of a dedicated input clock pin, up to three

frame synchronization pins, and up to 16 data pins. The input

clock supports parallel data rates up to half the system clock rate

and the synchronization signals can be configured as either

inputs or outputs.

Active Video Mode

Active video only mode is used when only the active video por-

tion of a field is of interest and not any of the blanking intervals.

The PPI does not read in any data between the end of active

Rev. PrC

|

Page 9 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

video (EAV) and start of active video (SAV) preamble symbols,

or any data present during the vertical blanking intervals. In this

mode, the control byte sequences are not stored to memory;

they are filtered by the PPI. After synchronizing to the start of

Field 1, the PPI ignores incoming samples until it sees an SAV

code. The user specifies the number of active video lines per

frame (in PPI_COUNT register).

written in order to set pin values, one register is written in

order to clear pin values, one register is written in order to

toggle pin values, and one register is written in order to

specify a pin value. Reading the GPIO status register allows

software to interrogate the sense of the pins.

• GPIO interrupt mask registers – The two GPIO interrupt

mask registers allow each individual GPIO pin to function

as an interrupt to the processor. Similar to the two GPIO

control registers that are used to set and clear individual

pin values, one GPIO interrupt mask register sets bits to

enable interrupt function, and the other GPIO interrupt

mask register clears bits to disable interrupt function.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO inter-

rupt sensitivity registers specify whether individual pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1. Data is transferred to or from the

synchronous channels through eight DMA engines that work

autonomously from the processor core.

TWI CONTROLLER INTERFACE

The processors include a two-wire interface (TWI) module for

providing a simple exchange method of control data between

multiple devices. The TWI is functionally compatible with the

widely used I²C^®bus standard. The TWI module offers the

capabilities of simultaneous master and slave operation, support

for both 7-bit addressing and multimedia data arbitration. The

TWI interface utilizes two pins for transferring clock (SCL) and

data (SDA) and supports the protocol at speeds up to 400K

bits/sec.

DYNAMIC POWER MANAGEMENT

The processor provides five operating modes, each with a differ-

ent performance/power profile. In addition, dynamic power

management provides the control functions to dynamically alter

the processor core supply voltage, further reducing power dissi-

pation. When configured for a 0 volt core supply voltage, the

processor enters the hibernate state. Control of clocking to each

of the processor peripherals also reduces power consumption.

See Table 4 for a summary of the power settings for each mode.

The TWI module is compatible with serial camera control bus

(SCCB) functionality for easier control of various CMOS cam-

era sensor devices.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

PORTS

The processor groups the many peripheral signals to two

ports—Port F and Port G. Most of the associated pins are shared

by multiple signals. The ports function as multiplexer controls.

General-Purpose I/O (GPIO)

Active Operating Mode—Moderate Dynamic Power

Savings

The processor has 32 bidirectional, general-purpose I/O (GPIO)

pins allocated across two separate GPIO modules—PORTFIO

and PORTGIO, associated with Port F and Port G respectively.

Each GPIO-capable pin shares functionality with other proces-

sor peripherals via a multiplexing scheme; however, the GPIO

functionality is the default state of the device upon power-up.

Neither GPIO output nor input drivers are active by default.

Each general-purpose port pin can be individually controlled by

manipulation of the port control, status, and interrupt registers:

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. DMA

access is available to appropriately configured L1 memories.

In the active mode, it is possible to disable the control input to

the PLL by setting the PLL_OFF bit in the PLL control register.

This register can be accessed with a user-callable routine in the

on-chip ROM called bfrom_SysControl(). If disabled, the PLL

control input must be re-enabled before transitioning to the

full-on or sleep modes.

• GPIO direction control register – Specifies the direction of

each individual GPIO pin as input or output.

• GPIO control and status registers – The processor employs

a “write one to modify” mechanism that allows any combi-

nation of individual GPIO pins to be modified in a single

instruction, without affecting the level of any other GPIO

pins. Four control registers are provided. One register is

Rev. PrC

|

Page 10 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

Table 4. Power Settings

preserved. Writing b#0 to the HIBERNATE bit causes

EXT_WAKE to transition low, which can be used to signal an

external voltage regulator to shut down.

Core

Clock

System

Clock

PLL

Core

Since V_DDEXTcan still be supplied in this mode, all of the exter-

nal pins three-state, unless otherwise specified. This allows

other devices that may be connected to the processor to still

have power applied without drawing unwanted current.

The processor can be woken up by asserting the RESET pin or

by a general-purpose flag wake up event. All hibernate wakeup

events initiate the hardware reset sequence. Individual sources

are enabled by the VR_CTL register. The EXT_WAKE signal

indicates the occurrence of a wakeup event.

Mode/State PLL

Bypassed (CCLK) (SCLK) Power

Full On

Active

Enabled No

Enabled Enabled On

Enabled/ Yes

Enabled Enabled On

Disabled

Enabled

Sleep

—

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

Deep Sleep Disabled —

Hibernate Disabled —

For more information about PLL controls, see the “Dynamic

Power Management” chapter in the ADSP-BF59x Blackfin Pro-

cessor Hardware Reference.

As long as V_DDEXTis applied, the VR_CTL register maintains its

state during hibernation. All other internal registers and memo-

ries, however, lose their content in the hibernate state.

Sleep Operating Mode—High Dynamic Power Savings

Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally, an external event wakes up the processor. When in the

sleep mode, asserting a wakeup enabled in the SIC_IWR0 regis-

ters causes the processor to sense the value of the BYPASS bit in

the PLL control register (PLL_CTL). If BYPASS is disabled, the

processor transitions to the full on mode. If BYPASS is enabled,

the processor transitions to the active mode.

As shown in Table 5, the processor supports two different

power domains, which maximizes flexibility while maintaining

compliance with industry standards and conventions. By isolat-

ing the internal logic of the processor into its own power

domain, separate from other I/O, the processor can take advan-

tage of dynamic power management without affecting the other

I/O devices. There are no sequencing requirements for the

various power domains, but all domains must be powered

according to the appropriate Specifications table for processor

operating conditions; even if the feature/peripheral is not used.

System DMA access to L1 memory is not supported in

sleep mode.

Table 5. Power Domains

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

Power Domain

All internal logic and memories

All other I/O

V_DDRange

V_DDINT

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals

may still be running but cannot access internal resources or

external memory. This powered-down mode can only be exited

by assertion of the reset interrupt (RESET) or by an asynchro-

nous interrupt generated by a GPIO pin. Assertion of RESET

while in deep sleep mode causes the processor to transition to

the full on mode. Assertion of a GPIO pin configured for

wakeup (in the VR_CTL register) causes the processor to transi-

tion to active mode, and execution resumes from where the

program counter was when deep sleep mode was entered.

V_DDEXT

The dynamic power management feature of the processor

allows both the processor’s input voltage (V_DDINT) and clock fre-

quency (f_CCLK) to be dynamically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation, while reducing the

voltage by 25% reduces dynamic power dissipation by more

than 40%. Further, these power savings are additive, in that if

the clock frequency and supply voltage are both reduced, the

power savings can be dramatic, as shown in the following

equations.

Note that when a GPIO pin is used to trigger wake from deep

sleep, the programmed wake level must linger for at least 10ns

to guarantee detection.

Hibernate State—Maximum Static Power Savings

Power Savings Factor

The hibernate state maximizes static power savings by disabling

clocks to the processor core (CCLK) and to all of the peripherals

(SCLK) as well as signaling an external voltage regulator that

2

f_CCLKRED

-------------------

f_CCLKNOM

V_DDINTRED

------------------------

V_DDINTNOM

T_RED

-----------

T_NOM

















=

×

V

_DDINTcan be shut off. Any critical information stored inter-

nally (for example, memory contents, register contents, and

other information) must be written to a non-volatile storage

device prior to removing power if the processor state is to be

% Power Savings = (1 – Power Savings Factor) × 100%

where the variables in the equations are:

f

_CCLKNOMis the nominal core clock frequency

Rev. PrC

|

Page 11 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

f

V

_CCLKREDis the reduced core clock frequency

_DDINTNOMis the nominal internal supply voltage

_DDINTREDis the reduced internal supply voltage

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations on multiple

devices over temperature range.

T

_NOMis the duration running at f_CCLKNOM

_REDis the duration running at f_CCLKRED

BLACKFIN

CLKOUT (SCLK)

CLKBUF

VOLTAGE REGULATION

TO PLL CIRCUITRY

EN

The ADSP-BF592 processor requires an external voltage regula-

tor to power the V_DDINTdomain. To reduce standby power

consumption, the external voltage regulator can be signaled

through EXT_WAKE to remove power from the processor core.

This signal is high-true for power-up and may be connected

directly to the low-true shut-down input of many common

regulators.

While in the hibernate state, the external supply, V_DDEXT, can

still be applied, eliminating the need for external buffers. The

external voltage regulator can be activated from this power

down state by asserting the RESET pin, which then initiates a

boot sequence. EXT_WAKE indicates a wakeup to the external

voltage regulator.

The power good (PG) input signal allows the processor to start

only after the internal voltage has reached a chosen level. In this

way, the startup time of the external regulator is detected after

hibernation. For a complete description of the power good

functionality, refer to the ADSP-BF59x Blackfin Processor Hard-

ware Reference.

EN

SELECT

560 ⍀

XTAL

EXTCLK

CLKIN

18 pF *

330 ⍀*

FOR OVERTONE

OPERATION ONLY:

18 pF *

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED

RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.

Figure 4. External Crystal Connections

A third-overtone crystal can be used for frequencies above 25

MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 4. A design procedure for third-overtone oper-

ation is discussed in detail in application note (EE-168) Using

Third Overtone Crystals with the ADSP-218x DSP on the Analog

Devices website (www.analog.com)—use site search on

“EE-168.”

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 5, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable 5× to 64× multiplication

factor (bounded by specified minimum and maximum VCO

frequencies). The default multiplier is 6×, but it can be modified

by a software instruction sequence.

On-the-fly frequency changes can be effected by simply writing

to the PLL_DIV register. The maximum allowed CCLK and

SCLK rates depend on the applied voltages V_DDINTand V_DDEXT

the VCO is always permitted to run up to the frequency speci-

fied by the part’s instruction rate. The CLKOUT pin reflects the

SCLK frequency to the off-chip world. The pin functions as a

reference signal in many timing specifications. While three-

stated by default, it can be enabled using the VRCTL register.

CLOCK SIGNALS

The processor can be clocked by an external crystal, a sine wave

input, or a buffered, shaped clock derived from an external

clock oscillator.

If an external clock is used, it should be a TTL-compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Alternatively, because the processor includes an on-chip oscilla-

tor circuit, an external crystal may be used. For fundamental

frequency operation, use the circuit shown in Figure 4. A paral-

lel-resonant, fundamental frequency, microprocessor-grade

crystal is connected across the CLKIN and XTAL pins. The on-

chip resistance between CLKIN and the XTAL pin is in the

500 kΩ range. Further parallel resistors are typically not recom-

mended. The two capacitors and the series resistor shown in

Figure 4 fine tune phase and amplitude of the sine frequency.

The capacitor and resistor values shown in Figure 4 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

;

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Rev. PrC

|

Page 12 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

In master boot modes, the processor actively loads data from

parallel or serial memories. In slave boot modes, the processor

receives data from external host devices.

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

Table 8. Booting Modes

CCLK

SCLK

÷ TBD

PLL

5ꢀ to 64ꢀ

BMODE2–0 Description

CLKIN

VCO

000

001

010

011

100

101

110

111

Idle/No Boot

÷ TBD

Reserved

SPI1 master boot from Flash, using SPI1_SSEL5 on PG11

SPI1 slave boot from external master

SPI0 master boot from Flash, using SPI0_SSEL2 on PF8

Boot from PPI port

SCLK ꢁ CCLK

Figure 5. Frequency Modification Methods

Boot from UART host device

Execute from Internal L1 ROM

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f_SCLK. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

The boot modes listed in Table 8 provide a number of mecha-

nisms for automatically loading the processor’s internal and

external memories after a reset. By default, all boot modes use

the slowest meaningful configuration settings. Default settings

can be altered via the initialization code feature at boot time.

The BMODE pins of the reset configuration register, sampled

during power-on resets and software-initiated resets, imple-

ment the modes shown in Table 8.

Table 7. Core Clock Ratios

• IDLE State / No Boot (BMODE - 0x0) — In this mode, the

boot kernel transitions the processor into Idle state. The

processor can then be controlled through JTAG for recov-

ery, debug, or other functions.

• SPI1 master boot from flash (BMODE = 0x2) — In this

mode SPI1 is configured to operate in master mode and to

connect to 8-, 16-, 24-, or 32-bit addressable devices. The

processor uses the PG11/SPI1_SSEL5 to select a single SPI

EEPROM/flash device, submits a read command and suc-

cessive address bytes (0×00) until a valid 8-, 16-, 24-, or 32-

bit addressable device is detected, and begins clocking data

into the processor. Pull-up resistors are required on the

SSEL and MISO pins. By default, a value of 0×85 is written

to the SPI_BAUD register.

• SPI1 slave boot from external master (BMODE = 0x3) — In

this mode SPI1 is configured to operate in slave mode and

to receive the bytes of the .LDR file from a SPI host (mas-

ter) agent. To hold off the host device from transmitting

while the boot ROM is busy, the Blackfin processor asserts

a GPIO pin, called host wait (HWAIT), to signal to the host

device not to send any more bytes until the pin is deas-

serted. The host must interrogate the HWAIT signal,

available on PF4, before transmitting every data unit to the

processor. A pull-up resistor is required on the SPI1_SS

input. A pull-down on the serial clock may improve signal

quality and booting robustness.

• SPI0 master boot from flash (BMODE = 0x4) — In this

mode SPI0 is configured to operate in master mode and to

connect to 8-, 16-, 24-, or 32-bit addressable devices. The

processor uses the PF8/SPI0_SSEL2 to select a single SPI

EEPROM/flash device, submits a read command and suc-

cessive address bytes (0×00) until a valid 8-, 16-, 24-, or 32-

Example Frequency Ratios

(MHz)

VCO

300

Signal Name Divider Ratio

CSEL1–0

VCO/CCLK

CCLK

300

150

100

25

00

01

10

11

1:1

2:1

4:1

8:1

300

400

200

Table 6. Example System Clock Ratios

Example Frequency Ratios

(MHz)

Signal Name Divider Ratio

SSEL3–0

VCO/SCLK

VCO

100

300

400

SCLK

50

0010

2:1

0110

6:1

50

1010

10:1

40

The maximum CCLK frequency both depends on the part’s

instruction rate (see Page 45) and depends on the applied

V

_DDINTvoltage. See Table 10 for details. The maximal system

clock rate (SCLK) depends on the chip package and the applied

V_DDINTand V_DDEXTvoltages (see Table 12).

BOOTING MODES

The processor has several mechanisms (listed in Table 8) for

automatically loading internal and external memory after a

reset. The boot mode is defined by the BMODE input pins dedi-

cated to this purpose. There are two categories of boot modes.

Rev. PrC

|

Page 13 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

bit addressable device is detected, and begins clocking data

into the processor. Pull-up resistors are required on the

SSEL and MISO pins. By default, a value of 0×85 is written

to the SPI_BAUD register.

• Boot from PPI host device (BMODE = 0x5) — The proces-

sor operates in PPI slave mode and is configured to receive

the bytes of the LDR file from a PPI host (master) agent.

• Boot from UART host device (BMODE = 0x6) — In this

mode UART0 is used as the booting source. Using an auto-

baud handshake sequence, a boot-stream formatted

program is downloaded by the host. The host selects a bit

rate within the UART clocking capabilities. When per-

forming the autobaud, the UART expects a “@” (0×40)

character (eight bits data, one start bit, one stop bit, no par-

ity bit) on the RXD pin to determine the bit rate. The

UART then replies with an acknowledgment which is com-

posed of 4 bytes (0xBF—the value of UART_DLL) and

(0×00—the value of UART_DLH). The host can then

download the boot stream. To hold off the host the proces-

sor signals the host with the boot host wait (HWAIT)

signal. Therefore, the host must monitor the HWAIT, (on

PF4), before every transmitted byte.

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core

processor resources.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded

in 16 bits.

• Execute from internal L1 ROM (BMODE = 0x7) — In this

mode the processor begins execution from the on-chip 64k

Byte L1 instruction ROM starting at address 0xFFA1 0000.

For each of the boot modes (except Execute from internal L1

ROM), a 16 byte header is first brought in from an external

device. The header specifies the number of bytes to be trans-

ferred and the memory destination address. Multiple memory

blocks may be loaded by any boot sequence. Once all blocks are

loaded, program execution commences from the start of L1

instruction SRAM.

The boot kernel differentiates between a regular hardware reset

and a wakeup-from-hibernate event to speed up booting in the

latter case. Bits 7–4 in the system reset configuration (SYSCR)

register can be used to bypass the boot kernel or simulate a

wakeup-from-hibernate boot in case of a software reset.

The boot process can be further customized by “initialization

code.” This is a piece of code that is loaded and executed prior to

the regular application boot. Typically, this is used to speed up

booting by managing the PLL, clock frequencies, or serial bit

rates.

The boot ROM also features C-callable functions that can be

called by the user application at run time. This enables second

stage boot or boot management schemes to be implemented

with ease.

DEVELOPMENT TOOLS

The processor is supported with a complete set of

CROSSCORE® software and hardware development tools,

including Analog Devices emulators and VisualDSP++® devel-

opment environment. The same emulator hardware that

supports other Blackfin processors also fully emulates the

ADSP-BF592 processor.

EZ-KIT Lite® Evaluation Board

For evaluation of the ADSP-BF592 processor, use the EZ-KIT

Lite boards soon to be available from Analog Devices. When

these evaluation kits are available, order using part number

ADZS-BF592-EZLITE. The boards come with on-chip emula-

tion capabilities and are equipped to enable software

development. Multiple daughter cards will be available.

DESIGNING AN EMULATOR-COMPATIBLE

PROCESSOR BOARD (TARGET)

The Analog Devices family of emulators are tools that every sys-

tem developer needs in order to test and debug hardware and

software systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG processor. The

emulator uses the TAP to access the internal features of the pro-

cessor, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers. The

processor must be halted to send data and commands, but once

an operation has been completed by the emulator, the processor

system is set running at full speed with no impact on

system timing.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

Rev. PrC

|

Page 14 of 46

|

August 2010

Preliminary Technical Data

ADSP-BF592

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see (EE-68) Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.


型号：	ADSP-BF592KCPZ-X
厂家：	ADI
描述：	Blackfin Embedded Processor Blackfin嵌入式处理器微控制器和处理器外围集成电路数字信号处理器时钟
文件：	总46页 (文件大小：1668K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF592KCPZ-X [ADI]

相关型号：

ADSP-BF606

ADSP-BF606BBCZ-4

ADSP-BF606KBCZ-4

ADSP-BF607

ADSP-BF607BBCZ-5

ADSP-BF607KBCZ-5

ADSP-BF608

ADSP-BF608BBCZ-5

ADSP-BF608KBCZ-5

ADSP-BF609

ADSP-BF609BBCZ-5

ADSP-BF609KBCZ-5