ADUM1402BRWZ [ADI]
Quad-Channel Digital Isolators; 四通道数字隔离器
| 型号： | ADUM1402BRWZ |
| 厂家： | 
ADI |
| 描述： | Quad-Channel Digital Isolators |
| 文件： | 总24页 (文件大小：1271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad-Channel Digital Isolators
ADuM1400/ADuM1401/ADuM1402
GENERAL DESCRIPTION
FEATURES
Low power operation
5 V operation
The ADuM140x are 4-channel digital isolators based on Analog
Devices’ iCoupler® technology. Combining high speed CMOS
and monolithic air core transformer technology, these isolation
components provide outstanding performance characteristics
superior to alternatives such as optocoupler devices.
1.0 mA per channel max @ 0 Mbps to 2 Mbps
3.5 mA per channel max @ 10 Mbps
31 mA per channel max @ 90 Mbps
3 V operation
0.7 mA per channel max @ 0 Mbps to 2 Mbps
2.1 mA per channel max @ 10 Mbps
20 mA per channel max @ 90 Mbps
Bidirectional communication
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discretes
is eliminated with these iCoupler products. Furthermore,
iCoupler devices consumes one-tenth to one-sixth the power of
optocouplers at comparable signal data rates.
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns max pulse-width distortion
2 ns max channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
The ADuM140x isolators provide four independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). All models operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In
addition, the ADuM140x provides low pulse-width distortion
(<2 ns for CRW grade) and tight channel-to-channel matching
(<2 ns for CRW grade). Unlike other optocoupler alternatives,
the ADuM140x isolators have a patented refresh feature that
ensures dc correctness in the absence of input logic transitions
and during power-up/power-down conditions.
Wide body 16-lead SOIC package, Pb-free models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
VDE certificate of conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
VIORM = 560 V peak
APPLICATIONS
General-purpose multichannel isolation
SPI® interface/data converter isolation
RS-232/RS-422/RS-485 transceiver
Industrial field bus isolation
FUNCTIONAL BLOCK DIAGRAMS
1
2
3
4
5
6
7
8
16
1
2
3
16
15
14
1
2
3
4
5
6
7
8
16
V
V
V
V
V
V
DD1
DD2
DD1
DD2
DD1
DD2
GND
15 GND
GND
GND
2
GND
15 GND
2
1
IA
IB
IC
2
1
IA
IB
IC
1
IA
IB
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
14
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
14
13
12
11
10
9
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OA
OB
OC
OD
E2
OA
OB
OC
ID
OA
OB
IC
13
12
11
10
9
4
5
6
7
8
13
12
11
10
9
V
V
OC
OD
V
V
OD
ID
NC
GND
ID
V
V
E1
E2
E1
E2
GND
2
GND
GND
2
GND
GND
2
1
1
1
Figure 1. ADuM1400 Functional Block Diagram
Figure 2. ADuM1401 Functional Block Diagram
Figure 3. ADuM1402 Functional Block Diagram
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADuM1400/ADuM1401/ADuM1402
TABLE OF CONTENTS
Specifications..................................................................................... 3
ESD Caution................................................................................ 14
Pin Configurations and Pin Function Descriptions.................. 15
Typical Performance Characteristics ........................................... 17
Application Information................................................................ 19
PC Board Layout ........................................................................ 19
Propagation Delay-Related Parameters................................... 19
DC Correctness and Magnetic Field Immunity........................... 19
Power Consumption .................................................................. 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 8
Package Characteristics ............................................................. 12
Regulatory Information............................................................. 12
Insulation and Safety-Related Specifications.......................... 12
DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics ............................................................................ 13
Recommended Operating Conditions .................................... 13
Absolute Maximum Ratings.......................................................... 14
REVISION HISTORY
6/04—Data Sheet Changed from Rev. A to Rev. B.
Changes to Format .............................................................Universal
Changes to Features.......................................................................... 1
Changes to Electrical Characteristics—5 V Operation ............... 3
Changes to Electrical Characteristics—3 V Operation ............... 5
Changes to Electrical Characteristics—Mixed 5 V/3 V or
3 V/5 V Operation ............................................................................ 7
Changes to DIN EN 60747-5-2 (VDE 0884 Part 2)
Insulation Characteristics Title..................................................... 11
Changes to the Ordering Guide.................................................... 19
5/04—Data Sheet Changed from Rev. 0 to Rev. A.
Updated Format..................................................................Universal
Changes to the Features................................................................... 1
Changes to Table 7 and Table 8..................................................... 14
Changes to Table 9.......................................................................... 15
Changes to the DC Correctness and Magnetic Field Immunity
Section.............................................................................................. 20
Changes to the Power Consumption Section ............................. 21
Changes to the Ordering Guide.................................................... 22
9/03—Revision 0: Initial Version.
Rev. B | Page 2 of 24
ADuM1400/ADuM1401/ADuM1402
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless other-
wise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
Output Supply Current, per Channel, Quiescent
ADuM1400, Total Supply Current, Four Channels2
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.50 0.53 mA
0.19 0.21 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
2.2
0.9
2.8
1.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
8.6
2.6
10.6 mA
3.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
76
21
100 mA
45 MHz logic signal freq.
45 MHz logic signal freq.
25
mA
ADuM1401, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.8
1.2
2.4
1.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
7.1
4.1
9.0
5.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
62
35
82
43
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1402, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
IDD1 (90), IDD2 (90)
1.5
5.6
49
2.1
7.0
62
mA
mA
mA
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
45 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH, VODH
–10
2.0
+0.01 +10 µA
V
0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.8
V
V
,
VDD1
VDD2 – 0.1
VDD1
VDD2 – 0.4
,
5.0
4.8
0.0
0.04 0.1
0.2 0.4
IOx = –20 µA, VIx = VIxH
IOx = –4 mA, VIx = VIxH
,
V
Logic Low Output Voltages
VOAL, VOBL
,
0.1
V
V
V
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
V
OCL, VODL
Rev. B | Page 3 of 24
ADuM1400/ADuM1401/ADuM1402
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
65
5
Pulse-Width Distortion, |tPLH – tPHL
Propagation Delay Skew6
Channel-to-Channel Matching7
ADuM140xBRW
|
40
50
50
ns
ns
ns
tPSKCD/OD
Minimum Pulse Width3
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
10
20
Propagation Delay5
tPHL, tPLH
PWD
32
5
50
3
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
15
3
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
ADuM140xCRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
27
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
18
Propagation Delay5
tPHL, tPLH
PWD
32
2
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
10
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output8
t
PHZ, tPLH
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
tPZH, tPZL
tR/tF
|CMH|
2.5
35
ns
kV/µs
25
25
Common-Mode Transient Immunity
at Logic Low Output8
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current, per Channel9
Output Dynamic Supply Current, per Channel9
IDDI (D)
IDDO (D)
0.19
0.05
mA/Mbps
mA/Mbps
See Notes on next page.
Rev. B | Page 4 of 24
ADuM1400/ADuM1401/ADuM1402
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on
Page 20. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11
through Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 20 for guidance on calculating the per-channel sup-
ply current for a given data rate.
Rev. B | Page 5 of 24
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—3 V OPERATION1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless other-
wise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
Output Supply Current, per Channel, Quiescent
ADuM1400, Total Supply Current, Four Channels2
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.26 0.31 mA
0.11 0.14 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.2
0.5
1.9 mA
0.9 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
4.5
1.4
6.5 mA
2.0 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
42
11
65
15
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1401, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.0
0.7
1.6 mA
1.2 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
3.7
2.2
5.4 mA
3.0 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
34
19
52
27
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1402, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
IDD1 (90), IDD2 (90)
0.9
3.0
27
1.5 mA
4.2 mA
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
39
mA
45 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH, VODH
–10
1.6
+0.01 +10 µA
V
0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or
V
DD2, 0 ≤ VE1,VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.4
V
V
V
V
V
V
,
VDD1, VDD2 – 0.1 3.0
VDD1, VDD2 – 0.4 2.8
0.0
IOx = –20 µA, VIx = VIxH
IOx = –4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.1
0.04 0.1
0.2
0.4
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
75
5
Pulse-Width Distortion, |tPLH – tPHL
|
40
50
50
ns
ns
ns
Propagation Delay Skew6
Channel-to-Channel Matching7
tPSKCD/OD
Rev. B | Page 6 of 24
ADuM1400/ADuM1401/ADuM1402
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
ADuM140xBRW
Minimum Pulse Width3
PW
100 ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
10
20
Propagation Delay5
tPHL, tPLH
PWD
38
5
50
3
ns
ns
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ps/°C
ns
ns
tPSK
tPSKCD
22
3
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
ADuM140xCRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
34
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
20
Propagation Delay5
tPHL, tPLH
PWD
45
2
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
16
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
tPHZ, tPLH
tPZH, tPZL
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
Common-Mode Transient Immunity
at Logic High Output8
Common-Mode Transient Immunity
at Logic Low Output8
|CMH|
25
25
35
kV/µs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current, per Channel9 IDDI (D)
Output Dynamic Supply Current, per Channel9 IDDO (D)
0.10
0.03
mA/Mbps
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on
Page 20. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11
through Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 20 for guidance on calculating the per-channel sup-
ply current for a given data rate.
Rev. B | Page 7 of 24
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all min/max
specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at
TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V.
Table 3.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent IDDI (Q)
5 V/3 V Operation
3 V/5 V Operation
0.50
0.26
0.53 mA
0.31 mA
Output Supply Current, per Channel, Quiescent IDDO (Q)
5 V/3 V Operation
3 V/5 V Operation
ADuM1400, Total Supply Current, Four Channels2
0.11
0.19
0.14 mA
0.21 mA
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
2.2
1.2
2.8 mA
1.9 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.5
0.9
0.9 mA
1.4 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
8.6
4.5
10.6 mA
6.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
1.4
2.6
2.0 mA
3.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (90)
76
42
100 mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
65
mA
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
11
21
15
25
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1401, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
1.8
1.0
2.4 mA
1.6 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.7
1.2
1.2 mA
1.8 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
7.1
3.7
9.0 mA
5.4 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
2.2
4.1
3.0 mA
5.0 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
Rev. B | Page 8 of 24
ADuM1400/ADuM1401/ADuM1402
Parameter
90 Mbps (CRW Grade Only)
Symbol
Min
Typ
Max Unit
Test Conditions
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (90)
62
34
82
52
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
19
35
27
43
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1402, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
1.5
0.9
2.1 mA
1.5 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.9
1.5
1.5 mA
2.1 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
5.6
3.0
7.0 mA
4.2 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
3.0
5.6
4.2 mA
7.0 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (90)
49
27
62
39
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
27
49
39
62
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
–10
+0.01
+10 µA
0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or
V
DD2, 0 ≤ VE1,VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIH, VEH
2.0
1.6
V
V
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIL, VEL
0.8
0.4
V
V
V
Logic High Output Voltages
VOAH, VOBH
,
VDD1
/
VDD1/VDD2
IOx = –20 µA, VIx = VIxH
IOx = –4 mA, VIx = VIxH
VOCH, VODH
VDD2 – 0.1
VDD1
/
VDD1
/
V
V
DD2 – 0.4
VDD2 – 0.2
Logic Low Output Voltages
VOAL, VOBL,
VOCL, VODL
0.0
0.04
0.2
0.1
0.1
0.4
V
V
V
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
70
5
Pulse-Width Distortion, |tPLH – tPHL
|
40
50
50
ns
ns
ns
Propagation Delay Skew6
Channel-to-Channel Matching7
tPSKCD/OD
Rev. B | Page 9 of 24
ADuM1400/ADuM1401/ADuM1402
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
ADuM140xBRW
Minimum Pulse Width3
PW
100 ns
Mbps
CL = 15 pF,CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
10
15
Propagation Delay5
tPHL, tPLH
PWD
35
5
50
3
ns
ns
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ps/°C
ns
ns
tPSK
tPSKCD
22
3
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
ADuM140xCRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
30
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
20
Propagation Delay5
tPHL, tPLH
PWD
40
2
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
14
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient Immunity
at Logic High Output8
Common-Mode Transient Immunity
at Logic Low Output8
tPHZ, tPLH
tPZH, tPZL
tR/tf
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
3.0
2.5
35
ns
ns
kV/µs
|CMH|
|CML|
fr
25
25
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
35
kV/µs
transient magnitude = 800 V
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Dynamic Supply Current, per Channel9
1.2
1.1
Mbps
Mbps
IDDI (D)
5 V/3 V Operation
3 V/5 V Operation
0.19
0.10
mA/Mbps
mA/Mbps
Output Dynamic Supply Current, per Channel9 IDDI (D)
5 V/3 V Operation
3 V/5 V Operation
0.03
0.05
mA/Mbps
mA/Mbps
See Notes on next page.
Rev. B | Page 10 of 24
ADuM1400/ADuM1401/ADuM1402
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 20. See Figure 8
through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 14 for total IDD1 and
I
DD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured
from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides
of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be
sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range
over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-
channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 20 for guidance on calculating the per-channel supply current for a
given data rate.
Rev. B | Page 11 of 24
ADuM1400/ADuM1401/ADuM1402
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Symbol
RI-O
CI-O
CI
θJCI
Min
Typ
1012
2.2
4.0
33
Max
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions
Resistance (Input-Output)1
Capacitance (Input-Output)1
Input Capacitance2
f = 1 MHz
IC Junction-to-Case Thermal Resistance, Side 1
IC Junction-to-Case Thermal Resistance, Side 2
Thermocouple located
at center of package
underside
θJCO
28
1 Device considered a 2-terminal device; Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM140x have been approved by the organizations listed in Table 5.
Table 5.
UL1
CSA
VDE2
Recognized under 1577
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN EN 60747-5-2
(VDE 0884 Part 2): 2003-012
component recognition program1
Double insulation, 2500 V rms
isolation voltage
Reinforced insulation per
CSA 60950-1-03 and IEC 60950-1,
400 V rms maximum working voltage
Basic insulation, 560 V peak
Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-
01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000
Reinforced insulation, 560 V peak
File 205078
File E214100
File 2471900-4880-0001
1 In accordance with UL1577, each ADuM140x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA).
2 In accordance with DIN EN 60747-5-2, each ADuM140x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection
limit = 5 pC). A “*” mark branded on the component designates DIN EN 60747-5-2 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Symbol
Value
Unit
Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
V rms
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
L(I01)
L(I02)
8.40 min mm
8.10 min mm
0.017 min mm
>175
IIIa
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index) CTI
Isolation Group
V
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. B | Page 12 of 24
ADuM1400/ADuM1401/ADuM1402
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
Table 7.
Description
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b1
I–IV
I–III
I–II
40/105/21
2
VIORM
VPR
560
1050
V peak
V peak
V
IORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a
After Environmental Tests Subgroup 1
VPR
896
V peak
V peak
V peak
V
IORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/3
IORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
672
V
Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec)
VTR
4000
Safety-Limiting Values (Maximum value allowed in the event of a failure; also see
Thermal Derating Curve, Figure 4)
Case Temperature
Side 1 Current
Side 2 Current
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
Insulation Resistance at TS, VIO = 500 V
This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protec-
tive circuits.
The * marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage.
350
RECOMMENDED OPERATING CONDITIONS
300
Table 8.
250
Parameter
Symbol
Min Max Unit
SIDE #2
Operating Temperature
Supply Voltages1
Input Signal Rise and Fall Times
TA
–40 +105 °C
200
150
100
50
VDD1, VDD 2 2.7
5.5
1.0
V
ms
SIDE #1
1 All voltages are relative to their respective ground.
See the DC Correctness and Magnetic Field Immunity section on Page 19 for
information on immunity to external magnetic fields.
0
0
50
100
CASE TEMPERATURE (°C)
150
200
Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. B | Page 13 of 24
ADuM1400/ADuM1401/ADuM1402
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 9.
Parameter
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
Max
Unit
°C
°C
V
V
V
Storage Temperature
Ambient Operating Temperature
Supply Voltages1
Input Voltage1, 2
Output Voltage1, 2
Average Output Current, Per Pin3
Side 1
TST
TA
+150
+105
+7.0
VDDI + 0.5
VDDO + 0.5
VDD1, VDD2
VIA, VIB, VIC, VID, VE1,VE2
VOA, VOB, VOC, VOD
IO1
IO2
–18
–22
–100
+18
+22
+100
mA
mA
kV/µs
Side 2
Common-Mode Transients4
1 All voltages are relative to their respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section.
3 See Figure 4 for maximum rated current values for various temperatures.
4 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or perma-
nent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Table 10. Truth Table (Positive Logic)
VIX Input1
VEX Input2 VDDI State1 VDDO State1 VOX Output1 Notes
H
L
X
X
H or NC
H or NC
L
Powered
Powered
Powered
Powered
Powered
Powered
H
L
Z
H
H or NC
Unpowered Powered
Outputs return to the input state within 1 µs of VDDI power
restoration.
X
X
L
X
Unpowered Powered
Z
Powered
Unpowered Indeterminate Outputs return to the input state within 1 µs of VDDO power
restoration if VEX state is H or NC. Outputs returns to high impedance
state within 8 ns of VDDO power restoration if VEX state is L.
1 VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEX to an external logic high or low is recommended.
Rev. B | Page 14 of 24
ADuM1400/ADuM1401/ADuM1402
PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS
V
V
V
V
DD2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
DD2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DD1
DD2
DD1
DD1
*GND
V
GND *
2
*GND
V
GND *
2
*GND
V
GND *
2
1
1
ADuM1401
TOP VIEW
(Not to Scale)
ADuM1402
TOP VIEW
(Not to Scale)
1
ADuM1400
TOP VIEW
(Not to Scale)
V
V
V
IA
IB
IC
OA
IA
IB
OA
IA
IB
IC
ID
OA
V
V
V
V
V
V
V
V
V
OB
OB
OB
V
V
V
V
V
OC
OC
IC
OC
V
V
V
V
OD
ID
OD
ID
OD
V
V
V
V
NC
*GND
V
E1
*GND
E2
E1
*GND
E2
E2
GND *
2
GND *
2
GND *
2
1
1
1
NC = NO CONNECT
Figure 6. ADuM1401 Pin Configuration
Figure 7. ADuM1402 Pin Configuration
Figure 5. ADuM1400 Pin Configuration
*Pins 2 and 8 are internally connected. Connecting both to GND1 is recommended. Pins 9 and 15 are internally connected. Connecting both to GND2 is recommended.
Output enable Pin 10 on the ADuM1400 may be left disconnected if outputs are to be always enabled. Output enable Pins 7 and 10 on the ADuM1401/ADuM1402
may be left disconnected if outputs are to be always enabled. In noisy environments, connecting Pin 7 (for ADuM1401 and ADuM1402) and Pin 10 (for all models) to
an external logic high or low is recommended.
Table 11. ADuM1400 Pin Function Descriptions
Pin
No. Mnemonic Function
1
2
3
4
5
6
7
8
9
VDD1
GND1
VIA
VIB
VIC
VID
NC
GND1
GND2
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
No Connect.
Ground 1. Ground reference for isolator Side 1.
Ground 2. Ground reference for isolator Side 2.
10 VE2
Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected. VOA, VOB, VOC, and
VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.
11 VOD
12 VOC
13 VOB
14 VOA
15 GND2
16 VDD2
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. B | Page 15 of 24
ADuM1400/ADuM1401/ADuM1402
Table 12. ADuM1401 Pin Function Descriptions
Pin
No. Mnemonic Function
1
2
3
4
5
6
7
VDD1
GND1
VIA
VIB
VIC
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
VOD
VE1
Logic Output D.
Output Enable 1. Active high logic input. VOD output is enabled when VE1 ishigh or disconnected. VOD is disabled when VE1 is low. In
noisy environments, connecting VE1 to an external logic high or low is recommended.
8
9
GND1
GND2
Ground 1. Ground reference for isolator Side 1.
Ground 2. Ground reference for isolator Side 2.
10 VE2
Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 ishigh or disconnected. VOA, VOB, and VOC
outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.
11 VID
Logic Input D.
12 VOC
13 VOB
14 VOA
15 GND2
16 VDD2
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for isolator Side 2.
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Table 13. ADuM1402 Pin Function Descriptions
Pin
No. Mnemonic Function
1
2
3
4
5
6
7
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for isolator Side 1.
Logic Input A.
Logic Input B.
Logic Output C.
VIB
VOC
VOD
VE1
Logic Output D.
Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 ishigh or disconnected. VOC and VOD outputs are
disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.
8
9
GND1
GND2
Ground 1. Ground reference for isolator Side 1.
Ground 2. Ground reference for isolator Side 2.
10 VE2
Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 ishigh or disconnected. VOA and VOB outputs are
disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.
11 VID
Logic Input D.
12 VIC
Logic Input C.
13 VOB
14 VOA
15 GND2
16 VDD2
Logic Output B.
Logic Output A.
Ground 2. Ground Reference for Isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. B | Page 16 of 24
ADuM1400/ADuM1401/ADuM1402
TYPICAL PERFORMANCE CHARACTERISTICS
20
80
70
60
50
40
30
20
10
0
15
10
5V
5V
3V
3V
5
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 8. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation
Figure 11. Typical ADuM1400 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
6
5
4
3
20
15
10
10
5V
5V
2
3V
3V
5
1
0
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 9. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
Figure 12. Typical ADuM1400 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
10
50
30
25
20
15
8
6
4
5V
5V
10
3V
3V
2
5
0
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 10. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
Figure 13. Typical ADuM1401 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. B | Page 17 of 24
ADuM1400/ADuM1401/ADuM1402
40
35
30
25
40
35
30
25
20
3V
5V
15
10
3V
5V
5
0
–50
–25
0
25
50
75
100
0
20
40
60
80
100
TEMPERATURE (°C)
DATA RATE (Mbps)
Figure 16. Propagation Delay vs. Temperature, C Grade
Figure 14. Typical ADuM1401 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
50
45
40
35
30
25
20
15
5V
3V
10
5
0
0
20
40
60
80
100
DATA RATE (Mbps)
Figure 15. Typical ADuM1402 VDD1 or VDD2 Supply Current vs.
Data Rate for 5 V and 3 V Operation
Rev. B | Page 18 of 24
ADuM1400/ADuM1401/ADuM1402
APPLICATION INFORMATION
PC BOARD LAYOUT
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
The ADuM140x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins
(Figure 17). Bypass capacitors are most conveniently connected
between Pins 1 and 2 for VDD1 and between Pins 15 and 16 for
VDD2. The capacitor value should be between 0.01 µF and 0.1 µF.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. Bypass-
ing between Pins 1 and 8 and between Pins 9 and 16 should also
be considered unless the ground pair on each package side is
connected close to the package.
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 2 µs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than about 5 µs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 10)
by the watchdog timer circuit.
V
GND
V
DD1
DD2
GND
The limitation on the ADuM140x’s magnetic field immunity is
set by the condition in which induced voltage in the transformer’s
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this may occur. The 3 V operating condition of the
ADuM140x is examined because it represents the most
susceptible mode of operation.
1
IA
IB
2
V
V
V
V
V
V
V
OA
OB
V
V
IC/OC
ID/OD
OC/IC
OD/ID
E2
V
E1
GND
GND
2
1
Figure 17. Recommended Printed Circuit Board Layout
The pulses at the transformer output have an amplitude greater than
1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore
establishing a 0.5 V margin in which induced voltages can be toler-
ated. The voltage induced across the receiving coil is given by
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isola-
tion barrier is minimized. Furthermore, the board layout should
be designed such that any coupling that does occur equally
affects all pins on a given component side. Failure to ensure this
could cause voltage differentials between pins exceeding the
device’s Absolute Maximum Ratings, thereby leading to latch-up
or permanent damage.
2
V = (–dβ/dt)∑∏rn ; n = 1, 2,…, N
where:
β is magnetic flux density (gauss).
PROPAGATION DELAY-RELATED PARAMETERS
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propaga-
tion delay to a logic low output may differ from the propagation
delay to a logic high.
Given the geometry of the receiving coil in the ADuM140x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 19.
INPUT (V
IX
)
50%
tPLH
tPHL
100.000
10.000
1.000
OUTPUT (V
)
50%
OX
Figure 18. Propagation Delay Parameters
Pulse-width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
0.100
Channel-to-channel matching refers to the maximum that
amount the propagation delay differs between channels within a
single ADuM140x component.
0.010
0.001
Propagation delay skew refers to the maximum that amount the
propagation delay differs between multiple ADuM140x compo-
nents operating under the same conditions.
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 19. Maximum Allowable External Magnetic Flux Density
Rev. B | Page 19 of 24
ADuM1400/ADuM1401/ADuM1402
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
POWER CONSUMPTION
The supply current at a given channel of the ADuM140x isola-
tor is a function of the supply voltage, the channel’s data rate,
and the channel’s output load.
For each input channel, the supply current is given by
I
I
DDI = IDDI (Q)
f ≤ 0.5fr
f > 0.5fr
DDI = IDDI (D) × (2f – fr) + IDDI (Q)
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM140x trans-
formers. Figure 20 expresses these allowable current magnitudes as
a function of frequency for selected distances. As seen, the
ADuM140x is extremely immune and can be affected only by ex-
tremely large currents operated at high frequency, very close to the
component. For the 1 MHz example noted, one would have to place
a 0.5 kA current 5 mm away from the ADuM140x to affect the
component’s operation.
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5fr
I
DDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f – fr) + IDDO (Q)
f > 0.5fr
where:
1000.00
I
DDI (D), IDDO (D) are the input and output dynamic supply currents
DISTANCE = 1m
per channel (mA/Mbps).
100.00
CL is output load capacitance (pF).
V
DDO is the output supply voltage (V).
10.00
DISTANCE = 100mm
f is the input logic signal frequency (MHz, half of the input data
1.00
rate, NRZ signaling).
DISTANCE = 5mm
fr is the input stage refresh rate (Mbps).
0.10
0.01
I
DDI (Q), IDDO (Q) are the specified input and output quiescent sup-
ply currents (mA).
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
To calculate the total IDD1 and IDD2 supply current, the supply
currents for each input and output channel corresponding to
IDD1 and IDD2 are calculated and totaled. Figure 8 and Figure 9
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 10 provides per-
channel supply current as a function of data rate for a 15 pF
output condition. Figure 11 through Figure 14 provide total
IDD1 and IDD2 supply current as a function of data rate for
ADuM1400/ADuM1401/ADuM1402 channel configurations.
Figure 20. Maximum Allowable Current
for Various Current-to-ADuM140x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
thresholds of succeeding circuitry. Care should be taken in the
layout of such traces to avoid this possibility.
Rev. B | Page 20 of 24
ADuM1400/ADuM1401/ADuM1402
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.75 (0.0295)
× 45°
2.65 (0.1043)
2.35 (0.0925)
0.25 (0.0098)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 21. 16-Lead Standard Small Outline Package [SOIC]
Wide Body (RW-16)
Dimension shown in millimeters (inches)
ORDERING GUIDE
Number of Number of Maximum Maximum
Maximum
Inputs,
VDD1 Side
Inputs,
VDD2 Side
Data Rate Propagation
(Mbps) Delay, 5 V (ns) Distortion (ns) Temperature Range (°C)
Pulse-Width
Package
Option1
Model
ADuM1400ARW2
ADuM1400BRW2
ADuM1400CRW2
ADuM1400ARWZ2, 3
ADuM1400BRWZ2, 3
ADuM1400CRWZ2, 3
ADuM1401ARW2
ADuM1401BRW2
ADuM1401CRW2
ADuM1401ARWZ2, 3
ADuM1401BRWZ2, 3
ADuM1401CRWZ2, 3
ADuM1402ARW2
ADuM1402BRW2
ADuM1402CRW2
ADuM1402ARWZ2, 3
ADuM1402BRWZ2, 3
ADuM1402CRWZ2, 3
4
0
1
100
50
32
100
50
32
40
3
2
40
3
2
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
4
4
4
4
4
3
3
3
3
3
3
2
2
2
2
2
2
0
0
0
0
0
1
1
1
1
1
1
2
2
2
2
2
2
10
90
1
10
90
1
10
90
1
10
90
1
10
90
1
10
90
100
50
32
100
50
32
40
3
2
40
3
2
100
50
32
100
50
32
40
3
2
40
3
2
1 RW-16 = 16-lead wide body SOIC.
2 Tape and reel are available. The addition of an “-RL” suffix designates a 13” (1,000 units) tape and reel option.
3 Z = Pb-free part.
Rev. B | Page 21 of 24
ADuM1400/ADuM1401/ADuM1402
NOTES
Rev. B | Page 22 of 24
ADuM1400/ADuM1401/ADuM1402
NOTES
Rev. B | Page 23 of 24
ADuM1400/ADuM1401/ADuM1402
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective owners.
C03786–0–6/04(B)
Rev. B | Page 24 of 24
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