ADV202BBCZRL-115 [ADI]
JPEG2000 Video Codec; JPEG2000视频编解码器
| 型号： | ADV202BBCZRL-115 |
| 厂家： | 
ADI |
| 描述： | JPEG2000 Video Codec |
| 文件： | 总40页 (文件大小：447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JPEG2000 Video Codec
ADV202
Data Sheet
FEATURES
APPLICATIONS
Complete single-chip JPEG2000 compression and
decompression solution for video and still images
Patented SURF® (spatial ultra-efficient recursive filtering)
technology enables low power and low cost wavelet-
based compression
Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Digital cinema systems
Supports both 9/7 and 5/3 wavelet transforms with up to
6 levels of transform
Professional video editing and recording
Digital still cameras
Programmable tile/image size with widths up to 2048 pixels in
3-component 4:2:2 interleaved mode, and up to 4096 pixels
in single-component mode
Digital camcorders
GENERAL DESCRIPTION
The ADV202 is a single-chip JPEG2000 codec targeted for
video and high bandwidth image compression applications that
can benefit from the enhanced quality and feature set provided
by the JPEG2000 (J2K)—ISO/IEC15444-1 image compression
standard. The part implements the computationally intensive
operations of the JPEG2000 image compression standard as well
as providing fully compliant code-stream generation for most
applications.
Maximum tile/image width: 4096 pixels
Video interface directly supporting ITU.R-BT656,
SMPTE125M PAL/ NTSC, SMPTE274M, SMPTE293M (525p),
ITU.R-BT1358 (625p) or any video format with a maximum
input rate of 65 MSPS for irreversible mode or 40 MSPS for
reversible mode
Two or more ADV202s can be combined to support full-
frame SMPTE274M HDTV (1080i) or SMPTE296M (720p)
Flexible asynchronous SRAM-style host interface allows
glueless connection to most 16-/32-bit microcontrollers
and ASICs
The ADV202’s dedicated video port provides glueless connection
to common digital video standards such as ITU.R-BT656,
SMPTE125M, SMPTE293M (525p), ITU.R-BT1358 (625p),
SMPTE274M (1080i), or SMPTE296M (720p). A variety of other
high speed, synchronous pixel and video formats can also be sup-
ported using the programmable framing and validation signals.
2.5 V to 3.3 V I/O and 1.5 V core supply
12 mm × 12 mm 121-lead CSPBGA, speed grade 115 MHz, or
13 mm × 13 mm 144-lead CSPBGA, speed grade 135 MHz, or
13 mm × 13 mm 144-lead CSPBGA, speed grade 150 MHz
(continued on Page 4)
FUNCTIONAL BLOCK DIAGRAM
ADV202
WAVELET
ENGINE
PIXEL I/F
HOST I/F
EC1
EC2
EC3
PIXEL I/F
EXTERNAL
DMA CTRL
PIXEL FIFO
INTERNAL BUS AND DMA ENGINE
CODE FIFO
ATTR FIFO
EMBEDDED
RISC
PROCESSOR
SYSTEM
RAM
ROM
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.
ADV202
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Embedded Processor System.................................................... 26
Memory System.......................................................................... 26
Internal DMA Engine................................................................ 26
ADV202 Interface........................................................................... 27
Video Interface (VDATA Bus).................................................. 27
Host Interface (HDATA Bus) ................................................... 27
Direct and Indirect Registers.................................................... 27
Control Access Registers ........................................................... 27
Pin Configuration and Bus Sizes/Modes ................................ 28
Stage Register.............................................................................. 28
JDATA Mode............................................................................... 28
External DMA Engine ............................................................... 28
Internal Registers............................................................................ 29
Direct Registers........................................................................... 29
Indirect Registers........................................................................ 30
PLL ............................................................................................... 31
Hardware Boot............................................................................ 31
Video Input Formats ...................................................................... 32
Applications..................................................................................... 34
Encode—Multichip Mode......................................................... 34
Decode—Multichip Master/Slave............................................ 35
Digital Still Camera/Camcorder .............................................. 35
Encode/Decode SDTV Video Application ............................. 36
ASIC Application (32-Bit Host/32-Bit ASIC)......................... 37
HIPI (Host Interface—Pixel Interface) ................................... 38
JDATA Interface ......................................................................... 38
Outline Dimensions....................................................................... 39
Ordering Guide .......................................................................... 40
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
JPEG2000 Feature Support.......................................................... 4
Specifications..................................................................................... 5
Supply Voltages and Current ...................................................... 5
Input/Output Specifications........................................................ 5
RESET
Clock and
Specifications ................................................ 6
Normal Host Mode—Read Operation ...................................... 7
Normal Host Mode—Write Operation ..................................... 8
DREQ DACK
/
DMA Mode—Single FIFO Write Operation.. 9
DMA Mode—Single FIFO Read Operation . 11
/
DREQ DACK
External DMA Mode—FIFO Write, Burst Mode .................. 13
External DMA Mode—FIFO Read, Burst Mode ................... 14
Streaming Mode (JDATA)—FIFO Read/Write...................... 16
VDATA Mode Timing............................................................... 17
Raw Pixel Mode Timing ............................................................ 18
Absolute Maximum Ratings.......................................................... 19
Thermal Resistance .................................................................... 19
ESD Caution................................................................................ 19
Pin BGA Assignments and Function Descriptions ................... 20
Pin BGA Assignments ............................................................... 20
Pin Function Descriptions ........................................................ 23
Theory of Operation ...................................................................... 26
Wavelet Engine ........................................................................... 26
Entropy Codecs........................................................................... 26
Rev. D | Page 2 of 40
Data Sheet
ADV202
REVISION HISTORY
1/12—Rev. C to Rev. D
Changes to Pin BGA Assignments and Function
Descriptions Section.......................................................................20
Changes to ADV202 Interface Section ........................................27
Changes to Table 19 ........................................................................29
Changes to Indirect Registers Section..........................................30
Changes to PLL Section..................................................................31
Changes to Table 23 ........................................................................31
Changes to Video Input Formats Section ....................................32
Changes to Figure 24 ......................................................................34
Changes to Figure 26 ......................................................................35
Changes to Ordering Guide...........................................................40
Updated Outline Dimensions........................................................39
Changes to Ordering Guide...........................................................40
11/06—Rev. B to Rev. C
Deleted ANC FIFO References ........................................Universal
Changes to Features ..........................................................................1
Changes to Figure 1...........................................................................1
Changes to JPEG2000 Feature Support Section............................4
Changes to Figure 8.........................................................................10
Changes to Figure 10 ......................................................................11
Changes to Figure 12 ......................................................................12
Changes to External DMA Mode—FIFO Write,
1/05—Rev. A to Rev. B
Updated Outline Dimensions........................................................39
Burst Mode Section.........................................................................13
Changes to External DMA Mode—FIFO Read,
12/04—Rev. 0 to Rev. A
Burst Mode Section.........................................................................13
Changes to Table 11 ........................................................................17
Changes to Figure 22 ......................................................................18
Deleted SPI Port Timing Section ..................................................18
Added Absolute Maximum Ratings Section ...............................19
Changes to Features ..........................................................................1
Changes to Table 2 ............................................................................4
Changes to Table 16 ........................................................................24
Changes to Table 23 ........................................................................32
7/04—Revision 0: Initial Version
Rev. D | Page 3 of 40
ADV202
Data Sheet
GENERAL DESCRIPTION
(continued from Page 1)
JPEG2000 FEATURE SUPPORT
The ADV202 supports a broad set of features that are included
in Part 1 of the JPEG2000 standard (ISO/IEC 15444). See
Getting Started with ADV202 for information on the JPEG2000
features that the ADV202 currently supports.
The ADV202 can process images at a rate of 40 MSPS in
reversible mode and at higher rates when used in irreversible
mode. The ADV202 contains a dedicated wavelet transform
engine, three entropy codecs, an on-board memory system, and
an embedded RISC processor that can provide a complete
JPEG2000 compression/decompression solution.
Depending on the particular application requirements, the
ADV202 can provide varying levels of JPEG2000 compression
support. It can provide raw code-block and attribute data
output, which allow the host software to have complete control
over the generation of the JPEG2000 code stream and other
aspects of the compression process such as bit-rate control.
Otherwise, the ADV202 can create a complete, fully compliant
JPEG2000 code stream (.j2c) and enhanced file formats such as
.jp2 and .j2c. See Getting Started with ADV202 for information
on the formats that the ADV202 currently supports.
The wavelet processor supports the 9/7 irreversible wavelet
transform and the 5/3 wavelet transform in reversible and
irreversible modes. The entropy codecs support all features in
the JPEG2000 Part 1 specification, except Maxshift ROI.
The ADV202 operates on a rectangular array of pixel samples
called a tile. A tile can contain a complete image, up to the
maximum supported size, or some portion of an image. The
maximum horizontal tile size supported depends on the wavelet
transform selected and the number of samples in the tile.
Images larger than the ADV202’s maximum tile size can be
broken into individual tiles and then sent sequentially to the
chip while still maintaining a single, fully compliant JPEG2000
code stream for the entire image.
Application notes and other ADV202 support documents can
be accessed over the ADV202 product page at:
•
•
http://www.analog.com/ADV202Notes or from
ftp://ftp.analog.com/pub/Digital_Imaging/ADV202_FTP_s
ite_contents_3.html
Rev. D | Page 4 of 40
Data Sheet
ADV202
SPECIFICATIONS
SUPPLY VOLTAGES AND CURRENT
Table 1.
Parameter
Description
Min
Typ
1.5
3.3
1.5
Max
1.575
3.63
1.575
VDDI/O + 0.3
+85
300
570
420
325
Unit
V
V
V
V
VDD
DC Supply Voltage, Core
DC Supply Voltage, I/O
DC Supply Voltage, PLL
Input Range
Operating Ambient Temperature Range in Free Air
Static Current1
Dynamic Current, Core (JCLK Frequency = 150 MHz)2
Dynamic Current, Core (JCLK Frequency = 108 MHz)
Dynamic Current, Core (JCLK Frequency = 81 MHz)
Dynamic Current, I/O
1.425
2.375
1.425
−0.3
−40
IOVDD
PLLVDD
VINPUT
Temp
IDD
+25
°C
mA
mA
mA
mA
mA
mA
20
2.6
Dynamic Current, PLL
1 No clock or I/O activity.
2 ADV202-150 only.
INPUT/OUTPUT SPECIFICATIONS
Table 2.
Parameter
VIH (3.3 V)
VIH (2.5 V)
VIL (3.3 V, 2.5 V)
VOH (3.3 V)
VOH (2.5 V)
VOL (3.3 V, 2.5 V)
IIH
IIL
IOZH
IOZL
CI
Description
Test Conditions
VDD = max
VDD = max
Min
Typ
Max
Unit
V
V
V
V
High Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
High Level Three-State Leakage Current
Low Level Three-State Leakage Current
Input Pin Capacitance
2.2
1.9
VDD = min
0.6
VDD = min, IOH = −0.5 mA
VDD = min, IOH = −0.5 mA
VDD = min, IOL = 2 mA
VDD = max, VIN = VDD
VDD = max, VIN = 0 V
2.4
2.0
V
V
0.4
1
1.0
1.0
µA
µA
µA
µA
pF
pF
VDD = max, VIN = VDD
VDD = max, VIN = 0 V
1.0
8
8
CO
Output Pin Capacitance
Rev. D | Page 5 of 40
ADV202
Data Sheet
CLOCK AND RESET SPECIFICATIONS
Table 3.
Parameter
Description
Min
13.3
6
6
13.4
5
Typ
Max
Unit
ns
ns
ns
ns
tMCLK
MCLK1 Period
100
tMCLKL
tMCLKH
tVCLK
tVCLKL
tVCLKH
tRST
MCLK Width Low
MCLK Width High
VCLK Period
VCLK Width Low
VCLK Width High
RESET Width Low
50
ns
ns
5
5
MCLK cycles
1 For a definition of MCLK, see the PLL section.
tMCLK
tMCLKL
tMCLKH
MCLK
tVCLK
tVCLKL
tVCLKH
VCLK
Figure 2. Input Clock
Rev. D | Page 6 of 40
Data Sheet
ADV202
NORMAL HOST MODE—READ OPERATION
Table 4.
Parameter
Description
Min
Typ
Max
1.5 × JCLK1 + 7.0
Unit
tACK [dir]
RD to ACK, Direct Registers and FIFO Accesses
5
ns
tACK [indir]
RD to ACK, Indirect Registers
10.5 × JCLK
15.5 × JCLK + 7.0
ns
tDRD [dir]
tDRD [indir]
tHZRD
tSC
Read Access Time, Direct Registers
Read Access Time, Indirect Registers
Data Hold
5
1.5 × JCLK + 7.0
15.5 × JCLK + 7.0
8.5
ns
ns
ns
ns
10.5 × JCLK
2
0
CS to RD Setup
tSA
Address Setup
2
ns
tHC
CS Hold
0
ns
tHA
Address Hold
2
ns
tRH
tRL
tRCYC
Read Inactive Pulse Width
Read Active Pulse Width
Read Cycle Time, Direct Registers
2.5
2.5
5.0
JCLK
JCLK
JCLK
1 For a definition of JCLK, see the PLL section.
tSA
tHA
ADDR
CS
tSC
tHC
tRCYC
tRL
tRH
RD
ACK
tACK
tDRD
tHZRD
VALID
HDATA
Figure 3. Normal Host Mode—Read Operation
Rev. D | Page 7 of 40
ADV202
Data Sheet
NORMAL HOST MODE—WRITE OPERATION
Table 5.
Parameter
Description
Min
Typ
Max
Unit
tACK (Direct)
WE to ACK, Direct Registers and FIFO Accesses
5
1.5 × JCLK1 + 7.0
ns
ns
tACK (Indirect)
WE to ACK, Indirect Registers
5
2.5 × JCLK + 7.0
tSD
tHD
tSA
Data Setup
Data Hold
Address Setup
3.0
1.5
2
ns
ns
ns
tHA
tSC
Address Hold
CS to WE Setup
2
0
ns
ns
tHC
tWH
tWL
tWCYC
CS Hold
0
ns
Write Inactive Pulse Width (Minimum Time Until Next WE Pulse)
Write Active Pulse Width
Write Cycle Time
2.5
2.5
5
JCLK
JCLK
JCLK
1 For a definition of JCLK, see the PLL section.
tSA
tHA
ADDR
CS
tSC
tHC
tWCYC
tWL
tWH
WE
tACK
ACK
tHD
tSD
VALID
HDATA
Figure 4. Nor/
mal Host Mode—Write Operation
Rev. D | Page 8 of 40
Data Sheet
ADV202
DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION
Table 6.
Parameter
Description
Min
1
Typ
Max
Unit
JCLK cycles2
1
DREQPULSE
DREQ Pulse Width
15
tDREQ
DACK Assert to Subsequent DREQ Delay
2.5
3.5 × JCLK + 7.5 ns
JCLK cycles
tWE
WE to DACK Setup
0
ns
SU
tSU
Data to DACK Deassert Setup
Data to DACK Deassert Hold
DACK Assert Pulse Width
2
2
2
2
0
ns
tHD
ns
DACKLO
DACKHI
JCLK cycles
JCLK cycles
ns
DACK Deassert Pulse Width
WE Hold After DACK Deassert
tWE
HD
WFSRQ
WE Assert to FSRQ Deassert (FIFO Full)
DACK to DREQ Deassert (DR × PULS = 0)
1.5
2.5
2.5 × JCLK + 7.5 ns
3.5 × JCLK + 7.5 ns
JCLK cycles
JCLK cycles
tDREQ
RTN
1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a value that is not 0. Pulse width depends on the value programmed
2 For a definition of JCLK, see the PLL section.
DREQ
PULSE
tDREQ
DREQ
DACK
DACK
HI
DACK
LO
tWESU
tWEHD
WE
tHD
tSU
HDATA
0
1
2
3
DREQ DACK
DMA Mode for Assigned DMA Channel
Figure 5. Single Write for
/
(EDMOD0/EDMOD1[14:11] NOT Programmed to a Value of 0000)
tDREQRTN
DREQ
DACK
DACK
HI
DACK
LO
tWESU
tWEHD
WE
tHD
tSU
HDATA
0
1
2
DREQ DACK
DMA Mode for Assigned DMA Channel
Figure 6. Single Write for
/
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
Rev. D | Page 9 of 40
ADV202
Data Sheet
DREQ
PULSE
tDREQ
DREQ
DACK
DACK
HI
DACK
LO
tWESU
tWEHD
WEFB
tHD
tSU
HDATA
0
1
2
DREQ
Figure 7. Fly-By DMA Mode—Single Write Cycle (
Pulse Width Is Programmable)
FSC0
WE
WFSRQ
FIFO NOT FULL
FIFO FULL
FSRQ0
HDATA
0
1
2
tHD
tSU
NOT WRITTEN TO FIFO
Figure 8. DCS DMA Mode—Single Write Access (Rev. 0.1 and Higher)
Rev. D | Page 10 of 40
Data Sheet
ADV202
/
DMA MODE—SINGLE FIFO READ OPERATION
DREQ DACK
Table 7.
Parameter
DREQPULSE
tDREQ
Description
Min
1
Typ
Max
Unit
DREQ Pulse Width1
15
JCLK cycles2
DACK Assert to Subsequent DREQ Delay
2.5
3.5 × JCLK + 7.5 ns
JCLK cycles
tRD
RD to DACK Setup
DACK to Data Valid
0
ns
ns
SU
tRD
2.5
11
tHD
DACKLO
DACKHI
Data Hold
1.5
2
ns
DACK Assert Pulse Width
DACK Deassert Pulse Width
RD Hold After DACK Deassert
JCLK cycles
JCLK cycles
ns
2
tRD
0
HD
RDFSRQ
RD Assert to FSRQ Deassert (FIFO Empty)
DACK to DREQ Deassert (DR × PULS = 0)
1.5
2.5
2.5 × JCLK + 7.5 ns
3.5 × JCLK + 7.5 ns
JCLK cycles
JCLK cycles
tDREQ
RTN
1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a nonzero value.
2 For a definition of JCLK, see the PLL section.
DREQ
PULSE
tDREQ
DREQ
DACK
HI
DACK
LO
DACK
RD
tRDSU
tRDHD
tRD
tHD
HDATA
0
1
2
DREQ DACK
DMA Mode for Assigned DMA Channel
Figure 9. Single Read for
/
(EDMOD0/EDMOD1[14:11] Not Programmed to a Value of 0000)
tDREQRTN
DREQ
DACK
HI
DACK
LO
DACK
RD
tRDSU
tRDHD
tRD
tHD
HDATA
0
1
2
DREQ DACK
DMA Mode for Assigned DMA Channel
Figure 10. Single Read for
/
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
Rev. D | Page 11 of 40
ADV202
Data Sheet
DREQ
PULSE
tDREQ
DREQ
DACK
HI
DACK
LO
DACK
RDFB
tRDSU
tRDHD
tRD
tHD
0
1
2
HDATA
Figure 11. Fly-By DMA Mode—Single Read Cycle
DREQ
(
Pulse Width Is Programmable)
FCS0
RD
RDFSRQ
FIFO NOT EMPTY
FIFO EMPTY
FSRQ0
HDATA
tHD
tRD
0
1
Figure 12. DCS DMA Mode—Single Read Access (Rev. 0.1 and Higher)
Rev. D | Page 12 of 40
Data Sheet
ADV202
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter
Description
DREQ Pulse Width1
Min
1
Typ
Max
Unit
JCLK2 cycles
DREQPULSE
15
tDREQ
WE to DREQ Deassert (DR × Pulse = 0)
2.5
3.5 × JCLK + 7.5 ns
JCLK cycles
RTN
tDACK
DACK to WE Setup
0
ns
SU
tSU
tHD
Data Setup
Data Hold
2.5
2
ns
ns
WELO
WEHI
WE Assert Pulse Width
WE Deassert Pulse Width
Last Burst Access to Next DREQ
1.5
1.5
2.5
JCLK cycles
JCLK cycles
JCLK cycles
tDREQ
4.5 × JCLK + 7.5 ns3
WAIT
1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a value that is not 0. Pulse width depends on the value programmed.
2 For a definition of JCLK, see the PLL section.
3 If sufficient space is available in FIFO.
DREQ
PULSE
tDREQWAIT
DREQ
DACK
tDACKSU
WE
LO
WE
HI
WE
tHD
tSU
0
1
13
14
15
HDATA
DREQ
Figure 13. Burst Write Cycle for
/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] NOT Programmed to a Value of 0000)
tDREQRTN
tDREQWAIT
DREQ
DACK
tDACKSU
WE
LO
WE
HI
WE
tHD
tSU
0
1
13
14
15
HDATA
DREQ
Figure 14. Burst Write Cycle for
/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
Rev. D | Page 13 of 40
ADV202
Data Sheet
tDREQRTN
tDREQWAIT
DREQ
DACK
tDACKSU
WE
LO
WE
HI
WEFB
tHD
tSU
0
1
13
14
15
HDATA
Figure 15. Burst Write Cycle for Fly-By DMA Mode
DREQ
(
Pulse Width Is Programmable)
EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter
Description
DREQ Pulse Width1
Min
1
Typ
Max
Unit
JCLK cycles2
DREQPULSE
15
tDREQ
RD to DREQ Deassert (DR × PULS = 0)
2.5
3.5 × JCLK + 7.5 ns
JCLK cycles
RTN
tDACK
DACK to RD Setup
RD to Data Valid
0
ns
ns
SU
tRD
2.5
9.7
tHD
RDLO
RDHI
Data Hold
2.5
1.5
1.5
2.5
ns
RD Assert Pulse Width
RD Deassert Pulse Width
Last Burst Access to Next DREQ
JCLK cycles
JCLK cycles
JCLK cycles
tDREQ
3.5 × JCLK + 7.5 ns3
WAIT
1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a value that is not 0. Pulse width depends on the value programmed.
2 For a definition of JCLK, see the PLL section.
3 If sufficient space is available in FIFO.
DREQ
tDREQWAIT
PULSE
DREQ
DACK
tDACKSU
RD
RD
HI
LO
RD
tHD
0
1
13
14
15
HDATA
tRD
DREQ DACK
DMA Mode for Assigned DMA Channel
Figure 16. Burst Read Cycle for
/
(EMOD0/EDMOD1[14:11] NOT Programmed to a Value of 0)
Rev. D | Page 14 of 40
Data Sheet
ADV202
tDREQWAIT
DREQ
tDREQRTN
DACK
tDACKSU
RD
RD
HI
LO
RD
tHD
0
1
13
14
15
HDATA
tRD
DREQ DACK
DMA Mode for Assigned DMA Channel
Figure 17. Burst Read Cycle for
/
(EMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
tDREQRTN
DREQ
DACK
tDREQWAIT
tDACKSU
RDFB
tHD
0
1
13
14
15
HDATA
tRD
Figure 18. Burst Read Cycle, Fly-By DMA Mode
DREQ
(
Pulse Width Is Programmable)
Rev. D | Page 15 of 40
ADV202
Data Sheet
STREAMING MODE (JDATA)—FIFO READ/WRITE
Table 10.
Parameter
JDATATD
VALIDTD
HOLDSU
HOLDHD
JDATASU
JDATAHD
Description
Min
1.5
1.5
3
3
3
Typ
Max
Unit
MCLK to JDATA Valid
2.5 × JCLK + 7.0 ns
2.5 × JCLK + .7.0 ns
JCLK cycles1
MCLK to VALID Assert/Deassert
HOLD Setup to Rising MCLK
HOLD Hold from Rising MCLK
JDATA Setup to Rising MCLK
JDATA Hold from Rising MCLK
JCLK cycles
ns
ns
ns
ns
3
1 For a definition of JCLK, see the PLL section.
MCLK
JDATA
HD
JDATA
TD
JDATA
JDATA
SU
VALID
TD
VALID
HOLD
HOLD
SU
HOLD
HD
Figure 19. Streaming Mode Timing—Encode Mode JDATA Output
MCLK
JDATA
HD
JDATA
SU
JDATA
VALID
HOLD
VALID
TD
HOLD
HD
HOLD
SU
Figure 20. Streaming Mode Timing—Decode Mode JDATA Input
Rev. D | Page 16 of 40
Data Sheet
ADV202
VDATA MODE TIMING
Table 11.
Parameter
VDATATD
VDATASU
VDATAHD
HSYNCSU
HSYNCHD
HSYNCTD
VSYNCSU
VSYNCHD
VSYNCTD
FIELDSU
Description
Min Typ Max Unit
VCLK to VDATA Valid Delay (VDATA Output)
VDATA Setup to Rising VCLK (VDATA Input)
VDATA Hold from Rising VCLK (VDATA Input)
HSYNC Setup to Rising VCLK
HSYNC Hold from Rising VCLK
VCLK to HSYNC Valid Delay
VSYNC Setup to Rising VCLK
VSYNC Hold from Rising VCLK
VCLK to VSYNC Valid Delay
FIELD Setup to Rising VCLK
12
ns
4
4
3
4
ns
ns
ns
ns
12
12
12
ns
ns
ns
ns
ns
ns
ns
3
4
4
3
FIELDHD
FIELDTD
FIELD Hold from Rising VCLK
VCLK to FIELD Valid
SYNC DELAY
Decode Data Sync Delay for HD Input with EAV/SAV Codes
Decode Data Sync Delay for SD Input with EAV/SAV Codes
Decode Data Sync Delay for HVF Input (from First Rising VCLK after HSYNC Low to
First Data Sample)
7
9
10
VCLK cycles
VCLK cycles
VCLK cycles
VCLK
VDATA
HD
Y
VDATA
SU
VDATA(IN)
Cr
Y
Cb
FF
EAV
FF
SAV
Cb
Y
Cr
ENCODE CCIR-656 LINE
VCLK
VDATA
TD
VDATA(OUT)
VCLK
Cr
Y
Cb
Y
FF
EAV
FF
SAV
Cb
Y
Cr
DECODE MASTER CCIR-656 LINE
VDATA
Y
TD
SYNC DELAY
VDATA(OUT)
VCLK
Y
Cr
Cb
Y
FF
EAV
FF
SAV
Cb
Y
DECODE SLAVE CCIR-656 LINE
VDATA
Cr
SYNC DELAY
TD
Cb
Y
Y
Cb
Y
Cb
Y
Cr
Y
Cb
VDATA(OUT)
HSYNC
HSYNC
*
HD
VSYNC
*
HD
VSYNC
VCLK
DECODE SLAVE HVF MODE
VDATA(IN)
HSYNC
Y
Cr
Y
Cb
Y
Cr
Y
Cb
Y
Cb
Y
Cr
Y
Cb
HSYNC
VSYNC
HSYNC
SU
HD
VSYNC
VSYNC
SU
HD
ENCODE HVF MODE
*HSYNC AND VSYNC DO NOT HAVE TO BE APPLIED SIMULTANEOUSLY
Figure 21. Video Mode Timing
Rev. D | Page 17 of 40
ADV202
Data Sheet
RAW PIXEL MODE TIMING
Table 12.
Parameter
VDATATD
VDATASU
VDATAHD
VRDYTD
VFRMSU
VFRMHD
VFRMTD
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
VCLK to PIXELDATA Valid Delay (PIXELDATA Output)
PIXELDATA Setup to Rising VCLK (PIXELDATA Input)
PIXELDATA Hold from Rising VCLK (PIXELDATA Input)
VCLK to VRDY Valid Delay
VFRM Setup to Rising VCLK (VFRAME Input)
VFRM Hold from Rising VCLK (VFRAME Input)
VCLK to VFRM Valid Delay (VFRAME Output)
VSTRB Setup to Rising VCLK
12
4
4
12
12
3
4
VSTRBSU
VSTRBHD
4
3
VSTRB Hold from Rising VCLK
ns
VCLK
VDATA
HD
VDATA
SU
PIXEL
DATA(IN)
N–1
N
0
1
2
VFRM
HD
VFRM
SU
VFRM(IN)
VRDY
VRDY
TD
VSTRB
HD
VSTRB
SU
VSTRB
VCLK
RAW PIXEL MODE – ENCODE
VDATA
TD
PIXEL
DATA
N
N
0
1
2
VRFM
TD
VFRM(OUT)
RAW PIXEL MODE – DECODE
Figure 22. Raw Pixel Mode Timing
Rev. D | Page 18 of 40
Data Sheet
ADV202
ABSOLUTE MAXIMUM RATINGS
Table 13.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
−0.3 V to +1.65 V
−0.3 V to +IOVDD + 0.3 V
−0.3 V to +1.65 V
−65°C to 150°C
VDD (Supply Voltage, Core)
IOVDD (Supply Voltage, I/O)
PLLVDD (Supply Voltage, PLL)
Storage Temperature (TS) Range
Table 14. Thermal Resistance
Package Type
θJA
θJC
Unit
C/W
C/W
ADV202 (144-Lead)
ADV202 (121-Lead)
22.5°
32.8°
3.8°
7.92°
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. D | Page 19 of 40
ADV202
Data Sheet
PIN BGA ASSIGNMENTS AND FUNCTION DESCRIPTIONS
PIN BGA ASSIGNMENTS
Table 15. Pin BGA Assignments for 121-Lead Package
Pin. No.
Pin Location
Pin Description
Pin. No.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
Pin Location
E6
E7
E8
E9
E10
E11
F1
F2
F3
Pin Description
DGND
DGND
IOVDD
VCLK
FIELD
DGND
DGND
HDATA[19]_VDATA[15]
HDATA[20]
HDATA[21]
DGND
1
2
3
4
5
6
7
8
A1
A2
A3
A4
A5
A6
A7
A8
DGND
HDATA[2]
VDD
DGND
HDATA[0]
HDATA[1]
VDATA[1]
VDD
DGND
VDATA[0]
DGND
HDATA[3]
HDATA[4]
HDATA[5]
HDATA[7]
HDATA[8]
IOVDD
VDATA[6]
VDATA[5]
VDATA[4]
VDATA[2]
VDATA[3]
DGND
HDATA[6]
HDATA[9]
HDATA[10]
HDATA[11]
IOVDD
VDATA[9]
IOVDD
VDATA[8]
VDATA[7]
DGND
HDATA[12]
HDATA[13]
HDATA[14]
HDATA[15]
IOVDD
9
A9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C3
C4
C5
F4
F5
F6
F7
DGND
DGND
DREQ0
F8
DACK0
F9
DREQ1
F10
F11
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
J1
DGND
DGND
HDATA[22]
HDATA[23]
HDATA[24]_JDATA[0]
DGND
DGND
DGND
IOVDD
DACK1
IRQ
C6
C7
C8
C9
DGND
HDATA[28]_JDATA[4]
HDATA[27]_JDATA[3]
HDATA[26]_JDATA[2]
HDATA[25]_JDATA[1]
IOVDD
DGND
VDD
ACK
C10
C11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
E1
RD
ADDR[1]
ADDR[3]
DGND
HDATA[31]_JDATA[7]
HDATA[30]_JDATA[6]
HDATA[29]_JDATA[5]
IOVDD
TEST1
WE
DGND
VDD
VSYNC
HSYNC
VDATA[10]
VDATA[11]
DGND
HDATA[18]_VDATA[14]
HDATA[17]_VDATA[13]
HDATA[16]_VDATA[12]
DGND
J2
J3
J4
J5
J6
E2
E3
E4
E5
J7
CS
J8
J9
ADDR[0]
Rev. D | Page 20 of 40
Data Sheet
ADV202
Pin. No.
98
99
Pin Location
Pin Description
TEST3
DGND
SCOMM[4]
SCOMM[3]
SCOMM[0]
SCOMM[1]
IOVDD
IOVDD
IOVDD
ADDR[2]
TEST2
TEST5
Pin. No.
110
111
112
113
114
115
116
117
118
119
120
121
Pin Location
Pin Description
DGND
DGND
SCOMM[7]
SCOMM[6]
SCOMM[5]
SCOMM[2]
TEST4
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
100
101
102
103
104
105
106
107
108
109
L5
L6
RESET
L7
L8
L9
L10
L11
DGND
MCLK
PLLVDD
DGND
Table 16. Pin BGA Assignments for 144-Lead Package
Pin No.
Pin Location
Pin Description
Pin No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Pin Location
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
F1
F2
F3
F4
F5
Pin Description
HDATA[10]
HDATA[9]
IOVDD
DGND
VDD
VDD
DGND
IOVDD
VDATA[11]
VDATA[10]
VDATA[9]
HDATA[14]
HDATA[13]
HDATA[12]
DGND
DGND
DGND
DGND
DGND
FIELD
VSYNC
HSYNC
VCLK
HDATA[18]_VDATA[14]
HDATA[17]_VDATA[13]
HDATA[16]_VDATA[12]
HDATA[15]
DGND
DGND
DGND
DGND
DACK1
1
2
3
4
5
6
7
8
A1
A2
A3
A4
A5
A6
A7
A8
DGND
HDATA[2]
HDATA[1]
HDATA[0]
DGND
DGND
DGND
DGND
9
A9
VDATA[2]
VDATA[1]
VDATA[0]
DGND
HDATA[5]
HDATA[4]
HDATA[3]
IOVDD
DGND
VDD
VDD
DGND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
IOVDD
VDATA[5]
VDATA[4]
VDATA[3]
HDATA[8]
HDATA[7]
HDATA[6]
IOVDD
DGND
VDD
VDD
DGND
F6
F7
F8
F9
C6
C7
C8
C9
C10
C11
C12
D1
IOVDD
F10
F11
F12
G1
DREQ1
VDATA[8]
VDATA[7]
VDATA[6]
HDATA[11]
DACK0
DREQ0
HDATA[22]
HDATA[21]
G2
Rev. D | Page 21 of 40
ADV202
Data Sheet
Pin No.
75
76
77
78
79
80
81
82
Pin Location
Pin Description
HDATA[20]
HDATA[19]_VDATA[15]
DGND
DGND
DGND
DGND
DGND
IRQ
Pin No.
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Pin Location
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L1
L2
L3
L4
L5
L6
L7
Pin Description
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
K1
SCOMM[0]
HDATA[31]_JDATA[7]
IOVDD
DGND
VDD
VDD
DGND
IOVDD
TEST3
TEST2
TEST1
SCOMM[4]
SCOMM[3]
SCOMM[2]
IOVDD
DGND
VDD
VDD
DGND
IOVDD
TEST5
83
ACK
84
RD
85
86
87
88
89
90
91
92
HDATA[26]_JDATA[2]
HDATA[25]_JDATA[1]
HDATA[24]_JDATA[0]
HDATA[23]
DGND
DGND
DGND
DGND
DGND
L8
L9
93
94
WR
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
95
CS
RESET
96
97
98
99
ADDR[0]
MCLK
DGND
SCOMM[7]
SCOMM[6]
SCOMM[5]
DGND
DGND
DGND
DGND
TEST4
HDATA[30]_JDATA[6]
HDATA[29]_JDATA[5]
HDATA[28]_JDATA[4]
HDATA[27]_JDATA[3]
DGND
VDD
VDD
DGND
DGND
ADDR[1]
ADDR[2]
ADDR[3]
SCOMM[1]
100
101
102
103
104
105
106
107
108
109
PLLVDD
DGND
DGND
Rev. D | Page 22 of 40
Data Sheet
ADV202
PIN FUNCTION DESCRIPTIONS
Table 17.
Pins
Mnemonic
Used 121-Lead Package
144-Lead Package
I/O
Description
MCLK
1
L9
L12
I
System Input Clock. For details, see the PLL section.
Maximum input frequency on MCLK is 74.25 MHz.
RESET
1
L7
L11
I
Reset. Causes the ADV202 to immediately reset. CS, RD,
WE, DACK0, DACK1, DREQ0, and DREQ1 must be held
high when a RESET is applied.
HDATA[15:0]
16
D4 to D1, C5 to C3,
B5, B4, C2, B3 to B1,
A2, A6 to A5
F4, E1 to E3, D1 to D3,
C1 to C3, B1 to B3, A2,
A3, A4
I/O
Host Data Bus. With HDATA[23:16], [27:24], [31:28], these
pins make up the 32-bit wide host data bus.
The async host interface is interfaced together with
ADDR[3:0], CS, WE, RD, and ACK. Unused HDATA pins
should be pulled down via a 10 kΩ resistor.
ADDR[3:0]
CS
4
1
H11, K8, H10, J9
J8
J12, J11, J10, H12
H11
I
I
Address Bus for the Host Interface.
Chip Select. This signal is used to qualify addressed read
and write access to the ADV202 using the host interface.
WE
1
1
1
J7
H10
G12
G11
I
Write Enable Used with the Host Interface.
RDFB
Read Enable When Fly-By DMA Is Enabled.
Note: Simultaneous assertion of WE and DACK low activates
the HDATA bus, even if the DMA channels are disabled.
Read Enable. Used with the host interface.
RD
H9
H8
I
WEFB
Write Enable When Fly-By DMA Is Enabled.
Note: Simultaneous assertion of RD and DACK low activates
the HDATA bus, even if the DMA channels are disabled.
ACK
O
Acknowledge. Used for direct register accesses. This signal
indicates that the last register access was successful.
Note: Due to synchronization issues, control and status
register accesses can incur an additional delay, so the host
software should wait for acknowledgment from the ADV202.
Accesses to the FIFOs (external DMA modes), on the other
hand, are guaranteed to occur immediately, if space is
available, and should not wait for ACK, if the timing
constraints are observed. If ACK is shared with more than
one device, ACK should be connected to a pull-up resistor
(10 kΩ) and the PLL_HI register, Bit 4, must be set to 1.
IRQ
1
1
G10
F8
G10
F12
O
O
Interrupt. This pin indicates that the ADV202 requires the
attention of the host processor. This pin can be
programmed to indicate the status of the internal
interrupt conditions within the ADV202. The interrupt
sources are enabled via bits in Register EIRQIE.
Data Request for External DMA Interface. Indicates that
the ADV202 is ready to send/receive data to/from the FIFO
assigned to DMA Channel 0.
DREQ0
FSRQ0
VALID
O
O
Used in DCS-DMA Mode. Service request from the FIFO
assigned to Channel 0 (asynchronous mode).
Valid Indication for JDATA Input/Output Stream. Polarity
of this pin is programmable in the EDMOD0 register.
VALID is always an output.
CFG[1]
DACK0
I
I
Boot Mode Configuration. This pin is read on reset to
determine the boot configuration of the on-board
processor. The pin should be tied to IOVDD or DGND
through a 10 kΩ resistor.
Data Acknowledge for External DMA Interface. Signal
from the host CPU, which indicates that the data transfer
request (DREQ0) has been acknowledged and data
transfer can proceed. This pin must be held high at all
times if the DMA interface is not used, even if the DMA
channels are disabled.
1
F9
F11
Rev. D | Page 23 of 40
ADV202
Data Sheet
Pins
Mnemonic
Used 121-Lead Package
144-Lead Package
I/O
Description
HOLD
I
External Hold Indication for JDATA Input/Output Stream.
Polarity is programmable in the EDMOD0 register. This pin
is always an input.
FCS0
I
Used in DCS-DMA Mode. Chip select for the FIFO assigned
to Channel 0 (asynchronous mode).
DREQ1
1
F10
F10
O
Data Request for External DMA Interface. Indicates that
the ADV202 is ready to send/receive data to/from the FIFO
assigned to DMA Channel 1.
FSRQ1
CFG[2]
O
I
Used in DCS-DMA Mode. Service request from the FIFO
assigned to Channel 1 (asynchronous mode).
Boot Mode Configuration. This pin is read on reset to
determine the boot configuration of the on-board
processor. The pin should be tied to IOVDD or DGND
through a 10 kΩ resistor.
DACK1
FCS1
1
G9
F9
I
Data Acknowledge for External DMA Interface. Signal
from the host CPU, which indicates that the data transfer
request (DREQ1) has been acknowledged and data
transfer can proceed. This pin must be held high at all
times unless a DMA or JDATA access is occurring. This pin
must be held high at all times if the DMA interface is not
used, even if the DMA channels are disabled.
I
Used in DCS-DMA Mode. Chip select for the FIFO assigned
to Channel 1 (asynchronous mode).
HDATA[31:28]
JDATA[7:4]
HDATA[27:24]
JDATA[3:0]
4
4
J2 to J4, H1
K3, J1 to J3
J4, H1 to H3
I/O
I/O
I/O
I/O
I/O
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Host Expansion Bus.
H2 to H4, G4
HDATA[23:16]
8
8
G3, G2, F4, F3, F2 E2, H4, G1 to G4, F1 to F3
E3, E4
SCOMM[7]
SCOMM[6]
SCOMM[5]
L2
L3
L4
M2
M3
M4
I/O
I/O
I/O
When not used, this pin should be tied low via a 10 kΩ
resistor.
When not used, this pin should be tied low via a 10 kΩ
resistor.
This pin must be used in multiple chip mode to align the
outputs of two or more ADV202s. For details, see the
Applications section and AN-796 ADV202 Multichip
Application application note. When not used, this pin
should be tied low via a 10 kΩ resistor.
SCOMM[4]
K1
L1
O
LCODE Output in Encode Mode. When LCODE is enabled,
the output on this pin indicates on a high transition that
the last data-word for a field has been read from the FIFO.
For an 8-bit interface, such as JDATA, LCODE is asserted for
four consecutive bytes and is enabled by default.
SCOMM[3]
SCOMM[2]
SCOMM[1]
SCOMM[0]
VCLK
K2
L5
K4
K3
E9
L2
L3
K1
K2
E12
O
O
I
O
I
This pin should be tied low via a 10 kΩ resistor.
This pin should be tied low via a 10 kΩ resistor.
This pin should be tied low via a 10 kΩ resistor.
This pin should be tied low via a 10 kΩ resistor.
Video Data Clock. Must be supplied if video data is
input/output on the VDATA bus.
1
VDATA[11:0]
12
D11, D10, C7, C9,
C10, B7, B8, B9, B11, C10 to C12,
B10, A7, A10
D8
D10 to D12,
I/O
I/O
Video Data. Unused pins should be pulled down via a
10 kΩ resistor.
B10 to B12, A9 to A11
E10
VSYNC
VFRM
1
1
Vertical Sync for Video Mode.
Raw Pixel Mode Framing Signal. Indicates first sample of a
tile when asserted high.
Horizontal Sync for Video Mode.
Raw Pixel Mode Ready Signal.
HSYNC
VRDY
D9
E11
I/O
O
Rev. D | Page 24 of 40
Data Sheet
ADV202
Pins
Used 121-Lead Package
Mnemonic
FIELD
VSTRB
144-Lead Package
I/O
Description
1
E10
E9
I/O
I
I
Field Sync for Video Mode.
Raw Pixel Mode Transfer Strobe.
This pin should be connected to ground via a pull-down
resistor.
This pin should be connected to ground via a pull-down
resistor.
This pin should be connected to ground via a pull-down
resistor.
TEST1
1
1
1
1
1
J6
K12
K11
K10
M9
TEST2
TEST3
TEST4
K9
J10
L6
I
I
I
This pin should be connected to ground via a pull-down
resistor.
No Connect.
TEST5
VDD
K10
L10
O
V
A3, A8, D7, H7
B6, B7, C6, C7, D6, D7,
J6, J7, K6, K7, L6, L7
Positive Supply for Core.
DGND
A1, A11, A4, A9, C1,
C11, D6, E1, E5 to E7,
E11, F1, F5 to F7,
F11, G1, G5 to G7,
G11, H6, J1, J11,
K11, L1, L8, L11
A1, A5 to A8, A12, B5,
B8, C5, C8, D5, D8, E4
to E8, F5 to F8, G5 to
G9, H5 to H9, J5, J8 to
J9, K5, K8, L5, L8, M1,
M5 to M8, M11, M12
GND Ground.
PLLVDD
IOVDD
1
L10
M10
V
V
Positive Supply for PLL.
Positive Supply for I/O.
B6, C6, C8, D5, E8,
G8, H5, J5, K5, K6, K7
B4, B9, C4, C9, D4, D9,
K4, K9, L4, L9
Rev. D | Page 25 of 40
ADV202
Data Sheet
THEORY OF OPERATION
The input video or pixel data is passed on to the ADV202’s pixel
interface, where samples are de-interleaved and passed on to the
wavelet engine, which decomposes each tile or frame into
subbands using the 5/3 or 9/7 filters. The resulting wavelet
coefficients are then written to internal memory. Next, the
entropy codecs code the image data so it conforms to the
JPEG2000 standard. An internal DMA provides high
bandwidth memory-to-memory transfers, as well as high
performance transfers between functional blocks and memory.
ENTROPY CODECS
The entropy codec block performs context modeling and
arithmetic coding on a code block of the wavelet coefficients.
Additionally, this block performs the distortion metric
calculations during compression that are required for optimal
rate and distortion performance. Because the entropy coding
process is the most computationally intensive operation in the
JPEG2000 compression process, three dedicated hardware
entropy codecs are provided on the ADV202.
WAVELET ENGINE
EMBEDDED PROCESSOR SYSTEM
The ADV202 provides a dedicated wavelet transform processor
based on Analog Devices’ proven and patented SURF
technology. This processor can perform up to six wavelet
decomposition levels on a tile. In encode mode, the wavelet
transform processor takes in uncompressed samples, performs
the wavelet transform and quantization, and writes the wavelet
coefficients in all frequency subbands to internal memory. Each
of these subbands is then further broken down into code blocks.
The code-block dimensions can be user-defined and are used
by the wavelet transform processor to organize the wavelet
coefficients into code blocks when writing to internal memory.
Each completed code block is then entropy coded by one of the
entropy codecs.
The ADV202 incorporates an embedded 32-bit RISC processor.
This processor is used for configuration, control, and manage-
ment of the dedicated hardware functions, as well as for parsing
and generating the JPEG2000 code stream. The processor
system includes memory for both program and data memory,
an interrupt controller, standard bus interfaces, and other
hardware functions such as timers and counters.
MEMORY SYSTEM
The memory system’s main function is to manage wavelet
coefficient data, interim code-block attribute data, and
temporary work space for creating, parsing, and storing the
JPEG2000 code stream. The memory system can also be used
for program and data memory for the embedded processor.
In decode mode, wavelet coefficients are read from internal
memory and recomposed into uncompressed samples.
INTERNAL DMA ENGINE
The internal DMA engine provides high bandwidth memory-
to-memory transfers, as well as high performance transfers
between memory and functional blocks. This function is critical
for high speed generation and parsing the code stream.
Rev. D | Page 26 of 40
Data Sheet
ADV202
ADV202 INTERFACE
There are several possible modes to interface to the ADV202 using
the VDATA bus and the HDATA bus or the HDATA bus alone.
The host interface is used for configuration, control, and status
functions, as well as for transferring compressed data streams. It
can be used for uncompressed data transfers in certain modes.
The host interface can be shared by as many as four concurrent
data streams in addition to control and status communications.
The data streams are
VIDEO INTERFACE (VDATA BUS)
The video interface can be used in applications in which
uncompressed pixel data is on a separate bus from compressed
data. For example, it is possible to use the VDATA bus to input
uncompressed video while using the HDATA bus to output the
compressed data. This interface is ideal for applications
requiring very high throughput such as live video capture.
•
•
Uncompressed tile data (for example, still image data)
Fully encoded JPEG2000 code stream (or unpackaged code
blocks)
•
Code-block attributes
Optionally, the ADV202 can compress ITU.R-BT656 resolution
video on a field-by-field basis or on a two-fields-combined
basis, which yields significantly more efficient compression
performance. Additionally, high definition digital video such as
SMPTE274M (1080i) is supported using two or more ADV202
devices.
The ADV202 uses big endian byte alignment for 16- and 32-bit
transfers. All data is left-justified (MSB).
Pixel Input on the Host Interface
Pixel input on the host interface supports 8-, 10-, 12-, 14-, and
16-bit raw pixel data formats. It can be used for pixel (still
image) input/output or compressed video output. Because there
are no timing codes or sync signals associated with the input
data on the host interface, dimension registers and internal
counters are used and must be programmed to indicate the start
and end of the frame. See the technical note on using HIPI
mode for details on how to use the ADV202 in this mode.
The video interface can support video data or still image data
input/output, 8-, 10-, and 12-bit single or multiplexed
components. The VDATA interface supports digital video in
YCbCr format or single component format. YCbCr data must
be in 4:2:2 format.
Video data can be input/output in several different modes on
the VDATA bus, as described in Table 18. In all these modes,
the pixel clock must be input on the VCLK pin.
Host Bus Configuration
For maximum flexibility, the host interface provides several
configurations to meet particular system requirements. The
default bus mode uses the same pins to transfer control, status,
and data to and from the ADV202. In this mode, the ADV202
can support 16- and 32-bit control transfers and 8-, 16-, and
32-bit data transfers. The size of these buses can be selected
independently, allowing, for example, a 16-bit microcontroller
to configure and control the ADV202 while still providing
32-bit data transfers to an ASIC or external memory system.
Table 18. Video Input/Output Modes
Mode
Description
EAV/SAV Accepts video with embedded EAV/SAV codes, where
the YCbCr data is interleaved onto a single bus.
HVF
Accepts video data accompanied with separate H, V,
and F signals where YCbCr data is interleaved onto a
single bus.
Raw
Video
Used for still picture data and nonstandard video.
VFRM, VSTRB, and VRDY are used to program the
dimensions of the image.
DIRECT AND INDIRECT REGISTERS
To minimize pin count and cost, the number of address pins has
been limited to four, which yields a total direct address space of
16 locations. These locations are most commonly used by the
external controller and are, therefore, accessible directly. All
other registers in the ADV202 can be accessed indirectly
through the IADDR and IDATA registers.
HOST INTERFACE (HDATA BUS)
The ADV202 can connect directly to a wide variety of host
processors and ASICs using an asynchronous SRAM-style
interface, DMA accesses, or streaming mode (JDATA) interface.
The ADV202 supports 16- and 32-bit buses for control and
8-, 16-, and 32-bit buses for data transfer.
CONTROL ACCESS REGISTERS
With the exception of the indirect address and data registers
(IADDR and IDATA), all control/status registers in the ADV202
are 16 bits wide and are half-word (16-bit) addressable only.
When 32-bit host mode is enabled, the upper 16 bits of the
HDATA bus are ignored on writes and return all 0s on reads of
16-bit registers.
The control and data channel bus widths can be specified
independently, which allows the ADV202 to support applica-
tions that require control and data buses of different widths.
Rev. D | Page 27 of 40
ADV202
Data Sheet
STAGE is accessed as a 16-bit register using HDATA[15:0].
Prior to writing to the desired register, the stage register must be
written with the upper (most significant) half-word.
PIN CONFIGURATION AND BUS SIZES/MODES
The ADV202 provides a wide variety of control and data
configurations, which allows it to be used in many applications
with little or no glue logic. The following modes are configured
using the BUSMODE register. In the following descriptions,
When the host subsequently writes the lower half-word to the
desired control register, HDATA is combined with the previously
staged value to create the required 32-bit value that is written.
When a register is read, the upper (most significant) half-word
is returned immediately on HDATA and the lower half-word
can be retrieved by reading the stage register on a subsequent
access. For details on using the stage register, see the ADV202
User’s Guide.
CS RD
DREQ DACK
).
host refers to normal addressed accesses (
and data refers to external DMA accesses (
/
/WR/ADDR)
/
32-Bit Host/32-Bit Data
In this mode, the HDATA[31:0] pins provide full 32-bit wide data
accesses to PIXEL, CODE, and ATTR FIFOs. The expanded
video interface (VDATA) is not available in this mode.
Note that the stage register does not apply to the three data
channels (PIXEL, CODE, and ATTR). These channels are
always accessed at the specified data width and do not require
the use of the stage register.
16-Bit Host/32-Bit Data
This mode allows a 16-bit host to configure and communicate
with the ADV202 while still allowing 32-bit accesses to the
PIXEL, CODE, and ATTR FIFOs using the external DMA
capability.
JDATA MODE
JDATA mode is typically used only when the dedicated video
interface (VDATA) is also enabled. This mode allows code
stream data (compressed data compliant with JPEG2000) to be
input or output on a single dedicated 8-bit bus (JDATA[7:0]).
The bus is always an output during compression operations
and is an input during decompression.
All addressed host accesses are 16 bits and, therefore, use only
the HDATA[15:0] pins. The HDATA[31:16] pins provide the
additional 16 bits necessary to support the 32-bit external DMA
transfers to and from the FIFOs only. The expanded video
interface (VDATA) is not available in this mode.
16-Bit Host/16-Bit Data
A 2-pin handshake is used to transfer data over this synchro-
nous interface. VALID is used to indicate that the ADV202 is
ready to provide or accept data and is always an output. HOLD
is always an input and is asserted by the host if it cannot accept/
provide data. For example, JDATA mode allows real-time
applications, in which pixel data is input over the VDATA bus
while the compressed data stream is output over the JDATA bus.
This mode uses 16-bit transfers, if used for host or external
DMA data transfers. This mode allows for the use of the
extended pixel interface modes.
16-Bit Host/8-Bit Data (JDATA Bus Mode)
This mode provides separate data input/output and host
control interface pins. Host control accesses are 16 bits and use
HDATA[15:0], while the dedicated data bus uses JDATA[7:0].
EXTERNAL DMA ENGINE
The external DMA interface is provided to enable high
bandwidth data I/O between an external DMA controller and
the ADV202 data FIFOs. Two independent DMA channels can
each be assigned to any one of the three data stream FIFOs
(PIXEL, CODE, or ATTR).
JDATA uses a valid/hold synchronous transfer protocol. The
direction of the JDATA bus is determined by the mode of the
ADV202. If the ADV202 is encoding (compression), JDATA[7:0]
is an output. If the ADV202 is decoding (decompression),
JDATA[7:0] is an input. Host control accesses remain
asynchronous (also refer to the JDATA Mode section).
The controller supports asynchronous DMA using a data-
DREQ DACK
request/data-acknowledge (
/
) protocol in either
STAGE REGISTER
single or burst access modes. Additional functionality is provided
for single address compatibility (fly-by) and dedicated chip
select (DCS) modes.
Because the ADV202 contains both 16-bit and 32-bit registers
and its internal memory is mapped as 32-bit data, a mechanism
has been provided to allow 16-bit hosts to access these registers
and memory locations using the stage register (STAGE).
Rev. D | Page 28 of 40
ADV202
INTERNAL REGISTERS
This section describes the internal registers of the ADV202.
The host must first initialize the direct registers before any
application-specific operation can be implemented.
DIRECT REGISTERS
For additional information on accessing and configuring these
registers, see the ADV202 User’s Guide.
The ADV202 has 16 direct registers, as listed in Table 19.
The direct registers are accessed over the ADDR[3:0],
CS RD WR
ACK
HDATA[31:0],
,
,
, and
pins.
Table 19. Direct Registers
Name
PIXEL
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Description
Pixel FIFO Access Register
Compressed Code Stream Access Register
Attribute FIFO Access Register
Reserved
CODE
ATTR
Reserved
CMDSTA
EIRQIE
Command Stack
External Interrupt Enabled
External Interrupt Flags
Software Flag Register
EIRQFLG
SWFLAG
BUSMODE
MMODE
STAGE
Bus Mode Configuration Register
Miscellaneous Mode Register
Staging Register
IADDR
IDATA
Indirect Address Register
Indirect Data Register
BOOT
Boot Mode Register
PLL_HI
PLL_LO
PLL Control Register—High Byte
PLL Control Register—Low Byte
Rev. D | Page 29 of 40
ADV202
Data Sheet
INDIRECT REGISTERS
Both 32-bit and 16-bit hosts can access the indirect registers.
32-bit hosts use the IADDR and IDATA registers, while the
16-bit hosts use IADDR, IDATA, and the stage register.
In certain modes, such as custom-specific input format or HIPI
mode, indirect registers must be accessed by the user through
the use of the IADDR and IDATA registers. The indirect
register address space starts at Internal Address 0xFFFF0000.
For additional information on accessing and configuring these
registers, see the ADV202 User’s Guide.
Table 20. Indirect Registers
Address
Name
Description
0xFFFF0400
0xFFFF0404
0xFFFF0408
0xFFFF040C
0xFFFF0410
0xFFFF0414
0xFFFF0418
0xFFFF041C
0xFFFF0420
0xFFFF0424
0xFFFF0428
0xFFFF042C
0xFFFF0430
0xFFFF0440
0xFFFF0444
0xFFFF0448
0xFFFF044C
0xFFFF1408
0xFFFF140C
0xFFFF1410
0xFFFF1414
0xFFFF1418
0xFFFF141C
0xFFFF1420
0xFFFF1428 to 0xFFFF14FC
PMODE1
COMP_CNT_STATUS
LINE_CNT_STATUS
XTOT
Pixel/Video Format
Horizontal Count
Vertical Count
Total Samples per Line
Total Lines per Frame
Start Line of Field 0 [F0]
Start Line of Field 1 [F1]
Start of Active Video Field 0 [F0]
Start of Active Video Field 1 [F1]
End of Active Video Field 0 [F0]
End of Active Video Field 1 [F1]
Horizontal Start of Active Video
Horizontal End of Active Video
Master/Slave Delay
YTOT
F0_START
F1_START
V0_START
V1_START
V0_END
V1_END
PIXEL_START
PIXEL_END
MS_CNT_DEL
Reserved
PMODE2
VMODE
Reserved
Pixel Mode 2
Video Mode
EDMOD0
EDMOD1
FFTHRP
External DMA Mode Register 0
External DMA Mode Register 1
FIFO Threshold for Pixel FIFO
Reserved
Reserved
Reserved
FFTHRC
Reserved
FIFO Threshold for CODE FIFO
FIFO Threshold for ATTR FIFO
Reserved
FFTHRA
Reserved
Rev. D | Page 30 of 40
Data Sheet
ADV202
PLL
The ADV202 uses the PLL_HI and PLL_LO direct registers to
configure the PLL. Any time the PLL_LO register is modified,
the host must wait at least 20 µs before reading or writing to any
other register. If this delay is not implemented, erratic behavior
could result.
•
•
•
The maximum burst frequency for external DMA modes is
≤0.36 JCLK.
For MCLK frequencies greater than 50 MHz, the input
clock divider must be enabled, that is, IPD set to 1.
IPD cannot be enabled for MCLK frequencies below 20 MHz.
The PLL can be programmed to have any possible final
multiplier value as long as
To achieve the lowest power consumption, an MCLK frequency
of 27 MHz is recommended for a standard definition CCIR656
input. The PLL circuit is recommended to have a multiplier of 3.
This sets JCLK and HCLK to 81 MHz.
•
•
•
•
•
•
•
•
•
JCLK > 50 MHz and < 150 MHz (144-lead version).
JCLK > 50 MHz and < 135 MHz (144-lead version).
JCLK > 50 MHz and < 115 MHz (121-lead version).
HCLK < 108 MHz (144-lead, 150 MHz version).
HCLK < 100 MHz (144-lead, 135 MHz version).
HCLK < 81 MHz (121-lead version).
JCLK ≥ 2 × VCLK for single-component input.
JCLK ≥ 2 × VCLK for YCrCb [4:2:2] input.
In JDATA mode (JDATA), JCLK must be 4 × MCLK or
higher.
BYPASS
IPD
MCLK
PHASE
DETECT
JCLK
HCLK
2
LPF
VCO
2
2
PLLMULT
HCLKD
LFB
•
For de-interlaced modes, JCLK must be ≥ 4 × MCLK.
Figure 23. PLL Architecture and Control Functions
Table 21. Recommended PLL Register Settings
IPD
LFB
PLLMULT
HCLKD
HCLK
JCLK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
N
N
N
N
N
N
N
N
0
1
0
1
0
1
0
1
N × MCLK
N × MCLK
N × MCLK
N × MCLK/2
2 × N × MCLK
N × MCLK
N × MCLK/2
N × MCLK/4
N × MCLK
2 × N × MCLK
2 × N × MCLK
N × MCLK/2
N × MCLK/2
N × MCLK
N × MCLK/2
N × MCLK
Table 22. Recommended Values for PLL_HI and PLL_LO Registers
Video Standard
CLKIN Frequency on MCLK
PLL_HI
0x0008
0x0008
0x0008
0x0008
PLL_LO
SMPTE125M or ITU-R.BT656 (NTSC or PAL)
SMPTE293M (525p)
ITU-R.BT1358 (625p)
27 MHz
27 MHz
27 MHz
74.25 MHz
0x0004
0x0004
0x0004
0x0084
SMPTE274M (1080i)
HARDWARE BOOT
The boot mode can be configured via hardware using the CFG pins or via software (see the ADV202 User’s Guide). The first boot mode
after power-up is set by the CFG pins. Only Boot Mode 2, Boot Mode 4, and Boot Mode 6, described in Table 23, are available via hardware.
Table 23. Hardware Boot Modes
Boot Mode
Hardware Boot CFG[1] tied high,
Mode 2 CFG[2] tied low
Settings
Description
No-Boot Host Mode. ADV202 does not boot, but all internal registers and memory are accessible
through normal host I/O operations.
For details, see the ADV202 User’s Guide and the Getting Started with the ADV202 application note.
Hardware Boot CFG[1] tied low,
Mode 4 CFG[2] tied high
Hardware Boot CFG[1] and CFG[2]
Mode 6 tied high
SoC Boot Mode.
Reserved.
Rev. D | Page 31 of 40
ADV202
VIDEO INPUT FORMATS
The ADV202 supports a wide variety of formats for
uncompressed video and still image data. The actual interface
and bus modes selected for transferring uncompressed data
dictates the allowed size of the input data and the number of
samples transferred with each access.
single component or YCbCr 4:2:2 formats. See the ADV202
User’s Guide for details. All formats can support less precision
than provided by specifying the actual data width/precision in
the PMODE register.
The maximum allowable data input rate is limited by using
irreversible or reversible compression modes and the data width
(or precision) of the input samples. Use Table 24 and Table 25 to
determine the maximum data input rate.
The host interface can support 8-, 10-, 12-, 14-, and 16-bit data
formats. The video interface can support video data or still image
data input/output. Supported formats are 8-, 10-, 12-, or 16-bit
Table 24. Maximum Pixel Data Input Rates
Approx Max Output Rate,
Compression
Interface Mode
144-LEAD PACKAGE
HDATA
Input Rate Limit Active
Input Format Resolution (MSPS)1
Approx Min Output Rate,
Compressed Data2 (Mbps)
Compressed Data3
(Mbps)
Irreversible
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
Reversible
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
8-bit data
10-bit data
12-bit data
16-bit data
8-bit data
10-bit data
12-bit data
14-bit data
8-bit data
10-bit data
12-bit data
8-bit data
10-bit data
12-bit data
45 [40]
45 [40]
45 [40]
45 [40]
40 [36]
32 [28]
27 [24]
23 [20]
65 [55]
65 [55]
65 [55]
40 [34]
32 [28]
27 [23]
130
130
130
130
130
130
130
130
130
130
130
130
130
130
200
200
200
200
200
200
200
200
200
200
200
200
200
200
VDATA
121-LEAD PACKAGE
HDATA
Irreversible
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
Reversible
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
8-bit data
10-bit data
12-bit data
16-bit data
8-bit data
10-bit data
12-bit data
14-bit data
8-bit data
10-bit data
12-bit data
8-bit data
10-bit data
12-bit data
34
34
34
34
30
24
20
17
48
48
48
30
24
20
98
98
98
98
98
98
98
98
98
98
98
98
98
98
150
150
150
150
150
150
150
150
150
150
150
150
150
150
VDATA
1 Input rate limits for HDATA can be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings. Values
in brackets refer to the 135 MHz speed grade version of the ADV202.
2 Minimum guaranteed sustained output rate or minimum sustainable compression rate (input rate/minimum peak output rate).
3 Maximum peak output rate, or output rate above this value is not possible .
Rev. D | Page 32 of 40
Data Sheet
ADV202
Table 25. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses
Compression Mode
Input Format
Tile/Precinct Maximum Width
9/7i
9/7i
9/7i
5/3i
5/3i
5/3i
5/3r
5/3r
5/3r
Single-component
Two-component
Three-component
Single-component
Two-component
Three-component
Single-component
Two-component
Three-component
2048
1024 each
1024 (Y)
4096
2048 (each)
2048 (Y)
4096
2048
1024
Rev. D | Page 33 of 40
ADV202
Data Sheet
APPLICATIONS
This section describes typical video applications for the
ADV202 JPEG2000 video processor.
In decode mode, a master/slave configuration (as shown in
Figure 25) or a slave/slave configuration can be used to
synchronize the outputs of the two ADV202s. See AN-796
ADV202 Multichip Application application note for details on
how to configure the ADV202s in a multichip application.
ENCODE—MULTICHIP MODE
Due to the data input rate limitation (see Table 24), an 1080i
application requires at least two ADV202s to encode or decode
full-resolution 1080i video. In encode mode, the ADV202
accepts Y and CbCr data on separate buses. The input data must
be in EAV/SAV format. An encode example is shown in Figure 24.
Applications that have two separate VDATA outputs sent to an
FPGA or buffer before they are sent to an encoder do not
require synchronization at the ADV202 outputs
32-BIT HOST CPU
ADV202
_1_SLAVE
HDATA[31:0]
10-BIT SD/HD
VIDEO
DECODER
DATA[31:0]
ADDR[3:0]
CS
ADDR[3:0]
CS
1080i
LLC
RD
RD
VCLK
MCLK
VIDEO IN
WR
WE
ACK
ACK
IRQ
Y
VDATA[11:2]
Y[9:0]
IRQ
DREQ
DACK
DREQ
DACK
FIELD
VSYNC
HSYNC
CbCr
G I/O
SCOMM[5]
C[9:0]
ADV202
_2_SLAVE
HDATA[31:0]
VCLK
MCLK
ADDR[3:0]
CS
RD
CS
RD
HSYNC
VSYNC
FIELD
WR
ACK
IRQ
WE
ACK
IRQ
CbCr
VDATA[11:2]
DREQ
DACK
DREQ
DACK
SCOMM[5]
Figure 24. Encode—Multichip Application
Rev. D | Page 34 of 40
Data Sheet
ADV202
DECODE—MULTICHIP MASTER/SLAVE
In a master/slave configuration, it is expected that the master HVF
outputs are connected to the slave HVF inputs and that each
SCOMM[5] pin is connected to the same GPIO on the host.
In a slave/slave configuration, the common HVF for both
ADV202s is generated by an external house sync, and each
SCOMM[5] is connected to the same GPIO output on the host.
SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be
unmasked on both devices to enable multichip mode.
74.25MHz
OSC
32-BIT HOST CPU
ADV202
_1_MASTER
10-BIT SD/HD
VIDEO
ENCODER
DATA[31:0]
ADDR[3:0]
CS
HDATA[31:0]
ADDR[3:0]
CS
RD
RD
1080i
VIDEO OUT
VCLK
MCLK
CLKIN
Y[9:0]
WR
WE
ACK
ACK
IRQ
Y
Y
VDATA[11:2]
IRQ
DREQ
DACK
DREQ
DACK
FIELD
VSYNC
HSYNC
CbCr
G I/O
SCOMM[5]
C[9:0]
ADV202
HDATA[31:0]
ADDR[3:0]
VCLK
MCLK
CS
RD
CS
RD
HSYNC
VSYNC
FIELD
WR
ACK
IRQ
WE
ACK
IRQ
CbCr
VDATA[11:2]
DREQ
DACK
DREQ
DACK
SCOMM[5]
Figure 25. Decode—Multichip Master/Slave Application
DIGITAL STILL CAMERA/CAMCORDER
Figure 26 is a typical configuration for a digital camera or camcorder.
AD9843A
D[9:0]
FPGA
ADV202
MCLK
10
DATA INPUTS[9:0]
VCLK
16-BIT
HOST CPU
VFRM
SDATA
SCK
SL
SERIAL DATA
SERIAL CLK
SERIAL EN
VRDY
VSTRB
VDATA[15:6]
HDATA[15:0]
DATA[15:0]
ADDR[3:0]
CS
ADDR[3:0]
CS
RD
RD
WE
WE
ACK
IRQ
ACK
IRQ
Figure 26. Digital Still Camera/Camcorder Encode Application for 10-Bit Pixel Data Using Raw Pixel Mode
Rev. D | Page 35 of 40
ADV202
Data Sheet
ENCODE/DECODE SDTV VIDEO APPLICATION
Figure 27 shows two ADV202 chips using 10-bit CCIR656 in normal host mode.
ENCODE MODE
ADV202
10-BIT
VIDEO
DECODER
VIDEO IN
VDATA[11:2]
P[19:10]
VCLK
MCLK
32-BIT
HOST CPU
LLC1
DATA[31:0]
INTR
HDATA[31:0]
IRQ
ADDR[3:0]
CS
ADDR[3:0]
CS
RD
RD
WE
WE
ACK
ACK
DECODE MODE
ADV202
10-BIT
VIDEO
ENCODER
VIDEO OUT
VDATA[11:2]
VCLK
P[9:0]
CLKIN
32-BIT
HOST CPU
MCLK
DATA[31:0]
INTR
HDATA[31:0]
IRQ
27MHz
OSC
ADDR[3:0]
CS
ADDR[3:0]
CS
RD
RD
WE
WE
ACK
ACK
Figure 27. Encode/Decode—SDTV Video Application
Rev. D | Page 36 of 40
Data Sheet
ADV202
ASIC APPLICATION (32-BIT HOST/32-BIT ASIC)
Figure 28 shows two ADV202 chips using 10-bit CCIR656 in normal host mode.
ASIC
ADV202
10-BIT
VIDEO
DECODER
VIDEO IN
DREQ0
DACK0
DREQ0
DACK0
VDATA[11:2]
VCLK
P[19:10]
DATA[31:0]
HDATA[31:0]
LLC1
MCLK
32-BIT
HOST CPU
DATA[31:0]
IRQ
ADDR[3:0]
CS
IRQ
ADDR[3:0]
CS
RD
RD
WE
WE
ACK
ACK
ENCODE MODE
ASIC
ADV202
10-BIT
VIDEO
ENCODER
VIDEO OUT
DREQ0
DACK0
DREQ0
DACK0
VDATA[11:2]
VCLK
P[9:0]
CLKIN
DATA[31:0]
HDATA[31:0]
MCLK
31 -BIT
HOST CPU
DATA[31:0]
27MHz
OSC
IRQ
ADDR[3:0]
CS
IRQ
ADDR[3:0]
CS
RD
RD
WE
WE
ACK
ACK
DECODE MODE
Figure 28. Encode/Decode ASIC Application
Rev. D | Page 37 of 40
ADV202
Data Sheet
HIPI (HOST INTERFACE—PIXEL INTERFACE)
Figure 29 is a typical configuration using HIPI mode.
Y0/G0<MSB>
Y0/G0<6>
Y0/G0<5>
Y0/G0<4>
Y0/G0<3>
Y0/G0<2>
Y0/G0<1>
Y0/G0<0>
Cb0/G1<MSB>
Cb0/G1<6>
Cb0/G1<5>
Cb0/G1<4>
Cb0/G1<3>
Cb0/G1<2>
Cb0/G1<1>
Cb0/G1<0>
Y1/G2<MSB>
Y1/G2<6>
Y1/G2<5>
Y1/G2<4>
Y1/G2<3>
Y1/G2<2>
Y1/G2<1>
Y1/G2<0>
Cr0/G3<MSB>
Cr0/G3<6>
Cr0/G3<5>
Cr0/G3<4>
Cr0/G3<3>
Cr0/G3<2>
Cr0/G3<1>
Cr0/G3<0>
HDATA<31>
HDATA<30>
HDATA<29>
HDATA<28>
HDATA<27>
HDATA<26>
HDATA<25>
HDATA<24>
HDATA<23>
HDATA<22>
HDATA<21>
HDATA<20>
HDATA<19>
HDATA<18>
HDATA<17>
HDATA<16>
HDATA<15>
HDATA<14>
HDATA<13>
HDATA<12>
HDATA<11>
HDATA<10>
HDATA<9>
HDATA<8>
HDATA<7>
HDATA<6>
HDATA<5>
HDATA<4>
HDATA<3>
HDATA<2>
HDATA<1>
HDATA<0>
32-BIT HOST
DATA [31:0]
CS
RD
CS
RD
WR
ACK
IRQ
WE
ACK
IRQ
DREQ
DACK
DREQ0
DACK0
RAW PIXEL
DATAPATH
DREQ
DACK
DREQ1
DACK1
COMPRESSED
DATAPATH
74.25MHz
MCLK
Figure 29. Host Interface—Pixel Interface Mode
JDATA INTERFACE
Figure 30 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR656.
ASIC
ADV202
YCrCb
JDATA[7:0] VDATA[11:2]
HOLD
P[19:10]
VIDEO IN
FIELD
VALID
FIELD
VS
HS
VSYNC
HSYNC
16-BIT
VCLK
HOST CPU
MCLK
LLC1
DATA[15:0]
HDATA[15:0]
IRQ
ADDR[3:0]
CS
IRQ
ADDR[3:0]
CS
RD
RD
WE
WE
ACK
ACK
Figure 30. JDATA Application
Rev. D | Page 38 of 40
Data Sheet
ADV202
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
12.20
12.00 SQ
11.80
11 10
7 1
9 8 6
4 2
5 3
A
B
C
D
E
F
BALL A1
CORNER
10.00
BSC SQ
G
H
J
1.00
BSC
K
L
BOTTOM VIEW
DETAIL A
TOP VIEW
DETAIL A
*
1.85
1.71
1.40
*
1.31
1.21
1.11
0.50 NOM
0.30 MIN
0.20
COPLANARITY
0.70
0.60
0.50
SEATING
PLANE
BALL DIAMETER
*COMPLIANT WITH JEDEC STANDARDS MO-192-ABD-1 WITH
EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.
Figure 31. 121-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-121-1)
Dimensions shown in millimeters
A1 CORNER
INDEX AREA
13 .00
BSC SQ
9
7
11
5
4
3
1
2
12
10
8
6
A
B
C
D
E
F
G
H
J
BALL A1
INDICATOR
11.00
BCS SQ
TOP VIEW
K
L
M
BOTTOM VIEW
DETAIL A
1.00 BSC
DETAIL A
*
1.85
MAX
*
1.32
1.21
1.11
0.53
0.43
COPLANARITY
0.20 MAX
0.70
0.60
0.50
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT WITH JEDEC STANDARDS MO-192-AAD-1 WITH
EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.
Figure 32. 144-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-3)
Dimensions shown in millimeters
Rev. D | Page 39 of 40
ADV202
Data Sheet
ORDERING GUIDE
Temperature
Range
Speed
Grade
Package
Option
Model1
Operating Voltage
Package Description
121-Lead CSP_BGA
121-Lead CSP_BGA
144-Lead CSP_BGA
144-Lead CSP_BGA
144-Lead CSP_BGA
ADV202BBCZ-115
ADV202BBCZRL-115
ADV202BBCZ-135
ADV202BBCZ-150
ADV202BBCZRL-150
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
115 MHz
115 MHz
135 MHz
150 MHz
150 MHz
1.5 V Internal, 2.5 V or 3.3 V I/O
1.5 V Internal, 2.5 V or 3.3 V I/O
1.5 V Internal, 2.5 V or 3.3 V I/O
1.5 V Internal, 2.5 V or 3.3 V I/O
1.5 V Internal, 2.5 V or 3.3 V I/O
BC-121-1
BC-121-1
BC-144-3
BC-144-3
BC-144-3
1 Z = RoHS Compliant Part.
©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04723-0-1/12(D)
Rev. D | Page 40 of 40
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