ADV7176A_15_技术文档

High Quality, 10-Bit, Digital CCIR-601

to PAL/NTSC Video Encoder

a

ADV7175A/ADV7176A*

CCIR and Square Pixel Operation

FEATURES

Integrated Subcarrier Locking to External Video Source

Color Signal Control/Burst Signal Control

Interlaced/Noninterlaced Operation

Complete On-Chip Video Timing Generator

Programmable Multimode Master/Slave Operation

Macrovision Antitaping Rev 7.01 (ADV7175A Only)**

Closed Captioning Support

ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder

High Quality 10-Bit Video DACs

Integral Nonlinearity <1 LSB at 10 Bits

NTSC-M, PAL-M/N, PAL-B/D/G/H/I

Single 27 MHz Clock Required (

؋

2 Oversampling)

80 dB Video SNR

32-Bit Direct Digital Synthesizer for Color Subcarrier

Multistandard Video Output Support:

Composite (CVBS)

Teletext Insertion Port (PAL-WST)

Onboard Color Bar Generation

Onboard Voltage Reference

Component S-Video (Y/C)

Component YUV and RGB

EuroSCART Output (RGB + CVBS/LUMA)

Video Input Data Port Supports:

2-Wire Serial MPU Interface (I²C Compatible)

Single Supply 5 V or 3 V Operation

Small 44-Lead MQFP Thermally Enhanced Package

CCIR-656 4:2:2 8-Bit Parallel Input Format

4:2:2 16-Bit Parallel Input Format

Full Video Output Drive or Low Signal Drive Capability

34.7 mA max into 37.5 ⍀ (Doubly-Terminated 75R)

5 mA min with External Buffers

APPLICATIONS

MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/

Cable Systems (Set Top Boxes/IRDs), Digital TVs,

CD Video/Karaoke, Video Games, PC Video/Multimedia

Programmable Simultaneous Composite

and S-Video Y/C or RGB (SCART)/YUV Video Outputs

Programmable Luma Filters (Low-Pass/Notch/Extended)

Programmable VBI (Vertical Blanking Interval)

Programmable Subcarrier Frequency and Phase

Programmable LUMA Delay

GENERAL DESCRIPTION

The ADV7175A/ADV7176A is an integrated digital video encoder

that converts Digital CCIR-601 4:2:2 8 or 16-bit component

video data into a standard analog baseband television signal

Individual ON/OFF Control of Each DAC

(Continued on page 11)

FUNCTIONAL BLOCK DIAGRAM

M

U

L

T

I

P

L

E

X

E

R

10

TELETEXT

INSERTION

BLOCK

TTX

10-BIT

DAC

DAC D (PIN 27)

DAC C (PIN 26)

DAC B (PIN 31)

TTXREQ

YUV TO

RBG

10-BIT

DAC

MATRIX

V

AA

10-BIT

DAC

Y

8

10

8

INTER-

ADD

LOW-PASS

FILTER

COLOR

DATA

POLATOR

SYNC

YCrCb

P7–P0

4:2:2 TO

4:4:4

U

8

10

TO

YUV

INTER-

POLATOR

ADD

BURST

LOW-PASS

FILTER

INTER-

10

P15–P8

10-BIT

DAC

MATRIX

POLATOR

DAC A (PIN 32)

V

8

INTER-

POLATOR

ADD

BURST

LOW-PASS

FILTER

ADV7175A/ADV7176A

10

HSYNC

REAL-TIME

CONTROL

CIRCUIT

V

REF

VOLTAGE

REFERENCE

CIRCUIT

2

VIDEO TIMING

GENERATOR

FIELD/VSYNC

I C MPU PORT

SIN/COS

DDS BLOCK

R

SET

BLANK

COMP

SCRESET/RTC

CLOCK

SCLOCK SDATA ALSB

GND

RESET

The Macrovision anticopy process is

licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.

NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADV7175A/ADV7176A–SPECIFICATIONS

(V = 5 V ؎ 5%¹, V_REF= 1.235 V, R_SET= 150 ⍀. All specifications T_MINto T_MAX²unless otherwise noted)

5 V SPECIFICATIONS

AA

Parameter

Conditions¹

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution (Each DAC)

Accuracy (Each DAC)

Integral Nonlinearity

10

Bits

1

LSB

Differential Nonlinearity

Guaranteed Monotonic

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2

V

µA

pF

0.8

1

50

3

V_IN= 0.4 V or 2.4 V

4

Input Capacitance, C_IN

10

DIGITAL OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current

I_SOURCE= 400 µA

I_SINK= 3.2 mA

2.4

V

µA

pF

0.4

10

Three-State Output Capacitance

ANALOG OUTPUTS

Output Current⁵

33

0

34.7

5

0.6

37

mA

%

V

kΩ

pF

Output Current⁶

DAC-to-DAC Matching

Output Compliance, V_OC

Output Impedance, R_OUT

Output Capacitance, C_OUT

5

1.4

15

I_OUT= 0 mA

30

VOLTAGE REFERENCE

Reference Range, V_REF

POWER REQUIREMENTS⁷

V_AA

I_VREFOUT= 20 µA

1.112

4.75

1.235

5.0

1.359

V

5.25

155

150

Normal Power Mode

I_DAC(max)⁸

150

20

100

mA

I

_DAC(min)⁸

9

I_CCT

Low Power Mode

I

_DAC(max)⁸

80

15

100

0.01

mA

%/%

I_DAC(min)⁸

9

I_CCT

150

0.5

Power Supply Rejection Ratio

COMP = 0.1 µF

NOTES

¹The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

²Temperature range T_MINto T_MAX: 0°C to 70°C.

³All digital input pins except pins RESET and RTC/SCRESET.

⁴Excluding all digital input pins except pins RESET and RTC/SCRESET.

⁵Full drive into 37.5 Ω load.

⁶Minimum drive current (used with buffered/scaled output load).

⁷Power measurements are taken with Clock Frequency = 27 MHz. Max T_J= 110°C.

⁸I_DACis the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual

DACs reduces I_DACcorrespondingly.

⁹I_CCT(Circuit Current) is the continuous current required to drive the device.

Specifications subject to change without notice.

–2–

REV. C

ADV7175A/ADV7176A

(V = 3.0 V–3.6 V¹, V_REF= 1.235 V, R_SET= 300 ⍀. All specifications T_MINto T_MAX²unless otherwise noted)

3.3 V SPECIFICATIONS

AA

Parameter

Conditions¹

Min

Typ

Max

Unit

STATIC PERFORMANCE³

Resolution (Each DAC)

Accuracy (Each DAC)

Integral Nonlinearity

10

Bits

1

LSB

Differential Nonlinearity

Guaranteed Monotonic

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

2

0.8

V

µA

pF

3, 4

Input Current, I_IN

V_IN= 0.4 V or 2.4 V

1

50

3, 5

Input Capacitance, C_IN

10

DIGITAL OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current³

Three-State Output Capacitance³

I_SOURCE= 400 µA

I_SINK= 3.2 mA

2.4

0.4

V

µA

pF

10

ANALOG OUTPUTS³

Output Current^{6, 7}

16.5

0

17.35

5

2.0

18.5

mA

%

V

kΩ

pF

Output Current⁸

DAC-to-DAC Matching

Output Compliance, V_OC

Output Impedance, R_OUT

Output Capacitance, C_OUT

1.4

30

15

I_OUT= 0 mA

POWER REQUIREMENTS^{3, 9}

V_AA

3.0

3.3

3.6

V

Normal Power Mode

I_DAC(max)¹⁰

150

20

45

155

mA

I

_DAC(min)¹⁰

9

I_CCT

Low Power Mode

I

_DAC(max)¹⁰

75

15

45

0.01

mA

%/%

I_DAC(min)¹⁰

11

I_CCT

Power Supply Rejection Ratio

COMP = 0.1 µF

0.5

NOTES

¹¹The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.

¹²Temperature range T_MINto T_MAX: 0°C to 70°C.

¹³Guaranteed by characterization.

¹⁴All digital input pins except pins RESET and RTC/SCRESET.

¹⁵Excluding all digital input pins except pins RESET and RTC/SCRESET.

¹⁶Full drive into 37.5 Ω load.

¹⁷DACs can output 35 mA typically at 3.3 V (R_SET= 150 Ω and R_L= 75 Ω), optimum performance obtained at 18 mA DAC current (R_SET= 300 Ω and R_L= 150 Ω.

¹⁸Minimum drive current (used with buffered/scaled output load).

¹⁹Power measurements are taken with Clock Frequency = 27 MHz. Max T_J= 110°C.

10

I

is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual

DAC

DACs reduces I_DACcorrespondingly.

11

I

(Circuit Current) is the continuous current required to drive the device.

CCT

Specifications subject to change without notice.

REV. C

–3–

ADV7175A/ADV7176A–SPECIFICATIONS

2

(V_AA= 4.75 V–5.25 V¹, V_REF= 1.235 V, R_SET= 150 ⍀. All specifications T_MINto T_MAX

unless otherwise noted.)

5 V DYNAMIC SPECIFICATIONS¹

Parameter

Conditions¹

Min

Typ

Max

Unit

Filter Characteristics

Luma Bandwidth³(Low-Pass Filter)

Stopband Cutoff

Passband Cutoff F_{3 dB}

Chroma Bandwidth

Stopband Cutoff

Passband Cutoff F_{3 dB}

Luma Bandwidth³(Low-Pass Filter)

Stopband Cutoff

Passband Cutoff F_{3 dB}

Chroma Bandwidth

Stopband Cutoff

NTSC Mode

>54 dB Attenuation

>3 dB Attenuation

NTSC Mode

>40 dB Attenuation

>3 dB Attenuation

PAL Mode

>50 dB Attenuation

>3 dB Attenuation

PAL Mode

>40 dB Attenuation

>3 dB Attenuation

Normal Power Mode

Lower Power Mode

RMS

7.0

4.2

MHz

3.2

2.0

MHz

7.4

5.0

MHz

4.0

2.4

MHz

%

Degree

%

Degree

dB rms

dB p-p

dB rms

dB p-p

Degree

%

Passband Cutoff F_{3 dB}

Differential Gain⁴

0.4

2.0

1.0

80

70

60

58

0.5

1.0

0.6

0.2

0.4

0.1

0.6

2.0

1.0

66

Differential Phase⁴

Differential Gain⁴

Differential Phase⁴

SNR⁴(Pedestal)

Peak Periodic

RMS

Peak Periodic

SNR⁴(Ramp)

Hue Accuracy⁴

Color Saturation Accuracy⁴

Chroma Nonlinear Gain⁴

Chroma Nonlinear Phase⁴

Chroma/Luma Intermod⁴

Chroma/Luma Gain Ineq⁴

Chroma/Luma Delay Ineq⁴

Luminance Nonlinearity⁴

Chroma AM Noise⁴

Chroma PM Noise⁴

Referenced to 40 IRE

NTSC

PAL

Referenced to 714 mV (NTSC)

Referenced to 700 mV (PAL)

%

Degree

%

ns

%

dB

63

NOTES

¹The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

²Temperature range T_MINto T_MAX: 0°C to 70°C.

³These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.

⁴Guaranteed by characterization.

Specifications subject to change without notice.

–4–

REV. C

ADV7175A/ADV7176A

2

(V_AA= 3.0 V–3.6 V¹, V_REF= 1.235 V, R_SET= 300 ⍀. All specifications T_MINto T_MAX

unless otherwise noted.)

3.3 V DYNAMIC SPECIFICATIONS¹

Parameter

Conditions¹

Min

Typ

Max

Unit

Filter Characteristics

Luma Bandwidth³(Low-Pass Filter)

Stopband Cutoff

Passband Cutoff F_{3 dB}

Chroma Bandwidth

Stopband Cutoff

Passband Cutoff F_{3 dB}

Luma Bandwidth³(Low-Pass Filter)

Stopband Cutoff

Passband Cutoff F_{3 dB}

Chroma Bandwidth

Stopband Cutoff

NTSC Mode

>54 dB Attenuation

>3 dB Attenuation

NTSC Mode

>40 dB Attenuation

>3 dB Attenuation

PAL Mode

>50 dB Attenuation

>3 dB Attenuation

PAL Mode

>40 dB Attenuation

>3 dB Attenuation

Normal Power Mode

RMS

7.0

4.2

MHz

3.2

2.0

MHz

7.4

5.0

MHz

4.0

2.4

MHz

%

Degree

dB rms

dB p-p

dB rms

dB p-p

Degree

%

dB

Passband Cutoff F_{3 dB}

Differential Gain⁴

0.7

0.5

75

68

58

Differential Phase⁴

SNR⁴(Pedestal)

Peak Periodic

RMS

Peak Periodic

SNR⁴(Ramp)

56

Hue Accuracy⁴

1.0

1.2

1.1

67

63

64

Color Saturation Accuracy⁴

Luminance Nonlinearity⁴

Chroma AM Noise⁴

Chroma PM Noise⁴

Chroma AM Noise⁴

Chroma PM Noise⁴

NTSC

PAL

63

dB

NOTES

¹The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.

²Temperature range T_MINto T_MAX: 0°C to 70°C.

³These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.

⁴Guaranteed by characterization.

Specifications subject to change without notice.

REV. C

–5–

ADV7175A/ADV7176A

(V_AA= 4.75 V–5.25 V¹, V_REF= 1.235 V, R_SET= 150 ⍀. All specifications T_MINto T_MAX²unless

5 V TIMING SPECIFICATIONS

otherwise noted.)

Parameter

Conditions

Min

Typ

Max

Unit

MPU PORT^{3, 4}

SCLOCK Frequency

0

100

kHz

µs

SCLOCK High Pulsewidth, t₁

SCLOCK Low Pulsewidth, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDATA, SCLOCK Rise Time, t₆

SDATA, SCLOCK Fall Time, t₇

Setup Time (Stop Condition), t₈

4.0

4.7

4.0

4.7

250

µs

After This Period the First Clock Is Generated

Relevant for Repeated Start Condition

µs

ns

µs

1

300

ns

µs

4.7

ANALOG OUTPUTS^{3, 5}

Analog Output Delay

DAC Analog Output Skew

5

0

ns

CLOCK CONTROL

AND PIXEL PORT^{3, 6}

F_CLOCK

27

MHz

Clock High Time, t₉

Clock Low Time, t₁₀

Data Setup Time, t₁₁

Data Hold Time, t₁₂

Control Setup Time, t₁₁

Control Hold Time, t₁₂

Digital Output Access Time, t₁₃

Digital Output Hold Time, t₁₄

Pipeline Delay, t₁₅

8

3.5

4

ns

3

24

4

37

Clock Cycles

TELETEXT PORT^{3, 7}

Digital Output Access Time, t₁₆

Data Setup Time, t₁₇

20

1

2

ns

Data Hold Time, t₁₈

RESET CONTROL^{3, 4}

RESET Low Time

6

ns

NOTES

¹The max/min specifications are guaranteed over this range.

²Temperature range T_MINto T_MAX: 0°C to 70°C.

³TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. Analog output load ≤ 10 pF.

⁴Guaranteed by characterization.

⁵Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

⁶Pixel Port consists of the following:

Pixel Inputs:

Pixel Controls:

Clock Input:

P15–P0

HSYNC, FIELD/VSYNC, BLANK

CLOCK

⁷Teletext Port consists of the following:

Teletext Output:

Teletext Input:

TTXREQ

TTX

Specifications subject to change without notice.

–6–

REV. C

ADV7175A/ADV7176A

(V_AA= 3.0–3.6¹, V_REF= 1.235 V, R_SET= 300 ⍀. All specifications T_MINto T_MAX²unless

otherwise noted.)

3.3 V TIMING SPECIFICATIONS

Parameter

Conditions

Min

Typ

Max

Unit

MPU PORT^{3, 4}

SCLOCK Frequency

0

100

kHz

µs

SCLOCK High Pulsewidth, t₁

SCLOCK Low Pulsewidth, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDATA, SCLOCK Rise Time, t₆

SDATA, SCLOCK Fall Time, t₇

Setup Time (Stop Condition), t₈

4.0

4.7

4.0

4.7

250

µs

After This Period the First Clock Is Generated

for Repeated Start Condition

µs

ns

µs

1

300

ns

µs

4.7

ANALOG OUTPUTS^{3, 5}

Analog Output Delay

DAC Analog Output Skew

7

0

ns

CLOCK CONTROL

AND PIXEL PORT^{3, 4, 6, 7}

F_CLOCK

27

MHz

Clock High Time, t₉

Clock Low Time, t₁₀

Data Setup Time, t₁₁

Data Hold Time, t₁₂

Control Setup Time, t₁₁

Control Hold Time, t₁₂

Digital Output Access Time, t₁₃

Digital Output Hold Time, t₁₄

Pipeline Delay, t₁₅

8

3.5

4

ns

3

24

4

37

Clock Cycles

TELETEXT PORT^{3, 6, 8}

Digital Output Access Time t₁₆

Data Setup Time, t₁₇

23

2

ns

Data Hold Time, t₁₈

RESET CONTROL^{3, 4}

RESET Low Time

6

ns

NOTES

¹The max/min specifications are guaranteed over this range.

²Temperature range T_MINto T_MAX: 0^oC to 70^oC.

³TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. Analog output load ≤ 10 pF.

⁴Guaranteed by characterization.

⁵Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

⁶Characterized by design.

⁷Pixel Port consists of the following:

Pixel Inputs:

Pixel Controls:

Clock Input:

P15–P0

HSYNC, FIELD/VSYNC, BLANK

CLOCK

⁸Teletext Port consists of the following:

Teletext Output:

Teletext Input:

TTXREQ

TTX

Specifications subject to change without notice.

REV. C

–7–

ADV7175A/ADV7176A

t₅

t₃

SDATA

t₆

t₁

SCLOCK

t₂

t₇

t₄

t₈

Figure 1. MPU Port Timing Diagram

CLOCK

t₁₂

t₉

t₁₀

HSYNC,

FIELD/VSYNC,

BLANK

CONTROL

I/PS

PIXEL INPUT

DATA

Cb

Y

Cr

Y

Cb

Y

t₁₁

t₁₃

HSYNC,

FIELD/VSYNC,

BLANK

CONTROL

O/PS

t₁₄

Figure 2. Pixel and Control Data Timing Diagram

TTXREQ

CLOCK

t₁₆

t₁₇

t₁₈

TTX

4 CLOCK

CYCLES

4 CLOCK

CYCLES

4 CLOCK

CYCLES

3 CLOCK

CYCLES

Figure 3. Teletext Timing Diagram

–8–

REV. C

ADV7175A/ADV7176A

PACKAGE THERMAL PERFORMANCE

ABSOLUTE MAXIMUM RATINGS¹

The 44-MQFP package used for this device takes advantage of

an ADI patented thermal coastline lead frame construction.

This maximizes heat transfer into the leads and reduces the

package thermal resistance.

V_AAto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on Any Digital Input Pin . GND – 0.5 V to V_AA+ 0.5 V

Storage Temperature (T_S) . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T_J) . . . . . . . . . . . . . . . . . . . . . . 150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 260°C

Analog Outputs to GND². . . . . . . . . . . . . GND – 0.5 to V_AA

The junction-to-ambient (θ_JA) thermal resistance in still air on a

four-layer PCB is 35.5°C/W. The junction-to-case thermal

resistance (θ_JC) is 13.75°C/W.

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those listed in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

²Analog output short circuit to any power supply or common can be of an indefinite

duration.

ORDERING GUIDE

Temperature Package

Range Description

Package

Option

Model

ADV7175AKS 0°C to 70°C

ADV7176AKS 0°C to 70°C

Plastic Quad Flatpack S-44

PIN CONFIGURATION

42

44 43

PIN 1

41 40 39 38 37 36 35 34

1

2

33

32

V

AA

REF

DAC A

IDENTIFIER

P5

P6

3

31 DAC B

V

30

4

P7

AA

5

29 GND

P8

ADV7175A/ADV7176A

V

6

MQFP

28

27

P9

AA

DAC D

TOP VIEW

(Not to Scale)

7

P10

P11

P12

GND

8

26 DAC C

25 COMP

24 SDATA

9

10

11

V

23

SCLOCK

AA

13

12

14 15 16 17 18 19

21 22

20

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADV7175A/ADV7176A feature proprietary ESD protection circuitry, permanent

damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,

proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. C

–9–

ADV7175A/ADV7176A

PIN FUNCTION DESCRIPTIONS

Input/

No.

Mnemonic

Output

Function

1, 11, 20,

28, 30

10, 19, 21,

29, 43

V_AA

P

Power Supply (3 V to 5 V).

Ground Pin.

GND

G

15

HSYNC

I/O

HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to

output (Master Mode) or accept (Slave Mode) Sync signals.

16

FIELD/VSYNC

I/O

Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This

pin may be configured to output (Master Mode) or accept (Slave Mode)

these control signals.

17

BLANK

Video Blanking Control Signal. The pixel inputs are ignored when this is

logic level “0.” This signal is optional.

18

22

ALSB

RESET

I

TTL Address Input. This signal sets up the LSB of the MPU address.

The input resets the on chip timing generator and sets the ADV7175A/

ADV7176A into default mode. This is NTSC operation, Timing Slave Mode

0, 8-bit operation, 2 × composite and S-Video out and all DACs powered on.

23

24

25

SCLOCK

SDATA

COMP

I

I/O

O

MPU Port Serial Interface Clock Input.

MPU Port Serial Data Input/Output.

Compensation Pin. Connect a 0.1 µF capacitor from COMP to V_AA. For

Optimum Dynamic Performance in Low Power Mode, the value of the

COMP capacitor can be lowered to as low as 2.2 nF.

26

27

31

32

DAC C

DAC D

DAC B

DAC A

O

RED/S-Video C/V Analog Output.

GREEN/S-Video Y/Y Analog Output.

BLUE/Composite/U Analog Output.

PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286

mV) for NTSC and 1300 mV for PAL.

33

34

V_REF

R_SET

I/O

I

Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

A 150 Ω resistor connected from this pin to GND is used to control full-scale

amplitudes of the video signals.

35

SCRESET/RTC

I

This pin can be configured as an input by setting MR22 and MR21 of Mode

Register 2. It can be configured as a subcarrier reset pin, in which case a low-

to-high transition on this pin will reset the subcarrier to Field 0. Alternatively

it may be configured as a Real Time Control (RTC) input.

36

37

TTXREQ/GND

TTX/V_AA

O

I

Teletext Data Request Signal/Defaults to GND when Teletext not selected

(enables backward compatibility to ADV7175/ADV7176).

Teletext Data/Defaults to V_AAwhen Teletext not selected (enables backward

compatibility to ADV7175/ADV7176).

38–42

P0–P15

I

8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or

2–9, 12–14

16-Bit YCrCb Pixel Port (P0–P15). P0 represents the LSB.

44

CLOCK

I

TTL Clock Input. Requires a stable 27 MHz reference Clock for standard

operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be

used for square pixel operation.

–10–

REV. C

ADV7175A/ADV7176A

(Continued from page 1)

DATA PATH DESCRIPTION

For PAL B, D, G, H, I, M, N and NTSC M modes, YCrCb

4:2:2 data is input via the CCIR-656 compatible pixel port at a

27 MHz Data Rate. The pixel data is demultiplexed to from

three data paths. Y typically has a range of 16 to 235, Cr and

Cb typically have a range of 128 112; however, it is pos-

sible to input data from 1 to 254 on both Y, Cb and Cr. The

ADV7175A/ADV7176A supports PAL (B, D, G, H, I, N, M)

and NTSC (with and without Pedestal) standards. The appropri-

ate SYNC, BLANK and Burst levels are added to the YCrCb

data. Macrovision antitaping (ADV7175A only), closed caption-

ing and teletext levels are also added to Y, and the resultant

data is interpolated to a rate of 27 MHz. The interpolated data

is filtered and scaled by three digital FIR filters.

compatible with worldwide standards. The 4:2:2 YUV video

data is interpolated to two times the pixel rate. The color-

difference components (UV) are quadrature modulated using

a subcarrier frequency generated by an on-chip 32-bit digital

synthesizer (also running at two times the pixel rate). The two

times pixel rate sampling allows for better signal-to-noise-ratio.

A 32-bit DDS with a 10-bit look-up table produces a superior

subcarrier in terms of both frequency and phase. In addition to

the composite output signal, there is the facility to output S-

Video (Y/C) video, YUV or RGB video. The Y/C, YUV or RGB

format is simultaneously available at the analog outputs with the

composite video signal.

Each analog output is capable of driving the full video-level

(35 mA) signal into an unbuffered, doubly terminated 75 Ω

load. With external buffering, the user has the additional option

to scale back the DAC output current to 5 mA min, thereby signifi-

cantly reducing the power dissipation of the device.

The U and V signals are modulated by the appropriate subcarrier

sine/cosine phases and added together to make up the chromi-

nance signal. The luma (Y) signal can be delayed 1–3 luma

cycles (each cycle is 74 ns) with respect to the chroma signal.

The luma and chroma signals are then added together to make

up the composite video signal. All edges are slew rate limited.

The ADV7175A/ADV7176A also supports both PAL and NTSC

square pixel operation.

The YCrCb data is also used to generate RGB data with

appropriate SYNC and BLANK levels. The RGB data is in

synchronization with the composite video output. Alternatively

analog YUV data can be generated instead of RGB.

The output video frames are synchronized with the incoming

data timing reference codes. Optionally the encoder accepts

(and can generate) HSYNC, VSYNC and FIELD timing signals.

These timing signals can be adjusted to change pulsewidth and

position while the part is in the master mode. The encoder

requires a single two times pixel rate (27 MHz) clock for standard

operation. Alternatively, the encoder requires a 24.5454 MHz

clock for NTSC or 29.5 MHz clock for PAL square pixel

mode operation. All internal timing is generated on-chip.

The four 10-bit DACs can be used to output:

1. Composite Video + RGB Video.

2. Composite Video + YUV Video

3. Two Composite Video Signals + LUMA and CHROMA

3. (Y/C) Signals.

A separate teletext port enables the user to directly input teletext

data during the vertical blanking interval.

Alternatively, each DAC can be individually powered off if

not required.

The ADV7175A/ADV7176A modes are set up over a two-wire

serial bidirectional port (I²C Compatible) with two slave addresses.

Video output levels are illustrated in Appendix 4 and Appendix 5.

INTERNAL FILTER RESPONSE

Functionally the ADV7175A and ADV7176A are the same with

the exception that the ADV7175A can output the Macrovision

anticopy algorithm.

The Y filter supports several different frequency responses,

including two 4.5 MHz/5.0 MHz low pass responses, PAL/

NTSC subcarrier notch responses and a PAL/NTSC extended

response. The U and V filters have a 2/2.4 MHz low-pass

response for NTSC/PAL. These filter characteristics are illus-

trated in Figures 4 to 12.

The ADV7175A/ADV7176A is packaged in a 44-lead thermally

enhanced MQFP package.

PASSBAND

CUTOFF (MHz)

PASSBAND

RIPPLE (dB)

STOPBAND

CUTOFF (MHz)

STOPBAND

ATTENUATION (dB)

F

3dB

FILTER SELECTION

MR04

MR03

NTSC

PAL

NTSC

PAL

NTSC/PAL

NTSC

PAL

0

1

0

1

0

1

2.3

3.4

1.0

1.4

4.0

2.3

3.4

0.026

0.098

0.085

0.107

0.150

0.054

0.106

7.0

7.3

3.57

4.43

7.5

>54

4.2

5.0

2.1

2.7

5.65

4.2

5.0

>50

>27.6

>29.3

>40

>54

>50.3

7.0

7.3

Figure 4. Luminance Internal Filter Specifications

PASSBAND

CUTOFF (MHz)

PASSBAND

RIPPLE (dB)

STOPBAND

CUTOFF (MHz)

STOPBAND

ATTENUATION (dB)

ATTENUATION @

1.3MHz (dB)

F

3dB

FILTER SELECTION

NTSC

PAL

1.0

1.3

0.085

0.04

3.2

4.0

>

40

0.3

0.02

2.05

2.45

>

Figure 5. Chrominance Internal Filter Specifications

–11–

REV. C

ADV7175A/ADV7176A

0

–10

–20

0

–10

TYPE A

–20

–30

–40

–50

–60

–30

–40

–50

–60

TYPE B

10

0

2

4

6

8

10

12

0

2

4

6

8

12

FREQUENCY – MHz

Figure 9. PAL Notch Filter

Figure 6. NTSC Low-Pass Filter

0

–10

–20

0

–10

–20

–30

–40

–50

–60

–30

–40

–50

–60

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY – MHz

Figure 10. NTSC/PAL Extended Mode Filter

Figure 7. NTSC Notch Filter

0

–10

–20

–10

TYPE B

–20

–30

–40

–50

–60

–30

–40

–50

–60

TYPE A

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY – MHz

Figure 11. NTSC UV Filter

Figure 8. PAL Low-Pass Filter

–12–

REV. C

ADV7175A/ADV7176A

0

–10

–20

SUBCARRIER RESET

Together with the SCRESET/RTC PIN and Bits MR22 and

MR21 of Mode Register 2, the ADV7175A/ADV7176A can be

used in subcarrier reset mode. The subcarrier will reset to

Field 0 at the start of the following field when a low to high

transition occurs on this input pin.

–30

–40

–50

–60

REAL TIME CONTROL

Together with the SCRESET/RTC PIN and Bits MR22 and

MR21 of Mode Register 2, the ADV7175A/ADV7176A can be

used to lock to an external video source. The real time control

mode allows the ADV7175A/ADV7176A to automatically alter

the subcarrier frequency to compensate for line length variation.

When the part is connected to a device that outputs a digital

datastream in the RTC format (such as an ADV7185 video

decoder [see Figure 13]), the part will automatically change to

the compensated subcarrier frequency on a line by line basis.

This digital datastream is 67 bits wide and the subcarrier is

contained in Bits 0 to 21. Each bit is two clock cycles long.

00HEX should be written to all four subcarrier frequency regis-

ters when using this mode.

0

2

4

6

8

10

12

FREQUENCY – MHz

Figure 12. PAL UV Filter

COLOR BAR GENERATION

The ADV7175A/ADV7176A can be configured to generate

100/7.5/75/7.5 for NTSC color bars or 100/0/75/0 for PAL

color bars. These are enabled by setting MR17 of Mode Reg-

ister 1 to Logic “1.”

VIDEO TIMING DESCRIPTION

The ADV7175A/ADV7176A is intended to interface to off-

the-shelf MPEG1 and MPEG2 Decoders. Consequently, the

ADV7175A/ADV7176A accepts 4:2:2 YCrCb Pixel Data via a

CCIR-656 pixel port and has several video timing modes of

operation that allow it to be configured as either system master

video timing generator or a slave to the system video timing

generator. The ADV7175A/ADV7176A generates all of the

required horizontal and vertical timing periods and levels for the

analog video outputs.

SQUARE PIXEL MODE

The ADV7175A/ADV7176A can be used to operate in square

pixel mode. For NTSC operation an input clock of 24.5454 MHz

is required. Alternatively an input clock of 29.5 MHz is required

for PAL operation. The internal timing logic adjusts accordingly

for square pixel mode operation.

COLOR SIGNAL CONTROL

The color information can be switched on and off the video

output using Bit MR24 of Mode Register 2.

The ADV7175A/ADV7176A calculates the width and place-

ment of analog sync pulses, blanking levels and color burst

envelopes. Color bursts are disabled on appropriate lines, and

serration and equalization pulses are inserted where required.

BURST SIGNAL CONTROL

The burst information can be switched on and off the video

output using Bit MR25 of Mode Register 2.

In addition the ADV7175A/ADV7176A supports a PAL or

NTSC square pixel operation in slave mode. The part requires

an input pixel clock of 24.5454 MHz for NTSC and an input

pixel clock of 29.5 MHz for PAL. The internal horizontal line

counters place the various video waveform sections in the cor-

rect location for the new clock frequencies.

NTSC PEDESTAL CONTROL

The pedestal on both odd and even fields can be controlled on a

line-by-line basis using the NTSC Pedestal Control Registers.

This allows the pedestals to be controlled during the vertical

blanking interval (Lines 10 to 25 and Lines 273 to 288).

The ADV7175A/ADV7176A has four distinct master and four

distinct slave timing configurations. Timing Control is estab-

lished with the bidirectional SYNC, BLANK and FIELD/

VSYNC pins. Timing Mode Register 1 can also be used to vary

the timing pulsewidths and where they occur in relation to

each other.

PIXEL TIMING DESCRIPTION

The ADV7175A/ADV7176A can operate in either 8-bit or

16-bit YCrCb Mode.

8-Bit YCrCb Mode

This default mode accepts multiplexed YCrCb inputs through

the P7-P0 pixel inputs. The inputs follow the sequence Cb0, Y0

Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a

rising clock edge.

16-Bit YCrCb Mode

This mode accepts Y inputs through the P7–P0 pixel inputs and

multiplexed CrCb inputs through the P15–P8 pixel inputs. The

data is loaded on every second rising edge of CLOCK. The inputs

follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.

REV. C

–13–

ADV7175A/ADV7176A

CLOCK

LLC1

SCRESET/RTC

GLL

COMPOSITE

VIDEO

e.g., VCR

OR CABLE

GREEN/LUMA/Y

RED/CHROMA/V

P7–P0

VIDEO

DECODER

ADV7185

P19–P12

BLUE/COMPOSITE/U

HSYNC

COMPOSITE

VSYNC/FIELD

ADV7175A/ADV7176A

SEQUENCE

RESERVED

2

BIT

H/LTRANSITION

COUNT START

RESET

4 BITS

RESERVED

5 BITS

RESERVED

3

BIT

LOW

128

14 BITS

RESERVED

1

FSCPLL INCREMENT

0

13

21

RTC

TIME SLOT: 01

6768

14

19

NOT USED IN

ADV7175A/ADV7176A

VALID

INVALID

8/LLC

SAMPLE SAMPLE

NOTES:

1

F

PLL INCREMENT IS 22 BITS LONG, VALUED LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS

SC

F

PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUB CARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD

SC

BE WRITTEN TO THE SUB CARRIER FREQUENCY REGISTERS OF THE ADV7175A/ADV7176A.

2

3

SEQUENCE BIT

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED

NTSC: 0 = NO CHANGE.

RESET BIT

RESET ADV7175A/ADV7176A’s DDS.

Figure 13. RTC Timing and Connections

Vertical Blanking Data Insertion

It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre/post-equalization

pulses (see Figures 15 to 26). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the

insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data

stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by

setting MR31 to 0.

Mode 0 (CCIR-656): Slave Option

(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7175A/ADV7176A is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel

data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately

before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 14. The HSYNC, FIELD/VSYNC and

BLANK (if not used) pins should be tied high during this mode.

–14–

REV. C

ADV7175A/ADV7176A

ANALOG

VIDEO

EAV CODE

SAV CODE

C

r

C

b

C

b

8

0

F

A A

B B

A

B

8

0

C

r

F

0

X

Y

1

0

8

0

1

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

r

Y

INPUT PIXELS

Y

ANCILLARY DATA

(HANC)

4 CLOCK

NTSC/PAL M SYSTEM

(525 LlNES/60Hz)

268 CLOCK

1440 CLOCK

1440 CLCOK

PAL SYSTEM

(625 LINES/50Hz)

280 CLOCK

END OF ACTIVE

VIDEO LINE

START OF ACTIVE

VIDEO LINE

Figure 14. Timing Mode 0 (Slave Mode)

Mode 0 (CCIR-656): Master Option

(Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7175A/ADV7176A generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video)

time codes in the CCIR-656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit

is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 15 (NTSC) and Figure 16 (PAL). The H, V and F transitions

relative to the video waveform are illustrated in Figure 17.

DISPLAY

VERTICAL BLANK

522

523

524

525

1

2

3

4

6

7

10

11

20

21

22

5

9

8

H

V

EVEN FIELD

ODD FIELD

F

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

H

V

ODD FIELD

EVEN FIELD

F

Figure 15. Timing Mode 0 (NTSC Master Mode)

REV. C

–15–

ADV7175A/ADV7176A

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

22

23

5

21

H

V

EVEN FIELD

ODD FIELD

F

DISPLAY

VERTICAL BLANK

335

336

318

334

309

310

311

312

313

314

315

316

317

319

320

H

V

F

ODD FIELD EVEN FIELD

Figure 16. Timing Mode 0 (PAL Master Mode)

ANALOG

VIDEO

H

F

V

Figure 17. Timing Mode 0 Data Transitions (Master Mode)

–16–

REV. C

ADV7175A/ADV7176A

Mode 1: Slave Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode the ADV7175A/ADV7176A accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input

when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled

the ADV7175A/ADV7176A automatically blanks all normally blank lines. Mode 1 is illustrated in Figure 18 (NTSC) and Fig-

ure 19 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

1

2

3

4

6

7

8

10

11

5

9

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

Figure 18. Timing Mode 1 (NTSC)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

5

21

22

23

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 19. Timing Mode 1 (PAL)

REV. C

–17–

ADV7175A/ADV7176A

Mode 1: Master Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode the ADV7175A/ADV7176A can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD

input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is

disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge

following the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the

HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.

HSYNC

FIELD

PAL = 12 * CLOCK/2

NTSC = 16 * CLOCK/2

BLANK

PIXEL

DATA

Cb

Y

Cr

Y

PAL = 132 * CLOCK/2

NTSC = 122 * CLOCK/2

Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave

Mode 2: Slave Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode the ADV7175A/ADV7176A accepts horizontal and vertical SYNC signals. A coincident low transition of both

HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of

an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks

all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

1

2

3

4

6

7

8

10

11

5

9

HSYNC

BLANK

VSYNC

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

Figure 21. Timing Mode 2 (NTSC)

–18–

REV. C

ADV7175A/ADV7176A

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

5

21

22

23

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

BLANK

VSYNC

ODD FIELD

EVEN FIELD

Figure 22. Timing Mode 2 (PAL)

Mode 2: Master Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode, the ADV7175A/ADV7176A can generate horizontal and vertical SYNC signals. A coincident low transition of both

HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of

an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks

all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illus-

trates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the

HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.

HSYNC

VSYNC

PAL = 12 * CLOCK/2

BLANK

NTSC = 16 * CLOCK/2

PIXEL

DATA

Cb

Y

Cr

Y

PAL = 132 * CLOCK/2

NTSC = 122 * CLOCK/2

Figure 23. Timing Mode 2 Even-to-Odd Field Transition Master/Slave

HSYNC

VSYNC

PAL = 864 * CLOCK/2

NTSC = 858 * CLOCK/2

PAL = 12 * CLOCK/2

NTSC = 16 * CLOCK/2

BLANK

PIXEL

DATA

Cb

Y

Cr

Y

Cb

PAL = 132 * CLOCK/2

NTSC = 122 * CLOCK/2

Figure 24. Timing Mode 2 Odd-to-Even Field Transition Master/Slave

–19–

REV. C

ADV7175A/ADV7176A

Mode 3: Master/Slave Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode, the ADV7175A/ADV7176A accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the

FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK

input is disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in

Figure 25 (NTSC) and Figure 26 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

1

2

3

4

6

7

8

10

11

5

9

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

Figure 25. Timing Mode 3 (NTSC)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

5

21

22

23

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

BLANK

FIELD

EVEN FIELD

ODD FIELD

Figure 26. Timing Mode 3 (PAL)

–20–

REV. C

ADV7175A/ADV7176A

POWER-ON RESET

1

0

1

A1

X

After power-up, it is necessary to execute a reset operation. A

reset occurs on the falling edge of a high-to-low transition on

the RESET pin. This initializes the pixel port so that the

pixel inputs, P7–P0 are selected. After reset, the ADV7175A/

ADV7176A is automatically set up to operate in NTSC mode.

Subcarrier frequency code 21F07C16HEX is loaded into the

subcarrier frequency registers. All other registers, with the

exception of Mode Register 0, are set to 00H. All bits in Mode

Register 0 are set to Logic Level “0” except Bit MR02. Bit

MR02 of Mode Register 0 is set to Logic “1.” This enables the

7.5 IRE pedestal.

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0

1

WRITE

READ

Figure 27. ADV7175A Slave Address

1

0

1

A1

X

0

SCH Phase Mode

ADDRESS

CONTROL

The SCH phase is configured in default mode to reset every

four (NTSC) or eight (PAL) fields to avoid an accumulation of

SCH phase error over time. In an ideal system, zero SCH phase

error would be maintained forever, but in reality, this is impos-

sible to achieve due to clock frequency variations. This effect is

reduced by the use of a 32-bit DDS, which generates this SCH.

SET UP BY

ALSB

READ/WRITE

CONTROL

0

1

WRITE

READ

Resetting the SCH phase every four or eight fields avoids the

accumulation of SCH phase error, and results in very minor

SCH phase jumps at the start of the four or eight field sequence.

Figure 28. ADV7176A Slave Address

To control the various devices on the bus, the following proto-

col must be followed: First, the master initiates a data transfer by

establishing a start condition, defined by a high-to-low transition

on SDATA while SCLOCK remains high. This indicates that

an address/data stream will follow. All peripherals respond to

the start condition and shift the next eight bits (7-bit address +

R/W bit). The bits transfer from MSB down to LSB. The

peripheral that recognizes the transmitted address responds by

pulling the data line low during the ninth clock pulse. This is

known as an acknowledge bit. All other devices withdraw from

the bus at this point and maintain an idle condition. The idle

condition is where the device monitors the SDATA and SCLOCK

lines waiting for the start condition and the correct transmitted

address. The R/W bit determines the direction of the data. A

Logic “0” on the LSB of the first byte means that the master

will write information to the peripheral. A Logic “1” on the LSB

of the first byte means that the master will read information

from the peripheral.

Resetting the SCH phase should not be done if the video source

does not have stable timing or the ADV7175A/ADV7176A is

configured in RTC mode (MR21 = 1 and MR22 = 1). Under

these conditions (unstable video) the subcarrier phase reset

should be enabled MR22 = 0 and MR21 = 1) but no reset

applied. In this configuration the SCH phase will never be reset,

which means that the output video will now track the unstable

input video. The subcarrier phase reset, when applied, will reset

the SCH phase to Field 0 at the start of the next field (e.g.,

subcarrier phase reset applied in Field 5 [PAL] on the start of

the next field SCH phase will be reset to Field 0).

MPU PORT DESCRIPTION

The ADV7175A and ADV7176A support a two-wire serial (I²C

Compatible) microprocessor bus driving multiple peripherals.

Two inputs, serial data (SDATA) and serial clock (SCLOCK),

carry information between any device connected to the bus. Each

slave device is recognized by a unique address. The ADV7175A

and ADV7176A each have four possible slave addresses for both

read and write operations. These are unique addresses for each

device and are illustrated in Figure 27 and Figure 28. The LSB

sets either a read or write operation. Logic Level “1” corre-

sponds to a read operation, while Logic Level “0” corresponds

to a write operation. A1 is set by setting the ALSB pin of the

ADV7175A/ADV7176A to Logic Level “0” or Logic Level “1.”

The ADV7175A/ADV7176A acts as a standard slave device on

the bus. The data on the SDATA pin is 8 bits long, supporting

the 7-bit addresses, plus the R/W bit. The ADV7175A has 37

subaddresses and the ADV7176A has 20 subaddresses to enable

access to the internal registers. It therefore interprets the first

byte as the device address and the second byte as the starting

subaddress. The subaddresses auto increment allow data to

be written to or read from the starting subaddress. A data

transfer is always terminated by a stop condition. The user can

REV. C

–21–

ADV7175A/ADV7176A

also access any unique subaddress register on a one by one basis

without having to update all the registers. There is one excep-

tion. The subcarrier frequency registers should be updated in

sequence, starting with Subcarrier Frequency Register 0. The

auto increment function should then be used to increment and

access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier

frequency registers should not be accessed independently.

1. In Read Mode, the highest subaddress register contents

will continue to be output until the master device issues a

no-acknowledge. This indicates the end of a read. A no-

acknowledge condition is where the SDATA line is not pulled

low on the ninth pulse.

2. In Write Mode, the data for the invalid byte will not be

loaded into any subaddress register, a no-acknowledge will

be issued by the ADV7175A/ADV7176A and the part will

return to the idle condition.

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of sequence

with normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCLOCK high

period, the user should issue only one start condition, one

stop condition or a single stop condition followed by a single

start condition. If an invalid subaddress is issued by the user,

the ADV7175A/ADV7176A will not issue an acknowledge and

will return to the idle condition. If, in auto-increment mode

the user exceeds the highest subaddress, the following action

will be taken:

SDATA

SCLOCK

S

1-7

8

9

1-7

8

9

1-7

DATA

8

9

P

START ADDR

ACK SUBADDRESS ACK

ACK

STOP

R/W

Figure 29. Bus Data Transfer

Figure 29 illustrates an example of data transfer for a read

sequence and the start and stop conditions.

Figure 30 shows bus write and read sequences.

WRITE

S

SLAVE ADDR A(S) SUB ADDR A(S)

LSB = 0

DATA

A(S)

DATA

A(M)

A(S) P

SEQUENCE

LSB = 1

READ

SEQUENCE

SLAVE ADDR A(S)

SUB ADDR A(S)

S

SLAVE ADDR A(S)

DATA

P

A(M)

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

S = START BIT

P = STOP BIT

A(S) = NO-ACKNOWLEDGE BY SLAVE

A(M) = NO-ACKNOWLEDGE BY MASTER

Figure 30. Write and Read Sequences

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

SR7–SR6 (00)

ZERO SHOULD BE WRITTEN

TO THESE BITS

ADV7175A SUBADDRESS REGISTER

ADV7176A SUBADDRESS REGISTER

SR5 SR4 SR3 SR2 SR1 SR0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

MODE REGISTER 0

MODE REGISTER 1

0

•

0

1

•

0

1

0

•

0

1

0

1

0

•

0

1

0

1

0

1

0

1

0

1

•

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

•

MODE REGISTER 0

MODE REGISTER 1

SUB CARRIER FREQ REGISTER 0

SUB CARRIER FREQ REGISTER 1

SUB CARRIER FREQ REGISTER 2

SUB CARRIER FREQ REGISTER 3

SUB CARRIER PHASE REGISTER

TIMING REGISTER 0

SUB CARRIER FREQ REGISTER 0

SUB CARRIER FREQ REGISTER 1

SUB CARRIER FREQ REGISTER 2

SUB CARRIER FREQ REGISTER 3

SUB CARRIER PHASE REGISTER

TIMING REGISTER 0

CLOSED CAPTIONING EXTENDED DATA Ϸ BYTE 0

CLOSED CAPTIONING EXTENDED DATA Ϸ BYTE 1

CLOSED CAPTIONING DATA Ϸ BYTE 0

CLOSED CAPTIONING DATA Ϸ BYTE 1

TIMING REGISTER 1

CLOSED CAPTIONING EXTENDED DATA Ϸ BYTE 0

CLOSED CAPTIONING EXTENDED DATA Ϸ BYTE 1

CLOSED CAPTIONING DATA Ϸ BYTE 0

CLOSED CAPTIONING DATA Ϸ BYTE 1

TIMING REGISTER 1

MODE REGISTER 2

NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*

NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1*

NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2*

NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3*

MODE REGISTER 3

NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*

NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1*

NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2*

NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3*

MODE REGISTER 3

TTXREQ CONTROL REGISTER

MACROVISION REGISTER

"

*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY

IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL

•

1

•

0

•

0

•

0

1

•

1

0

•

1

0

MACROVISION REGISTER

TTXREQ CONTROL REGISTER

*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY

IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL

Figure 31. Subaddress Register

–22–

REV. C

ADV7175A/ADV7176A

REGISTER ACCESSES

MODE REGISTER 0 MR0 (MR07–MR00)

The MPU can write to or read from all of the ADV7175A/

ADV7176A registers except the subaddress register, which is a

write-only register. The subaddress register determines which

register the next read or write operation accesses. All communi-

cations with the part through the bus start with an access to the

subaddress register. A read/write operation is performed from/to

the target address, which then increments to the next address

until a stop command on the bus is performed.

(Address [SR4–SR0] = 00H)

Figure 32 shows the various operations under the control of Mode

Register 0. This register can be read from as well as written to.

MR0 BIT DESCRIPTION

Output Video Standard Selection (MR01–MR00)

These bits are used to set up the encode mode. The ADV7175A/

ADV7176A can be set up to output NTSC, PAL (B, D, G, H, I)

and PAL (M) standard video.

REGISTER PROGRAMMING

Pedestal Control (MR02)

The following section describes each register, including subaddress

register, mode registers, subcarrier frequency registers, subcarrier

phase register, timing registers, closed captioning extended data

registers, closed captioning data registers and NTSC pedestal

control registers in terms of its configuration.

This bit specifies whether a pedestal is to be generated on

the NTSC composite video signal. This bit is invalid if the

ADV7175A/ADV7176A is configured in PAL mode.

Luminance Filter Control (MR04–MR03)

The luminance filters are divided into two sets (NTSC/PAL) of

four filters, low-pass A, low-pass B, notch and extended. When

PAL is selected, bits MR03 and MR04 select one of four PAL

luminance filters; likewise, when NTSC is selected, bits MR03

and MR04 select one of four NTSC luminance filters. The fil-

ters are illustrated in Figures 4 to 12.

Subaddress Register (SR7–SR0)

The communications register is an 8-bit write-only register.

After the part has been accessed over the bus, and a read/write

operation is selected, the subaddress is set up. The subaddress

register determines to/from which register the operation takes

place.

RGB Sync (MR05)

Figure 31 shows the various operations under the control of

the subaddress register. Zero should always be written to

SR7–SR6.

This bit is used to set up the RGB outputs with the sync infor-

mation encoded on all RGB outputs. (This funcionality is only

available on the ADV7176A.)

Register Select (SR5–SR0)

These bits are set up to point to the required starting address.

Output Select (MR06)

This bit specifies if the part is in composite video or RGB/YUV

mode. Please note that the main composite signal is still avail-

able in RGB/YUV mode.

MR01

MR06

MR05

MR04

MR03

MR02

MR00

MR07

LUMINANCE FILTER CONTROL

MR04 MR03

OUTPUT VIDEO

OUTPUT SELECT

MR06

STANDARD SELECTION

MR01

MR00

0

1

YC OUTPUT

RGB/YUV OUTPUT

0

1

0

1

0

1

LOW PASS FILTER (A)

NOTCH FILTER

EXTENDED MODE

LOW PASS FILTER (B)

0

1

0

1

0

1

NTSC

PAL (B, D, G, H, I)

PAL (M)

RESERVED

PEDESTAL

CONTROL

RGB SYNC

MR07

(0)

MR05

MR02

ZERO SHOULD

BE WRITTEN TO

THIS BIT

0

1

DISABLE

ENABLE

0

1

PEDESTAL OFF

PEDESTAL ON

Figure 32. Mode Register 0 (MR0)

MR11

MR17

MR16

MR15

MR14

MR13

MR12

MR10

DAC D

CONTROL

CLOSED CAPTIONING

FIELD SELECTION

DAC A

CONTROL

MR16

MR14

MR12

MR11

0

1

NORMAL

POWER-DOWN

0

1

NORMAL

POWER-DOWN

0

1

0

1

0

1

NO DATA OUT

ODD FIELD ONLY

EVEN FIELD ONLY

DATA OUT

(BOTH FIELDS)

COLOR BAR

CONTROL

DAC B

CONTROL

DAC C

CONTROL

INTERLACED MODE

CONTROL

MR15

MR13

MR10

MR17

0

1

INTERLACED

NONINTERLACED

0

1

NORMAL

POWER-DOWN

0

1

NORMAL

POWER-DOWN

0

1

DISABLE

ENABLE

Figure 33. Mode Register 1 (MR1)

–23–

REV. C

ADV7175A/ADV7176A

MODE REGISTER 1 MR1 (MR17–MR10)

SUBCARRIER

FREQUENCY

REG 3

FSC30

FSC31

FSC29 FSC28 FSC27 FSC26 FSC25 FSC24

(Address (SR4–SR0) = 01H)

SUBCARRIER

FREQUENCY

REG 2

Figure 33 shows the various operations under the control of Mode

Register 1. This register can be read from as well as written to.

FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

SUBCARRIER

FREQUENCY

REG 1

FSC14

FSC6

FSC15

FSC7

FSC13 FSC12 FSC11 FSC10 FSC9

FSC8

FSC0

MR1 BIT DESCRIPTION

Interlaced Mode Control (MR10)

This bit is used to set up the output to interlaced or noninter-

laced mode. This mode is only relevant when the part is in

composite video mode.

SUBCARRIER

FREQUENCY

REG 0

FSC5

FSC4

FSC3 FSC2 FSC1

Figure 34. Subcarrier Frequency Register

Closed Captioning Field Selection (MR12–MR11)

These bits control the fields on which closed captioning data is

displayed; closed captioning information can be displayed on an

odd field, even field or both fields.

SUBCARRIER PHASE REGISTER (FP7–FP0)

(Address [SR4–SR0] = 06H)

This 8-bit-wide register is used to set up the subcarrier phase.

Each bit represents 1.41°.

DAC Control (MR16–MR13)

These bits can be used to power down the DACs. This can

be used to reduce the power consumption of the ADV7175A/

ADV7176A if any of the DACs are not required in the application.

TIMING REGISTER 0 (TR07–TR00)

(Address [SR4–SR0] = 07H)

Figure 35 shows the various operations under the control of

Timing Register 0. This register can be read from as well as

written to. This register can be used to adjust the width and

position of the master mode timing signals.

Color Bar Control (MR17)

This bit can be used to generate and output an internal color

bar test pattern. The color bar configuration is 100/7.5/75/7.5

for NTSC and 100/0/75/0 for PAL. It is important to note that

when color bars are enabled the ADV7175A/ADV7176A is

configured in a master timing mode as per the one selected by

bits TR01 and TR02.

TR0 BIT DESCRIPTION

Master/Slave Control (TR00)

This bit controls whether the ADV7175A/ADV7176A is in

master or slave mode.

SUBCARRIER FREQUENCY REGISTER 3-0

(FSC3–FSC0)

(Address [SR4–SR0] = 05H–02H)

These 8-bit-wide registers are used to set up the subcarrier

frequency. The value of these registers are calculated by using

the following equation:

Timing Mode Selection (TR02–TR01)

These bits control the timing mode of the ADV7175A/

ADV7176A. These modes are described in the Timing and

Control section of the data sheet.

BLANK Input Control (TR03)

This bit controls whether the BLANK input is used when the

part is in slave mode.

2³²–1

F_CLK

× F_SCF

Subcarrier Frequency Register =

i.e.: NTSC Mode,

Luma Delay (TR05–TR04)

These bits control the addition of a luminance delay. Each bit

represents a delay of 74 ns.

F

_CLK= 27 MHz,

F_SCF= 3.5795454 MHz

Pixel Port Control (TR06)

2³²–1

27×10⁶

This bit is used to set the pixel port to accept 8-bit or 16-bit

data. If an 8-bit input is selected the data will be set up on Pins

P7–P0.

× 3.5795454 ×10⁶

Subcarrier Frequency Value =

= 21F07C16 HEX

Timing Register Reset (TR07)

Figure 34 shows how the frequency is set up by the four registers.

Toggling TR07 from low to high and low again resets the inter-

nal timing counters. This bit should be toggled after power-up,

reset or changing to a new timing mode.

TR01

TR07

TR06

TR05

TR04

TR03

TR02

TR00

TIMING

REGISTER RESET

MASTER/SLAVE

CONTROL

BLANK INPUT

CONTROL

TR03

0

1

TR00

0

1

TR07

ENABLE

DISABLE

SLAVE TIMING

MASTER TIMING

PIXEL PORT

CONTROL

LUMA DELAY

TIMING MODE

SELECTION

TR05 TR04

TR06

TR02 TR01

0

1

0

1

0

1

0ns DELAY

0

1

8-BIT

16-BIT

0

1

0

1

0

1

MODE 0

74ns DELAY

148ns DELAY

222ns DELAY

MODE 1

MODE 2

MODE 3

Figure 35. Timing Register 0

–24–

REV. C

ADV7175A/ADV7176A

CLOSED CAPTIONING EVEN FIELD

TR1 BIT DESCRIPTION

DATA REGISTER 1–0 (CED15–CED0)

HSYNC Width (TR11–TR10)

(Address [SR4–SR0] = 09–08H)

These bits adjust the HSYNC pulsewidth.

These 8-bit-wide registers are used to set up the closed captioning

extended data bytes on even fields. Figure 36 shows how the

high and low bytes are set up in the registers.

HSYNC to FIELD/VSYNC Delay (TR13–TR12)

These bits adjust the position of the HSYNC output relative to

the FIELD/VSYNC output.

HSYNC to FIELD Rising Edge Delay (TR15–TR14)

When the ADV7175A/ADV7176A is in Timing Mode 1, these

bits adjust the position of the HSYNC output relative to the

FIELD output rising edge.

CED15 CED14 CED13 CED12 CED11 CED10

CED9

CED8

BYTE 1

CED7

CED6

CED5

CED4

CED3

CED2

CED1

CED0

BYTE 0

Figure 36. Closed Captioning Extended Data Register

VSYNC Width (TR15–TR14)

When the ADV7175A/ADV7176A is in Timing Mode 2, these

bits adjust the VSYNC pulsewidth.

CLOSED CAPTIONING ODD FIELD

DATA REGISTER 1–0 (CCD15–CCD0)

(Subaddress [SR4–SR0] = 0B–0AH)

These 8-bit-wide registers are used to set up the closed captioning

data bytes on odd fields. Figure 37 shows how the high and low

bytes are set up in the registers.

HSYNC to Pixel Data Adjust (TR17–TR16)

This enables the HSYNC to be adjusted with respect to the

pixel data. This allows the Cr and Cb components to be

swapped. This adjustment is available in both master and slave

timing modes.

CCD15

CCD14 CCD13 CCD12 CCD11 CCD10

CCD9

CCD8

BYTE 1

MODE REGISTER 2 MR2 (MR27–MR20)

(Address [SR4–SR0] = 0DH)

Mode Register 2 is an 8-bit-wide register.

CCD7

CCD6

CCD5

CCD4

CCD3

CCD2

CCD1

CCD0

BYTE 0

Figure 39 shows the various operations under the control of Mode

Register 2. This register can be read from as well as written to.

Figure 37. Closed Captioning Data Register

TIMING REGISTER 1 (TR17–TR10)

(ADDRESS [SR4–SR0] = 0CH)

Timing Register 1 is an 8-Bit-Wide Register

MR2 BIT DESCRIPTION

Square Pixel Control (MR20)

This bit is used to set up square pixel mode. This is available in

slave mode only. For NTSC, a 24.5454 MHz clock must be

supplied. For PAL, a 29.5 MHz clock must be supplied.

Figure 38 shows the various operations under the control of

Timing Register 1. This register can be read from as well as

written to. This register can be used to adjust the width and

position of the master mode timing signals.

TR11

TR17

TR16

TR15

TR14

TR13

TR12

TR10

HSYNC TO FIELD

RISING EDGE DELAY

(MODE 1 ONLY)

HSYNC WIDTH

HSYNC TO PIXEL

DATA ADJUST

HSYNC TO

FIELD/VSYNC DELAY

T

TR11 TR10

A

TR17 TR16

T

0

1

0

1

0

1

1 x T

4 x T

TR13 TR12

B

PCLK

T

TR15 TR14

C

0

1

0

1

0

1

0 x T

1 x T

2 x T

3 x T

0

1

0

1

0

1

0 x T

4 x T

8 x T

PCLK

x

0

1

T

B

16 x T

PCLK

128 x T

PCLK

+ 32␮s

B

PCLK

16 x T

PCLK

VSYNC WIDTH

(MODE 2 ONLY)

TR15 TR14

0

1

0

1

0

1

1 x T

4 x T

PCLK

16 x T

PCLK

128 x T

PCLK

TIMING MODE 1 (MASTER/PAL)

LINE 1

LINE 313

LINE 314

T_A

T_B

HSYNC

T_C

FIELD/VSYNC

Figure 38. Timing Register 1

REV. C

–25–

ADV7175A/ADV7176A

MR21

MR27

MR26

MR25

MR24

MR23

MR22

MR20

CHROMINANCE

CONTROL

RGB/YUV

CONTROL

GENLOCK SELECTION

MR22 MR21

MR24

MR26

x

0

1

DISABLE GENLOCK

ENABLE SUBCARRIER

RESET PIN

0

1

RGB OUTPUT

YUV OUTPUT

0

1

ENABLE COLOR

DISABLE COLOR

1

ENABLE RTC PIN

LOWER POWER

MODE

BURST

CONTROL

ACTIVE VIDEO LINE WIDTH

CONTROL

SQUARE PIXEL

CONTROL

MR27

MR25

MR23

MR20

0

1

DISABLE

ENABLE

0

1

ENABLE BURST

DISABLE BURST

0

1

DISABLE

ENABLE

0

1

720 PIXELS

710/702 PIXELS

Figure 39. Mode Register 2

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0

Genlock Selection (MR22–MR21)

These bits control the genlock feature of the ADV7175A/

ADV7176A. Setting MR21 to a Logic “1” configures the

SCRESET/RTC pin as an input. Setting MR22 to Logic Level

“0” configures the SCRESET/RTC pin as a subcarrier reset

input, therefore, the subcarrier will reset to Field 0, following a

low-to-high transition on the SCRESET/RTC pin. Setting

MR22 to Logic Level “1” configures the SCRESET/RTC pin as

a real-time control input.

FIELD 1/3

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0

FIELD 2/4

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8

Active Video Line Width Control (MR23)

This bit switches between two active video line durations. A

zero selects CCIR.REC601 (720 pixels PAL/NTSC) and a one

selects ITU-R.BT.470 “analog” standard for active video dura-

tion (710 pixels NTSC 702 pixels PAL).

Figure 40. Pedestal Control Registers

LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7

TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0

FIELD 1/3

Chrominance Control (MR24)

This bit enables the color information to be switched on and off

the video output.

LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15

TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8

Burst Control (MR25)

This bit enables the burst information to be switched on and off

the video output.

LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7

TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0

FIELD 2/4

LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15

TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8

RGB/YUV Control (MR26)

This bit enables the output from the RGB DACs to be set to

YUV output video standard. Bit MR06 of Mode Register 0

must be set to Logic Level “1” before MR26 is set.

Figure 41. Teletext Control Registers

Lower Power Mode (MR27)

This bit enables the lower power mode of the ADV7175A/

ADV7176A. This will reduce the DAC current by 50%.

MODE REGISTER 3 MR3 (MR37–MR30)

(Address [SR4–SR0] = 12H)

Mode Register 3 is an 8-bit-wide register.

Figure 42 shows the various operations under the control of

Mode Register 3.

NTSC PEDESTAL/PAL TELETEXT CONTROL

REGISTERS 3–0 (PCE15–0, PCO15–0)/ (TXE15–0, TXO15–0)

(Subaddress [SR4–SR0] = 11–0EH)

MR3 BIT DESCRIPTION

These 8-bit-wide registers are used to set up the NTSC pedes-

tal/PAL teletext on a line-by-line basis in the vertical blanking

interval for both odd and even fields. Figures 40 and 41 show

the four control registers. A Logic “1” in any of the bits of these

registers has the effect of turning the pedestal OFF on the

equivalent line when used in NTSC. A Logic “1” in any of the

bits of these registers has the effect of turning teletext ON the

equivalent line when used in PAL.

Revision Code (MR30)

This bit is read only and indicates the revision of the device.

VBI Pass-Through (MR31)

This bit determines whether or not data in the vertical blanking

interval (VBI) is output to the analog outputs or blanked. VBI

Pass-Through is available in all timing modes except Slave 0.

Also when both VBI Pass-Through and BLANK input control

(TR03) are enabled, TR03 takes priority.

Reserved (MR33–MR32)

These bits are reserved.

Teletext Enable (MR34)

This bit must be set to “1” to enable teletext data insertion on

the TTX pin.

–26–

REV. C

ADV7175A/ADV7176A

DAC Output Switching (MR37)

This bit is used to switch the DAC outputs from SCART to a

EUROSCART configuration. A complete table of all DAC

output configurations is shown below.

Input Default Color (MR36)

This bit determines the default output color from the DACs for

zero input data (or disconnected). A Logical “0” means that the

color corresponding to 00000000 will be displayed. A Logical “1”

forces the output color to black for 00000000 input video data.

Table I. DAC Output Configuration Matrix

DAC A DAC B DAC C

CVBS

MR06

MR26

MR37

DAC D

Simultaneous Output

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CVBS

Y

C

Y

CVBS

Y

CVBS

G

CVBS

2 Composite and Y/C

RGB and Composite

YUV and Composite

CVBS

B

C

R

V

CVBS

Y

CVBS

G

B

U

CVBS

Y

CVBS

NOTE

CVBS: Composite Video Baseband Signal

Each DAC can be individually powered ON or OFF with the following control bits

(“0” = ON, “1” = OFF):

MR13 - DAC C

MR14 - DAC D

MR15 - DAC B

MR16 - DAC A

Y:

C:

U:

V:

R:

G:

B:

Luminance Component Signal (For YUV or Y/C Mode)

Chrominance Signal (For Y/C Mode)

Chrominance Component Signal (For YUV Mode)

RED Component Video (For RGB Mode)

GREEN Component Video (For RGB Mode)

BLUE Component Video (For RGB Mode)

MR31

MR36

MR35

MR34

MR33

MR32

MR30

MR37

RESERVED

MR35 = 0

ZERO SHOULD

BE WRITTEN TO

THIS BIT

REV CODE

(READ ONLY)

INPUT DEFAULT COLOR

MR36

TELETEXT ENABLE

VBI PASSTHROUGH

MR31

MR34

0

1

INPUT COLOR

BLACK

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

DAC OUTPUT

SWITCHING

MR37

DAC A

DAC B

DAC C

DAC D

0

1

COMPOSITE

GREEN/LUMA/Y

BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y

BLUE/COMP/U RED/CHROMA/V COMPOSITE

Figure 42. Mode Register 3

TTXREQ Falling Edge Control (TC03–TC00)

TTXREQ CONTROL REGISTER TC07 (TC07–TC00)

(Address [SR4–SR0] = 24H)

Teletext Control Register is an 8-bit-wide register.

These bits control the position of the falling edge of TTXREQ.

It can be programmed from zero CLOCK cycles to a max of 15

CLOCK cycles. This controls the active window for teletext

data. Increasing this value reduces the amount of teletext bits

below the default of 360. If bits TC03–TC00 are unchanged

when bits TC07–TC04 are changed, the falling edge of TTXREQ

will track that of the rising edge (i.e., the time between the fall-

ing and rising edge remains constant)—see Figure 48.

TTXREQ Rising Edge Control (TC07–TC04)

These bits control the position of the rising edge of TTXREQ.

It can be programmed from zero CLOCK cycles to a max of 15

CLOCK cycles—see Figure 48.

TC06

TC05

TC04

TC03

TC02

TC01

TC00

TC07

TTXREQ RISING EDGE CONTROL

TC07 TC06 TC05 TC04

TTXREQ FALLING EDGE CONTROL

TC03 TC02 TC01 TC00

0

"

1

0

"

1

0

"

1

0

1

"

0

1

0 PCLK

0

"

1

0

"

1

0

"

1

0

1

"

0

1

0 PCLK

1 PCLK

" PCLK

14 PCLK

15 PCLK

1 PCLK

" PCLK

14 PCLK

15 PCLK

Figure 43. Teletext Control Register

–27–

REV. C

ADV7175A/ADV7176A

APPENDIX 1

BOARD DESIGN AND LAYOUT CONSIDERATIONS

The ADV7175A/ADV7176A is a highly integrated circuit contain-

ing both precision analog and high speed digital circuitry. It has

been designed to minimize interference effects on the integrity

of the analog circuitry by the high speed digital circuitry. It is

imperative that these same design and layout techniques be

applied to the system level design so that high speed, accurate

performance is achieved. The “Recommended Analog Circuit

Layout” shows the analog interface between the device and

monitor.

to reduce the lead inductance. Best performance is obtained

with 0.1 µF ceramic capacitor decoupling. Each group of V_AA

pins on the ADV7175A/ADV7176A must have at least one 0.1 µF

decoupling capacitor to GND. These capacitors should be

placed as close to the device as possible.

It is important to note that while the ADV7175A/ADV7176A

contains circuitry to reject power supply noise, this rejection

decreases with frequency. If a high frequency switching power

supply is used, the designer should pay close attention to reduc-

ing power supply noise and consider using a three terminal voltage

regulator for supplying power to the analog power plane.

The layout should be optimized for lowest noise on the ADV7175A/

ADV7176A power and ground lines by shielding the digital

inputs and providing good decoupling. The lead length between

groups of V_AAand GND pins should by minimized to minimize

inductive ringing.

Digital Signal Interconnect

The digital inputs to the ADV7175A/ADV7176A should be

isolated as much as possible from the analog outputs and other

analog circuitry. Also, these input signals should not overlay the

analog power plane.

Ground Planes

The ground plane should encompass all ADV7175A/ADV7176A

ground pins, voltage reference circuitry, power supply bypass

circuitry for the ADV7175A/ADV7176A, the analog out-

put traces, and all the digital signal traces leading up to the

ADV7175A/ADV7176A. The ground plane is the board’s

common ground plane.

Due to the high clock rates involved, long clock lines to

the ADV7175A/ADV7176A should be avoided to reduce

noise pickup.

Any active termination resistors for the digital inputs should be

connected to the regular PCB power plane (V_CC) and not the

analog power plane.

Power Planes

The ADV7175A/ADV7176A and any associated analog circuitry

should have its own power plane, referred to as the analog

power plane (V_AA). This power plane should be connected to

the regular PCB power plane (V_CC) at a single point through a

ferrite bead. This bead should be located within three inches of

the ADV7175A/ADV7176A.

Analog Signal Interconnect

The ADV7175A/ADV7176A should be located as close to the

output connectors as possible to minimize noise pickup and

reflections due to impedance mismatch.

The video output signals should overlay the ground plane, not

the analog power plane, to maximize the high frequency power

supply rejection.

The metallization gap separating device power plane and

board power plane should be as narrow as possible to mini-

mize the obstruction to the flow of heat from the device into

the general board.

Digital inputs, especially pixel data inputs and clocking signals,

should never overlay any of the analog signal circuitry and

should be kept as far away as possible.

The PCB power plane should provide power to all digital logic

on the PC board, and the analog power plane should provide

power to all ADV7175A/ADV7176A power pins and voltage

reference circuitry.

For best performance, the outputs should each have a 75 Ω

load resistor connected to GND. These resistors should be

placed as close as possible to the ADV7175A/ADV7176A as to

minimize reflections.

Plane-to-plane noise coupling can be reduced by ensuring that

portions of the regular PCB power and ground planes do not

overlay portions of the analog power plane unless they can be

arranged so that the plane-to-plane noise is common-mode.

The ADV7175A/ADV7176A should have no inputs left float-

ing. Any inputs that are not required should be tied to ground.

Supply Decoupling

For optimum performance, bypass capacitors should be installed

using the shortest leads possible, consistent with reliable operation,

–28–

REV. C

ADV7175A/ADV7176A

POWER SUPPLY DECOUPLING

FOR EACH POWER SUPPLY GROUP

0.1␮F

0.01␮F

L1

(FERRITE BEAD)

5V (V

AA

)

5V

(V

5V (V

AA

)

5V (V )

AA

)

1, 11, 20, 28, 30

33␮F

10␮F

CC

0.1␮F

GND

0.1␮F

V

AA

COMP

25

33

27

DAC D

V

REF

75⍀

ADV7175A

ADV7176A

38–42,

2–9, 12–14

26

DAC C

5V (V

AA

)

P15–P0

S VIDEO

4k⍀

35

DAC B 31

SCRESET/RTC

RESET

100nF

15 HSYNC

“UNUSED

INPUTS

SHOULD BE

GROUNDED”

FIELD/VSYNC

16

17

22

5V (V

)

32

DAC A

CC

5V (V

CC

)

5V (V

CC

)

BLANK

RESET

TTX

100k⍀

5k⍀

TTX

TTX REQ

100⍀

37

36

44

SCLOCK 23

SDATA 24

MPU BUS

TTX REQ

CLOCK

100k⍀

34

R

SET

5V (V

AA

)

ALSB

18

GND

150⍀

TELETEXT PULL-UP AND

PULL-DOWN RESISTORS

SHOULD ONLY BE USED

IF THESE PINS ARE NOT

CONNECTED

10k⍀

10, 19, 21

29, 43

27MHz CLOCK

(SAME CLOCK AS USED BY

MPEG2 DECODER)

Figure 44. Recommended Analog Circuit Layout

The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform

is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if

the 13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the

ADV7175A/ADV7176A in the correct sequence.

D

Q

13.5MHz

D

Q

CLOCK

CK

HSYNC

Figure 45. Circuit to Generate 13.5 MHz

REV. C

–29–

ADV7175A/ADV7176A

APPENDIX 2

CLOSED CAPTIONING

The ADV7175A/ADV7176A supports closed captioning, conforming to the standard television synchronizing waveform for color

transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284

of even fields.

Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in

signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. 16 bits of data follow the start bit.

These consist of two 8-bit bytes, seven data bits and one odd parity bit. The data for these bytes is stored in closed captioning Data

Registers 0 and 1.

The ADV7175A/ADV7176A also supports the extended closed captioning operation, which is active during even fields, and is

encoded on scan Line 284. The data for this operation is stored in closed captioning extended Data Registers 0 and 1.

All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7175A/

ADV7176A. All pixels inputs are ignored during Lines 21 and 284.

FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines

21 and 284.

The ADV7175A/ADV7176A uses a single buffering method. This means that the closed captioning buffer is only one byte deep,

therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. The data

must be loaded at least one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of

this method is to use VSYNC to interrupt a microprocessor, which will in turn load the new data (two bytes) every field. If no new

data is required for transmission you must insert zeros in both the data registers; this is called NULLING. It is also important to load

“control codes,” all of which are double bytes on Line 21, or a TV will not recognize them. If you have a message like “Hello World”

which has an odd number of characters, it is important to pad it out to an even number to get “end of caption” 2-byte control code to

land in the same field.

10.5 ؎ 0.25␮s

12.91␮s

7 CYCLES

OF 0.5035 MHz

(CLOCKRUN-IN)

TWO 7-BIT + PARITY

ASCII CHARACTERS

(DATA)

P

A

R

I

T

Y

S

T

A

R

T

P

A

R

I

T

Y

D0–D6

50 IRE

40 IRE

BYTE 1

BYTE 0

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F = 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003␮s

33.764␮s

27.382␮s

Figure 46. Closed Captioning Waveform (NTSC)

–30–

REV. C

ADV7175A/ADV7176A

APPENDIX 3

TELETEXT INSERTION

Time T_PDtime needed by the ADV7175A/ADV7176A to interpolate input data on TTX and insert it onto the CVBS or Y outputs,

such that it appears T_SYNTTXOUT= 10.2 µs after the leading edge of the horizontal signal. Time TTX_DELis the pipeline delay time by

the source that is gated by the TTXREQ signal in order to deliver TTX data.

With the programmability that is offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the

correct position of 10.2 µs after the leading edge of Horizontal Sync pulse, which enables a source interface with variable pipeline

delays.

The width of the TTXREQ signal must always be maintained so it allows the insertion of 360 (to comply with the Teletext Standard

“PAL–WST”) teletext bits at a text data rate of 6.9375 Mbits/s; this is achieved by setting TC03–TC00 to zero. The insertion

window is not open if the Teletext Enable bit (MR34) is set to zero.

Teletext Protocol

The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:





27 MHz

= 6.75 MHz









4

6







6.9375 × 10

 6.75 × 10⁶

= 1.027777





Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7175A/ADV7176A

uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal

which can be outputted on the CVBS and Y outputs.

At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX bits

10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock

cycles are 47, 56, 65 and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All

teletext lines are implemented in the same way. Individual control of teletext lines are controlled by Teletext Setup Registers.

45 BYTES (360 BITS) – PAL

ADDRESS & DATA

TELETEXT VBI LINE

RUN-IN CLOCK

Figure 47. Teletext VBI Line

t_SYNTTXOUT

CVBS/Y

t_PD

HSYNC

10.2␮s

TTX

DATA

TTX

DEL

TTXREQ

TTX

ST

PROGRAMMABLE PULSE EDGES

t_SYNTTXOUT= 10.2␮s

t_PD= PIPELINE DELAY THROUGH ADV7175A/ADV7176A

TTX = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])

DEL

Figure 48. Teletext Functionality Diagram

–31–

REV. C

ADV7175A/ADV7176A

APPENDIX 4

NTSC WAVEFORMS (WITH PEDESTAL)

1268.1mV

1048.4mV

130.8 IRE

100 IRE

PEAK COMPOSITE

REF WHITE

714.2mV

387.6mV

334.2mV

7.5 IRE

0 IRE

BLACK LEVEL

BLANK LEVEL

48.3mV

SYNC LEVEL

–40 IRE

Figure 49. NTSC Composite Video Levels

1048.4mV

100 IRE

REF WHITE

714.2mV

387.6mV

334.2mV

7.5 IRE

0 IRE

BLACK LEVEL

BLANK LEVEL

48.3mV

SYNC LEVEL

–40 IRE

Figure 50. NTSC Luma Video Levels

PEAK CHROMA

963.8mV

629.7mV (p-p)

286mV (p-p)

BLANK/BLACK LEVEL

PEAK CHROMA

650mV

335.2mV

0mV

Figure 51. NTSC Chroma Video Levels

100 IRE

REF WHITE

1052.2mV

720.8mV

7.5 IRE

0 IRE

BLACK LEVEL

BLANK LEVEL

387.5mV

331.4mV

SYNC LEVEL

–40 IRE

45.9mV

Figure 52. NTSC RGB Video Levels

–32–

REV. C

ADV7175A/ADV7176A

NTSC WAVEFORMS (WITHOUT PEDESTAL)

130.8 IRE

100 IRE

1289.8mV

1052.2mV

PEAK COMPOSITE

REF WHITE

714.2mV

0 IRE

BLANK/BLACK LEVEL

SYNC LEVEL

338mV

52.1mV

–40 IRE

Figure 53. NTSC Composite Video Levels

1052.2mV

100 IRE

REF WHITE

714.2mV

338mV

52.1mV

0 IRE

BLANK/BLACK LEVEL

SYNC LEVEL

–40 IRE

Figure 54. NTSC Luma Video Levels

PEAK CHROMA

978mV

650mV

694.9mV (p-p)

286mV (p-p)

BLANK/BLACK LEVEL

PEAK CHROMA

299.3mV

0mV

Figure 55. NTSC Chroma Video Levels

100 IRE

1052.2mV

REF WHITE

715.7mV

BLANK/BLACK LEVEL 336.5mV

51mV

0 IRE

SYNC LEVEL

–40 IRE

Figure 56. NTSC RGB Video Levels

REV. C

–33–

ADV7175A/ADV7176A

PAL WAVEFORMS

PEAK COMPOSITE

REF WHITE

1284.2mV

1047.1mV

696.4mV

350.7mV

50.8mV

BLANK/BLACK LEVEL

SYNC LEVEL

Figure 57. PAL Composite Video Levels

REF WHITE

1047mV

696.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

350.7mV

50.8mV

Figure 58. PAL Luma Video Levels

PEAK CHROMA

989.7mV

672mV (p-p)

307mV (p-p)

BLANK/BLACK LEVEL

650mV

PEAK CHROMA

317.7mV

0mV

Figure 59. PAL Chroma Video Levels

REF WHITE

1050.2mV

698.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

351.8mV

51mV

Figure 60. PAL RGB Video Levels

–34–

REV. C

ADV7175A/ADV7176A

UV WAVEFORMS

505mV

423mV

334mV

BETACAM LEVEL

171mV

82mV

BETACAM LEVEL

0mV

–82mV

0mV

؊171mV

–423mV

؊334mV

–505mV

؊505mV

Figure 61. NTSC 100% Color Bars No Pedestal U Levels

Figure 64. NTSC 100% Color Bars No Pedestal V Levels

467mV

391mV

309mV

BETACAM LEVEL

76mV

158mV

BETACAM LEVEL

0mV

–76mV

0mV

–158mV

–391mV

–467mV

–309mV

–467mV

Figure 65. NTSC 100% Color Bars with Pedestal V Levels

Figure 62. NTSC 100% Color Bars with Pedestal U Levels

350mV

293mV

350mV

232mV

SMPTE LEVEL

57mV

118mV

0mV

SMPTE LEVEL

–57mV

0mV

–118mV

–293mV

–350mV

–232mV

–350mV

Figure 66. PAL 100% Color Bars V Levels

Figure 63. PAL 1005 Color Bars U Levels

REV. C

–35–

ADV7175A/ADV7176A

APPENDIX 5

REGISTER VALUES

The ADV7175A/ADV7176A registers can be set depending on

the user standard required.

Address

Data

10Hex Pedestal Control Register 2

11Hex Pedestal Control Register 3

12Hex Mode Register 3

00Hex

The following examples give the various register formats for

several video standards.

24Hex Teletext Request Control Register

In each case the output is set to composite o/p with all DACs

powered up and with the BLANK input control disabled. Addi-

tionally, the burst and color information are enabled on the

output and the internal color bar generator is switched off. In

the examples shown, the timing mode is set to Mode 0 in slave

format. TR02–TR00 of the Timing Register 0 control the

timing modes. For a detailed explanation of each bit in the

command registers, please turn to the Register Programming

section of the data sheet. TR07 should be toggled after setting

up a new timing mode. Timing Register 1 provides additional

control over the position and duration of the timing signals. In

the examples, this register is programmed in default mode.

PAL M (F_SC= 3.57561149 MHz)

Address

00Hex Mode Register 0

Data

06Hex

00Hex

A3Hex

EFHex

E6Hex

21Hex

00Hex

08Hex

00Hex

01Hex Mode Register 1

02Hex Subcarrier Frequency Register 0

03Hex Subcarrier Frequency Register 1

04Hex Subcarrier Frequency Register 2

05Hex Subcarrier Frequency Register 3

06Hex Subcarrier Phase Register

07Hex Timing Register 0

08Hex Closed Captioning Ext Register 0

09Hex Closed Captioning Ext Register 1

0AHex Closed Captioning Register 0

0BHex Closed Captioning Register 1

0CHex Timing Register 1

NTSC (F_SC= 3.5795454 MHz)

Address

Data

00Hex Mode Register 0

01Hex Mode Register 1

04Hex

00Hex

16Hex

7CHex

F0Hex

21Hex

00Hex

08Hex

00Hex

0DHex Mode Register 2

02Hex Subcarrier Frequency Register 0

03Hex Subcarrier Frequency Register 1

04Hex Subcarrier Frequency Register 2

05Hex Subcarrier Frequency Register 3

06Hex Subcarrier Phase Register

07Hex Timing Register 0

08Hex Closed Captioning Ext Register 0

09Hex Closed Captioning Ext Register 1

0AHex Closed Captioning Register 0

0BHex Closed Captioning Register 1

0CHex Timing Register 1

0EHex Pedestal Control Register 0

0FHex Pedestal Control Register 1

10Hex Pedestal Control Register 2

11Hex Pedestal Control Register 3

12Hex Mode Register 3

24Hex Teletext Request Control Register

0DHex Mode Register 2

0EHex Pedestal Control Register 0

0FHex Pedestal Control Register 1

10Hex Pedestal Control Register 2

11Hex Pedestal Control Register 3

12Hex Mode Register 3

24Hex Teletext Request Control Register

PAL B, D, G, H, I (F_SC= 4.43361875 MHz)

Address

00Hex Mode Register 0

01Hex Mode Register 1

01 Hex

00 Hex

CBHex

8A Hex

09 Hex

2AHex

00 Hex

08 Hex

00 Hex

02Hex Subcarrier Frequency Register 0

03Hex Subcarrier Frequency Register 1

04Hex Subcarrier Frequency Register 2

05Hex Subcarrier Frequency Register 3

06Hex Subcarrier Phase Register

07Hex Timing Register 0

08Hex Closed Captioning Ext Register 0

09Hex Closed Captioning Ext Register 1

0AHex Closed Captioning Register 0

0BHex Closed Captioning Register 1

0CHex Timing Register 1

0DHex Mode Register 2

0EHex Pedestal Control Register 0

0FHex Pedestal Control Register 1

–36–

REV. C

ADV7175A/ADV7176A

APPENDIX 6

OPTIONAL OUTPUT FILTER

If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7175A/ADV7176A, the following filter in

Figure 67 can be used. Plots of the filter characteristics are shown in Figures 68. An output filter is not required if the outputs of the

ADV7175A/ADV7176A are connected to an analog monitor or an analog TV; however, if the output signals are applied to a system

where sampling is used (e.g., digital TV), a filter is required to prevent aliasing.

L

1␮H

2.7␮H

0.68␮H

0

–16.7

–33.3

–50

IN

OUT

C

56pF

R

470pF

330pF

75⍀

Figure 67. Output Filter

–66.7

–83.3

–100

100k

1M

10M

100M

FREQUENCY – Hz

Figure 68. Output Filter Plot

REV. C

–37–

ADV7175A/ADV7176A

APPENDIX 7

OPTIONAL DAC BUFFERING

For external buffering of the ADV7175A/ADV7176A DAC outputs, the configuration in Figure 69 is recommended. This configu-

ration shows the DAC outputs running at half (18 mA) their full current (36 mA) capability. This will allow the ADV7175A/ADV7176A

to dissipate less power, the analog current is reduced by 50% with a R_SETof 300 Ω and a R_LOADof 75 Ω. This mode is recommended for

3.3 volt operation as optimum performance is obtained from the DAC outputs at 18 mA with a V_AAof 3.3 volts. This buffer also

adds extra isolation on the video outputs, see buffer circuit in Figure 70. When calculating absolute output full current and voltage,

use the following equation:

V_OUT= I_OUT× R_LOAD

V_REF× K

(

)

I_OUT

=

R_SET

K = 4.2146 constant,V_REF= 1.235 V

V

AA

ADV7175A/ADV7176A

OUTPUT

BUFFER

V

REF

DAC A

75⍀

OUTPUT

BUFFER

DAC B

PIXEL

PORT

DIGITAL

CORE

OUTPUT

BUFFER

DAC C

DAC D

R

SET

OUTPUT

BUFFER

300⍀

Figure 69. Output DAC Buffering Configuration

V

CC+

OUTPUT TO

TV/MONITOR

AD8051

INPUT/

OPTIONAL

FILTER O/P

V

CC–

Figure 70. Recommended Output DAC Buffer

–38–

REV. C

ADV7175A/ADV7176A

APPENDIX 8

OUTPUT WAVEFORMS

0.6

0.4

0.2

0.0

؊0.2

L608

0.0

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NOISE REDUCTION: 0.00 dB

APL = 39.1%

PRECISION MODE OFF

SYNCHRONOUS

SOUND-IN-SYNC OFF

SYNC = SOURCE

625 LINE PAL

NO FILTERING

SLOW CLAMP TO 0.00 V AT 6.72 ␮s

FRAMES SELECTED: 1 2 3 4

Figure 71. 100/0/75/0 PAL Color Bars

0.5

0.0

L575

0.0

10.0

20.0

30.0

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS

40.0

50.0

60.0

70.0

APL NEEDS SYNC = SOURCE!

625 LINE PAL

SOUND-IN-SYNC OFF

SYNC = A

NO FILTERING

SLOW CLAMP TO 0.00 V AT 6.72 ␮s

FRAMES SELECTED: 1

Figure 72. 100/0/75/0 PAL Color Bars Luminance

REV. C

–39–

ADV7175A/ADV7176A

0.5

0.0

–0.5

L575

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NO BRUCH SIGNAL

APL NEEDS SYNC = SOURCE!

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 V AT 6.72 ␮s

PRECISION MODE OFF

SYNCHRONOUS

SOUND-IN-SYNC OFF

SYNC = A

FRAMES SELECTED: 1

Figure 73. 100/0/75/0 PAL Color Bars Chrominance

100.0

0.5

50.0

0.0

F1

L76

–50.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

APL = 44.6%

525 LINE NTSC

PRECISION MODE OFF

SYNCHRONOUS

NO FILTERING

SYNC = A

SLOW CLAMP TO 0.00 V AT 6.72 ␮s

FRAMES SELECTED: 1 2

Figure 74. 100/7.5/75/7.5 NTSC Color Bars

–40–

REV. C

ADV7175A/ADV7176A

0.6

0.4

0.2

50.0

0.0

–0.2

F2

L238

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL = 44.7%

PRECISION MODE OFF

525 LINE NTSC

NO FILTERING

SYNCHRONOUS

SYNC = SOURCE

SLOW CLAMP TO 0.00 V AT 6.72 ␮s

FRAMES SELECTED: 1 2

Figure 75. 100/7.5/75/7.5 NTSC Color Bars Chrominance

0.4

50.0

0.2

0.0

–0.2

–0.4

–50.0

F1

L76

0.0

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL NEEDS SYNC = SOURCE!

PRECISION MODE OFF

SYNCHRONOUS

525 LINE NTSC

NO FILTERING

SYNC = B

SLOW CLAMP TO 0.00 V AT 6.72 ␮s

FRAMES SELECTED: 1 2

Figure 76. 100/7.5/75/7.5 NTSC Color Bars Chrominance

REV. C

–41–

ADV7175A/ADV7176A

V

APL = 39.6%

SYSTEM LINE L608

ANGLE (DEG) 0.0

GAIN x 1.000 0.000dB

625 LINE PAL

cy

BURST FROM SOURCE

DISPLAY +V & –V

R

g

M

g

75%

100%

YI

b

U

yl

B

G

Cy

m

g

r

SOUND IN SYNC OFF

Figure 77. PAL Vector Plot

R-Y

APL = 45.1%

SYSTEM LINE L76F1

ANGLE (DEG) 0.0

GAIN x 1.000 0.000dB

525 LINE NTSC

cy

I

BURST FROM SOURCE

R

M

g

Q

YI

b

100%

B-Y

75%

B

G

Cy

–Q

–I

SETUP 7.5%

Figure 78. NTSC Vector Plot

–42–

REV. C

ADV7175A/ADV7176A

COLOR BAR (NTSC)

FIELD = 2 LINE = 28

LUMINANCE LEVEL (IRE)

WFM -->

FCC COLOR BAR

0.4

0.2

0.0

0.2

0.1

0.2

0.1

30.0

20.0

10.0

0.0

–10.0

CHROMINANCE LEVEL (IRE)

0.0

–0.2

–0.3

–0.2

–0.3

0.0

1.0

0.0

–1.0

CHROMINANCE PHASE (DEG)

. . . . .

–0.1

–0.2

–0.1

–0.3

–0.2

- - - - -

0.0

–1.0

–2.0

GRAY

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

AVERAGE: 32 --> 32

REFERENCE 75/7.5/75/7.5 COLOR BAR STANDARD

Figure 79. NTSC Color Bar Measurement

DGDP (NTSC)

BLOCK MODE START F2 L64, STEP = 32, END = 192

DIFFERENTIAL GAIN (%)

WFM -->

MOD 5 STEP

MIN = –0.00 MAX = 0.11 p-p/MAX = 0.11

0.00

0.08

0.07

0.11 0.07

0.05

0.3

0.2

0.1

0.0

–0.1

DIFFERENTIAL PHASE (DEG)

0.00 0.03

MIN = –0.02 MAX = 0.14 p-p = 0.16

0.14 0.10

–0.02

0.10

0.20

0.15

0.10

0.05

–0.00

–0.05

–0.10

1ST

2ND

3RD

4TH

5TH

6TH

Figure 80. NTSC Differential Gain and Phase Measurement

REV. C

–43–

ADV7175A/ADV7176A

LUMINANCE NONLINEARITY (NTSC)

WFM -->

5 STEP

FIELD = 2 LINE = 21

LUMINANCE NONLINEARITY (%)

p-p = 0.2

99.9

100.0

99.9

99.8

100.4

100.3

100.2

100.1

100.0

99.9

99.8

99.7

99.6

99.5

99.4

99.3

99.2

99.1

99.0

98.9

98.8

98.7

98.6

1ST

2ND

3RD

4TH

5TH

Figure 81. NTSC Luminance Nonlinearity Measurement

CHROMINANCE AM PM (NTSC)

FULL FIELD (BOTH FIELDS)

BANDWIDTH 100Hz TO 500kHz

WFM -->

APPROPRIATE

AM NOISE

–68.4dB RMS

–75.0

–70.0

–65.0

–60.0

–55.0

–50.0

–45.0

–40.0

dB RMS

PM NOISE

–64.4dB RMS

–75.0

–70.0

–65.0

–60.0

–55.0

–50.0

–45.0

–40.0

dB RMS

(0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)

Figure 82. NTSC AMPM Noise Measurement

–44–

REV. C

ADV7175A/ADV7176A

NOISE SPECTRUM (NTSC)

FIELD = 2 LINE = 64

AMPLITUDE (0 dB = 714mV p-p)

BANDWIDTH 100kHz TO FULL

WFM -->

PEDESTAL

NOISE LEVEL = –80.1 dB RMS

–5.0

–10.0

–15.0

–20.0

–25.0

–30.0

–35.0

–40.0

–45.0

–50.0

–55.0

–60.0

–65.0

–70.0

–75.0

–80.0

–85.0

–90.0

–95.0

–100.0

1.0

2.0

3.0

4.0

5.0

6.0

MHz

Figure 83. NTSC SNR Pedestal Measurement

NOISE SPECTRUM (NTSC)

WFM -->

RAMP SIGNAL

FIELD = 2 LINE = 64

AMPLITUDE (0 dB = 714mV p-p)

BANDWIDTH 10kHz TO FULL (TILT NULL)

NOISE LEVEL = –61.7 dB RMS

–5.0

–10.0

–15.0

–20.0

–25.0

–30.0

–35.0

–40.0

–45.0

–50.0

–55.0

–60.0

–65.0

–70.0

–75.0

–80.0

–85.0

–90.0

–95.0

–100.0

1.0

2.0

3.0

4.0

5.0

MHz

Figure 84. NTSC SNR Ramp Measurement

REV. C

–45–

ADV7175A/ADV7176A

PARADE SMPTE/EBU PAL

mV Y(A)

mV

250

Pb(B)

mV

Pr(C)

250

700

600

200

150

100

50

200

150

100

50

500

400

300

200

0

100

–50

0

–100

–150

–200

–250

–100

–150

–200

–250

؊100

؊200

؊300

Figure 85. PAL YUV Parade Plot

VM700A DEV 3 WC TEMP = 90؇C V = 5.25V

DD

CHANNEL C SYSTEM DEFAULT

10-APR-97 09:23:07

LIGHTNING

L183

COLORBARS: 75% SMPTE/EBU (50Hz)

Pk-WHITE (100%) 700.0mV SETUP 0.0% COLOR p-p 525.0mV

AVERAGE 15 --> 32

YI

G

R

CY

88.31

0.28%

M

B

–274.82

–173.24

0.19%

–88.36

0.19%

174.35

–0.65%

260.51

–0.14%

0.93%

B-Y

W

YI

CY

864.78

–0.88%

462.80

–0.50%

YI

G

307.54

–0.21%

CY

M

216.12

–0.33%

R

M

R

156.63

–0.22%

B

61.00

1.92%

B

R

G

M

CY

YI

W

R-Y

CY

–262.17

–0.13%

G

B

YI

M

R

–218.70

–0.51%

–42.54

0.69%

41.32

212.28

–3.43%

252.74

–3.72%

–0.76%

COLOR P-P: B-Y 532.33mV

1.40%

R-Y 514.90mV –1.92%

DELAY: B-Y –6ns R-Y –6ns

Pk-WHITE: 700.4mV (100%) SETUP –0.01%

Figure 86. PAL YUV Lighting Plot

–46–

REV. C

ADV7175A/ADV7176A

COMPONENT NOISE

LINE = 202

AMPLITUDE (0dB = 700mV p-p)

BANDWIDTH 10kHz TO 5.0MHz

NOISE dB RMS

0.0

–5.0

–10.0

–15.0

–20.0

–25.0

–30.0

-->Y –82.1

Pb –82.3

Pr –83.3

–35.0

–40.0

–45.0

–50.0

–55.0

–60.0

–65.0

–70.0

–75.0

–80.0

–85.0

–90.0

–95.0

–100.0

1.0

2.0

3.0

4.0

5.0

6.0

MHz

Figure 87. PAL YUV SNR Plot

COMPONENT MULTIBURST

LINE = 202

AMPLITUDE (0dB = 100% OF 688.1mV

683.4mV

–0.05

668.9mV

(dB)

0.04

–0.02

–0.68

–2.58

–8.05

0.0

–5.0

Y

–10.0

0.49

0.99

2.00

3.99

4.79

5.79

0.21

0.23

–0.78

–2.59

–7.15

0.0

Pb –5.0

–10.0

0.49

0.25

0.99

0.25

1.99

2.39

2.89

–0.77

–2.59

–7.13

0.0

Pr –5.0

–10.0

0.49

0.99

1.99

2.39

2.89

(MHz)

Figure 88. PAL YUV Multiburst Response

REV. C

–47–

ADV7175A/ADV7176A

COMPONENT VECTOR SMPTE/EBU, 75%

R

M

g

YI

BK

B

G

CY

Figure 89. PAL YUV Vector Plot

RGB PARADE SMPTE/EBU

mV GREEN (A)

mV

BLUE (B)

mV

RED (C)

700

600

700

600

500

400

300

200

100

0

600

500

400

300

200

100

0

500

400

300

200

100

0

؊100

؊200

؊300

؊100

؊200

؊300

؊100

؊200

؊300

20 --> 32

Figure 90. PAL RGB Waveforms

–48–

REV. C

ADV7175A/ADV7176A

INDEX

Contents

Page No.

Contents

Page No.

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1

ADV7175A/ADV7176A SPECIFICATIONS . . . . . . . . . . . 2

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 9

PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . 10

DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . 11

INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . 11

COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . 13

SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . 13

COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . 13

BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . 13

NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . 13

PIXEL TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . 13

SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

REAL TIME CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . 13

VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . 13

Timing Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Timing Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Timing Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Timing Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

OUTPUT VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . 21

POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 21

REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 23

REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . 23

MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 23

MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 24

SUBCARRIER FREQUENCY REGISTER . . . . . . . . . . . 24

SUBCARRIER PHASE REGISTER . . . . . . . . . . . . . . . . . 24

TIMING REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 24

CLOSED CAPTIONING EVEN FIELD . . . . . . . . . . . . . 25

CLOSED CAPTIONING ODD FIELD . . . . . . . . . . . . . 25

TIMING REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25

TR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 25

MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 25

NTSC PEDESTAL/PAL TELETEXT CONTROL

REGISTERS 3–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 26

TTXREQ CONTROL REGISTER TC07 . . . . . . . . . . . . 27

APPENDIX 1. BOARD DESIGN AND LAYOUT

CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

APPENDIX 2. CLOSED CAPTIONING . . . . . . . . . . . . 30

APPENDIX 3. TELETEXT INSERTION . . . . . . . . . . . 31

APPENDIX 4. WAVEFORMS . . . . . . . . . . . . . . . . . . . . 32

APPENDIX 5. REGISTER VALUES . . . . . . . . . . . . . . . 36

APPENDIX 6. OPTIONAL OUTPUT FILTER . . . . . . . 37

APPENDIX 7. OPTIONAL DAC BUFFERING . . . . . . 38

APPENDIX 8. OUTPUT WAVEFORMS . . . . . . . . . . . . 39

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 50

REV. C

–49–

ADV7175A/ADV7176A

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic Quad Flatpack

(S-44)

0.548 (13.925)

0.546 (13.875)

0.096 (2.44)

0.398 (10.11)

MAX

0.390 (9.91)

0.037 (0.94)

0.025 (0.64)

8°

0.8°

33

23

34

22

SEATING

PLANE

TOP VIEW

(PINS DOWN)

44

12

1

11

0.040 (1.02)

0.032 (0.81)

0.040 (1.02)

0.032 (0.81)

0.033 (0.84)

0.029 (0.74)

0.016 (0.41)

0.012 (0.30)

0.083 (2.11)

0.077 (1.96)

–50–

REV. C


型号：	ADV7176A_15
厂家：	ADI
描述：	High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
文件：	总50页 (文件大小：413K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADV7176A_15 [ADI]

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