ADV7181DWBCPZ_技术文档

10-Bit, 10-Channel, Multiformat SDTV/HDTV

Video Decoder and RGB Graphics Digitizer

Data Sheet

ADV7181D

FEATURES

GENERAL DESCRIPTION

Four 10-bit ADCs sampling up to 75 MHz

10 analog input channels

SCART fast blank support

The ADV7181D is a high quality, single-chip, multiformat video

decoder and graphics digitizer. This multiformat decoder supports

the conversion of PAL, NTSC, and SECAM standards in the form

of composite or S-Video into a digital ITU-R BT.656 format.

Internal antialiasing filters

NTSC, PAL, and SECAM color standards supported

525p/625p component progressive scan supported

720p/1080i component HDTV supported

Digitizes RGB graphics up to 1024 × 768 at 70 Hz (XGA)

3 × 3 color space conversion matrix

Industrial temperature range: −40°C to +85°C

12-bit 4:4:4 DDR, 8-/10-/16-/20-bit SDR pixel output interface

Programmable interrupt request output pin

Small package

The ADV7181D also supports the decoding of a component

RGB/YPrPb video signal into a digital YCrCb or RGB pixel

output stream. Support for component video includes standards

such as 525i, 625i, 525p, 625p, 720p, 1080i, and many other HD

and SMPTE standards.

Graphics digitization is also supported by the ADV7181D; it is

capable of digitizing RGB graphics signals from VGA to XGA

rates and converting them into a digital DDR RGB or YCrCb

pixel output stream. SCART and overlay functionality are enabled

by the ability of the ADV7181D to simultaneously process CVBS

and standard definition RGB signals. The mixing of these signals

is controlled by the fast blank (FB) pin.

Low pin count

Single front end for video and graphics

VBI data slicer (including teletext)

Qualified for automotive applications

The ADV7181D contains two main processing sections. The

first section is the standard definition processor (SDP), which

processes all PAL, NTSC, and SECAM signal types. The second

section is the component processor (CP), which processes YPrPb

and RGB component formats, including RGB graphics.

APPLICATIONS

Automotive entertainment

HDTVs

LCD/DLP® projectors

HDTV STBs with PVR

DVD recorders with progressive scan input support

AVR receivers

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADV7181D

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Standard Definition Processor (SDP) Pixel Data Output

Modes........................................................................................... 12

Component Processor (CP) Pixel Data Output Modes ........ 12

Composite and S-Video Processing......................................... 12

Component Video Processing.................................................. 13

RGB Graphics Processing ......................................................... 13

General Features......................................................................... 13

Detailed Descriptions .................................................................... 14

Analog Front End....................................................................... 14

Standard Definition Processor (SDP)...................................... 14

Component Processor (CP)...................................................... 14

Analog Input Muxing ................................................................ 15

Pixel Output Formatting................................................................ 18

Recommended External Loop Filter Components.................... 19

Typical Connection Diagram ....................................................... 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

Automotive Products................................................................. 21

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Electrical Characteristics............................................................. 4

Video Specifications..................................................................... 5

Analog Specifications................................................................... 6

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings............................................................ 9

Reflow Solder ................................................................................ 9

Package Thermal Performance................................................... 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Functional Overview...................................................................... 12

Analog Front End....................................................................... 12

REVISION HISTORY

12/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

Data Sheet

ADV7181D

FUNCTIONAL BLOCK DIAGRAM

1 0 0 4 - 9 9 0 9

R E T T A R M O F

A N O D F I F U P T U T O

Figure 1.

Rev. 0 | Page 3 of 24

ADV7181D

Data Sheet

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range = 1.6 V. T_MIN

to T_MAX= −40°C to +85°C, unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.

Table 1.

Parameter¹

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

STATIC PERFORMANCE^{2, 3}

Resolution (Each ADC)

Integral Nonlinearity

N

INL

10

2.ꢁ

Bits

LSB

BSL at 27 MHz (10-bit level)

BSL at ꢁ4 MHz (10-bit level)

BSL at 74 MHz (10-bit level)

At 27 MHz (10-bit level)

At ꢁ4 MHz (10-bit level)

At 74 MHz (10-bit level)

0.ꢀ

−0.ꢀ/+0.7

1.4

Differential Nonlinearity

DNL

−0.2/+0.2ꢁ −0.99/+2.ꢁ LSB

−0.2/+0.2ꢁ

0.9

LSB

DIGITAL INPUTS

Input High Voltage⁴

V_IH

V_IL

2

0.7

V

μA

pF

HS_IN, VS_IN low trigger mode

Input Low Voltage^ꢁ

0.8

0.3

+10

10

Input Current

I_IN

C_IN

−10

2.4

Input Capacitance^ꢀ

DIGITAL OUTPUTS

Output High Voltage⁷

Output Low Voltage⁷

V_OH

V_OL

I_SOURCE= 0.4 mA

I_SINK= 3.2 mA

Pin 1

V

μA

pF

0.4

ꢀ0

10

20

High Impedance Leakage Current I_LEAK

All other output pins

Output Capacitance^ꢀ

POWER REQUIREMENTS^ꢀ

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply

C_OUT

DVDD

DVDDIO

PVDD

AVDD

I_DVDD

1.ꢀꢁ

3.0

1.71

3.1ꢁ

1.8

3.3

1.8

3.3

10ꢁ

90

10ꢀ

4

38

11

12

99

1ꢀꢀ

200

2.2ꢁ

1ꢀ

2.0

3.ꢀ

1.89

3.4ꢁ

V

Analog Power Supply

Digital Core Supply Current

CVBS input sampling at ꢁ4 MHz

Graphics RGB sampling at 7ꢁ MHz

SCART RGB FB sampling at ꢁ4 MHz

CVBS input sampling at ꢁ4 MHz

Graphics RGB sampling at 7ꢁ MHz

CVBS input sampling at ꢁ4 MHz

Graphics RGB sampling at 7ꢁ MHz

CVBS input sampling at ꢁ4 MHz

Graphics RGB sampling at 7ꢁ MHz

SCART RGB FB sampling at ꢁ4 MHz

mA

ms

Digital I/O Supply Current

PLL Supply Current

I_DVDDIO

I_PVDD

Analog Supply Current⁸

I_AVDD

Power-Down Current

Green Mode Power-Down

Power-Up Time

I_PWRDN

I_PWRDNG

t_PWRUP

Synchronization bypass function

20

¹All specifications are obtained using the Analog Devices, Inc., recommended programming scripts.

²All ADC linearity tests performed at input range of full scale − 12.ꢁ% and at zero scale + 12.ꢁ%.

³Maximum INL and DNL specifications obtained with part configured for component video input.

⁴To obtain specified V_IHlevel on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then V_IHon Pin 22 is 1.2 V.

^ꢁTo obtain specified V_ILlevel on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then V_ILon Pin 22 is 0.4 V.

^ꢀGuaranteed by characterization.

⁷V_OHand V_OLlevels obtained using default drive strength value (0xDꢁ) in Register Subaddress 0xF4.

⁸For CVBS current measurements only, ADC0 is powered up. For RGB current measurements only, ADC0, ADC1, and ADC2 are powered up. For SCART FB current

measurements, all four ADCs are powered up.

Rev. 0 | Page 4 of 24

Data Sheet

ADV7181D

VIDEO SPECIFICATIONS

AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T_MINto T_MAX= −40°C to +85°C,

unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.

Table 2.

Parameter¹

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

NONLINEAR SPECIFICATIONS

Differential Phase

Differential Gain

DP

DG

LNL

CVBS input, modulated ꢁ step

CVBS input, ꢁ step

0.ꢁ

Degrees

%

Luma Nonlinearity

NOISE SPECIFICATIONS

Signal-to-Noise Ratio, Unweighted

SNR

Luma ramp

Luma flat field

ꢁ4

ꢁ8

ꢁꢀ

ꢀ0

dB

Analog Front-End Crosstalk

LOCK TIME SPECIFICATIONS

Horizontal Lock Range

Vertical Lock Range

−ꢁ

40

+ꢁ

70

%

Hz

f_SCSubcarrier Lock Range

Color Lock-In Time

1.3

ꢀ0

kHz

Lines

%

Synchronization Depth Range²

20

ꢁ

200

Color Burst Range

%

Vertical Lock Time

Horizontal Lock Time

2

100

Fields

Lines

CHROMA SPECIFICATIONS

Hue Accuracy

Color Saturation Accuracy

Color AGC Range

1

Degrees

%

CL_AC

ꢁ

400

Chroma Amplitude Error

Chroma Phase Error

Chroma Luma Intermodulation

LUMA SPECIFICATIONS

Luma Brightness Accuracy

Luma Contrast Accuracy

0.ꢁ

0.4

0.2

%

Degrees

%

CVBS, 1 V input

1

%

¹Guaranteed by characterization.

²Nominal synchronization depth is 300 mV at 100% synchronization depth range.

Rev. 0 | Page ꢁ of 24

ADV7181D

Data Sheet

ANALOG SPECIFICATIONS

AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T_MINto T_MAX= −40°C to +85°C,

unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range. The recommended analog

input video signal range is 0.5 V to 1.6 V, typically 1 V p-p.

Table 3.

Parameter¹

Test Conditions/Comments

Min

Typ

Max

Unit

CLAMP CIRCUITRY

External Clamp Capacitor

Input Impedance

0.1

μF

All Pins Except for Pin 32 (FB)

Pin 32 (FB)

Clamps switched off

10

20

1.8ꢀ

MΩ

kΩ

V

mA

μA

Common-Mode Level (CML)

ADC Full-Scale Level

ADC Zero-Scale Level

ADC Dynamic Range

Clamp Level (When Locked)

CML + 0.8

CML − 0.8

1.ꢀ

CML − 0.292

CML − 0.4

CML − 0.292

CML

CML − 0.3

0.7ꢁ

CVBS input

SCART RGB input (R, G, B signals)

S-Video input (Y signal)

S-Video input (C signal)

Component input (Y, Pr, Pb signals)

PC RGB input (R, G, B signals)

SDP only

Large Clamp Source Current

Large Clamp Sink Current

Fine Clamp Source Current

Fine Clamp Sink Current

0.9

17

¹Guaranteed by characterization.

Rev. 0 | Page ꢀ of 24

Data Sheet

ADV7181D

TIMING CHARACTERISTICS

AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T_MINto T_MAX= −40°C to +85°C,

unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.

Table 4.

Parameter¹

Symbol Description

Min

Typ

Max

Unit

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency

Crystal Frequency Stability

Horizontal Sync Input Frequency

LLC Frequency Range

I²C PORT²

28.ꢀ3ꢀ3ꢀ

MHz

ppm

kHz

ꢁ0

110

7ꢁ

14.8

12.82ꢁ

MHz

SCLK Frequency

SCLK Minimum Pulse Width High t₁

400

kHz

μs

ns

μs

0.ꢀ

1.3

0.ꢀ

100

SCLK Minimum Pulse Width Low

Hold Time (Start Condition)

Setup Time (Start Condition)

SDATA Setup Time

SCLK and SDATA Rise Time

SCLK and SDATA Fall Time

Setup Time (Stop Condition)

RESET FEATURE

t₂

t₃

t₄

t_ꢁ

t_ꢀ

t₇

t₈

300

0.ꢀ

Reset Pulse Width

ꢁ

ms

CLOCK OUTPUTS

LLC Mark-Space Ratio

t₉:t₁₀

4ꢁ:ꢁꢁ

ꢁꢁ:4ꢁ

% duty

cycle

DATA AND CONTROL OUTPUTS

Data Output Transition Time

SDR (SDP)³

t₁₁

t₁₂

t₁₃

t₁₄

t_1ꢁ

t_1ꢀ

t₁₇

t₁₈

Negative clock edge to start of valid data

End of valid data to negative clock edge

Negative clock edge to start of valid data

Positive clock edge to end of valid data

Positive clock edge to start of valid data

Negative clock edge to end of valid data

3.ꢀ

2.4

2.8

0.1

ns

SDR (CP)⁴

DDR (CP)^{4, ꢁ}

−4 + T_LLC/4

0.2ꢁ + T_LLC/4

−2.9ꢁ + T_LLC/4

Negative clock edge to start of valid data −0.ꢁ + T_LLC/4

¹Guaranteed by characterization.

²TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.

³SDP timing figures obtained using default drive strength value (0xDꢁ) in Register Subaddress 0xF4.

⁴CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.

^ꢁDDR timing specifications dependent on LLC output pixel clock; T_LLC/4 = 9.2ꢁ ns at LLC = 27 MHz.

Timing Diagrams

t₃

t₅

t₃

SDATA

SCLK

t₆

t₁

t₂

t₇

t₄

t₈

Figure 2. I²C Timing

Rev. 0 | Page 7 of 24

ADV7181D

Data Sheet

t₉

t₁₀

LLC

t₁₁

t₁₂

P0 TO P19, VS,

HS/CS, FIELD/DE,

SFL/SYNC_OUT

Figure 3. Pixel Port and Control SDR Output Timing (SDP Core)

t₉

t₁₀

LLC

t₁₃

t₁₄

P0 TO P19

Figure 4. Pixel Port and Control SDR Output Timing (CP Core)

LLC

t₁₆

t₁₈

t₁₅

t₁₇

P6 TO P19

Figure 5. Pixel Port and Control DDR Output Timing (CP Core)

Rev. 0 | Page 8 of 24

Data Sheet

ADV7181D

ABSOLUTE MAXIMUM RATINGS

PACKAGE THERMAL PERFORMANCE

Table 5.

To reduce power consumption when using the part, turn off any

unused ADCs.

Parameter

Rating

AVDD to GND

4 V

DVDD to GND

PVDD to GND

2.2 V

4 V

It is imperative that the recommended scripts be used for the

following high current modes: SCART, 720p, 1080i, and all

RGB graphic standards. Using the recommended scripts ensures

correct thermal performance. These scripts are available from

a local field applications engineer (FAE).

DVDDIO to GND

DVDDIO to AVDD

PVDD to DVDD

DVDDIO to PVDD

DVDDIO to DVDD

AVDD to PVDD

AVDD to DVDD

Digital Inputs to GND

−0.3 V to +0.3 V

−0.3 V to +2 V

GND − 0.3 V to

DVDDIO + 0.3 V

GND − 0.3 V to

DVDDIO + 0.3 V

GND − 0.3 V to

AVDD + 0.3 V

−40°C to +8ꢁ°C

12ꢁ°C

−ꢀꢁ°C to +1ꢁ0°C

2ꢀ0°C

The junction temperature must always stay below the maximum

junction temperature (T_{J MAX}) of 125°C. The junction temperature

can be calculated by

T_J= T_{A MAX}+ (θ_JA× W_MAX

where:

_{A MAX}= 85°C.

_JA= 20.3°C/W.

)

Digital Outputs to GND

Analog Inputs to GND

T

θ

W

_MAX= ((AVDD × I_AVDD) + (DVDD × I_DVDD) +

(DVDDIO × I_DVDDIO) + (PVDD × I_PVDD))

Operating Temperature Range

Maximum Junction Temperature (T_{J MAX}

Storage Temperature Range

)

THERMAL RESISTANCE

Infrared Reflow, Soldering (20 sec)

Table 6 specifies the typical values for the junction-to-ambient

thermal resistance (θ_JA) and the junction-to-case thermal resis-

tance (θ_JC) for an ADV7181D soldered on a 4-layer PCB with

solid ground plane.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 6. Thermal Resistance

Package Type

1

θ_JA

θ_JC

Unit

ꢀ4-Lead LFCSP (CP-ꢀ4-3)

20.3

1.2

°C/W

¹In still air.

REFLOW SOLDER

The ADV7181D is a Pb-free, environmentally friendly product.

It is manufactured using the most up-to-date materials and pro-

cesses. The coating on the leads of each device is 100% pure Sn

electroplate. The device is suitable for Pb-free applications and

can withstand surface-mount soldering at up to 255°C 5°C.

ESD CAUTION

In addition, the ADV7181D is backward-compatible with

conventional SnPb soldering processes. This means that the

electroplated Sn coating can be soldered with Sn/Pb solder

pastes at conventional reflow temperatures of 220°C to 235°C.

Rev. 0 | Page 9 of 24

ADV7181D

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

INT

A

9

8

7

6

IN

PIN 1

2

3

HS/CS

GND

4

DVDDIO

5

P15

CAPC2

CML

6

P14

7

P13

REFOUT

AVDD

ADV7181D

8

P12

TOP VIEW

(Not to Scale)

9

SFL/SYNC_OUT

CAPY2

CAPY1

10

11

12

13

14

15

16

GND

DVDDIO

P11

A

5

4

3

2

1

IN

P10

P9

P8

P7

SOG

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO GND.

Figure 6. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

1

INT

Output

Interrupt. This pin can be active low or active high. When SDP/CP status bits change,

this pin is triggered. The set of events that triggers an interrupt is under user control.

2

HS/CS

Output

Horizontal Synchronization Output Signal (HS). Available in SDP and CP modes.

Digital Composite Synchronization Signal (CS). Available in CP mode only.

3, 10, 24, ꢁ7

4, 11

GND

DVDDIO

Ground

Power

Ground.

Digital I/O Supply Voltage (3.3 V).

28 to 2ꢁ, 19 to 12, P0 to P19

8 to ꢁ, ꢀ2 to ꢁ9

Output

Video Pixel Output Port. See Table 10 and Table 11 for output configuration modes.

9

SFL/SYNC_OUT Output

Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be

used to lock the subcarrier frequency when this decoder is connected to any Analog

Devices digital video encoder.

Sliced Synchronization Output Signal (SYNC_OUT). Available in CP mode only.

20

21

LLC

XTAL1

Output

Line-Locked Clock Output for Pixel Data. The range is 12.82ꢁ MHz to 7ꢁ MHz.

This pin should be connected to the 28.ꢀ3ꢀ3ꢀ MHz crystal or left unconnected if an

external 3.3 V, 28.ꢀ3ꢀ3ꢀ MHz clock oscillator source is used to clock the ADV7181D.

In crystal mode, the crystal must be a fundamental crystal.

22

XTAL

Input

Input Pin for the 28.ꢀ3ꢀ3ꢀ MHz Crystal. This input can be overdriven by an external

3.3 V, 28.ꢀ3ꢀ3ꢀ MHz clock oscillator source to clock the ADV7181D.

23, ꢁ8

29

DVDD

PWRDWN

ELPF

Power

Input

Digital Core Supply Voltage (1.8 V).

Power-Down Input. A Logic 0 on this pin places the ADV7181D in power-down mode.

30

Output

External Loop Filter Output. The recommended external loop filter must be connected

to this pin (see the Recommended External Loop Filter Components section).

31

32

PVDD

FB

Power

Input

PLL Supply Voltage (1.8 V).

Fast Blank Input. Fast switch between CVBS and RGB analog signals.

Rev. 0 | Page 10 of 24

Data Sheet

ADV7181D

Pin No.

Mnemonic

Type

Input

Description

33

SOG

Sync on Green Input. Used in embedded synchronization mode.

Analog Video Input Channels.

ADC Capacitor Network. See Figure 9 for a recommended capacitor network for

these pins.

34 to 38, 4ꢁ to 49 A_IN1 to A_IN10

39, 40

CAPY1, CAPY2

41

42

AVDD

REFOUT

Power

Output

Analog Supply Voltage (3.3 V).

Internal Voltage Reference Output. See Figure 9 for a recommended capacitor network

for this pin.

43

CML

Output

Common-Mode Level Pin for the Internal ADCs. See Figure 9 for a recommended

capacitor network for this pin.

44

ꢁ0

ꢁ1

CAPC2

SOY

RESET

Input

ADC Capacitor Network. See Figure 9 for a recommended capacitor network for this pin.

Sync on Luma Input. Used in embedded synchronization mode.

System Reset Input, Active Low. A minimum low reset pulse width of ꢁ ms is required

to reset the ADV7181D circuitry.

ꢁ2

ALSB

Input

This pin selects the I²C address for the ADV7181D control and VBI readback ports. When

set to Logic 0, this pin sets the address for a write to Control Port 0x40 and the readback

address for VBI Port 0x21. When set to Logic 1, this pin sets the address for a write to

Control Port 0x42 and the readback address for VBI Port 0x23.

ꢁ3

SDATA

Input/

I²C Port Serial Data Input/Output Pin.

Output

Input

ꢁ4

ꢁꢁ

SCLK

VS_IN

I²C Port Serial Clock Input. Maximum clock rate of 400 kHz.

Vertical Synchronization Input Signal. This pin can be configured in CP mode to extract

timing in a ꢁ-wire mode.

ꢁꢀ

HS_IN/CS_IN

FIELD/DE

Input

Horizontal Synchronization Input Signal (HS_IN). This pin can be configured in CP mode

to extract timing in a ꢁ-wire mode.

Composite Synchronization Input Signal (CS_IN). This pin can be configured in CP mode

to extract timing in a 4-wire mode.

Field Synchronization Output Signal (FIELD). Used in all interlaced video modes.

Data Enable Signal (DE). This pin can also be used as a data enable (DE) signal in CP mode

to allow direct connection to an HDMI/DVI transmitter IC.

Vertical Synchronization Output Signal (SDP and CP Modes).

The exposed pad must be connected to GND.

ꢀ3

Output

ꢀ4

EP

VS

Exposed Pad

Rev. 0 | Page 11 of 24

ADV7181D

Data Sheet

FUNCTIONAL OVERVIEW

This section provides a brief description of the functionality of

the ADV7181D. More detailed information is available in the

Detailed Descriptions section.

COMPOSITE AND S-VIDEO PROCESSING

Composite and S-Video processing features offer support for

NTSC M/J, NTSC 4.43, PAL B/D/I/G/H, PAL60, PAL M, PAL N,

and SECAM (B, D, G, K, and L) standards in the form of CVBS

and S-Video. Superadaptive, 2D, five-line comb filters for NTSC

and PAL provide superior chrominance and luminance separa-

tion for composite video.

ANALOG FRONT END

The analog front end of the ADV7181D contains four high

quality, 10-bit ADCs and a multiplexer (mux) with 10 analog

input channels to enable multisource connection without the

requirement of an external multiplexer. The analog front end

also provides the following:

Composite and S-Video processing features also include full auto-

matic detection and autoswitching of all worldwide standards

(PAL, NTSC, and SECAM) and automatic gain control (AGC)

with white peak mode to ensure that the video is always processed

without loss of the video processing range. Other features include

•

Four current and voltage clamp control loops to ensure

that dc offsets are removed from the video signal

SCART functionality and standard definition (SD) RGB

overlay on CVBS controlled by the fast blank (FB) input

Four internal antialiasing filters to remove out-of-band

noise on standard definition input video signals

•

Adaptive Digital Line Length Tracking (ADLLT™), a

proprietary architecture for locking to weak, noisy, and

unstable sources from VCRs and tuners

IF filter block to compensate for high frequency luma

attenuation due to tuner SAW filter

•

STANDARD DEFINITION PROCESSOR (SDP)

PIXEL DATA OUTPUT MODES

•

Chroma transient improvement (CTI)

The ADV7181D features the following SDP pixel data output

modes:

Luminance digital noise reduction (DNR)

Color controls including hue, brightness, saturation,

contrast, and Cr and Cb offset controls

•

8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time

codes and/or HS, VS, and FIELD

•

Certified Macrovision® copy protection detection on

composite and S-Video for all worldwide formats

(PAL/NTSC/SECAM)

4× oversampling (54 MHz) for CVBS, S-Video, and

YUV modes

•

16-/20-bit 4:2:2 YCrCb with embedded time codes and/or

HS, VS, and FIELD

COMPONENT PROCESSOR (CP) PIXEL DATA

OUTPUT MODES

•

Line-locked clock (LLC) output

Letterbox detection support

Free-run output mode to provide stable timing when no

video input is present

The ADV7181D features the following CP pixel data output

modes for single data rate (SDR) and double data rate (DDR):

•

SDR 8-/10-bit 4:2:2 YCrCb for 525i and 625i

SDR 16-/20-bit 4:2:2 YCrCb for all standards

DDR 8-/10-bit 4:2:2 YCrCb for all standards

DDR 12-bit 4:4:4 RGB for graphics inputs

•

Vertical blanking interval (VBI) data processor, including

teletext, video programming system (VPS), vertical interval

time codes (VITC), closed captioning (CC), extended data

service (XDS), wide screen signaling (WSS), copy genera-

tion management system (CGMS), and compatibility with

GemStar® 1×/2× electronic program guide

Clocked from a single 28.63636 MHz crystal

Subcarrier frequency lock (SFL) output for downstream

video encoder

•

Differential gain, typically 0.5%

Differential phase, typically 0.5°

Rev. 0 | Page 12 of 24

Data Sheet

ADV7181D

COMPONENT VIDEO PROCESSING

GENERAL FEATURES

Component video processing supports formats including 525i,

625i, 525p, 625p, 720p, 1080i, and many other HD formats, as

well as automatic adjustments that include gain (contrast) and

offset (brightness), and manual adjustment controls. Other

features supported by component video processing include

The ADV7181D features HS/CS, VS, and FIELD/DE output

signals with programmable position, polarity, and width, as well

INT

as a programmable interrupt request output pin,

SDP/CP status changes. Other features include

, that signals

•

Low power consumption: 1.8 V digital core, 3.3 V analog

and digital I/O, low power, power-down mode, and green

PC mode

•

Analog component YPrPb/RGB video formats with

embedded synchronization or with separate HS, VS, or CS

Color space conversion matrix to support YCrCb-to-DDR

RGB and RGB-to-YCrCb conversions

Standard identification (STDI) to enable system level

component format detection

Synchronization source polarity detector (SSPD) to

determine the source and polarity of the synchronization

signals that accompany the input video

•

Industrial temperature range of −40°C to +85°C

64-lead, 9 mm × 9 mm, Pb-free LFCSP

3.3 V ADCs giving enhanced dynamic range and

performance

•

Certified Macrovision copy protection detection on

component formats (525i, 625i, 525p, and 625p)

Free-run output mode to provide stable timing when

no video input is present

Arbitrary pixel sampling support for nonstandard video

sources

RGB GRAPHICS PROCESSING

RGB graphics processing offers a 75 MSPS conversion rate

that supports RGB input resolutions up to 1024 × 768 at 70 Hz

(XGA), automatic or manual clamp and gain controls for

graphics modes, and contrast and brightness controls. Other

features include

•

32-phase DLL to allow optimum pixel clock sampling

Automatic detection of synchronization source and

polarity by SSPD block

•

Standard identification enabled by the STDI block

RGB that can be color space converted to YCrCb and

decimated to a 4:2:2 format for videocentric back-end

IC interfacing

•

Data enable (DE) output signal supplied for direct

connection to HDMI®/DVI transmitter IC

Arbitrary pixel sampling support for nonstandard video

sources

RGB graphics supported on 12-bit DDR format

Rev. 0 | Page 13 of 24

ADV7181D

Data Sheet

DETAILED DESCRIPTIONS

The SDP also contains a chroma transient improvement (CTI)

processor. This processor increases the edge rate on chroma

transitions, resulting in a sharper video image.

ANALOG FRONT END

The ADV7181D analog front end comprises four 10-bit ADCs

that digitize the analog video signal before applying it to the SDP

or CP. The analog front end uses differential channels to each

ADC to ensure high performance in a mixed-signal application.

The SDP can process a variety of VBI data services, such as tele-

text, closed captioning (CC), wide screen signaling (WSS), video

programming system (VPS), vertical interval time codes (VITC),

copy generation management system (CGMS), GemStar 1×/2×,

and extended data service (XDS). The ADV7181D SDP section has

a Macrovision 7.1 detection circuit that allows it to detect Type I,

Type II, and Type III protection levels. The decoder is also fully

robust to all Macrovision signal inputs.

The front end also includes a 10-channel input mux that enables

multiple video signals to be applied to the ADV7181D. Current

and voltage clamps are positioned in front of each ADC to ensure

that the video signal remains within the range of the converter.

Fine clamping of the video signals is performed downstream by

digital fine clamping in either the CP or SDP.

COMPONENT PROCESSOR (CP)

Optional antialiasing filters are positioned in front of each ADC.

These filters can be used to band-limit standard definition video

signals, removing spurious out-of-band noise.

The CP section is capable of decoding and digitizing a wide range

of component video formats in any color space. Component video

standards supported by the CP are 525i, 625i, 525p, 625p, 720p,

1080i, graphics up to XGA at 70 Hz, and many other standards.

The ADCs are configured to run in 4× oversampling mode

when decoding composite and S-Video inputs; 2× oversampling

is performed for component 525i, 625i, 525p, and 625p sources.

All other video standards are 1× oversampled. Oversampling

the video signals reduces the cost and complexity of external

antialiasing filters with the benefit of an increased signal-to-

noise ratio (SNR).

The CP section of the ADV7181D contains an AGC block.

When no embedded synchronization is present, the video

gain can be set manually. The AGC section is followed by a

digital clamp circuit, which ensures that the video signal is

clamped to the correct blanking level. Automatic adjustments

within the CP include gain (contrast) and offset (brightness);

manual adjustment controls are also supported.

The ADV7181D can support simultaneous processing of CVBS

and RGB standard definition signals to enable SCART compati-

bility and overlay functionality. A combination of CVBS and

RGB inputs can be mixed and output under the control of the

I²C registers and the fast blank (FB) pin.

A fixed mode graphics RGB to component output is available.

A color space conversion matrix is placed between the analog

front end and the CP section. This enables YCrCb-to-DDR RGB

and RGB-to-YCrCb conversions. Many other standards of color

space can be implemented using the color space converter.

STANDARD DEFINITION PROCESSOR (SDP)

The SDP section is capable of decoding a large selection of

baseband video signals in composite, S-Video, and YUV

formats. The video standards supported by the SDP include

PAL B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC 4.43,

and SECAM B/D/G/K/L. The ADV7181D automatically detects

the video standard and processes it accordingly.

The output section of the CP is highly flexible. It can be config-

ured in SDR mode with one data packet per clock cycle or in

DDR mode where data is presented on the rising and falling

edges of the clock. In SDR and DDR modes, HS/CS, VS, and

FIELD/DE (where applicable) timing reference signals are

provided. In SDR mode, a 20-bit 4:2:2 is possible. In DDR

mode, the ADV7181D can be configured in an 8-bit or 10-bit

4:2:2 YCrCb or in a 12-bit 4:4:4 RGB pixel output interface with

corresponding timing signals.

The SDP has a five-line, superadaptive, 2D comb filter that pro-

vides superior chrominance and luminance separation when

decoding a composite video signal. This highly adaptive filter

automatically adjusts its processing mode according to video

standards and signal quality with no user intervention required.

The SDP has an IF filter block that compensates for attenuation

in the high frequency luma spectrum due to the tuner SAW filter.

The CP section contains circuitry to enable the detection of

Macrovision encoded YPrPb signals for 525i, 625i, 525p, and

625p. It is designed to be fully robust when decoding these

types of signals.

The SDP has specific luminance and chrominance parameter

control for brightness, contrast, saturation, and hue.

VBI extraction of component data is performed by the CP

section of the ADV7181D for interlaced, progressive, and high

definition scanning rates. The data extracted can be read back

over the I²C interface.

The ADV7181D implements a patented ADLLT algorithm to

track varying video line lengths from sources such as a VCR.

ADLLT enables the ADV7181D to track and decode poor

quality video sources such as VCRs, noisy sources from tuner

outputs, VCD players, and camcorders.

Rev. 0 | Page 14 of 24

Data Sheet

ADV7181D

ANALOG INPUT MUXING

The ADV7181D has an integrated analog muxing section, which allows more than one source of video signal to be connected to the

decoder. Figure 7 outlines the overall structure of the input muxing provided in the ADV7181D.

ADC_SW_MAN_EN

A

1

2

3

4

5

6

7

8

9

10

IN

1

ADC0_SW[3:0]

ADC0

A

4

IN

5

1

ADC1_SW[3:0]

6

7

8

ADC1

9

10

A

3

1

ADC2_SW[3:0]

IN

6

7

8

ADC2

9

10

1

ADC3_SW[3:0]

A

1

6

IN

ADC3

Figure 7. Internal Pin Connections

Rev. 0 | Page 1ꢁ of 24

ADV7181D

Data Sheet

Table 8 provides the recommended ADC mapping for the ADV7181D.

Table 8. Recommended ADC Mapping

Mode

Required ADC Mapping Analog Input Channel

Core

Configuration¹

CVBS

ADC0

CVBS = A_IN1

SDP

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

YC/YC Auto

Y = ADC0

C = ADC1

Y = A_IN7

C = A_IN9

SDP

CP

INSEL[3:0] = 0000

SDM_SEL[1:0] = 11

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

Component YUV

SCART RGB

Y = ADC0

U = ADC2

V = ADC1

Y = A_IN10

U = A_IN8

V = A_INꢀ

INSEL[3:0] = 1001

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

Y = ADC0

U = ADC2

V = ADC1

Y = A_IN10

U = A_IN8

V = A_INꢀ

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 1010

CBVS = ADC0

G = ADC1

B = ADC3

CVBS = A_IN4

G = A_IN10

B = A_INꢀ

SDP

CP

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

R = ADC2

R = A_IN8

Graphics

RGB Mode

G = ADC0

B = ADC2

R = ADC1

G = A_IN2

B = A_IN3

R = A_INꢁ

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0010

VID_STD[3:0] = 1100

¹Configuration to format follow-on blocks in correct frame.

Rev. 0 | Page 1ꢀ of 24

Data Sheet

ADV7181D

The analog input muxes of the ADV7181D must be controlled

directly. This is referred to as manual input muxing. The manual

muxing is activated by setting the ADC_SW_MAN_EN bit (see

Table 9). It affects only the analog switches in front of the ADCs.

The INSEL, SDM_SEL, PRIM_MODE, and VID_STD bits must

still be set so that the follow-on blocks process the video data in

the correct format.

Table 9 explains the ADC mapping configuration for the following:

•

ADC_SW_MAN_EN, manual input muxing enable,

IO map, Address C4[7]

ADC0_SW[3:0], ADC0 mux configuration, IO map,

Address C3[3:0]

ADC1_SW[3:0], ADC1 mux configuration, IO map,

Address C3[7:4]

ADC2_SW[3:0], ADC2 mux configuration, IO map,

Address C4[3:0]

Not every input pin can be routed to any ADC. The analog

signal routing inside the IC imposes restrictions on the channel

routing. See Table 9 for an overview of the routing capabilities

inside the chip. The four mux sections can be controlled by the

reserved control signal buses ADC0_SW[3:0], ADC1_SW[3:0],

ADC2_SW[3:0], and ADC3_SW[3:0].

ADC3_SW[3:0], ADC3 mux configuration, IO map,

Address F3[7:4]

Table 9. Manual MUX Settings for All ADCs

ADC_SW_MAN_EN = 1

ADC1

ADC1_SW[3:0] Connection

ADC0

ADC2

ADC3

ADC0_SW[3:0] Connection

ADC2_SW[3:0] Connection

ADC3_SW[3:0] Connection

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

N/A

A_IN2

A_IN3

A_INꢁ

A_INꢀ

A_IN8

A_IN10

N/A

A_IN1

N/A

A_IN4

N/A

A_IN7

A_IN9

N/A

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

N/A

A_INꢁ

A_INꢀ

A_IN8

A_IN10

N/A

A_IN4

N/A

A_IN7

A_IN9

N/A

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

N/A

A_IN3

N/A

A_INꢀ

A_IN8

A_IN10

N/A

A_IN7

A_IN9

N/A

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

N/A

A_INꢀ

N/A

A_IN1

N/A

Rev. 0 | Page 17 of 24

ADV7181D

Data Sheet

PIXEL OUTPUT FORMATTING

Table 10. SDP Output Formats—SDR 4:2:2 (8-/10-/16-/20-Bit)

8-Bit SDR

ITU-R BT.656

10-Bit SDR

ITU-R BT.656

Pixel Output Pin

16-Bit SDR

Y7

Yꢀ

Yꢁ

Y4

Y3

Y2

Y1

Y0

High-Z

Cb7, Cr7

Cbꢀ, Crꢀ

Cbꢁ, Crꢁ

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

High-Z

20-Bit SDR

P19

P18

P17

P1ꢀ

P1ꢁ

P14

P13

P12

P11

P10

P9

P8

P7

Pꢀ

Pꢁ

P4

P3

P2

P1

Y7, Cb7, Cr7

Yꢀ, Cbꢀ, Crꢀ

Yꢁ, Cbꢁ, Crꢁ

Y4, Cb4, Cr4

Y3, Cb3, Cr3

Y2, Cb2, Cr2

Y1, Cb1, Cr1

Y0, Cb0, Cr0

High-Z

Y9, Cb9, Cr9

Y8, Cb8, Cr8

Y7, Cb7, Cr7

Yꢀ, Cbꢀ, Crꢀ

Yꢁ, Cbꢁ, Crꢁ

Y4, Cb4, Cr4

Y3, Cb3, Cr3

Y2, Cb2, Cr2

Y1, Cb1, Cr1

Y0, Cb0, Cr0

High-Z

Y9

Y8

Y7

Yꢀ

Yꢁ

Y4

Y3

Y2

Y1

Y0

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cbꢀ, Crꢀ

Cbꢁ, Crꢁ

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

P0

High-Z

Table 11. CP Output Formats—SDR 4:2:2 (16-/20-Bit) and DDR 4:4:4 (12-Bit)

SDR 4:2:2

12-Bit DDR 4:4:4¹

Clock Fall

R3-1

Pixel Output

P19

P18

P17

P1ꢀ

P1ꢁ

P14

P13

P12

P11

P10

P9

P8

P7

Pꢀ

Pꢁ

P4

P3

P2

P1

16-Bit SDR

Y7

Yꢀ

Yꢁ

Y4

Y3

Y2

Y1

Y0

High-Z

Cb7, Cr7

Cbꢀ, Crꢀ

Cbꢁ, Crꢁ

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

High-Z

20-Bit SDR

Y9

Y8

Y7

Yꢀ

Yꢁ

Y4

Y3

Y2

Clock Rise

B7-0

Bꢀ-0

Bꢁ-0

B4-0

B3-0

B2-0

B1-0

B0-0

High-Z

G3-0

G2-0

G1-0

R2-1

R1-1

R0-1

G7-1

Gꢀ-1

Gꢁ-1

G4-1

High-Z

R7-1

Rꢀ-1

Rꢁ-1

Y1

Y0

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cbꢀ, Crꢀ

Cbꢁ, Crꢁ

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

G0-0

R4-1

High-Z

P0

¹xx-0 corresponds to data clocked at the rising edge; xx-1 corresponds to data clocked at the falling edge.

Rev. 0 | Page 18 of 24

Data Sheet

ADV7181D

RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS

The external loop filter components for the ELPF pin should be placed as close to the pin as possible. Figure 8 shows the recommended

component values.

30

ELPF

1.69kΩ

10nF

82nF

PVDD = 1.8V

Figure 8. ELPF Components

Rev. 0 | Page 19 of 24

ADV7181D

Data Sheet

TYPICAL CONNECTION DIAGRAM

0 0 9 4 - 9 9 0 9

Figure 9. Typical Connection

Rev. 0 | Page 20 of 24

Data Sheet

ADV7181D

OUTLINE DIMENSIONS

0.60 MAX

9.00

BSC SQ

0.60

MAX

PIN 1

INDICATOR

64

49

48

1

PIN 1

INDICATOR

0.50

BSC

7.25

7.10 SQ

6.95

8.75

BSC SQ

TOP VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

16

17

33

32

0.25 MIN

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 10. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2}

ADV7181DBCPZ

ADV7181DBCPZ-RL

ADV7181DWBCPZ

ADV7181DWBCPZ-RL

EVAL-ADV7181DEBZ

Temperature Range

−40°C to +8ꢁ°C

Package Description

ꢀ4-Lead LFCSP

Package Option

CP-ꢀ4-3

Evaluation Board

¹Z = RoHS Compliant Part.

²W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The ADV7181DW models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

Rev. 0 | Page 21 of 24

ADV7181D

NOTES

Data Sheet

Rev. 0 | Page 22 of 24

Data Sheet

NOTES

ADV7181D

Rev. 0 | Page 23 of 24

ADV7181D

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D09994-0-12/11(0)

Rev. 0 | Page 24 of 24


型号：	ADV7181DWBCPZ
厂家：	ADI
描述：	10-Bit, 10-Channel, Multiformat SDTV/HDTV 10位， 10通道，多格式SDTV / HDTV 转换器色度信号转换器消费电路商用集成电路电视
文件：	总24页 (文件大小：360K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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